A core particle interconnect topology

Abstract

The application provides a core particle interconnection topology. In the application, the interconnection interface of a core particle is simplified to four (2-way input interface+2-way output interface), which can effectively reduce the area, power consumption and cost of the interconnection interface of the core particle. Based on the four independent interconnection interfaces of the core particle, the two-way transmission path exists between any two core particles in the core particle interconnection topology through the interconnection interface connection between the core particles, and there is no transmission path missing, so that each interconnection interface of each core particle in the core particle interconnection topology can be effectively utilized, the interface waste is avoided as much as possible, and the transmission path between any two core particles in the core particle interconnection topology is simple (easy to deduce), direct, clear and short.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chiplet interconnection topology. BACKGROUND

[0002] Moor's Law is an observation and prediction made by Gordon Moore, one of the founders of Intel Corporation, in 1965. It states that the number of transistors that can be placed on an integrated circuit will double approximately every two years, and that the performance of integrated circuits will also improve by a factor of two. This reflects the speed of progress in information technology.

[0003] However, in recent years, the number of transistors that can be placed on an integrated circuit cannot be further increased by reducing transistor size and increasing single-chip area. Therefore, chiplet technology has emerged.

[0004] Chiplet technology is an innovative solution to the increasing complexity and cost of chip manufacturing. It can be widely used in high-performance computing, artificial intelligence, data centers, and communication fields, and has become one of the important development directions of the semiconductor industry. Chiplet technology has the advantages of functional modularization, heterogeneous integration, cost-effectiveness, high performance, and scalability, SUMMARY

[0005] The present application shows a chiplet interconnection topology, which comprises:

[0006] a plurality of chiplets;

[0007] each chiplet includes two input interfaces and two output interfaces;

[0008] For a first chiplet in the plurality of chiplets, a first input interface of the first chiplet is directly connected to a first output interface of a second chiplet; a first output interface of the first chiplet is directly connected to a first input interface of a third chiplet; a second input interface of the first chiplet is directly connected to a second output interface of a fourth chiplet; and a second output interface of the first chiplet is directly connected to a second input interface of a fifth chiplet.

[0009] The first chiplet is any one of the plurality of chiplets, and the second output interface of the fifth chiplet is connected to the second input interface of the fourth chiplet via at least one chiplet.

[0010] In an optional implementation, the first output interface of the third chiplet is connected to the first input interface of the second chiplet via at least one chiplet.

[0011] In an optional implementation, the second output interface of the third chiplet is connected to the first input interface of the fourth chiplet via at least one chiplet.

[0012] In an optional implementation, the first output interface of the fifth corelet is connected to the second input interface of the second corelet via at least one corelet.

[0013] In an optional implementation, the first output interface of the third corelet is directly connected to the first input interface of the fourth corelet.

[0014] In an optional implementation, the first output interface of the fifth corelet is directly connected to the first input interface of the second corelet.

[0015] In an optional implementation, the second output interface of the third corelet is directly connected to the second input interface of the second corelet.

[0016] The present application also shows a topology of corelet interconnection, which comprises:

[0017] a plurality of corelets;

[0018] each corelet comprises two input interfaces and two output interfaces;

[0019] for a first corelet in the plurality of corelets, the first output interface of the first corelet is directly connected to the first input interface of a second corelet, the first input interface of the first corelet is directly connected to the first output interface of the second corelet; the second input interface of the first corelet is directly connected to the second output interface of a third corelet; the second output interface of the first corelet is directly connected to the second input interface of a fourth corelet;

[0020] the first corelet is any one of the plurality of corelets, and the second corelet, the third corelet and the fourth corelet are three different corelets from the first corelet in the plurality of corelets.

[0021] In an optional implementation, the second output interface of the second corelet is connected to the first input interface of the third corelet via at least one corelet.

[0022] In an optional implementation, the first output interface of the fourth corelet is connected to the second input interface of the second corelet via at least one corelet.

[0023] In an optional implementation, the second output interface of the fourth corelet is connected to the second input interface of the third corelet via at least one corelet.

[0024] The present application also shows a topology of corelet interconnection, which comprises:

[0025] a plurality of corelets;

[0026] each corelet comprises two input interfaces and two output interfaces;

[0027] For the first core in a plurality of cores, the first output interface of the first core is directly connected to the first input interface of the second core, and the second input interface of the first core is directly connected to the second output interface of the second core; the second output interface of the first core is directly connected to the second input interface of the third core, and the first input interface of the first core is directly connected to the first output interface of the third core.

[0028] The first core is any one of the multiple cores, and the second and third cores are the two different cores that are closest to the first core.

[0029] The technical solution provided in this application may include the following beneficial effects:

[0030] In this application, the interconnect interface of a single chip is simplified to four (2 input interfaces + 2 output interfaces), which can effectively reduce the area, power consumption and cost of the interconnect interface of the chip.

[0031] The four interconnect interfaces of a chip are independent of each other. That is, any one of the four interconnect interfaces of the chip is treated independently. The interconnect interface is unidirectional. For example, the interconnect interface is either an input interface or an output interface. If the interconnect interface is an input interface, the transmission direction is from other output interfaces (such as the output interfaces of other chips) to the interconnect interface. Or, if the interconnect interface is an output interface, the transmission direction is from the interconnect interface to other input interfaces (such as the input interfaces of other chips).

[0032] In this application, based on the four independent interconnect interfaces of the core particles, the interconnection method between the core particles in this application can ensure that there is a bidirectional transmission path between any two core particles in the core particle interconnection topology, and there is no situation where the transmission path is missing. This allows each interconnect interface of each core particle in the core particle interconnection topology to be effectively utilized, which can minimize interface waste. Furthermore, the transmission path between any two core particles in the core particle interconnection topology is simple (easy to derive), direct, clear, and short in distance. Attached Figure Description

[0033] Figure 1 A schematic diagram of a current chip interconnect topology is shown.

[0034] Figure 2 A schematic diagram of a current chip interconnect topology is shown.

[0035] Figure 3 A schematic diagram of four sets of bidirectional interconnect interfaces for a current type of chip is shown.

[0036] Figure 4 A schematic diagram of a four-way unidirectional interconnect interface of a corelet of the present application is shown

[0037] Figure 5 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0038] Figure 6 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0039] Figure 7 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0040] Figure 8 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0041] Figure 9 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0042] Figure 10 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0043] Figure 11 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0044] Figure 12 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0045] Figure 13 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0046] Figure 14 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0047] Figure 15 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0048] Figure 16 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0049] Figure 17 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0050] Figure 18 A schematic diagram of a corelet interconnect topology of the present application is shown.

[0051] Figure 19 A schematic diagram of a corelet interconnect topology of the present application is shown. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort are within the protection scope of the present application.

[0053] Among them, the chiplet technology decomposes a complex large chip into multiple smaller and relatively independent small chips, and integrates these small chips together through advanced packaging technology to form a complete system, which can improve performance while achieving low cost and high yield.

[0054] At present, the chiplet technology has gradually become an important way for the semiconductor industry to continue Moore's Law.

[0055] The chiplet interconnection topology is a network structure for realizing communication between multiple chiplets. The chiplet interconnection topology includes a full connection topology, a ring topology, and a two-dimensional grid topology, etc. Different topologies have different characteristics and can be applied to different application scenarios and requirements.

[0056] For example, Figure 1 A schematic diagram of a current chiplet interconnection topology is shown, which adopts a full connection topology. If the central cross-interconnection part is removed, a ring topology can be obtained.

[0057] For another example, Figure 2 A schematic diagram of another current chiplet interconnection topology is shown, which is a two-dimensional grid topology.

[0058] However, the communication and interconnection of chiplets gradually face many challenges. The interconnection interface (D2D Interface) of chiplets brings additional problems such as area increase, power consumption increase, and cost increase.

[0059] For example, the current chiplet interconnection topology relies on the coordinated work of multiple interconnection interfaces of chiplets, for example, Figure 2 In the chiplet interconnection topology shown, the chiplets in the central part need at least 4 sets of bidirectional interconnection interfaces (a total of 4 output interfaces and 4 input interfaces).

[0060] For example, in the current chiplet interconnection topology, the interconnection interface of the chiplet adopts a bidirectional design, Figure 3A schematic diagram of four sets of bidirectional interconnection interfaces of a current core particle is shown, one input interface and one output interface form a set of interconnection interfaces, in fact, the core particle has 8 interfaces (4 input interfaces + 4 output interfaces), which form four sets of bidirectional interconnection interfaces.

[0061] However, in actual core particle communication services, not all interconnection interfaces are effectively utilized, resulting in waste.

[0062] Therefore, in order to improve the utilization rate of the interconnection interface of the core particle, and reduce the area of the interconnection interface of the core particle, the power consumption of the interconnection interface of the core particle and the cost of the interconnection interface of the core particle, the scheme of the present application is proposed.

[0063] Figure 4 A schematic diagram of four sets of bidirectional interconnection interfaces of a current core particle is shown, one input interface and one output interface form a set of interconnection interfaces, in fact, the core particle has 8 interfaces (4 input interfaces + 4 output interfaces), which form four sets of bidirectional interconnection interfaces.

[0064] Unidirectional is not one input interface and one output interface form a set of interconnection interfaces, but the four interconnection interfaces of the core particle are independent of each other, that is, for any one of the four interconnection interfaces of the core particle, the interconnection interface is either an input interface or an output interface, if the interconnection interface is an input interface, the transmission direction is from other output interfaces (such as the output interfaces of other core particles) to the interconnection interface, or if the interconnection interface is an output interface, the transmission direction is from the interconnection interface to other input interfaces (such as the input interfaces of other core particles).

[0065] However, due to the unidirectional restriction of the interconnection interface of the core particle, it may cause the problem of missing transmission path or too complex transmission path between some core particles in the topology of core particle interconnection.

[0066] Therefore, in the present application, based on the above-mentioned unidirectional interconnection interface of the core particle, a variety of topologies such as ring topology, two-dimensional grid topology, three-dimensional grid topology, tree topology and hybrid topology can be constructed, and there is a simple transmission path between any two core particles in the topology.

[0067] In one example, the core particles in the topology of core particle interconnection of the present application satisfy at least one of the following rules:

[0068] 1. The output interface of a core particle can be connected to the input interface of other core particles (in the drawings of the present application, OUT is the output interface, IN is the input interface, the output interface is the starting point of the unidirectional arrow, and the input interface is the end point of the unidirectional arrow).

[0069] 2、One output interface of a chiplet can be connected with one input interface (such as an input interface of another chiplet, etc.), or part of the output interfaces of a chiplet are not connected with other input interfaces; one input interface of a chiplet can be connected with one output interface, or part of the input interfaces of a chiplet are not connected with other output interfaces.

[0070] 3、Three or more chiplets can form a unidirectional circulation path (a clockwise circulation path or an anticlockwise circulation path) through their input interfaces and output interfaces.

[0071] 4、Different direction circulation paths (clockwise circulation paths or anticlockwise circulation paths) can share part of the chiplets and data paths.

[0072] 5、Same direction circulation paths (clockwise circulation paths or anticlockwise circulation paths) can share chiplets but not share data paths.

[0073] Thus, the transmission path between any two chiplets is simple (easy to deduce), direct, clear and short, there is a bidirectional transmission path between any two chiplets, and there is no missing transmission path.

[0074] The scheme of the present application is described in detail below.

[0075] The present application shows a topology of chiplet interconnection, which comprises:

[0076] A plurality of chiplets.

[0077] Each chiplet comprises two input interfaces and two output interfaces.

[0078] For example, the two input interfaces in a chiplet are a first input interface IN1 and a second input interface IN2, and the two output interfaces are a first output interface OUT1 and a second output interface OUT2.

[0079] For a first chiplet in the plurality of chiplets, the first input interface of the first chiplet is directly connected with the first output interface of a second chiplet; the first output interface of the first chiplet is directly connected with the first input interface of a third chiplet, the second input interface of the first chiplet is directly connected with the second output interface of a fourth chiplet; and the second output interface of the first chiplet is directly connected with the second input interface of a fifth chiplet.

[0080] The first chiplet is any one of the plurality of chiplets.

[0081] The second output interface of the fifth chiplet is connected with the second input interface of the fourth chiplet via at least one chiplet.

[0082] Further, the first output interface of the third kernel is connected to the first input interface of the second kernel via at least one kernel.

[0083] Further, the second output interface of the third kernel is connected to the first input interface of the fourth kernel via at least one kernel; and / or, the first output interface of the fifth kernel is connected to the second input interface of the second kernel via at least one kernel.

[0084] Further, the first output interface of the third kernel is directly connected to the first input interface of the fourth kernel; and / or, the first output interface of the fifth kernel is directly connected to the first input interface of the second kernel; and / or, the second output interface of the third kernel is directly connected to the second input interface of the second kernel.

[0085] For example, referring to Figure 5 The topology includes a plurality of kernels. The plurality of kernels in the topology form a two-dimensional grid structure.

[0086] Sixteen kernels are illustrated in this embodiment, but in fact there can be more than sixteen kernels, and the dashed lines can also connect other kernels, which are not shown in the figure.

[0087] Figure 5 The kernel in the second row and the second column is taken as the first kernel for example.

[0088] The first kernel, the third kernel, and the fifth kernel are in the same row in the two-dimensional grid structure.

[0089] The first kernel, the second kernel, and the fourth kernel are in the same column in the two-dimensional grid structure.

[0090] The second output interface (illustrated as OUT2) of the fifth kernel is connected to the second input interface (illustrated as IN2) of the fourth kernel via a five-four relay kernel; the five-four relay kernel and the fifth kernel are in the same column in the two-dimensional grid structure, and the five-four relay kernel and the fourth kernel are in the same row in the two-dimensional grid structure, for example, the five-four relay kernel is the kernel in the third row and the third column.

[0091] And / or, the second output interface (illustrated as OUT2) of the third kernel is connected to the first input interface (illustrated as IN1) of the fourth kernel via a three-four relay kernel; the three-four relay kernel and the third kernel are in the same column in the two-dimensional grid structure, and the three-four relay kernel and the fourth kernel are in the same row in the two-dimensional grid structure, for example, the three-four relay kernel is the kernel in the third row and the first column.

[0092] And / or, the first output interface (illustrated as OUT1) of the fifth corelet is connected with the second input interface (illustrated as IN2) of the second corelet via a five-two transit corelet; the five-two transit corelet and the fifth corelet are located in the same column in the two-dimensional grid structure, and the five-two transit corelet and the second corelet are located in the same row in the two-dimensional grid structure. For example, the five-two transit corelet is the corelet located in the third column of the first row.

[0093] And / or, the first output interface (illustrated as OUT1) of the third corelet is connected with the first input interface (illustrated as IN1) of the second corelet via a three-two transit corelet; the three-two transit corelet and the third corelet are located in the same column in the two-dimensional grid structure, and the three-two transit corelet and the second corelet are located in the same row in the two-dimensional grid structure. For example, the three-two transit corelet is the corelet located in the first column of the first row.

[0094] In this way, nine circulation paths can be formed.

[0095] For example, circulation path 1: the first corelet→the fifth corelet→the five-two transit corelet→the second corelet→the first corelet.

[0096] Circulation path 2: the first corelet→the third corelet→the three-two transit corelet→the second corelet→the first corelet.

[0097] Circulation path 3: the first corelet→the fifth corelet→the five-four transit corelet→the fourth corelet→the first corelet.

[0098] Circulation path 4: the first corelet→the third corelet→the three-four transit corelet→the fourth corelet→the first corelet.

[0099] Circulation path 5: the fourth corelet→the corelet in the second column of the fourth row→the corelet in the first column of the fourth row→the three-four transit corelet→the fourth corelet.

[0100] Circulation path 6: the fourth corelet→the corelet in the second column of the fourth row→the corelet in the third column of the fourth row→the five-four transit corelet→the fourth corelet.

[0101] Circulation path 7: the fifth corelet→the five-two transit corelet→the corelet in the fourth column of the first row→the corelet in the fourth column of the second row→the fifth corelet.

[0102] Circulation path 8: the fifth corelet→the five-four transit corelet→the corelet in the fourth column of the third row→the corelet in the fourth column of the second row→the fifth corelet.

[0103] Circulation path 9: the five-four transit corelet→the corelet in the fourth column of the third row→the corelet in the fourth column of the fourth row→the corelet in the third column of the fourth row→the five-four transit corelet.

[0104] For example, see Figure 6 For example, the topology structure includes a plurality of corelets. The structure formed by the plurality of corelets in the topology structure is a two-dimensional grid structure.

[0105] In this embodiment, 16 cores are illustrated, but in fact, there can be more than 16 cores, and the dashed lines can also connect other cores, which are not shown in the figure.

[0106] Figure 6 Take the core in the third column of the second row as an example.

[0107] The first core, the third core and the fifth core are in the same column in the two-dimensional grid structure; the first core, the second core and the fourth core are in the same row in the two-dimensional grid structure.

[0108] The second output interface (illustrated as OUT2) of the fifth core is connected to the second input interface (illustrated as IN2) of the fourth core via the five-four relay core; the five-four relay core is in the same row as the fifth core in the two-dimensional grid structure, and the five-four relay core is in the same column as the fourth core in the two-dimensional grid structure, for example, the five-four relay core is the core in the second column of the third row.

[0109] And / or, the second output interface (illustrated as OUT2) of the third core is connected to the first input interface (illustrated as IN1) of the fourth core via the three-four relay core; the three-four relay core is in the same row as the third core in the two-dimensional grid structure, and the three-four relay core is in the same column as the fourth core in the two-dimensional grid structure, for example, the three-four relay core is the core in the second column of the first row.

[0110] And / or, the first output interface (illustrated as OUT1) of the fifth core is connected to the second input interface (illustrated as IN2) of the second core via the five-two relay core; the five-two relay core is in the same row as the fifth core in the two-dimensional grid structure, and the five-two relay core is in the same column as the second core in the two-dimensional grid structure. For example, the five-two relay core is the core in the fourth column of the third row.

[0111] And / or, the first output interface (illustrated as OUT1) of the third core is connected to the first input interface (illustrated as IN1) of the second core via the three-two relay core; the three-two relay core is in the same row as the third core in the two-dimensional grid structure, and the three-two relay core is in the same column as the second core in the two-dimensional grid structure. For example, the three-two relay core is the core in the first column of the fourth row.

[0112] For another example, see Figure 7 Take the topology structure including a plurality of cores as an example. The structure composed of the plurality of cores in the topology structure is a tree structure.

[0113] In this embodiment, a plurality of cores are illustrated, but in fact, there can be more than the illustrated plurality of cores, and the dashed lines can also connect other cores, which are not shown in the figure.

[0114] Figure 7 The shown tree structure includes 6 layers. Figure 7 Take the second core grain from the left in the third layer as the first core grain for example.

[0115] Figure 7 In the embodiment, the second core grain is located at the upper left corner of the first core grain, the third core grain is located at the upper right corner of the first core grain, the fourth core grain is located at the lower right corner of the first core grain, and the fifth core grain is located at the lower left corner of the first core grain.

[0116] The second core grain and the third core grain are respectively the parent nodes of the first core grain.

[0117] The first core grain is respectively the child node of the fourth core grain and the fifth core grain.

[0118] The second output interface (OUT2) of the fifth core grain is connected with the second input interface (IN2) of the fourth core grain via the fifth-fourth relay core grain; the fifth-fourth relay core grain is the child node of the fifth core grain and the child node of the fourth core grain.

[0119] And / or, the second output interface (OUT2) of the third core grain is connected with the first input interface (IN1) of the fourth core grain via the third-fourth relay core grain; the third-fourth relay core grain is the parent node of the fourth core grain and the child node of the third core grain, and the third-fourth relay core grain is located at the same layer as the first core grain but is not the first core grain.

[0120] And / or, the first output interface (OUT1) of the fifth core grain is connected with the second input interface (IN2) of the second core grain via the fifth-second relay core grain; the fifth-second relay core grain is the parent node of the fifth core grain and the child node of the second core grain, and the fifth-second relay core grain is located at the same layer as the first core grain but is not the first core grain and is not the third-fourth relay core grain.

[0121] And / or, the first output interface (OUT1) of the third core grain is connected with the first input interface (IN1) of the second core grain via the third-second relay core grain; the third-second relay core grain is the parent node of the third core grain and the parent node of the second core grain.

[0122] In this way, a plurality of circulating paths can be formed.

[0123] For example, circulating path 1: the first core grain→the fifth core grain→the fifth-second relay core grain→the second core grain→the first core grain.

[0124] Circulating path 2: the first core grain→the third core grain→the third-second relay core grain→the second core grain→the first core grain.

[0125] Circulating path 3: the first core grain→the third core grain→the third-fourth relay core grain→the fourth core grain→the first core grain.

[0126] Loop path 4: first corelet -> fifth corelet -> five-fourth corelet -> fourth corelet -> first corelet.

[0127] Loop path 5: fourth corelet (in the fourth layer) -> third corelet from the left in the fifth layer (child of the fourth corelet, same level as the five-fourth corelet but not the five-fourth corelet) -> fourth corelet from the left in the fourth layer (child of the three-fourth corelet but not the fourth corelet) -> three-fourth corelet -> fourth corelet.

[0128] Loop path 6: fourth corelet (in the fourth layer) -> third corelet from the left in the fifth layer (child of the fourth corelet, same level as the five-fourth corelet but not the five-fourth corelet) -> second corelet from the left in the sixth layer (child of the five-fourth corelet) -> five-fourth corelet -> fourth corelet.

[0129] Other loop paths are not described one by one.

[0130] For example, see Figure 8 The topology structure includes a plurality of corelets. The plurality of corelets in the topology structure form a tree structure.

[0131] In this embodiment, a plurality of corelets are illustrated. In fact, there can be more than the illustrated plurality of corelets. The dashed lines can also connect other corelets, which are not shown in the figure.

[0132] Figure 8 The illustrated tree structure includes six layers. Figure 8 The second corelet from the left in the third layer is taken as the first corelet for illustration.

[0133] Figure 8 In the figure, the second corelet is located at the upper right corner of the first corelet, the third corelet is located at the lower right corner of the first corelet, the fourth corelet is located at the lower left corner of the first corelet, and the fifth corelet is located at the upper left corner of the first corelet.

[0134] The second corelet and the fifth corelet are parent nodes of the first corelet, respectively.

[0135] The first corelet is a parent node of the third corelet and the fourth corelet, respectively.

[0136] The second output interface (OUT2) of the fifth corelet is connected to the second input interface (IN2) of the fourth corelet via the five-fourth corelet; the five-fourth corelet is a child node of the fifth corelet, and the five-fourth corelet is a parent node of the fourth corelet. The five-fourth corelet is in the same level as the first corelet but not the first corelet.

[0137] And / or, the second output interface (illustrated as OUT2) of the third kernel is connected with the first input interface (illustrated as IN1) of the fourth kernel via a third-fourth transit kernel; the third-fourth transit kernel is a child node of the fourth kernel, and the third-fourth transit kernel is a child node of the third kernel.

[0138] And / or, the first output interface (illustrated as OUT1) of the fifth kernel is connected with the second input interface (illustrated as IN2) of the second kernel via a fifth-second transit kernel; the fifth-second transit kernel is a parent node of the fifth kernel, and the fifth-second transit kernel is a parent node of the second kernel.

[0139] And / or, the first output interface (illustrated as OUT1) of the third kernel is connected with the first input interface (illustrated as IN1) of the second kernel via a third-second transit kernel; the third-second transit kernel is a parent node of the third kernel, and the third-second transit kernel is a child node of the second kernel. The third-second transit kernel is in the same level as the first kernel but is neither the first kernel nor the fifth-fourth transit kernel.

[0140] For example, refer to Figure 9 The topology structure includes a plurality of kernels. The plurality of kernels in the topology structure form a three-dimensional grid structure.

[0141] In this embodiment, 16 kernels are illustrated. In fact, there can be more than 16 kernels. The dashed lines can also connect other kernels, which are not illustrated in the figure.

[0142] Figure 9 In the illustrated three-dimensional grid structure, there are 6 planes, two XY planes from top to bottom, two XZ planes from front to back, and two YZ planes from left to right.

[0143] In the upper XY plane of the two XY planes from top to bottom and the front XZ plane of the two XZ planes from front to back, the second kernel from left to right is taken as the first kernel for example. Each plane can be regarded as a two-dimensional grid topology structure of kernel interconnection.

[0144] The first kernel, the second kernel, the third kernel, and the fifth kernel are located in the first plane (the upper XY plane of the two XY planes from top to bottom) in the three-dimensional grid structure; the first kernel and the fourth kernel are located in the second plane (the front XZ plane of the two XZ planes from front to back) in the two-dimensional grid structure.

[0145] The second output interface (illustrated as OUT2) of the fifth kernel is connected with the second input interface (illustrated as IN2) of the fourth kernel via a fifth-fourth transit kernel; the fifth-fourth transit kernel is located in the second plane, the fifth-fourth transit kernel is in the same column as the fifth kernel in the second plane, and the fifth-fourth transit kernel is in the same row as the fourth kernel in the second plane, for example, the fifth-fourth transit kernel is the first kernel in the second row and the first column in the second plane.

[0146] and / or, the second output interface (illustrated as OUT2) of the third corelet is connected with the first input interface (illustrated as IN1) of the fourth corelet via a three-fourth transit corelet; the three-fourth transit corelet is located in the second plane, the three-fourth transit corelet is in the same column as the third corelet in the second plane, the three-fourth transit corelet is in the same row as the fourth corelet in the second plane, for example, the three-fourth transit corelet is a corelet in the third column of the second row in the second plane.

[0147] and / or, the first output interface (illustrated as OUT1) of the fifth corelet is connected with the second input interface (illustrated as IN2) of the second corelet via a fifth-second transit corelet; the fifth-second transit corelet is located in the first plane, the fifth-second transit corelet is in the same column as the fifth corelet in the first plane, the fifth-second transit corelet is in the same row as the second corelet in the first plane, for example, the fifth-second transit corelet is a corelet in the first column of the first row in the first plane.

[0148] and / or, the first output interface (illustrated as OUT1) of the third corelet is connected with the first input interface (illustrated as IN1) of the second corelet via a third-second transit corelet; the third-second transit corelet is located in the first plane, the third-second transit corelet is in the same column as the third corelet in the first plane, the third-second transit corelet is in the same row as the second corelet in the first plane, for example, the third-second transit corelet is a corelet in the third column of the first row in the first plane.

[0149] In this way, a plurality of circulation paths can be formed.

[0150] For example, circulation path 1: first corelet→fifth corelet→fifth-second transit corelet→second corelet→first corelet.

[0151] circulation path 2: first corelet→third corelet→third-second transit corelet→second corelet→first corelet.

[0152] circulation path 3: first corelet→fifth corelet→fifth-fourth transit corelet→fourth corelet→first corelet.

[0153] circulation path 4: first corelet→third corelet→third-fourth transit corelet→fourth corelet→first corelet.

[0154] Other circulation paths are not described one by one.

[0155] For example, see Figure 10 The plurality of corelets in the topology structure are taken as an example for illustration. The structure composed of the plurality of corelets in the topology structure is a three-dimensional grid structure.

[0156] Sixteen corelets are illustrated in this embodiment, and in fact, there can be more than sixteen corelets. The dashed lines can also connect other corelets, which are not shown in the figure.

[0157] Figure 10 In the illustrated three-dimensional grid structure, there are six planes, two XY planes, two XZ planes, and two YZ planes.

[0158] In the upper XY plane of the two XY planes and the front XZ plane of the two XZ planes, the first core is taken as an example, which is the third core from left to right in a row of cores intersecting the upper XY plane and the front XZ plane. Each plane can be regarded as a two-dimensional grid of core interconnections.

[0159] The first core, the second core, the third core, and the fourth core are located in the first plane (the upper XY plane of the two XY planes) in the three-dimensional grid structure; the first core and the fifth core are located in the second plane (the front XZ plane of the two XZ planes) in the two-dimensional grid structure.

[0160] The second output interface (OUT2) of the fifth core is connected to the second input interface (IN2) of the fourth core via a five-four relay core; the five-four relay core is located in the second plane, the five-four relay core and the fifth core are located in the same row of the second plane, and the five-four relay core and the fourth core are located in the same column of the second plane, for example, the five-four relay core is a core located in the fourth column of the second row of the second plane.

[0161] And / or, the second output interface (OUT2) of the third core is connected to the first input interface (IN1) of the fourth core via a three-four relay core; the three-four relay core is located in the first plane, the three-four relay core and the third core are located in the same row of the first plane, and the three-four relay core and the fourth core are located in the same column of the first plane, for example, the three-four relay core is a core located in the fourth column of the first row of the second plane.

[0162] And / or, the first output interface (OUT1) of the fifth core is connected to the second input interface (IN2) of the second core via a five-two relay core; the five-two relay core is located in the second plane, the five-two relay core and the fifth core are located in the same row of the second plane, and the five-two relay core and the second core are located in the same column of the second plane, for example, the five-two relay core is a core located in the second column of the first row of the second plane.

[0163] And / or, the first output interface (OUT1) of the third core is connected to the first input interface (IN1) of the second core via a three-two relay core; the three-two relay core is located in the first plane, the three-two relay core and the third core are located in the same row of the first plane, and the three-two relay core and the second core are located in the same column of the first plane, for example, the three-two relay core is a core located in the second column of the first row of the first plane.

[0164] For example, referring toFigure 11 For example, the topology includes a plurality of core particles. The structure formed by the plurality of core particles in the topology is a structure combining a tree structure and a single ring structure.

[0165] In the structure of this embodiment, there are three rows, the number of core particles in the first row is the same as the number of core particles in the third row, and the number of core particles in the second row is less than the number of core particles in the first row by a value of 1.

[0166] In this embodiment, 7 core particles are illustrated, for example, 3 core particles in the first row, 2 core particles in the second row, 3 core particles in the third row, and so on.

[0167] It can be understood that there can be more than 7 core particles, for example, more than 4 core particles in the first row, more than 3 core particles in the second row, more than 4 core particles in the third row, and so on, which are not shown in the figure. Alternatively, more than 5 core particles in the first row, more than 4 core particles in the second row, more than 5 core particles in the third row, and so on, which are not shown in the figure.

[0168] Figure 11 For example, the first core particle is the first core particle from the left in the second row.

[0169] The second core particle is the first core particle from the left in the first row.

[0170] The fifth core particle is the second core particle from the left in the first row.

[0171] The third core particle is the first core particle from the left in the third row.

[0172] The fourth core particle is the second core particle from the left in the third row.

[0173] The second output interface (OUT2) of the fifth core particle is connected to the second input interface (IN2) of the fourth core particle via the fifth-fourth relay core particle.

[0174] And / or, the first output interface (OUT1) of the third core particle is directly connected to the first input interface (IN1) of the fourth core particle.

[0175] And / or, the first output interface (OUT1) of the fifth core particle is directly connected to the first input interface (IN1) of the second core particle.

[0176] And / or, the second output interface (OUT2) of the third core particle is directly connected to the second input interface (IN2) of the second core particle.

[0177] In this way, a plurality of circulating paths can be formed.

[0178] For example, cycle path 1: first core bead → fifth core bead → second core bead → first core bead.

[0179] Cycle path 2: first core bead → third core bead → second core bead → first core bead.

[0180] Cycle path 3: first core bead → fifth core bead → fifth-fourth transfer core bead → fourth core bead → first core bead.

[0181] Cycle path 4: first core bead → third core bead → fourth core bead → first core bead.

[0182] Cycle path 5: second core bead → third core bead in the first row from the left → fifth core bead → second core bead.

[0183] Cycle path 6: third core bead → third core bead in the third row from the left → fourth core bead → third core bead.

[0184] Cycle path 7: fifth core bead → fifth-fourth transfer core bead → third core bead in the first row from the left → fifth core bead.

[0185] Cycle path 8: fourth core bead → third core bead in the third row from the left → fifth-fourth transfer core bead → fourth core bead.

[0186] Cycle path 9: fifth-fourth transfer core bead → third core bead in the first row from the left → third core bead in the third row from the left → fifth-fourth transfer core bead.

[0187] For another example, see Figure 12 The plurality of core beads in the topological structure form a structure that is a combination of a tree structure and a single ring structure.

[0188] In the structure of this embodiment, there are three rows, the number of core beads in the first row is the same as the number of core beads in the third row, and the number of core beads in the second row is one less than the number of core beads in the first row.

[0189] In this embodiment, seven core beads are shown, for example, three core beads in the first row, two core beads in the second row, three core beads in the third row, and so on.

[0190] It can be understood that there can be more than seven core beads in practice, for example, more than four core beads in the first row, more than three core beads in the second row, more than four core beads in the third row, and so on, which are not shown in the figure. Alternatively, more than five core beads in the first row, more than four core beads in the second row, more than five core beads in the third row, and so on, which are not shown in the figure.

[0191] Figure 12 Take the core bead in the second position from the left in the first row as the first core bead for example.

[0192] The third core particle is the first core particle from the left in the first row.

[0193] The second core particle is the third core particle from the left in the first row.

[0194] The fourth core particle is the first core particle from the left in the second row.

[0195] The fifth core particle is the second core particle from the left in the second row.

[0196] The second output interface (OUT2) of the fifth core particle is connected to the second input interface (IN2) of the fourth core particle via the fifth-to-fourth core particle.

[0197] The first output interface (OUT1) of the third core particle is directly connected to the first input interface (IN1) of the fourth core particle.

[0198] The first output interface (OUT1) of the fifth core particle is directly connected to the first input interface (IN1) of the second core particle.

[0199] The second output interface (OUT2) of the third core particle is directly connected to the second input interface (IN2) of the second core particle.

[0200] For another example, refer to Figure 13 The topology structure includes a plurality of core particles. The structure formed by the plurality of core particles in the topology structure is a structure combining tree structure and single ring structure.

[0201] In the structure of this embodiment, there are three rows, the number of core particles in the first row is the same as the number of core particles in the third row, and the number of core particles in the second row is less than the number of core particles in the first row by a value of 1.

[0202] In this embodiment, 7 core particles are shown, for example, there are 3 core particles in the first row, 2 core particles in the second row, and 3 core particles in the third row.

[0203] It can be understood that there can be more than 7 core particles, for example, there are more than 4 core particles in the first row, more than 3 core particles in the second row, and more than 4 core particles in the third row, which are not shown in the figure. Alternatively, there are more than 5 core particles in the first row, more than 4 core particles in the second row, and more than 5 core particles in the third row, which are not shown in the figure.

[0204] Figure 13 The first core particle is taken as the second core particle from the left in the third row.

[0205] The second core particle is the first core particle from the left in the third row.

[0206] The third core particle is the third core particle from the left in the third row.

[0207] The fourth core particle is the second core particle from the left in the second row.

[0208] The fifth core particle is the first core particle from the left in the second row.

[0209] The second output interface (OUT2) of the fifth core particle is connected to the second input interface (IN2) of the fourth core particle via the fifth-fourth core particle.

[0210] The first output interface (OUT1) of the third core particle is directly connected to the first input interface (IN1) of the fourth core particle.

[0211] The first output interface (OUT1) of the fifth core particle is directly connected to the first input interface (IN1) of the second core particle.

[0212] The second output interface (OUT2) of the third core particle is directly connected to the second input interface (IN2) of the second core particle.

[0213] For another example, referring to Figure 14 The present application shows a core particle interconnection topology, and the structure formed by a plurality of core particles in the topology is a windmill structure. The windmill structure can be a windmill structure constructed on the basis of a single ring topology of four clockwise circulation paths and a single ring topology of one counterclockwise clockwise circulation path.

[0214] In the structure of this embodiment, there are four rows and four columns.

[0215] In this embodiment, 16 core particles are shown, but in fact there can be more than 16 core particles, and the dashed lines can also connect other core particles, which are not shown in the figure.

[0216] Alternatively, the interfaces of the dashed lines are no longer connected to other core particles.

[0217] Figure 14 Taking the core particle located in the second row and the second column as the first core particle as an example.

[0218] The first core particle, the third core particle, and the fourth core particle are located in the same row in the two-dimensional grid structure.

[0219] The first core particle, the second core particle, and the fifth core particle are located in the same column in the two-dimensional grid structure.

[0220] The first output interface (OUT1) of the third core particle is connected to the first input interface (IN1) of the second core particle via the third-second core particle.

[0221] The second output interface (OUT2) of the fifth corelet is connected to the second input interface (IN2) of the fourth corelet via the fifth-fourth transit corelet.

[0222] In this way, multiple loop paths can be formed.

[0223] For example, loop path 1: first corelet→third corelet→third-two transit corelet→second corelet→first corelet.

[0224] Loop path 2: first corelet→fifth corelet→corelet in the third row and the third column→fourth corelet→first corelet.

[0225] Loop path 3: fourth corelet→corelet in the first row and the third column→corelet in the first row and the fourth column→corelet in the second row and the fourth column→fourth corelet.

[0226] Loop path 4: fifth corelet→corelet in the fourth row and the second column→corelet in the fourth row and the first column→corelet in the third row and the first column→fifth corelet.

[0227] Loop path 5: corelet in the third row and the third column→corelet in the third row and the fourth column→corelet in the fourth row and the fourth column→corelet in the fourth row and the third column→corelet in the third row and the third column.

[0228] For another example, referring to Figure 15 The present application shows a topology of corelet interconnection, and the structure formed by the plurality of corelets in the topology is a windmill structure. The windmill structure can be a windmill structure constructed on the basis of a single ring topology of four clockwise loop paths and a single ring topology of one counterclockwise clockwise loop path.

[0229] In the structure of this embodiment, there are four rows and four columns.

[0230] In this embodiment, 16 corelets are shown, but in fact, there can be more than 16 corelets, and the dashed lines can also be connected to other corelets, which are not shown in the figure.

[0231] Alternatively, the interfaces of the dashed lines are no longer connected to other corelets.

[0232] Figure 15 Take the corelet in the third column of the second row as the first corelet for example.

[0233] The first corelet, the second corelet and the fifth corelet are located in the same row in the two-dimensional grid structure.

[0234] The first corelet, the third corelet and the fourth corelet are located in the same column in the two-dimensional grid structure.

[0235] The first output interface (OUT1) of the third corelet is connected to the first input interface (IN1) of the second corelet via the third-two transit corelet.

[0236] The second output interface (OUT2) of the fifth corelet is connected to the second input interface (IN2) of the fourth corelet via the fifth-fourth transfer corelet.

[0237] In addition, the present application shows a corelet interconnection topology, which includes:

[0238] A plurality of corelets.

[0239] Each corelet includes two input interfaces and two output interfaces.

[0240] For example, the two input interfaces in a corelet are a first input interface IN1 and a second input interface IN2, and the two output interfaces are a first output interface OUT1 and a second output interface OUT2.

[0241] For a first corelet in the plurality of corelets, the first output interface of the first corelet is directly connected to the first input interface of a second corelet, and the second input interface of the first corelet is directly connected to the second output interface of the second corelet; the second output interface of the first corelet is directly connected to the second input interface of a third corelet, and the first input interface of the first corelet is directly connected to the first output interface of the third corelet.

[0242] The first corelet is any one of the plurality of corelets, and the second corelet and the third corelet are two different corelets closest to the first corelet in the plurality of corelets.

[0243] In the present application, the positions of the plurality of corelets can be set first, and in the case where the positions of the plurality of corelets have been set (fixed and no longer changed), the distance between any two corelets is determined (fixed and no longer changed). Thus, in the plurality of corelets, for a first corelet, two different corelets closest to the first corelet can be found from the other corelets in the plurality of corelets except the first corelet.

[0244] For each of the other corelets in the plurality of corelets, if it is regarded as a first corelet, and if the two different corelets closest to it are regarded as a second corelet and a third corelet, the above-mentioned characteristics of the first corelet, i.e., the first output interface of the first corelet is directly connected to the first input interface of the second corelet, the first input interface of the first corelet is directly connected to the first output interface of the second corelet; the second output interface of the first corelet is directly connected to the first input interface of the third corelet, and the second input interface of the first corelet is directly connected to the first output interface of the third corelet, are also satisfied.

[0245] The second corelet and the third corelet can be directly connected through their own ports, which can be seen in the embodiments shown in Figure 16 .

[0246] Alternatively, the second core particle and the third core particle can be connected through other core particles (at least one core particle), which can be seen from the embodiment shown in Figure 17

[0247] For example, see Figure 16 The topology includes three core particles as an example.

[0248] The three core particles include a first core particle, a second core particle and a third core particle.

[0249] Since the topology of this embodiment has three core particles, any one core particle can be regarded as the first core particle, and the other two core particles can be regarded as the two different core particles closest to the first core particle.

[0250] The first core particle includes a first input interface IN1, a first output interface OUT1, a second input interface IN2 and a second output interface OUT2.

[0251] The second core particle includes a first input interface IN1, a first output interface OUT1, a second input interface IN2 and a second output interface OUT2.

[0252] The third core particle includes a first input interface IN1, a first output interface OUT1, a second input interface IN2 and a second output interface OUT2.

[0253] The first output interface OUT1 of the first core particle is directly connected to the first input interface IN1 of the second core particle, and the direction is from the first output interface OUT1 of the first core particle to the first input interface IN1 of the second core particle.

[0254] The second input interface IN2 of the first core particle is directly connected to the second output interface OUT2 of the second core particle, and the direction is from the second output interface OUT2 of the second core particle to the second input interface IN2 of the first core particle.

[0255] The second output interface OUT2 of the first core particle is directly connected to the second input interface IN2 of the third core particle, and the direction is from the second output interface OUT2 of the second core particle to the second input interface IN2 of the third core particle.

[0256] The first input interface IN1 of the first core particle is directly connected to the first output interface OUT1 of the third core particle, and the direction is from the first output interface OUT1 of the third core particle to the first input interface IN1 of the first core particle.

[0257] In addition, the first output interface OUT1 of the second core particle is directly connected to the first input interface IN1 of the third core particle, and the direction is from the first output interface OUT1 of the second core particle to the first input interface IN1 of the third core particle. ​

[0258] The second input interface IN2 of the second core particle is directly connected with the second output interface OUT2 of the third core particle, and the direction is from the second output interface OUT2 of the third core particle to the second input interface IN2 of the second core particle.

[0259] In this way, the first core particle, the second core particle and the third core particle constitute a ring-shaped topology, and two circulation paths can be formed.

[0260] For example, the clockwise circulation path is: the first core particle→the second core particle→the third core particle→the first core particle.

[0261] And the counterclockwise circulation path is: the first core particle→the third core particle→the second core particle→the first core particle.

[0262] For another example, referring to Figure 17 The topology includes four core particles as an example.

[0263] The four core particles include a first core particle, a second core particle, a third core particle and a fourth core particle.

[0264] Since the topology of this embodiment has four core particles, Figure 4 The positions of the four core particles in the figure have been fixed, so any one core particle can be regarded as the first core particle, for example, Figure 4 In the figure, the core particle in the upper left corner is regarded as the first core particle, and among the other three core particles, the distance between the core particle in the lower left corner and the first core particle is less than the distance between the core particle in the lower right corner and the first core particle, and the distance between the core particle in the upper right corner and the first core particle is less than the distance between the core particle in the lower right corner and the first core particle. Therefore, the core particle in the lower left corner and the core particle in the upper right corner can be regarded as the two different core particles closest to the first core particle.

[0265] Alternatively, if the core particle in the lower left corner is regarded as the first core particle, the core particle in the upper left corner and the core particle in the lower right corner can be regarded as the two different core particles closest to the first core particle (not shown in the figure).

[0266] The first core particle includes a first input interface IN1, a first output interface OUT1, a second input interface IN2 and a second output interface OUT2.

[0267] The second core particle includes a first input interface IN1, a first output interface OUT1, a second input interface IN2 and a second output interface OUT2.

[0268] The third core particle includes a first input interface IN1, a first output interface OUT1, a second input interface IN2 and a second output interface OUT2.

[0269] In this embodiment, the remaining one corelet can be regarded as a fourth corelet, which includes the first input interface IN1, the first output interface OUT1, the second input interface IN2 and the second output interface OUT2.

[0270] The first output interface OUT1 of the first corelet is directly connected with the first input interface IN1 of the second corelet, and the direction is from the first output interface OUT1 of the first corelet to the first input interface IN1 of the second corelet.

[0271] The second input interface IN2 of the first corelet is directly connected with the second output interface OUT2 of the second corelet, and the direction is from the second output interface OUT2 of the second corelet to the second input interface IN2 of the first corelet.

[0272] The second output interface OUT2 of the first corelet is directly connected with the second input interface IN2 of the third corelet, and the direction is from the second output interface OUT2 of the first corelet to the second input interface IN2 of the third corelet.

[0273] The first input interface IN1 of the first corelet is directly connected with the first output interface OUT1 of the third corelet, and the direction is from the first output interface OUT1 of the third corelet to the first input interface IN1 of the first corelet.

[0274] In addition, the first output interface OUT1 of the second corelet is directly connected with the first input interface IN1 of the fourth corelet, and the direction is from the first output interface OUT1 of the second corelet to the first input interface IN1 of the fourth corelet.

[0275] The second input interface IN2 of the second corelet is directly connected with the second output interface OUT2 of the fourth corelet, and the direction is from the second output interface OUT2 of the fourth corelet to the second input interface IN2 of the second corelet.

[0276] In addition, the second output interface OUT2 of the third corelet is directly connected with the second input interface IN2 of the fourth corelet, and the direction is from the second output interface OUT2 of the third corelet to the second input interface IN2 of the fourth corelet.

[0277] The first input interface IN1 of the third corelet is directly connected with the first output interface OUT1 of the fourth corelet, and the direction is from the first output interface OUT1 of the fourth corelet to the first input interface IN1 of the third corelet.

[0278] In addition, the first output interface OUT1 of the second corelet is directly connected with the first input interface IN1 of the fourth corelet, and the direction is from the first output interface OUT1 of the second corelet to the first input interface IN1 of the fourth corelet.

[0279] A plurality of corelets.

[0280] Each corelet includes two input interfaces and two output interfaces.

[0281] For example, two input interfaces in one core particle are a first input interface IN1 and a second input interface IN2, and two output interfaces are a first output interface OUT1 and a second output interface OUT2.

[0282] For a first core particle in the plurality of core particles, the first output interface of the first core particle is directly connected to the first input interface of a second core particle, and the first input interface of the first core particle is directly connected to the first output interface of the second core particle; the second input interface of the first core particle is directly connected to the second output interface of a third core particle; and the second output interface of the first core particle is directly connected to the second input interface of a fourth core particle.

[0283] The first core particle is any one of the plurality of core particles, and the second core particle, the third core particle, and the fourth core particle are three different core particles different from the first core particle in the plurality of core particles.

[0284] The second output interface of the second core particle is connected to the first input interface of the third core particle via at least one core particle.

[0285] The first output interface of the fourth core particle is connected to the second input interface of the second core particle via at least one core particle.

[0286] The second output interface of the fourth core particle is connected to the second input interface of the third core particle via at least one core particle.

[0287] In the present application, the positions of the plurality of core particles can be set first so that the plurality of core particles are arranged in a nested annular shape, that is, the plurality of core particles are arranged in at least two nested annular shapes.

[0288] For example, two annular shapes, a large one and a small one, are set first, the small annular shape is nested in the large annular shape, and then the plurality of core particles are divided into two parts, one part of the core particles is uniformly arranged on the large ring, and the other part of the core particles is uniformly arranged on the small ring.

[0289] Alternatively, three annular shapes, for example, a small annular shape, a middle annular shape, and a large annular shape, are set first, the small annular shape is nested in the middle annular shape, and the middle annular shape is nested in the large annular shape, and then the plurality of core particles are divided into three parts, one part of the core particles is uniformly arranged on the large ring, another part of the core particles is uniformly arranged on the middle ring, and the other part of the core particles is uniformly arranged on the small ring.

[0290] For example, N annular shapes are set, N is greater than or equal to 2, the N annular shapes are numbered 1, 2, …, N, the 1st annular shape is smaller than the 2nd annular shape, …, the (N-1)th annular shape is smaller than the Nth annular shape.

[0291] The 1st ring shape is nested in the 2nd ring shape, the N-1st ring shape is nested in the Nth ring shape.

[0292] The plurality of core particles are divided into N parts, the 1st part of core particles are evenly arranged on the 1st ring shape, the 2nd part of core particles are evenly arranged on the 2nd ring shape, and the Nth part of core particles are evenly arranged on the Nth ring shape.

[0293] In this way, the positions of the core particles on each ring shape have been set (fixed and no longer change), and the distance between any two core particles is determined (fixed and no longer change).

[0294] In this way, in the two adjacent ring shapes, if the first core particle is one of the core particles in the small ring, the second core particle is the core particle in the large ring that is closest to the first core particle, and the third and fourth core particles are the core particles in the small ring, and the third and fourth core particles are the two core particles in the small ring that are closest to the first core particle.

[0295] In this way, in the plurality of core particles, for the first core particle, the second core particle closest to the first core particle can be found from the plurality of core particles in the large ring, and the third and fourth core particles closest to the first core particle can be found from the plurality of core particles in the small ring.

[0296] Alternatively, if the first core particle is one of the core particles in the large ring, the second core particle is the core particle in the small ring that is closest to the first core particle, and the third and fourth core particles are the core particles in the large ring, and the third and fourth core particles are the two core particles in the large ring that are closest to the first core particle.

[0297] In this way, in the plurality of core particles, for the first core particle, the second core particle closest to the first core particle can be found from the plurality of core particles in the large ring, and the third and fourth core particles closest to the first core particle can be found from the plurality of core particles in the small ring.

[0298] For example, referring to Figure 18 The plurality of core particles in the topology form a nested ring structure.

[0299] Eight core particles are illustrated in this embodiment, but in fact there can be more than eight core particles.

[0300] Figure 18 The macrocycle has 4 core particles and the microcycle has 4 core particles.

[0301] Take the core particle in the upper left corner of the microcycle as the first core particle for example.

[0302] The second core particle is in the macrocycle, and the third and fourth core particles are in the microcycle.

[0303] Since the second core particle needs to be the core particle in the macrocycle that is closest to the first core particle, the second core particle can be the core particle in the upper left corner of the macrocycle.

[0304] Since the third and fourth core particles need to be the two core particles in the microcycle that are closest to the first core particle, the third core particle can be the core particle in the lower left corner of the microcycle, and the fourth core particle can be the core particle in the upper right corner of the microcycle.

[0305] The second output interface (OUT2) of the second core particle is connected to the first input interface (IN1) of the third core particle via at least one core particle (the core particle in the lower left corner of the macrocycle).

[0306] And / or, the first output interface (OUT1) of the fourth core particle is connected to the second input interface (IN2) of the second core particle via at least one core particle (the core particle in the upper right corner of the macrocycle).

[0307] And / or, the second output interface (OUT2) of the fourth core particle is connected to the second input interface (IN2) of the third core particle via at least one core particle (the core particle in the lower right corner of the microcycle).

[0308] In this way, five circulation paths can be formed.

[0309] For example, circulation path 1: first core particle → second core particle → core particle in the lower left corner of the macrocycle → third core particle → first core particle.

[0310] Circulation path 2: first core particle → fourth core particle → core particle in the upper right corner of the macrocycle → second core particle → first core particle.

[0311] Circulation path 3: first core particle → fourth core particle → core particle in the lower right corner of the microcycle → third core particle → first core particle.

[0312] Circulation path 4: fourth core particle → core particle in the lower right corner of the microcycle → core particle in the lower right corner of the macrocycle → core particle in the upper right corner of the macrocycle → fourth core particle.

[0313] Loop path 5: third bead -> bead in lower left corner of macrocycle -> bead in lower right corner of macrocycle -> bead in lower right corner of microcycle -> third bead.

[0314] For example, see Figure 19 The topology is exemplified by a plurality of beads. The plurality of beads in the topology form a nested loop structure.

[0315] Eight beads are illustrated in this embodiment, but in practice there can be more than eight beads.

[0316] Figure 19 The macrocycle has four beads and the microcycle has four beads.

[0317] The first bead is exemplified by the bead in the upper left corner of the macrocycle.

[0318] The second bead is in the microcycle, and the third and fourth beads are in the macrocycle.

[0319] The second bead can be the bead in the upper left corner of the microcycle because it needs to be the closest bead to the first bead among the plurality of beads in the microcycle.

[0320] The third bead can be the bead in the upper right corner of the macrocycle and the fourth bead can be the bead in the lower left corner of the macrocycle because they need to be the two closest beads to the first bead among the plurality of beads in the macrocycle.

[0321] The second output interface (illustrated as OUT2) of the second bead is connected to the first input interface (illustrated as IN1) of the third bead via at least one bead (illustrated as the bead in the upper right corner of the microcycle).

[0322] And / or, the first output interface (illustrated as OUT1) of the fourth bead is connected to the second input interface (illustrated as IN2) of the second bead via at least one bead (illustrated as the bead in the lower left corner of the microcycle).

[0323] And / or, the second output interface (illustrated as OUT2) of the fourth bead is connected to the second input interface (illustrated as IN2) of the third bead via at least one bead (illustrated as the bead in the lower right corner of the macrocycle).

[0324] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0325] Those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disc) and includes a plurality of instructions for causing a terminal (which can be a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in various embodiments of the present application.

[0326] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific embodiments, which are only illustrative and not restrictive. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims.

[0327] Those skilled in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present application can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0328] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device, and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0329] In the embodiments of the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the described embodiments of the apparatus are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0330] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0331] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0332] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc.

[0333] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A topology of core-particle interconnections, characterized by, The topology comprises: a plurality of core particles; each of the core particles comprises two input interfaces and two output interfaces respectively; for a first core particle of the plurality of core particles, a first input interface of the first core particle is directly connected with a first output interface of a second core particle, a first output interface of the first core particle is directly connected with a first input interface of a third core particle, a second input interface of the first core particle is directly connected with a second output interface of a fourth core particle, and a second output interface of the first core particle is directly connected with a second input interface of a fifth core particle; the first core particle is any one of the plurality of core particles, and the second output interface of the fifth core particle is connected with the second input interface of the fourth core particle via at least one core particle; three or more core particles form a unidirectional circulation path through the input interfaces and the output interfaces.

2. The topology of claim 1, wherein, The first output interface of the third core particle is connected with the first input interface of the second core particle via at least one core particle.

3. The topology of claim 2, wherein, The second output interface of the third core particle is connected with the first input interface of the fourth core particle via at least one core particle.

4. The topology of claim 2 or 3, characterized in that, The first output interface of the fifth core particle is connected with the second input interface of the second core particle via at least one core particle.

5. The topology of claim 1, wherein, The first output interface of the third core particle is directly connected with the first input interface of the fourth core particle.

6. The topology of claim 1, wherein, The first output interface of the fifth core particle is directly connected with the first input interface of the second core particle.

7. The topology of claim 1, wherein, The second output interface of the third core particle is directly connected with the second input interface of the second core particle.

8. A topology of core-particle interconnections, characterized by, The topology comprises: a plurality of core particles; each of the core particles comprises two input interfaces and two output interfaces respectively; for a first core particle of the plurality of core particles, a first output interface of the first core particle is directly connected with a first input interface of a second core particle, a first input interface of the first core particle is directly connected with a first output interface of the second core particle, a second input interface of the first core particle is directly connected with a second output interface of a third core particle, and a second output interface of the first core particle is directly connected with a second input interface of a fourth core particle; the first core particle is any one of the plurality of core particles, and the second, third and fourth core particles are three different core particles from the first core particle; three or more core particles form a unidirectional circulation path through the input interfaces and the output interfaces.

9. The topology of claim 8, wherein, The second output interface of the second core particle is connected with the first input interface of the third core particle via at least one core particle.

10. The topology of claim 8 or 9, characterized in that, The first output interface of the fourth core particle is connected with the second input interface of the second core particle via at least one core particle.

11. The topology of claim 10, wherein, The second output interface of the fourth core particle is connected with the second input interface of the third core particle via at least one core particle.

12. A topology of core-particle interconnections, characterized by, The topology comprises: a plurality of core particles; each of the core particles comprises two input interfaces and two output interfaces respectively; for a first core particle of the plurality of core particles, a first output interface of the first core particle is directly connected with a first input interface of a second core particle, a second input interface of the first core particle is directly connected with a second output interface of the second core particle, a second output interface of the first core particle is directly connected with a second input interface of a third core particle, and a first input interface of the first core particle is directly connected with a first output interface of the third core particle; The first core particle is any one of the plurality of core particles, and the second core particle and the third core particle are two different core particles closest to the first core particle among the plurality of core particles; The three core particles or more core particles form a one-way circulation path through the input interface and the output interface.

Images