Image data processing apparatus, method, device and storage medium

Abstract

The application relates to the technical field of image processing, and provides image data processing device, method, equipment and storage medium, the device comprises a first data path and a second data path; the first data path comprises a first reading module, a first bit width conversion module and an address module; the second data path comprises a second reading module, an address module and a writing module; the first reading module is used for reading an address block from a first memory in a first running mode; the first bit width conversion module is used for segmenting the address block to obtain a plurality of addresses; the address module is used for generating an absolute address corresponding to each address based on each address and a preset reading parameter; the second reading module is used for reading image data to be processed of each absolute address from a second memory; and the writing module is used for writing a plurality of image data to be processed into a first preset address block of the second memory. The technical scheme of the application improves the data bit width of the data path when the image data to be processed is stored in the OCM.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, and in particular to an image data processing apparatus, method, device and storage medium. BACKGROUND

[0002] At present, in the image data processing process, an address module is often used for non-continuous memory access or irregular memory access. The address module includes a gather module and a scatter module. The gather module can "gather" image data from multiple discontinuous addresses into a vector, and the scatter module can write a vector into discontinuous addresses.

[0003] In the related art, the address module is mainly applied to the following two scenarios: first, image data is stored in a double data rate synchronous dynamic random access memory (DDR), and addresses are stored in an on-chip memory (OCM); second, image data is stored in an OCM, and addresses are stored in a DDR / OCM.

[0004] However, the above two scenarios need to share one data path, which reduces the data bit width of the second scenario from the data bit width of the OCM to the data bit width of the DDR, that is, reduces the output efficiency of the second scenario. SUMMARY

[0005] Embodiments of the present application provide an image data processing apparatus, method, device and storage medium. According to the running mode, the data path is configured, the data bit width of the data path is maximized, the data bit width of the data path when the image data to be processed is stored in the OCM is improved, and the output efficiency of the apparatus is improved. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, an image data processing apparatus is provided, comprising:

[0007] a first data path and a second data path;

[0008] The first data path includes a first read module, a first bit width conversion module and an address module.

[0009] The second data path includes a second read module, the address module and a write module.

[0010] The first reading module is configured to read an address block from the first memory in a first operation mode, wherein the first operation mode indicates that the address block is stored in the first memory or the second memory, and image data to be processed is stored in the second memory, and a data bit width of the second memory is greater than a data bit width of the first memory.

[0011] The first bit width conversion module is configured to divide the address block to obtain a plurality of addresses.

[0012] The address module is configured to generate an absolute address corresponding to each address based on each address and a preset reading parameter.

[0013] The second reading module is configured to read the image data to be processed of each absolute address from the second memory.

[0014] The writing module is configured to write a plurality of the image data to be processed to a first preset address block of the second memory.

[0015] In some embodiments, the address module comprises a gathering module and a scattering module, and the gathering module and the scattering module are not operated at the same time.

[0016] The gathering module is configured to generate the absolute address corresponding to each address based on each address and the preset reading parameter.

[0017] In some embodiments, the first reading module is further configured to read an address block from the first memory.

[0018] The first bit width conversion module is further configured to divide the address block to obtain a plurality of addresses.

[0019] The scattering module is further configured to generate an absolute address corresponding to each address based on each address and a preset writing parameter.

[0020] The second reading module is further configured to read a plurality of the image data to be processed of a second preset address block from the second memory.

[0021] The writing module is further configured to write each of the image data to be processed to a corresponding absolute address in the second memory.

[0022] In some embodiments, the first data path further comprises a first selector.

[0023] The second data path further comprises a second selector, the third selector and the fourth selector.

[0024] The first reading module is further configured to transmit the address block to the first selector.

[0025] the first selector is configured to transmit the address block to the first bit width conversion module;

[0026] the second reading module is further configured to transmit the to-be-processed image data to the second selector;

[0027] the second selector is configured to transmit the to-be-processed image data to the aggregation module;

[0028] the aggregation module is further configured to transmit the to-be-processed image data to the third selector;

[0029] the third selector is configured to transmit the to-be-processed image data to the fourth selector;

[0030] the fourth selector is configured to transmit the to-be-processed image data to the writing module.

[0031] In some embodiments, the apparatus further comprises a third data path and a fourth data path;

[0032] the third data path comprises the second reading module, the first bit width conversion module, and the aggregation module;

[0033] the fourth data path comprises the first reading module, a second bit width conversion module, the aggregation module, and the writing module;

[0034] the second reading module is further configured to read the address block from the second memory in a second operation mode, the second operation mode indicating that the address block is stored in the second memory and the to-be-processed image data is stored in the first memory;

[0035] the first bit width conversion module is configured to divide the address block to obtain a plurality of addresses;

[0036] the aggregation module is configured to generate the absolute address corresponding to each address based on each address and the preset reading parameter;

[0037] the first reading module is configured to read the to-be-processed image data of each absolute address from the first memory;

[0038] the second bit width conversion module is configured to combine a plurality of to-be-processed image data to obtain combined image data;

[0039] the writing module is configured to write the combined image data to a first preset address block of the second memory.

[0040] In some embodiments, the third data path further comprises the first selector;

[0041] The fourth data path further comprises the second selector, the third selector and the fourth selector.

[0042] The second reading module is further configured to transmit the address block to the first selector.

[0043] The first selector is further configured to transmit the address block to the first bit width conversion module.

[0044] The second bit width conversion module is further configured to transmit the combined image data to the second selector.

[0045] The second selector is further configured to transmit the combined image data to the aggregation module.

[0046] The aggregation module is further configured to transmit the combined image data to the third selector.

[0047] The third selector is further configured to transmit the combined image data to the fourth selector.

[0048] The fourth selector is further configured to transmit the combined image data to the writing module.

[0049] In some embodiments, the apparatus further comprises a fifth data path.

[0050] The fifth data path comprises the first reading module, the second bit width conversion module and the writing module.

[0051] The first reading module is configured to read a plurality of the to-be-processed image data of the second preset address block from the first memory in a third operation mode; the third operation mode indicates that the to-be-processed image data is stored in the first memory or a second memory.

[0052] The second bit width conversion module is configured to combine a plurality of the to-be-processed image data to obtain the combined image data.

[0053] The writing module is configured to write the combined image data into the first preset address block of the second memory.

[0054] In some embodiments, the fifth data path further comprises the third selector and the fourth selector.

[0055] The second bit width conversion module is further configured to transmit the combined image data to the third selector.

[0056] The third selector is further configured to transmit the combined image data to the fourth selector.

[0057] The fourth selector is further configured to transmit the combined image data to the write module.

[0058] In some embodiments, the apparatus further comprises a sixth data path;

[0059] The sixth data path comprises the second read module and the write module.

[0060] The second read module is configured to read, in a fourth operation mode, a plurality of the to-be-processed image data of the second preset address block from the second memory; the fourth operation mode indicates that the to-be-processed image data is stored in the second memory.

[0061] The write module is configured to write a plurality of the to-be-processed image data into the first preset address block of the second memory.

[0062] In some embodiments, the sixth data path further comprises the fourth selector.

[0063] The second read module is further configured to transmit a plurality of the to-be-processed image data to the fourth selector.

[0064] The fourth selector is further configured to transmit a plurality of the to-be-processed image data to the write module.

[0065] In some embodiments, the first memory is DDR, and the second memory is OCM.

[0066] According to a second aspect of the embodiments of the present application, an image data processing method is provided, comprising: reading an address block from a first memory in a first operation mode; the first operation mode indicates that the address block is stored in the first memory or a second memory, and to-be-processed image data is stored in the second memory; a data bit width of the second memory is greater than a data bit width of the first memory;

[0067] segmenting the address block to obtain a plurality of addresses;

[0068] generating an absolute address corresponding to each of the addresses based on each of the addresses and a preset read parameter;

[0069] reading the to-be-processed image data of each of the absolute addresses from the second memory;

[0070] writing a plurality of the to-be-processed image data into a first preset address block of the second memory.

[0071] According to a third aspect of the embodiments of the present application, a computer device is provided, which comprises a processor and a memory, the memory being configured to store at least one program, the at least one program being loaded and executed by the processor to implement the image data processing method.

[0072] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores at least one program, the at least one program being loaded and executed by a processor to implement the image data processing method.

[0073] In the embodiments of the present application, the device comprises a first data path and a second data path; the first data path comprises a first reading module, a first bit width conversion module and an address module; the second data path comprises a second reading module, an address module and a writing module; the first reading module reads an address block from a first memory in a first running mode; a data bit width of a second memory is greater than a data bit width of the first memory; the first bit width conversion module divides the address block to obtain a plurality of addresses; the address module generates an absolute address corresponding to each address based on each address and a preset reading parameter; the second reading module reads image data to be processed of each absolute address from the second memory; and the writing module writes a plurality of image data to be processed into a first preset address block of the second memory. In the above technical solution, the first reading module and the second reading module do not need to share one data path, which ensures that the data bit width of the second data path is maximized, improves the data bit width of the second reading module and the address module, and thus improves the output efficiency of the second reading module and the address module, and further improves the output efficiency of the device. BRIEF DESCRIPTION OF DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0075] Figure 1 is a schematic diagram of an implementation environment provided according to the embodiments of the present application;

[0076] Figure 2 is a structural schematic diagram of a first image data processing device provided according to the embodiments of the present application;

[0077] Figure 3 is a structural schematic diagram of a second image data processing device provided according to the embodiments of the present application;

[0078] Figure 4 is a structural schematic diagram of a third image data processing device provided according to the embodiments of the present application;

[0079] Figure 5 is a structural schematic diagram of a fifth data path according to an embodiment of the present application;

[0080] Figure 6 is a structural schematic diagram of a sixth data path according to an embodiment of the present application;

[0081] Figure 7 is a flow schematic diagram of an image data processing method according to an embodiment of the present application;

[0082] Figure 8 is a structural schematic diagram of a terminal according to an embodiment of the present application;

[0083] Figure 9 is a structural schematic diagram of a server according to an embodiment of the present application. DETAILED DESCRIPTION

[0084] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0085] The exemplary embodiments will be described in detail herein below with reference to the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0086] The terms "first", "second", and the like in the present application are used to distinguish between similar or identical items or elements having substantially the same function and should be understood not to have a logical or chronological dependency between "first", "second", "n-th", and should not limit the number and execution order. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms.

[0087] These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, a first action can be called a second action, and similarly, a second action can be called a first action. The first action and the second action can both be actions, and in some cases, can be separate and distinct actions.

[0088] Wherein, at least one refers to one or more than one, for example, at least one action can be one action, two actions, three actions, etc. any integer greater than or equal to one action. And multiple refers to two or more than two, for example, multiple actions can be two actions, three actions, etc. any integer greater than or equal to two actions.

[0089] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application, which can include a terminal 101 and a server 102.

[0090] In the terminal 101, a neural processing unit (NPU) and a DDR are provided, and the NPU is provided with an OCM and an image data processing apparatus; the image data processing apparatus includes a first reading module, a second reading module, a first bit width conversion module, a second bit width conversion module, and an address module.

[0091] For example, the terminal 101 can be a wearable device, a personal computer, a laptop computer, a tablet computer, a smart television, a vehicle-mounted terminal, etc.

[0092] The server 102 can be a server, a server cluster composed of multiple servers, or a cloud processing center.

[0093] The terminal 101 is connected to the server 102 through a wired or wireless network.

[0094] In some embodiments, the wireless network or the wired network uses standard communication technologies and / or protocols. The network is usually the Internet, but can also be any network, including but not limited to a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), a mobile, wired or wireless network, a private network or a virtual private network of any combination. In some embodiments, technologies and / or formats such as hyper text mark-up language (HTML), extensible markup language (XML), etc. are used to represent data exchanged through the network. In addition, all or some links can be encrypted using conventional encryption technologies such as secure socket layer (SSL), transport layer security (TLS), virtual private network (VPN), Internet protocol security (IPsec), etc. In other embodiments, custom and / or dedicated data communication technologies can be used instead of or in addition to the above data communication technologies.

[0095] In the related art, the address module is usually used in Single Instruction, Multiple Data (SIMD) instruction set, Graphics Processing Unit (GPU) programming and sparse data processing. It is mainly applied to the following two scenarios: first, image data is stored in DDR, and the address is stored in on-chip memory OCM; second, image data is stored in OCM, and the address is stored in DDR / OCM.

[0096] Since the data bit width of DDR is small, the data bit width of OCM is large, and one Direct Memory Access (DMA) is fixed to read the address only, and another DMA is fixed to read the image data only, the data bit width of the DMA reading the image data in DDR is usually small, and the data bit width of the DMA reading the image data in OCM is large.

[0097] However, the above two scenarios need to share one data path, which leads to the reduction of the data bit width of the second scenario from OCM to DDR, that is, the output efficiency of the second scenario is reduced.

[0098] To solve the above technical problems, an embodiment of the present application provides an image data processing device,

[0099] supports multiple operation modes, different operation modes are configured with different data paths, the first reading module and the second reading module have different functions in different operation modes, and do not need to share one data path, so that the data bit width of each data path is maximized, thereby improving the data bit width and output efficiency of the second reading module and the address module, and further improving the output efficiency of the device. In addition, the embodiment of the present application configures multiple data paths by multiplexing some hardware, which realizes hardware multiplexing and greatly reduces the hardware area.

[0100] Figure 2 is a structural schematic diagram of the first image data processing device 200 provided by the embodiment of the present application. The first image data processing device 200 includes a first data path and a second data path. Figure 2 The image data processing device is described in detail. The device includes a first data path and a second data path.

[0101] In some examples, the first data path includes a first reading module 201, a first bit width conversion module 203 and an address module 204. The second data path includes a second reading module 202, an address module 204 and a writing module 205.

[0102] Exemplarily, the first operation mode indicates that the address block is stored in the first memory or the second memory, and the image data to be processed is stored in the second memory. The data bit width of the second memory is greater than the data bit width of the first memory.

[0103] Exemplarily, the first reading module 201 reads the address block from the first memory in the first operation mode; the first bit width conversion module 203 divides the address block to obtain a plurality of addresses; the address module 204 generates an absolute address corresponding to each address based on each address and a preset reading parameter; the second reading module 202 reads the image data to be processed of each absolute address from the second memory; and the writing module 205 writes the plurality of image data to be processed into the first preset address block of the second memory. The address block includes a plurality of non-continuous addresses.

[0104] Exemplarily, since the address module 204 can only receive one address at a time, in the embodiment of the present application, the first reading module 201 reads one address block from the first memory in each clock cycle. The first bit width conversion module 203 divides the address block to obtain a plurality of addresses, and transmits one address to the address module 204 at a time. The address corresponds to the image data to be processed one by one.

[0105] For example, the address block includes a plurality of addresses, and after dividing the address block, four addresses are obtained. The bit width of each address is 32 bits.

[0106] Exemplarily, when the image data to be processed is stored in the first memory, the address module 204 outputs n bit image data to be processed per clock cycle, that is, the output efficiency of the address module 204 is unchanged. n is the data bit width of the first memory. The data bit width of the first memory is n bits, which means that n bit image data to be processed can be requested from the first memory per clock cycle. n is an integer greater than or equal to 1.

[0107] Exemplarily, when the image data to be processed is stored in the second memory, the address module 204 outputs n bit image data to be processed per clock cycle, which is improved to m bit image data to be processed per clock cycle, that is, the output efficiency of the address module 204 is improved by m / n times. m is the data bit width of the second memory. The data bit width of the second memory is m bits, which means that m bit image data to be processed can be requested from the second memory per clock cycle. m is an integer greater than or equal to 1.

[0108] For example, the first memory is DDR, and the data bit width of DDR is 64 bits, that is, n is 64; the second memory is OCM, and the data bit width of OCM is 256 bits, that is, m is 256.

[0109] It can be understood that the first reading module 201 can access both the DDR and the OCM, so the data bit width of the first reading module 201 can only be 64 bits. The second reading module 202 can only access the OCM, so the data bit width of the second reading module 202 is 256 bits.

[0110] Exemplarily, the first preset address block includes a plurality of continuous addresses. The addresses correspond to the image data to be processed one by one. The first preset address block is stored in a first register configured in advance.

[0111] It can be understood from the above analysis that, in the first running mode, if the aggregation module 2041 is started, the second reading module 202 reads a plurality of image data to be processed from a plurality of non-continuous absolute addresses in the second memory; and the writing module 205 writes the plurality of image data to be processed into a plurality of continuous addresses in the second memory.

[0112] Exemplarily, after the device is powered on, the first register is configured according to the first running mode, and after the configuration of the first register is completed, the device determines the plurality of modules corresponding to the first running mode to be started according to the value of the first register, and executes the first running mode. Wherein, which running mode the device needs to execute is determined by the previous device.

[0113] For example, starting the address module 204 indicates that the subsequent device needs to use the image data output by the device for convolution calculation, that is, needs to read the image data to be processed stored in a plurality of non-continuous addresses. And not starting the address module 204 indicates that the subsequent device needs to use the image data output by the device for non-convolution calculation, that is, needs to sequentially read the image data to be processed stored in a plurality of continuous addresses. Therefore, the first running mode is applied to the scene of convolution calculation of the subsequent module.

[0114] It should be noted that, since the previous device and the subsequent device are not within the protection scope of the present application, the embodiments of the present application will not be described in detail.

[0115] In some examples, the address module 204 includes an aggregation module 2041 and a dispersion module 2042; the aggregation module 2041 and the dispersion module 2042 do not run at the same time. The aggregation module 2041 generates an absolute address corresponding to each address based on each address and a preset reading parameter.

[0116] Exemplarily, after the device is powered on, when the aggregation module 2041 is started, the dispersion module 2042 is closed; or when the aggregation module 2041 is closed, the dispersion module 2042 is started.

[0117] Exemplarily, the preset read parameter comprises a read base address and a read offset address; the aggregation module 2041 calculates the read base address, the read offset address and the address to obtain the absolute address. The read base address and the read offset address are obtained by the value of the first register preconfigured.

[0118] In some examples, in a first running mode, the first read module 201 reads an address block from the first memory; the first bit width conversion module 203 splits the address block to obtain a plurality of addresses; the dispersion module 2042 generates an absolute address corresponding to each address based on each address and a preset write parameter; the second read module 202 reads a plurality of to-be-processed image data of a second preset address block from the second memory; and the write module 205 writes each to-be-processed image data into the corresponding absolute address in the second memory.

[0119] Exemplarily, the preset write parameter comprises a write base address and a write offset address; the dispersion module 2042 calculates the write base address, the write offset address and the address to obtain the absolute address; wherein the write base address and the write offset address are obtained by the value of the first register preconfigured.

[0120] Exemplarily, the second preset address block is stored in the first register preconfigured.

[0121] From the above analysis, it can be seen that, in the first running mode, if the dispersion module 2042 is started, the second read module 202 reads a plurality of to-be-processed image data from a plurality of continuous addresses in the second memory; and the write module 205 writes the plurality of to-be-processed image data into a plurality of discontinuous absolute addresses in the second memory.

[0122] In the first running mode, the second read module 202 reads the to-be-processed image data from the second memory through the second data path, so that the first read module 201 and the second read module 202 do not share the first data path. Since the data bit width of the second memory is large, the data bit width of the second read module 202 is also large. That is, compared with the first read module 201 and the second read module 202 sharing one data path in the related art, the embodiment of the present application improves the data bit width of the second read module 202 and the data bit width of the aggregation module 2041, thereby improving the output efficiency of the second read module 202 and the aggregation module 2041.

[0123] Figure 3 is a structural schematic diagram of a second image data processing apparatus 200 provided by an embodiment of the present application. In combination with Figure 3 The image data processing apparatus is described in detail. The apparatus comprises:

[0124] In some examples, the first data path further comprises a first selector 206; and the second data path further comprises a second selector 207, a third selector 208 and a fourth selector 209.

[0125] For example, the first read module 201 transmits the address block to the first selector 206; the first selector 206 transmits the address block to the first bit width conversion module 203; the second read module 202 transmits the plurality of image data to be processed to the second selector 207; the second selector 207 transmits the plurality of image data to be processed to the aggregation module 2041; the aggregation module 2041 transmits the plurality of image data to be processed to the third selector 208; the third selector 208 transmits the plurality of image data to be processed to the fourth selector 209; and the fourth selector 209 transmits the plurality of image data to be processed to the write module 205.

[0126] For example, the first read module 201 transmits the address block to the first selector 206; the first selector 206 transmits the address block to the first bit width conversion module 203; the second read module 202 transmits the plurality of image data to be processed to the second selector 207; the second selector 207 transmits the plurality of image data to be processed to the dispersion module 2042; the dispersion module 2042 transmits the plurality of image data to be processed to the third selector 208; the third selector 208 transmits the plurality of image data to be processed to the fourth selector 209; and the fourth selector 209 transmits the plurality of image data to be processed to the write module 205.

[0127] For example, the first selector 206 comprises a first input end, a second input end and a first output end. The second selector 207 comprises a third input end, a fourth input end and a second output end. The third selector 208 comprises a fifth input end, a sixth input end and a third output end. The fourth selector 209 comprises a seventh input end, an eighth input end and a fourth output end.

[0128] For example, the conduction state of the first selector 206, the second selector 207, the third selector 208 and the fourth selector 209 is determined by the value of the second register corresponding to the first selector 206, the second selector 207, the third selector 208 and the fourth selector 209.

[0129] For example, when the value of the second register is 2 (==2), the first input of the first selector and the third input of the second selector are enabled; when the value of the second register is not 2 (!=2), the second input of the first selector and the fourth input of the second selector are enabled. When the value of the second register is 0 (==0), the fifth input of the third selector is enabled; when the value of the second register is not 0 (!=0), the sixth input of the third selector is enabled. When the value of the second register is not 1 (!=1), the seventh input of the fourth selector is enabled; when the value of the second register is 1 (==1), the eighth input of the fourth selector is enabled.

[0130] For example, when the value of the second register is 3, the second input terminal of the first selector 206, the fourth input terminal of the second selector 207, the sixth input terminal of the third selector 208, and the seventh input terminal of the fourth selector 209 are turned on.

[0131] For example, the first read module 201 transmits the address block to the second input terminal of the first selector 206, and the first selector 206 transmits the address block to the first width conversion module 203 through the first output terminal; the second read module 202 transmits multiple image data to be processed to the fourth input terminal of the second selector 207; the second selector 207 transmits multiple image data to be processed to the aggregation module 2041 through the second output terminal; the aggregation module 2041 transmits multiple image data to be processed to the sixth input terminal of the third selector 208; the third selector 208 transmits multiple image data to be processed to the seventh input terminal of the fourth selector 209 through the third output terminal; and the fourth selector 209 transmits the image data to be processed to the write module 205 through the fourth output terminal.

[0132] For example, the first selector 206, the second selector 207, the third selector 208, and the fourth selector 209 are all implemented based on a multiplexer.

[0133] Figure 4 This is a structural schematic diagram of a third image data processing apparatus 200 provided according to an embodiment of this application. (In conjunction with...) Figure 4 A detailed description of the image data processing apparatus is provided. The apparatus includes:

[0134] In some examples, the device further includes a third data path and a fourth data path; the third data path includes a second read module 202, a first bit width conversion module 203, and an aggregation module 2041; the fourth data path includes a first read module 201, a second bit width conversion module 210, an aggregation module 2041, and a write module 205.

[0135] Exemplarily, the second operation mode indicates that the address block is stored in the second memory, and the image data to be processed is stored in the first memory. The second operation mode is applied to a scenario in which the post-stage module performs convolution calculation.

[0136] Exemplarily, the second reading module 202 reads the address block from the second memory in the second operation mode; the first bit width conversion module 203 splits the address block to obtain a plurality of addresses; the gathering module 2041 generates an absolute address corresponding to each address based on each address and a preset reading parameter; the first reading module 201 reads the image data to be processed of each absolute address from the first memory; and the second bit width conversion module 210 combines a plurality of image data to be processed to obtain combined image data; and the writing module 205 writes the combined image data into the first preset address block of the second memory. The address block includes a plurality of continuous addresses.

[0137] Exemplarily, the second reading module 202 reads the address block from the second memory in the second operation mode; the first bit width conversion module 203 splits the address block to obtain a plurality of addresses; the gathering module 2041 generates an absolute address corresponding to each address based on each address and a preset reading parameter; the first reading module 201 reads the image data to be processed of each absolute address from the first memory; and the second bit width conversion module 210 combines a plurality of image data to be processed to obtain combined image data; and the writing module 205 writes the combined image data into the first preset address block of the second memory. The address block includes a plurality of continuous addresses.

[0138] Exemplarily, the second bit width conversion module 210 receives a plurality of clock cycles of image data to be processed, combines a plurality of clock cycles of image data to be processed to obtain a combined image data, and outputs the combined image data. In the embodiment of the present application, the second bit width conversion module 210 combines and transmits the image data to be processed, which not only shortens the transmission period, but also improves the data bit width of the gathering module 2041 or the scattering module 2042 under the premise that the amount of image data to be transmitted is unchanged.

[0139] For example, the second bit width conversion module 210 receives 4 clock cycles of image data to be processed, combines the 4 clock cycles of image data to be processed into a combined image data, and outputs the combined image data at the 4th clock cycle. When the bit width of each image data to be processed is 64 bits, the bit width of the combined image data is 256 bits.

[0140] In some examples, the third data path further includes a first selector 206; and the fourth data path further includes a second selector 207, a third selector 208, and a fourth selector 209.

[0141] Exemplarily, the second reading module 202 transmits the address block to the first selector 206; the first selector 206 transmits the address block to the first bit width conversion module 203; the second bit width conversion module 210 transmits the combined image data to the second selector 207; the second selector 207 transmits the combined image data to the aggregation module 2041; the aggregation module 2041 transmits the combined image data to the third selector 208; the third selector 208 transmits the combined image data to the fourth selector 209; and the fourth selector 209 transmits the combined image data to the writing module 205.

[0142] For example, when the value of the second register is 2, the first input end of the first selector 206, the third input end of the second selector 207, the sixth input end of the third selector 208 and the seventh input end of the fourth selector 209 are turned on.

[0143] For example, the second reading module 202 transmits the address block to the first input end of the first selector 206; the first selector 206 transmits the address block to the first bit width conversion module 203 through the first output end; the second bit width conversion module 210 transmits the combined image data to the third input end of the second selector 207; the second selector 207 transmits the combined image data to the aggregation module 2041 through the second output end; the aggregation module 2041 transmits the combined image data to the sixth input end of the third selector 208; the third selector 208 transmits the combined image data to the seventh input end of the fourth selector 209 through the third output end; and the fourth selector 209 transmits the combined image data to the writing module 205 through the fourth output end.

[0144] Figure 5 is a structural schematic diagram of a fifth data path provided by an embodiment of the present application. In combination with Figure 5 The fifth data path is described in detail. The fifth data path comprises a first reading module 201, a second bit width conversion module 210 and a writing module 205.

[0145] Exemplarily, the third operation mode indicates that the to-be-processed image data is stored in the first memory or the second memory. The third operation mode is applied to a scenario in which a later-stage device performs non-convolution calculation.

[0146] Exemplarily, in the third operation mode, the first reading module 201 reads a plurality of to-be-processed image data of a second preset address block from the first memory; the second bit width conversion module 210 combines the plurality of to-be-processed image data to obtain combined image data; and the writing module 205 writes the combined image data into a first preset address block of the second memory.

[0147] In some examples, the fifth data path further comprises a third selector 208 and a fourth selector 209. Illustratively, the second bit-width conversion module 210 transmits the combined image data to the third selector 208; the third selector 208 transmits the combined image data to the fourth selector 209; and the fourth selector 209 transmits the combined image data to the write module 205.

[0148] For example, when the value of the second register is 0, the fifth input end of the third selector 208 and the seventh input end of the fourth selector 209 are turned on.

[0149] For example, the second bit-width conversion module 210 transmits the combined image data to the fifth input end of the third selector 208; the third selector 208 transmits the combined image data to the seventh input end of the fourth selector 209 through the third output end; and the fourth selector 209 transmits the combined image data to the write module 205 through the fourth output end.

[0150] Figure 6 FIG. 6 is a structural schematic diagram of a sixth data path according to an embodiment of the present application. In combination with Figure 6 The fifth data path is described in detail. The sixth data path comprises the second read module 202 and the write module 205.

[0151] Illustratively, the fourth operation mode indicates that the to-be-processed image data is stored in the second memory; and the fourth operation mode is applied to a scenario in which the post-stage device performs non-convolution calculation.

[0152] Illustratively, the second read module 202 is configured to read, in the fourth operation mode, a plurality of to-be-processed image data of a second preset address block from the second memory; and the write module 205 is configured to write the plurality of to-be-processed image data into a first preset address block of the second memory.

[0153] In some examples, the sixth data path further comprises the fourth selector 209.

[0154] Illustratively, the second read module 202 transmits the plurality of to-be-processed image data to the fourth selector 209; and the fourth selector 209 transmits the plurality of to-be-processed image data to the write module 205.

[0155] For example, when the value of the second register is 1, the eighth input end of the fourth selector 209 is turned on.

[0156] For example, the second read module 202 transmits the plurality of to-be-processed image data to the eighth input end of the fourth selector 209; and the output end of the fourth selector 209 transmits the plurality of to-be-processed image data to the write module 205.

[0157] It should be noted that the image data processing apparatus provided in the above embodiments is only taken as an example for the segmentation of the above functional modules when performing the corresponding steps, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is segmented into different functional modules to complete all or part of the above-described functions.

[0158] Embodiments of the present application configure multiple data paths through the first reading module, the second reading module, the address module, the first bit width conversion module, the second bit width conversion module, and the plurality of selectors, so that the first reading module and the second reading module do not need to share one data path, thereby ensuring that the data bit width of each data path is maximized, improving the data bit width of the second reading module and the address module, thereby improving the output efficiency of the second reading module and the address module, and further improving the output efficiency of the device; and multiple operation modes can be performed through the multiple data paths, thereby being suitable for multiple scenarios and expanding the scope of application. In addition, embodiments of the present application, through multiplexing data paths and multiple modules, not only integrate multiple functions, but also reduce the hardware area.

[0159] Figure 7 is a flowchart of an image data processing method according to an embodiment of the present application. In combination with Figure 7 The image data processing method will be described in detail. The method includes steps S701 to S705:

[0160] In step S701, in a first operation mode, an address block is read from a first memory.

[0161] The first operation mode indicates that the address block is stored in the first memory or the second memory, and the image data to be processed is stored in the second memory; the data bit width of the second memory is greater than that of the first memory.

[0162] In step S702, the address block is divided to obtain multiple addresses.

[0163] In step S703, based on each address and a preset reading parameter, an absolute address corresponding to each address is generated.

[0164] In step S704, the image data to be processed of each absolute address is read from the second memory.

[0165] In step S705, the multiple image data to be processed are written into a first preset address block of the second memory.

[0166] In some embodiments, the address module includes an aggregation module and a dispersion module; the aggregation module and the dispersion module do not operate at the same time.

[0167] The aggregation module is configured to generate an absolute address corresponding to each address based on each address and preset reading parameters.

[0168] In some embodiments, the first reading module is further configured to read the address block from the first memory.

[0169] The first bit width conversion module is further configured to divide the address block to obtain a plurality of addresses.

[0170] The dispersion module is further configured to generate an absolute address corresponding to each address based on each address and preset writing parameters.

[0171] The second reading module is further configured to read a plurality of to-be-processed image data of a second preset address block from the second memory.

[0172] The writing module is further configured to write each to-be-processed image data into a corresponding absolute address in the second memory.

[0173] In some embodiments, the first data path further comprises a first selector.

[0174] The second data path further comprises a second selector, a third selector and a fourth selector.

[0175] The first reading module is further configured to transmit the address block to the first selector.

[0176] The first selector is configured to transmit the address block to the first bit width conversion module.

[0177] The second reading module is further configured to transmit the to-be-processed image data to the second selector.

[0178] The second selector is configured to transmit the to-be-processed image data to the aggregation module.

[0179] The aggregation module is further configured to transmit the to-be-processed image data to the third selector.

[0180] The third selector is configured to transmit the to-be-processed image data to the fourth selector.

[0181] The fourth selector is configured to transmit the to-be-processed image data to the writing module.

[0182] In some embodiments, the system further comprises a third data path and a fourth data path.

[0183] The third data path comprises the second reading module, the first bit width conversion module and the aggregation module.

[0184] The fourth data path comprises the first reading module, the second bit width conversion module, the aggregation module and the writing module.

[0185] The second reading module is further configured to read the address block from the second memory in the second operation mode, wherein the second operation mode indicates that the address block is stored in the second memory and the image data to be processed is stored in the first memory.

[0186] The first bit width conversion module is configured to divide the address block to obtain a plurality of addresses.

[0187] The aggregation module is configured to generate an absolute address corresponding to each address based on each address and a preset reading parameter.

[0188] The first reading module is configured to read the image data to be processed of each absolute address from the first memory.

[0189] The second bit width conversion module is configured to combine the plurality of image data to be processed to obtain combined image data.

[0190] The writing module is configured to write the combined image data into the first preset address block of the second memory.

[0191] In some embodiments, the third data path further includes a first selector.

[0192] The fourth data path further includes a second selector, a third selector and a fourth selector.

[0193] The second reading module is further configured to transmit the address block to the first selector.

[0194] The first selector is further configured to transmit the address block to the first bit width conversion module.

[0195] The second bit width conversion module is further configured to transmit the combined image data to the second selector.

[0196] The second selector is further configured to transmit the combined image data to the aggregation module.

[0197] The aggregation module is further configured to transmit the combined image data to the third selector.

[0198] The third selector is further configured to transmit the combined image data to the fourth selector.

[0199] The fourth selector is further configured to transmit the combined image data to the writing module.

[0200] In some embodiments, the fifth data path further includes a fifth selector.

[0201] The fifth data path includes the first reading module, the second bit width conversion module and the writing module.

[0202] The first reading module is configured to read the plurality of to-be-processed image data of the second preset address block from the first memory in a third operation mode, and the third operation mode indicates that the to-be-processed image data is stored in the first memory or the second memory.

[0203] The second bit width conversion module is configured to combine the plurality of to-be-processed image data to obtain combined image data.

[0204] The writing module is configured to write the combined image data into the first preset address block of the second memory.

[0205] In some embodiments, the fifth data path further includes a third selector and a fourth selector.

[0206] The second bit width conversion module is further configured to transmit the combined image data to the third selector.

[0207] The third selector is further configured to transmit the combined image data to the fourth selector.

[0208] The fourth selector is further configured to transmit the combined image data to the writing module.

[0209] In some embodiments, the sixth data path further includes a fourth selector.

[0210] The sixth data path includes the second reading module and the writing module.

[0211] The second reading module is configured to read the plurality of to-be-processed image data of the second preset address block from the second memory in a fourth operation mode, and the fourth operation mode indicates that the to-be-processed image data is stored in the second memory.

[0212] The writing module is configured to write the plurality of to-be-processed image data into the first preset address block of the second memory.

[0213] In some embodiments, the sixth data path further includes a fourth selector.

[0214] The second reading module is further configured to transmit the plurality of to-be-processed image data to the fourth selector.

[0215] The fourth selector is further configured to transmit the plurality of to-be-processed image data to the writing module.

[0216] In some embodiments, the first memory is a DDR, and the second memory is an OCM.

[0217] In addition, the image data processing device and the image data processing method provided by the above-mentioned embodiments belong to the same concept, and the specific implementation process is detailed in the device embodiments, which will not be described here.

[0218] Embodiments of the present application, the first reading module reads an address block from the first memory in the first running mode; the data bit width of the second memory is greater than the data bit width of the first memory; the first bit width conversion module divides the address block to obtain a plurality of addresses; the address module generates an absolute address corresponding to each address based on each address and a preset reading parameter; the second reading module reads the to-be-processed image data of each absolute address from the second memory; and the writing module writes the plurality of to-be-processed image data into the first preset address block of the second memory. In the above technical solution, the first reading module and the second reading module do not need to share one data path, which maximizes the data bit width of the second data path, improves the data bit width of the second reading module and the address module, and thus improves the output efficiency of the second reading module and the address module, and further improves the output efficiency of the device.

[0219] Embodiments of the present application also provide a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0220] For example, taking a computer device as a terminal, Figure 8 is a structural schematic diagram of a terminal provided by an embodiment of the present application, referring to Figure 8 The terminal 800 can be a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a notebook computer or a desktop computer. The terminal 800 can also be referred to as a user equipment, a portable terminal, a laptop terminal, a desktop terminal or other names.

[0221] Generally, the terminal 800 includes a processor 801 and a memory 802.

[0222] The processor 801 can include one or more processing cores, such as a 4-core processor, a 5-core processor, and the like. The processor 801 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 801 can also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a CPU (Central Processing Unit), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor 801 can be integrated with a GPU (Graphics Processing Unit) for rendering and drawing content required to be displayed by the display screen. In some embodiments, the processor 801 can further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

[0223] The memory 802 can include one or more computer-readable storage media that can be non-transitory. The memory 802 can also include a high-speed random access memory, and a nonvolatile memory such as one or more disk storage devices, flash storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 802 is used to store at least one program code for being executed by the processor 801 to implement the processes performed by the terminal in the above-described methods according to the method embodiments of the present application.

[0224] In some embodiments, the terminal 800 can also optionally include a peripheral device interface 803 and at least one peripheral device. The processor 801, the memory 802, and the peripheral device interface 803 can be connected through a bus or a signal line. Each peripheral device can be connected to the peripheral device interface 803 through a bus, a signal line, or a circuit board. Specifically, the peripheral device includes at least one of a display screen 804, a camera assembly 805, an audio circuit 806, and a power supply 807.

[0225] The peripheral interface 803 can be used to connect at least one I / O (Input / Output) related peripheral device to the processor 801 and the memory 802. In some embodiments, the processor 801, the memory 802 and the peripheral interface 803 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 801, the memory 802 and the peripheral interface 803 can be implemented on a separate chip or circuit board, and the embodiments of the present application do not limit this.

[0226] The display screen 804 is used to display a UI (User Interface). The UI can include graphics, text, icons, videos and any combination thereof. When the display screen 804 is a touch display screen, the display screen 804 also has the ability to collect touch signals on or above the surface of the display screen 804. The touch signals can be input as control signals to the processor 801 for processing. At this time, the display screen 804 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 804 can be one, arranged on the front panel of the terminal 800; in some other embodiments, the display screen 804 can be at least two, arranged on different surfaces of the terminal 800 or in a folding design; in some other embodiments, the display screen 804 can be a flexible display screen, arranged on a curved surface or a folding surface of the terminal 800. Even, the display screen 804 can also be arranged in an irregular shape other than a rectangle, that is, a special-shaped screen. The display screen 804 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0227] The camera assembly 805 is used to collect images or videos. In some embodiments, the camera assembly 805 includes a front camera and a rear camera. Generally, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, the rear camera is at least two, which are any one of a main camera, a depth-of-field camera, a wide-angle camera and a long-focus camera, to realize the background blur function of the main camera and the depth-of-field camera, the panoramic shooting and VR (Virtual Reality) shooting function of the main camera and the wide-angle camera, or other fusion shooting functions. In some embodiments, the camera assembly 805 can also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. The dual-color temperature flash is a combination of a warm light flash and a cold light flash, which can be used for light compensation under different color temperatures.

[0228] The audio circuit 806 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals which are then input to the processor 801 for processing. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal 800. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert the electrical signals from the processor 801 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 806 may also include a headphone jack.

[0229] Power supply 807 is used to power the various components in terminal 800. Power supply 807 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 807 includes a rechargeable battery, the rechargeable battery can support wired or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0230] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on terminal 800 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0231] Taking computer equipment as a server as an example, Figure 9 This is a schematic diagram of a server structure provided in an embodiment of this application. The server 900 can vary significantly due to different configurations or performance. It may include one or more processors 901 (Central Processing Units, CPUs) and one or more memories 902. The one or more memories 902 store at least one computer program, which is loaded and executed by the one or more processors 901 to implement the aforementioned image data processing method. Of course, the server 900 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server 900 may also include other components for implementing device functions, which will not be elaborated upon here.

[0232] The embodiments of the present application further provide a computer readable storage medium including a stored computer program, wherein the computer readable storage medium controls a device where the computer readable storage medium is located to perform the method as above when the computer program is running. Optionally, the computer readable storage medium can be a Read-Only Memory (ROM), a Random Access Memory (RAM), a Compact-Disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0233] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by a program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium, and the storage medium mentioned above can be a Read-Only Memory, a magnetic disk or an optical disk, etc.

[0234] The above only describes optional embodiments of the present application, and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An image data processing apparatus characterized by comprising: include: First data path and second data path; The first data path includes a first read module, a first bit width conversion module, and an address module; The second data path includes a second read module, the address module, and a write module; The first read module is used to read an address block from a first memory in a first operating mode; the first operating mode indicates that the address block is stored in the first memory or the second memory, and the image data to be processed is stored in the second memory; The data bit width of the second memory is greater than that of the first memory; The first bit-width conversion module is used to segment the address block to obtain multiple addresses; The address module is used to generate an absolute address corresponding to each address based on each address and a preset read parameter; The second read module is used to read the image data to be processed from each of the absolute addresses in the second memory; The write module is used to write multiple images to be processed into a first preset address block of the second memory; The address module includes an aggregation module; The first data path also includes a first selector; The second data path also includes a second selector, a third selector, and a fourth selector; The first read module is also used to transmit the address block to the first selector; The first selector is used to transmit the address block to the first bit-width conversion module; The second reading module is also used to transmit the image data to be processed to the second selector; The second selector is used to transmit the image data to be processed to the aggregation module; The aggregation module is also used to transmit the image data to be processed to the third selector; The third selector is used to transmit the image data to be processed to the fourth selector; The fourth selector is used to transmit the image data to be processed to the write module.

2. The apparatus of claim 1, wherein, The address module further includes a distribution module; the aggregation module and the distribution module do not operate simultaneously. The aggregation module is used to generate the absolute address corresponding to each address based on each address and the preset read parameters.

3. The apparatus of claim 2, wherein, The first read module is also used to read an address block from the first memory; The first bit-width conversion module is also used to segment the address block to obtain multiple addresses; The distributed module is also used to generate an absolute address corresponding to each address based on each address and a preset write parameter; The second read module is further configured to read multiple image data to be processed from the second memory at a second preset address block; The write module is further configured to write each of the image data to be processed to the corresponding absolute address in the second memory.

4. The apparatus of claim 2, wherein, The device further includes a third data path and a fourth data path; The third data path includes the second read module, the first bit-width conversion module, and the aggregation module; The fourth data path includes the first read module, the second bit-width conversion module, the aggregation module, and the write module; The second reading module is further configured to read the address block from the second memory in a second operation mode. The second operation mode indicates that the address block is stored in the second memory, and the image data to be processed is stored in the first memory. The first bit width conversion module is configured to divide the address block to obtain a plurality of addresses. The aggregation module is configured to generate the absolute address corresponding to each address based on each address and the preset reading parameter. The first reading module is configured to read the image data to be processed of each absolute address from the first memory. The second bit width conversion module is configured to combine a plurality of the image data to be processed to obtain combined image data. The writing module is configured to write the combined image data into a first preset address block of the second memory.

5. The apparatus of claim 4, wherein, The third data path further comprises the first selector. The fourth data path further comprises the second selector, the third selector, and the fourth selector. The second reading module is further configured to transmit the address block to the first selector. The first selector is further configured to transmit the address block to the first bit width conversion module. The second bit width conversion module is further configured to transmit the combined image data to the second selector. The second selector is further configured to transmit the combined image data to the aggregation module. The aggregation module is further configured to transmit the combined image data to the third selector. The third selector is further configured to transmit the combined image data to the fourth selector. The fourth selector is further configured to transmit the combined image data to the writing module.

6. The apparatus of claim 1, wherein, The device further comprises a fifth data path. The fifth data path comprises the first reading module, the second bit width conversion module, and the writing module. The first reading module is configured to read a plurality of the image data to be processed of a second preset address block from the first memory in a third operation mode. The third operation mode indicates that the image data to be processed is stored in the first memory or the second memory. The second bit width conversion module is configured to combine a plurality of the image data to be processed to obtain combined image data. The writing module is configured to write the combined image data into the first preset address block of the second memory.

7. The apparatus of claim 6, wherein, The fifth data path further comprises a third selector and a fourth selector. The second bit width conversion module is further configured to transmit the combined image data to the third selector. The third selector is further configured to transmit the combined image data to the fourth selector. The fourth selector is further configured to transmit the combined image data to the writing module.

8. The apparatus of claim 1, wherein, The device further comprises a sixth data path. The sixth data path comprises the second reading module and the writing module. The second reading module is configured to read a plurality of the image data to be processed of a second preset address block from the second memory in a fourth operation mode. The fourth operation mode indicates that the image data to be processed is stored in the second memory. The writing module is configured to write the plurality of to-be-processed image data into the first preset address block of the second memory.

9. The apparatus of claim 8, wherein, The sixth data path further comprises a fourth selector. The second reading module is further configured to transmit the plurality of to-be-processed image data to the fourth selector. The fourth selector is further configured to transmit the plurality of to-be-processed image data to the writing module.

10. The apparatus of any one of claims 1 to 9, wherein, The first memory is a DDR, and the second memory is an OCM.

11. An image data processing method, characterized by, Comprise: In the first operation mode, read an address block from the first memory; The first operation mode indicates that the address block is stored in the first memory or the second memory, and the to-be-processed image data is stored in the second memory; The data bit width of the second memory is greater than the data bit width of the first memory; Divide the address block to obtain a plurality of addresses; Generate an absolute address corresponding to each address based on each address and a preset reading parameter; Read the to-be-processed image data of each absolute address from the second memory; Write the plurality of to-be-processed image data into the first preset address block of the second memory; Further comprise: Transmit the address block to a first selector; Transmit the address block to a first bit width conversion module; Transmit the to-be-processed image data to a second selector; Transmit the to-be-processed image data to an aggregation module; Transmit the to-be-processed image data to a third selector; Transmit the to-be-processed image data to a fourth selector; Transmit the to-be-processed image data to a writing module.

12. A computer device, comprising: The computer device comprises a processor and a memory, and the memory is configured to store at least one program, and the at least one program is loaded and executed by the processor to implement the image data processing method in claim 11.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the image data processing method in claim 11.

Images