Integrated circuit packaging structure and electronic equipment

Abstract

The invention discloses an integrated circuit packaging structure and electronic equipment, and relates to the technical field of integrated circuits. The integrated circuit packaging structure comprises a lead frame, a low-voltage side chip and a high-voltage side chip, the lead frame is provided with a first side and comprises a first base island, a second base island, a first pin, a second pin and a third pin which are isolated from one another, the second pin is connected with the first base island, the first pin is arranged on the side, close to the first base island, of the second pin, and the third pin is arranged on the side, close to the second base island, of the second pin. The third pin is arranged on one side, close to the second base island, of the second pin and is isolated from the second base island; the low-voltage side chip is packaged on the first base island; the high-voltage side chip is packaged on the second base island. According to the integrated circuit packaging structure provided by the invention, the purpose of placing two groups of independent chips in the same packaging structure is achieved, an aluminum gasket does not need to be used as a connecting bridge of the two chips, the cost is reduced, the process deviation risk is reduced, and the overall packaging yield is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an integrated circuit packaging structure and electronic device. Background Technology

[0002] In surface mount technology (SMT) packages for medium-power transistors or MOSFETs, the package frame typically employs a single-island design. In existing technologies, to achieve a cascaded structure, GaN power chips are integrated into the single-island package of the power transistor or MOSFET. Due to the limited voltage withstand capability of the insulating adhesive used to encapsulate the chip within the single-island frame, aluminum pads are typically used as intermediate connection structures to connect the vertical power transistors to lead out the lower electrode. The upper surface of the aluminum pad is aluminum, and the lower surface is a high-voltage insulating layer of aluminum oxide. The low-voltage vertical power transistor is attached to the upper surface of the aluminum pad using conductive adhesive, and the aluminum pad is attached to the single-island frame using insulating adhesive. Other low-voltage main control chips are directly attached to the single-island frame using insulating adhesive. This structure not only requires additional aluminum pad material procurement, increasing production costs, but also involves multiple die attach and adhesive application processes, extending the production cycle, increasing the risk of process deviations, and ultimately leading to a decrease in overall package yield. Summary of the Invention

[0003] In view of this, this application provides an integrated circuit packaging structure and an electronic device, with the aim of solving one of the technical problems in the prior art.

[0004] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides an integrated circuit packaging structure, comprising: A lead frame has a first side, the lead frame includes a first base island and a second base island that are isolated from each other, the lead frame also includes a first pin, a second pin and a third pin that are isolated from each other, the first pin, the second pin and the third pin are all disposed on the first side, the second pin is connected to the first base island, the first pin is disposed on the side of the second pin close to the first base island and is isolated from the first base island, and the third pin is disposed on the side of the second pin close to the second base island and is isolated from the second base island; The low-voltage side chip is packaged in the first base island; The high-voltage side chip is packaged in the second base island.

[0005] In an optional embodiment, the first base island includes a first main base island and a first extended base island, the first extended base island being formed by extending outward from the side of the first main base island near the first side, and the first extended base island protruding from the first side. The second pin is electrically connected to the first extended base island.

[0006] In an optional embodiment, the second base island includes a second main base island and a second extended base island, and the lead frame further includes a second side, wherein the first side and the second side are arranged perpendicularly. The second main base island and the first main base island are spaced apart in a direction parallel to the first side, and the second extended base island extends outward from the side of the second main base island near the second side.

[0007] In an optional embodiment, on the first side, the first main base island and the second main base island are spaced apart, and the edges of the first main base island and the edges of the second main base island are flush. On the second side, the first main base island and the second extended base island are spaced apart, and the edges of the first main base island and the second extended base island are flush.

[0008] In an optional implementation, the first pin is a gate pin and the third pin is a source pin; The second pin is either the drain pin or the F pin.

[0009] In an optional implementation, when the second pin is an F pin, the lead frame further includes a fourth pin, which is electrically connected to the back side of the second main base island or the second extended base island.

[0010] In an optional implementation, the area of ​​the first extended base island is S. 11 The area of ​​the first main island is S 12 Satisfying: S 11 ≤S 12 .

[0011] In an optional implementation, the area of ​​the second extended base island is S. 21 The area of ​​the second main island is S. 22 The area of ​​the second base island is S 21 +S 22 Satisfying: S 12 ≤S 21 +S 22 .

[0012] In an optional implementation, the low-voltage side chip includes a MOSFET, and the high-voltage side chip includes a depletion-mode GaN power device.

[0013] In an optional embodiment, the gate and source of the MOSFET are located on the upper surface, and the drain is located on the lower surface; The gate of the MOSFET is electrically connected to the first pin via wire bonding; the source of the MOSFET is electrically connected to the third pin via wire bonding; and the drain of the MOSFET is electrically connected to the first main base island. In an optional embodiment, the source, drain, and gate of the GaN power device are all located on the upper surface. The source of the depletion-type GaN power device is connected to the first main base island via wire bonding; the drain of the depletion-type GaN power device is connected to the second main base island via wire bonding; and the gate of the depletion-type GaN power device is connected to the third pin via wire bonding.

[0014] In an optional implementation, the low-voltage side chip is a synchronous rectifier chip, and the high-voltage side chip is an enhancement-mode GaN power device or a MOSFET.

[0015] In an optional implementation, the low-voltage side chip is a MOSFET and a diode, and the high-voltage side chip is a depletion-mode GaN.

[0016] In an optional embodiment, the integrated circuit packaging structure further includes a housing, in which the lead frame, the high-voltage side chip, and the low-voltage side chip are all packaged.

[0017] Secondly, this application provides an electronic device, including a circuit board and an integrated circuit packaging structure as described in any of the foregoing embodiments, wherein a plurality of pads are distributed on the circuit board, and the integrated circuit packaging structure is connected to the pads through a conductive material.

[0018] Compared to existing technologies, the advantages of this application are as follows: This application proposes an integrated circuit packaging structure, including a lead frame, a low-voltage side chip, and a high-voltage side chip. The lead frame has a first side, and the lead frame includes a first base island and a second base island that are isolated from each other. The lead frame also includes a first pin, a second pin, and a third pin that are isolated from each other. The first pin, the second pin, and the third pin are all located on the first side. The second pin is connected to the first base island. The first pin is located on the side of the second pin closest to the first base island and is isolated from the first base island. The third pin is located on the side of the second pin closest to the second base island and is isolated from the second base island. By centrally arranging the first pin, the second pin, and the third pin on the first side of the lead frame body, unified operation of the pins is achieved, improving packaging efficiency and consistency. In addition, the centralized pin layout facilitates the alignment and contact of test probes, improving testing efficiency and yield.

[0019] Furthermore, the low-voltage side chip is packaged on the first base island, and the high-voltage side chip is packaged on the second base island. This achieves the goal of placing two independent chips within the same package structure, eliminating the need for aluminum pads as a connection bridge between the two chips, reducing costs, eliminating multiple die attach and adhesive application processes, shortening the production cycle, reducing the risk of process deviations, and improving the overall package yield. Simultaneously, packaging the two independent chips on different base islands also utilizes the electrical isolation characteristics of the first and second base islands, which is beneficial for high and low voltage separation and reduces signal interference. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This paper shows one of the structural schematic diagrams of the integrated circuit packaging structure in some embodiments of this application; Figure 2 This paper shows one of the structural schematic diagrams of the lead frame in some embodiments of this application; Figure 3 This is shown as a second schematic diagram of the lead frame structure in some embodiments of this application; Figure 4 This is shown as a second schematic diagram of the integrated circuit packaging structure in some embodiments of this application; Figure 5 The third schematic diagram of the integrated circuit packaging structure in some embodiments of this application is shown.

[0022] Key component symbols: 100 - Integrated circuit package structure; 110 - Lead frame; 120 - Low-voltage side chip; 130 - High-voltage side chip; 111 - Lead frame body; 112 - Heat dissipation pad; 1111 - First side; 1112 - Second side; 1113 - First base island; 11131 - First main base island; 11132 - First extended base island; 1114 - Second base island; 11141 - Second main base island; 11142 - Second extended base island; 113 - First pin; 114 - Second pin; 115 - Third pin. Detailed Implementation

[0023] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0024] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0027] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0028] In the prior art, in order to achieve the cascaded structure, GaN power chips are integrated into a single-island frame package of power transistors or MOSFETs.

[0029] For example, in a power transistor, the emitter and base are located on the upper surface of the transistor, while the collector is located on the lower surface. In a MOSFET, the source and gate are located on the upper surface, while the drain is located on the lower surface. For vertically oriented power transistors, because one electrode is on the lower surface, conductive adhesive is needed to connect the back of the transistor to the base island surface for electrical connection and heat dissipation. D-mode GaN transistors, due to their negative turn-on voltage (Vth -20~-16V), are difficult to control directly, thus requiring an additional low-voltage MOSFET in a cascaded structure. This necessitates integrating two or more chips within a single package.

[0030] Because the insulating adhesive used to encapsulate chips within a single-island frame has limited voltage withstand capability, aluminum pads are typically used as intermediate connection structures to connect vertical power transistors to the lower electrode. The upper surface of the aluminum pad is aluminum, and the lower surface is a high-voltage insulating layer of aluminum oxide. Low-voltage vertical power transistors are attached to the upper surface of the aluminum pad using conductive adhesive. The aluminum pad is then attached to the single-island frame using insulating adhesive. Other low-voltage main control chips are directly attached to the single-island frame using insulating adhesive. This structure not only requires additional aluminum pad material procurement, increasing production costs, but also involves multiple die attach and adhesive application processes, extending the production cycle, increasing the risk of process deviations, and ultimately leading to a decrease in overall packaging yield.

[0031] In response to the above problems, such as Figure 1 As shown, an embodiment of this application provides an integrated circuit packaging structure 100, including a lead frame 110, a low-voltage side chip 120, and a high-voltage side chip 130.

[0032] The lead frame 110 is made of metal sheet (usually copper alloy) and is stamped to provide chip connection and heat dissipation path.

[0033] The lead frame 110 has a first side 1111. For example... Figure 1 The lead frame 110 includes a lead frame body 111 encapsulated in a housing and a heat dissipation pad 112 exposed in the housing. The first side 1111 is the side away from the lead frame body 111 and away from the heat dissipation pad 112.

[0034] It should be noted that power devices (such as MOSFETs and ICs) are packaged in lead frame 110 and generate a lot of heat when operating. The heat dissipation pad 112, as the exposed part of lead frame 110, can be directly soldered to the copper foil of PCB and dissipated through PCB.

[0035] In addition, the exposed heat dissipation pad 112 can further improve its heat dissipation capacity by installing additional heat sinks or metal casings.

[0036] In some embodiments, notches are made at the edges of the heat dissipation pad 112 or through holes are made in the center of the heat dissipation pad 112 to reduce pad deformation. Making holes in the center of the heat dissipation pad 112 also allows for mounting with external heat sinks.

[0037] The lead frame body 111 includes a first base island 1113 and a second base island 1114 that are isolated from each other. It should be noted that mutual isolation refers to electrical isolation between the first base island 1113 and the second base island 1114. In this embodiment, the electrical isolation between the first base island 1113 and the second base island 1114 is achieved by spaced-apart metal plates on the first base island 1113 and the second base island 1114.

[0038] The lead frame 110 also includes a first pin 113, a second pin 114, and a third pin 115 that are isolated from each other. It should be noted that the mutual isolation refers to the electrical isolation between the first pin 113, the second pin 114, and the third pin 115.

[0039] The first pin 113, the second pin 114, and the third pin 115 are all located on the first side 1111. For example... Figure 1 As shown, the lead frame body 111 is generally rectangular, with the first side 1111 being the lower long side of the rectangle. The long side of the lead frame body 111 has sufficient length to allow the first pin 113, the second pin 114, and the third pin 115 to be spaced apart, forming electrical isolation.

[0040] Such pin mounting distribution and sufficiently large spacing help to stagger the high-voltage, high-current traces involving power switching transistors and the low-voltage signal traces involving controller pins on the PCB, thus avoiding interference from high-voltage, high-current switching signals on the controller's detection feedback signals.

[0041] In addition, a sufficiently large spacing helps to increase the area of ​​the first pin 113, the second pin 114 and the third pin 115, thereby improving the heat dissipation performance of the lead frame 110.

[0042] In some embodiments, the second pin 114 is connected to the first base island 1113, increasing the mechanical strength of the first base island 1113, providing a low-impedance current path using the metal substrate (typically copper) of the lead frame body 111, reducing the use of bonding wires, simplifying the manufacturing process, reducing the parasitic resistance of the bonding wires, and reducing the Joule heating effect of the bonding wires under high current.

[0043] In some embodiments, the first pin 113 is located on the side of the second pin 114 near the first base island 1113 and is isolated from the first base island 1113. The third pin 115 is located on the side of the second pin 114 near the second base island 1114 and is isolated from the second base island 1114. By centrally arranging the first pin 113, the second pin 114, and the third pin 115 on the first side 1111 of the lead frame body 111, unified pin operation is achieved, improving packaging efficiency and consistency. Furthermore, the centralized pin layout facilitates the alignment and contact of test probes, improving testing efficiency and yield.

[0044] In some embodiments, the low-voltage side chip 120 is packaged on the first base island 1113 and the high-voltage side chip 130 is packaged on the second base island 1114, achieving the purpose of placing two independent chips in the same package structure. This eliminates the need to use aluminum pads as a connection bridge between the two chips, reducing costs. It also eliminates the need for multiple die attach and adhesive application processes, shortening the production cycle, reducing the risk of process deviations, and improving the overall packaging yield.

[0045] Furthermore, packaging two independent chips on different base islands can utilize the electrical isolation characteristics of the first base island 1113 and the second base island 1114, which is beneficial for high and low voltage separation and reduces signal interference. In one embodiment, the first base island 1113 includes a first main base island 11131 and a first extended base island 11132. The first extended base island 11132 extends outward from the side of the first main base island 11131 near the first side 1111, and the first extended base island 11132 protrudes from the first side 1111.

[0046] The first extended base island 11132 is mainly used for connection of the second pin 114. It is formed by stamping a metal sheet to reduce the use of bonding wires. Setting the first extended base island 11132 can increase the heat dissipation area of ​​the chip. When the low-voltage side chip 120 includes high-power devices, good heat dissipation can extend the life of the devices and maintain their stable performance. By setting the first extended base island 11132, a larger conductive path is obtained to support higher current, thereby improving the overall current carrying capacity of the lead frame body 111.

[0047] In the SMT (Surface Mount Technology) process, the first extended base island 11132 provides solder joints, enhancing solder strength and reliability.

[0048] GaN is a planar structure device, which is divided into two types: enhancement-mode (E-mode) and depletion-mode (D-mode). The turn-on threshold of E-mode GaN is a positive voltage (Vth 1V~2V), which is lower than that of traditional MOS (Vth 3~4V). Because of the low turn-on voltage, it is difficult to be compatible with traditional MOS drive and is prone to accidental turn-on, resulting in low reliability and difficulty in market promotion. Therefore, D-mode GaN is currently the mainstream in the market.

[0049] It should be noted that when the high-voltage side chip 130 or the low-voltage side chip 120 includes a depletion-mode GaN power device, the switching speed of the depletion-mode GaN power device is usually determined by the internally integrated drive circuit. In traditional packaging structures, the depletion-mode GaN power device is encapsulated inside the housing, resulting in the switching speed not being externally adjustable and poor EMC.

[0050] In response to the above problems, such as Figure 1 As shown, in this embodiment, the second pin 114 is electrically connected to the first extended base island 11132, and the second pin 114 is the F (Filter or Frequency Adjustment) pin. Thus, by setting the first pin 113 or the third pin 115 as the S pin of the lead frame body 111, the F pin and the S (Source) pin of the lead frame body 111 form a controllable parallel path. An external capacitor (or variable capacitor) is connected in parallel between the F pin and the S pin. By changing the Cgs (capacitance formed between the gate and source) of the depletion-mode GaN power device, the switching speed is adjusted, thereby achieving the purpose of adjusting the switching speed of the GaN power device.

[0051] By adjusting the capacitor value, the di / dt and dv / dt during the switching process can be controlled, thereby reducing high-frequency EMI noise and meeting EMC standards.

[0052] In addition, the F and S pins are packaged together, which simplifies the external circuitry and improves regulation efficiency.

[0053] For example, when the depletion-type GaN power device is disposed on the first base island 1113, the source of the depletion-type GaN power device is connected to the second pin 114, and the F pin is electrically connected to the first base island 1113 through wire bonding.

[0054] The integrated circuit package structure 100 of this application realizes EMC regulation through the package F pin, without the need to set up additional complex peripheral circuits. By changing or adjusting the capacitor value, it can adapt to the EMC test standards or working environment of the low-voltage side chip 120 and the high-voltage side chip 130, thereby reducing costs.

[0055] like Figure 1 The lead frame body 111 also includes a second side 1112, with the first side 1111 and the second side 1112 arranged perpendicularly. It should be noted that the second side 1112 is the shorter side of the rectangular lead frame body 111; for example, the second side 1112 is... Figure 1 The left short side in the middle.

[0056] In these embodiments, the second base island 1114 includes a second main base island 11141 and a second extended base island 11142. The second main base island 11141 and the first main base island 11131 are spaced apart along a direction parallel to the first side 1111. The second extended base island 11142 extends outward from the side of the second main base island 11141 near the second side 1112.

[0057] like Figure 1 As shown, the second extended base island 11142 is roughly rectangular. The edges of the second main base island 11141 and the second extended base island 11142 away from the first side 1111 are connected to the heat dissipation pad 112. The edge of the second extended base island 11142 away from the second side 1112 is connected to the second main base island 11141. The second main base island 11141 and the second extended base island 11142 are continuous structures.

[0058] In one embodiment, the second base island 1114 has a figure-7 shape, with the first main base island 11131 partially surrounding it. In other words, the first main base island 11131 is one corner of the rectangular lead frame body 111, and the remaining part is the second base island 1114. This structure reduces the processing difficulty of the first base island 1113 and the second base island 1114 in the lead frame body 111, thereby reducing costs.

[0059] The second main base island 11141 may or may not have chips arranged on it. Correspondingly, the second extended base island 11142 may or may not have chips arranged on it. The high-voltage side chip 130 may be partially disposed on the second extended base island 11142 and partially disposed on the second main base island 11141; or, all of the high-voltage side chip 130 may be disposed on the second extended base island 11142; or, all of the high-voltage side chip 130 may be disposed on the second main base island 11141.

[0060] Some or all of the base islands in the second main base island 11141 and the second extended base island 11142 can be used to arrange chips of special size or chips that require specific placement positions.

[0061] like Figure 1 As shown, the first main base island 11131 and the second main base island 11141 are spaced apart by 0.5-3mm, and the first main base island 11131 and the second extended base island 11142 are spaced apart by 0.5-3mm.

[0062] It should be noted that there are no restrictions on the shape of the first main base island 11131, the second extended base island 11142, and the second main base island 11141. For example, the shape of the first main base island 11131, the second extended base island 11142, and the second main base island 11141 can be a square, a rectangle, an L-shape, a T-shape, or other irregular shapes.

[0063] like Figure 2 As shown, in other embodiments, the second extended base island 11142 and the second main base island 11141 are not continuous structures, and there is electrical isolation between the second extended base island 11142 and the second main base island 11141, which is equivalent to the lead frame body 111 being split into three independent base islands. The second extended base island 11142 and the first main base island 11131 are spaced apart, and the spacing is 2-3 mm.

[0064] It should be noted that the shapes of the separate first main base island 11131, second extended base island 11142, and second main base island 11141 are not limited. For example, the shapes of the first main base island 11131, second extended base island 11142, and second main base island 11141 can be square, rectangle, L-shaped, T-shaped, or other irregular shapes.

[0065] In one embodiment, such as Figure 2 As shown, the second extended base island 11142 is connected to the second pin 114, and the first main base island 11131 and the second pin 114 are independent of each other.

[0066] In one embodiment, the first main base island 11131 and the second pin 114 are connected, and the second extended base island 11142 is independent of the second pin 114.

[0067] In some embodiments, on the first side 1111, a first main base island 11131 and a second main base island 11141 are spaced apart, and the edges of the first main base island 11131 and the edges of the second main base island 11141 are flush; and on the second side 1112, a first main base island 11131 and a second extended base island 11142 are spaced apart, and the edges of the first main base island 11131 and the edges of the second extended base island 11142 are flush. Figure 1 As shown, both the first side 1111 and the second side 1112 have the boundaries of the first base island 1113 and the second base island 1114. It can be understood that a 0.3-0.5mm bonding area is reserved around the first base island 1113 and the second base island 1114. By setting the boundaries of the first base island 1113 and the second base island 1114 to be aligned, it is convenient to plan and process the bonding area.

[0068] It should be noted that the areas of the first main base island 11131, the second extended base island 11142, and the third extended base island can be set according to the specific situation of the chip. For example, high-power chips or chips with high heat dissipation requirements (such as MOSFETs) can be packaged in base islands with larger areas.

[0069] In some embodiments, such as Figure 1 As shown, the area of ​​the first extended base island 11132 is S. 11 The area of ​​the first main island 11131 is S. 12Satisfying: S 11 ≤S 12 By setting a larger area for the first main base island 11131, higher support is provided for the low-voltage side chip 120, thereby improving the stability of the packaging structure of the first base island 1113 and the low-voltage side chip 120.

[0070] See also Figure 1 and Figure 3 As shown, Figure 1 When the second extended base island 11142 is connected to the second main base island 11141, and no chip is configured on the second extended base island 11142, the second extended base island 11142 is reduced in size, and the reduced area is compensated to the first main base island 11131 or the second main base island 11141, thereby expanding the area of ​​the second main base island 11141 or the first main base island 11131. Figure 3 .

[0071] In some embodiments, such as Figure 1 and Figure 2 As shown, the area of ​​the second extended base island 11142 is set to S. 21 The area of ​​the second main island, 11141, is S. 22 The area of ​​the second base island 1114 is S 21 +S 22 Satisfying: S 12 <S 21 +S 22 .

[0072] In one embodiment, such as Figure 3 As shown, when the area of ​​the second extended base island 11142 is 0, the areas of the first main base island 11131 and the second main base island 11141 are close, and the first main base island 11131 and the second main base island 11141 are set at intervals on the left and right.

[0073] In some embodiments, the lead frame 110 further includes a fourth pin (not shown).

[0074] The heat sink 112 is electrically connected to the lead frame body 111. The heat sink 112 is used for internal electrical connections (such as a common drain structure). The fourth pin is electrically connected to the heat sink 112.

[0075] The fourth pin connects to the heatsink pad 112, simplifying external wiring. Simultaneously, the heatsink pad 112, acting as a drain pin, can directly connect to a large copper area on the PCB, reducing wire resistance and parasitic inductance, making it suitable for high-frequency / high-current applications (such as switching power supplies).

[0076] like Figure 1As shown, the heat dissipation pad 112 is connected to the second extended base island 11142 and the second main base island 11141. Correspondingly, the fourth pin is electrically connected to the back of the second main base island 11141 or the second extended base island 11142.

[0077] like Figure 2 The three base islands are set independently, and the fourth pin is connected to the back of the second main base island 11141.

[0078] like Figure 3 When the first main base island 11131 and the second main base island 11141 are set apart from each other, the second main base island 11141 is connected to the heat dissipation pad 112, the first main base island 11131 and the second main base island 11141 are electrically isolated, and the fourth pin is connected to the back of the second main base island 11141.

[0079] like Figure 1 , Figure 2 and Figure 3 As shown, when the fourth pin is the drain pin, the first pin 113 is the gate pin, and the third pin 115 is the source pin, short metal pins are connected externally to the first pin 113 and the third pin 115, and no external metal pin is connected to the second pin 114, so that the integrated circuit package structure 100 of this application is configured as a TO-252 type package structure.

[0080] like Figure 1 , Figure 2 and Figure 3 As shown, when the switching speed of GaN power devices needs to be adjusted, an F pin for EMC can be connected at the second pin 114, so that the integrated circuit package structure 100 of this application is configured as a TO-252 type package structure with EMC adjustment pin.

[0081] like Figure 1 , Figure 2 and Figure 3 As shown, in one embodiment, the first pin 113 is set as the gate pin, the second pin 114 is set as the drain pin, and the second pin 114 is electrically connected to the heat sink 112. The third pin 115 is set as the source pin. External metal pins are connected to the first pin 113, the second pin 114 and the third pin 115, so that the integrated circuit package structure 100 of this application is configured as a TO-251 type package structure.

[0082] like Figure 1 , Figure 2 and Figure 3As shown, in one embodiment, the first pin 113 is set as the gate pin, the second pin 114 is set as the drain pin, and the second pin 114 is electrically connected to the heat sink 112. The third pin 115 is set as the source pin. Both the first pin 113 and the third pin 115 are connected to external long metal pins. When the second pin 114 is not connected to external metal pins, the integrated circuit package structure 100 of this application is configured as a TO-263 type package structure.

[0083] In one embodiment, such as Figure 1 As shown, a low-voltage MOSFET is disposed on the first main base island 11131 in the first base island 1113, and a depletion-mode GaN power device is disposed on the second main base island 11141 in the second base island 1114. The low-voltage MOSFET is encapsulated on the first main base island 11131 with conductive adhesive, and the depletion-mode GaN is bonded to the second main base island 11141 with insulating adhesive.

[0084] In one embodiment, such as Figure 4 As shown, a low-voltage MOSFET is arranged on the first main base island 11131, a Schottky diode is arranged on the second extended base island 11142, and a depletion-mode GaN is arranged on the second main base island 11141. The MOSFET is attached to the first main base island 11131 with conductive adhesive, the depletion-mode GaN is attached to the second main base island 11141 with insulating adhesive, and the diode is attached to the second extended base island 11142 with conductive adhesive.

[0085] In one embodiment, such as Figure 5 As shown, a synchronous rectifier IC is arranged on the first main base island 11131, and an enhancement-mode GaN or MOSFET is arranged on the second main base island 11141. The synchronous rectifier chip is attached to the first main base island 11131 with insulating adhesive, and the enhancement-mode GaN is attached to the second main base island 11141 with insulating adhesive, or the MOSFET is attached to the second main base island 11141 with conductive adhesive.

[0086] In one embodiment, when the integrated circuit package structure 100 is configured as a TO-252 / TO-251 / TO-263 package structure, the bonding method between the low-voltage side chip 120 and the high-voltage side chip 130 and the lead frame body 111 is as follows: like Figure 1 As shown, the low-voltage side chip 120 includes a low-voltage MOS, and the high-voltage side chip 130 includes a depletion-mode GaN. The gate and source of the low-voltage MOS are located on the upper surface, and the drain is located on the lower surface.

[0087] The gate of the low-voltage MOSFET is electrically connected to the first pin 113 via wire bonding; the source of the low-voltage MOSFET is electrically connected to the third pin 115 via wire bonding; and the drain of the low-voltage MOSFET is electrically connected to the first main base island 11131 via conductive adhesive.

[0088] The source, drain, and gate of the depletion-type GaN are all located on the upper surface of the second semiconductor chip.

[0089] The source of the depletion-type GaN is connected to the first main base island 11131 by wire bonding; the drain of the depletion-type GaN is connected to the second main base island 11141 by wire bonding; and the gate of the depletion-type GaN is connected to the third pin 115 by wire bonding.

[0090] In one embodiment, such as Figure 4 As shown, when the integrated circuit package structure 100 is configured as a TO-251 / TO-252 / TO-263 package structure, the bonding method between the low-voltage side chip 120 and the high-voltage side chip 130 and the lead frame body 111 is as follows: The low-voltage side chip 120 includes a low-voltage MOS and a diode, while the high-voltage side chip 130 includes a depletion-mode GaN.

[0091] In a MOSFET, the gate and source are located on the upper surface, and the drain is located on the lower surface; in a diode, the anode is located on the upper surface, and the cathode is located on the lower surface; in a depletion-mode GaN power device, the source, drain, and gate are all located on the upper surface. The gate of the MOSFET is electrically connected to the first pin 113 via wire bonding; the source of the MOSFET is electrically connected to the third pin 115 via wire bonding; and the drain of the MOSFET is electrically connected to the first main base island 11131 via conductive adhesive.

[0092] The source of the depletion-type GaN power device is connected to the first main base island 11131 by wire bonding; the drain of the depletion-type GaN power device is connected to the second main base island 11141 by wire bonding; and the gate of the depletion-type GaN power device is connected to the third pin 115 by wire bonding.

[0093] The positive terminal of the diode is connected to the first main base island 11131 by wire bonding, and the negative terminal is electrically connected to the third main base island by conductive adhesive.

[0094] In one embodiment, such as Figure 5 As shown, when the integrated circuit package structure 100 is configured as a TO-251 / TO-252 / TO-263 package structure, the bonding method between the low-voltage side chip 120 and the high-voltage side chip 130 and the lead frame body 111 is as follows: The low-voltage side chip 120 includes a synchronous rectifier chip, and the high-voltage side chip 130 includes an enhancement GaN or MOSFET.

[0095] In a MOSFET, the gate and source are located on the upper surface, and the drain is located on the lower surface; in an enhancement-mode power device, the source, drain, and gate are all located on the upper surface.

[0096] When the high-voltage side chip 130 is an enhancement-mode GaN, the source, drain, and gate of the enhancement-mode GaN power device are all located on the upper surface. The source of the enhancement-mode GaN power device is electrically connected to the third pin 115 via wire bonding; the drain of the enhancement-mode GaN power device is connected to the second main base island 11141 via wire bonding; and the gate of the enhancement-mode GaN power device is connected to the synchronous rectifier chip Gate via wire bonding.

[0097] When the high-voltage side chip 130 is a MOSFET, the source and gate of the MOSFET power device are located on the upper surface, and the drain is located on the lower surface. The source of the MOSFET power device is electrically connected to the third pin 115 via wire bonding; the drain of the MOSFET power device is electrically connected to the second main base island 11141 via conductive adhesive; and the gate of the MOSFET power device is connected to the gate of the synchronous rectifier chip via wire bonding.

[0098] The synchronous rectifier chip is bonded to the surface of the first main base island 11131 using insulating adhesive. The synchronous rectifier chip has four bonding pads: VDD (power supply pin), GND (ground pin), Gate (gate), and SW (switch node pin). VDD is electrically connected to the first pin 113 via wire bonding, GND is electrically connected to the third pin 115 via wire bonding, Gate is electrically connected to the gate of the enhancement-mode GaN or MOSFET via wire bonding, and SW is electrically connected to the first main base island 11131 via wire bonding.

[0099] In some embodiments, the integrated circuit package structure 100 further includes a housing, in which the lead frame body 111, the high-voltage side chip 130, and the low-voltage side chip 120 are all encapsulated. When the heat dissipation pad 112 is electrically connected to the lead frame body 111, the housing is made of plastic; when the heat dissipation pad 112 is electrically isolated from the lead frame body 111, the housing is made of plastic or metal.

[0100] This application provides an electronic device, including a circuit board and an integrated circuit package structure 100 according to any of the foregoing embodiments. The circuit board has a plurality of pads distributed on it, and the integrated circuit package structure 100 is connected to the pads through a conductive material.

[0101] In some embodiments, when the integrated circuit package structure 100 is configured as a TO-252 or TO-263 package, multiple pads are spaced apart and are respectively positioned corresponding to the heat dissipation pad 112, the first pin 113 and the third pin 115.

[0102] When the integrated circuit package structure 100 is configured as a TO-251 package, multiple pads are spaced apart and are respectively positioned to correspond to the positions of the heat dissipation pad 112, the first pin 113, the second pin 114 and the third pin 115.

[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0104] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An integrated circuit packaging structure, characterized in that, include: A lead frame (110) has a first side (1111). The lead frame (110) includes a first base island (1113) and a second base island (1114) that are isolated from each other. The lead frame (110) also includes a first pin (113), a second pin (114) and a third pin (115) that are isolated from each other. The first pin (113), the second pin (114) and the third pin (115) are all located on the first side (1111). The second pin (114) is connected to the first base island (1113). The first pin (113) is located on the side of the second pin (114) close to the first base island (1113) and is isolated from the first base island (1113). The third pin (115) is located on the side of the second pin (114) close to the second base island (1114) and is isolated from the second base island (1114). The low-voltage side chip (120) is packaged in the first base island (1113). The high-voltage side chip (130) is packaged in the second base island (1114).

2. The integrated circuit packaging structure according to claim 1, characterized in that, The first base island (1113) includes a first main base island (11131) and a first extended base island (11132). The first extended base island extends outward from the side of the first main base island (11131) near the first side (1111), and the first extended base island (11132) protrudes from the first side (1111). The second pin (114) is electrically connected to the first extended base island (11132).

3. The integrated circuit packaging structure according to claim 2, characterized in that, The second base island (1114) includes a second main base island (11141) and a second extended base island (11142), and the lead frame (110) also includes a second side (1112), with the first side (1111) and the second side (1112) being arranged vertically; The second main base island (11141) and the first main base island (11131) are spaced apart in a direction parallel to the first side (1111), and the second extended base island (11142) extends outward from the side of the second main base island (11141) near the second side (1112).

4. The integrated circuit packaging structure according to claim 3, characterized in that, On the first side (1111), the first main base island (11131) and the second main base island (11141) are spaced apart, and the edge of the first main base island (11131) is flush with the edge of the second main base island (11141); On the second side (1112), the first main base island (11131) and the second extended base island (11142) are spaced apart, and the edge of the first main base island (11131) is flush with the edge of the second extended base island (11142).

5. The integrated circuit packaging structure according to claim 3 or 4, characterized in that, The first pin (113) is the gate pin, and the third pin (115) is the source pin; The second pin (114) is either the drain pin or the F pin.

6. The integrated circuit packaging structure according to claim 5, characterized in that, When the second pin (114) is an F pin, the lead frame (110) also includes a fourth pin, which is electrically connected to the back side of the second main base island (11141) or the second extended base island (11142).

7. The integrated circuit packaging structure according to claim 3 or 4, characterized in that, The area of ​​the first extended base island (11132) is S 11 The area of ​​the first main island (11131) is S. 12 Satisfying: S 11 ≤S 12 .

8. The integrated circuit packaging structure according to claim 7, characterized in that, The area of ​​the second extended base island (11142) is S 21 The area of ​​the second main island (11141) is S. 22 The area of ​​the second base island (1114) is S 21 +S 22 Satisfying: S 12 ≤S 21 +S 22 .

9. The integrated circuit packaging structure according to claim 3 or 4, characterized in that, The low-voltage side chip (120) is a MOSFET, and the high-voltage side chip (130) is a depletion-mode GaN power device.

10. The integrated circuit packaging structure according to claim 9, characterized in that, The gate and source of the MOSFET are located on the upper surface, and the drain is located on the lower surface; The gate of the MOSFET is electrically connected to the first pin (113) via wire bonding; the source of the MOSFET is electrically connected to the third pin (115) via wire bonding; and the drain of the MOSFET is electrically connected to the first main base island (11131).

11. The integrated circuit packaging structure according to claim 10, characterized in that, The source, drain, and gate of the depletion-type GaN power device are all located on the upper surface; The source of the depletion-type GaN power device is connected to the first main base island (11131) by wire bonding; the drain of the depletion-type GaN power device is connected to the second main base island (11141) by wire bonding; and the gate of the depletion-type GaN power device is connected to the third pin (115) by wire bonding.

12. The integrated circuit packaging structure according to claim 3 or 4, characterized in that, The low-voltage side chip (120) is a synchronous rectifier chip, and the high-voltage side chip (130) is an enhanced GaN power device or a MOSFET.

13. The integrated circuit packaging structure according to claim 3 or 4, characterized in that, The low-voltage side chip (120) is a MOSFET and a diode, and the high-voltage side chip (130) is a depletion-mode GaN power device.

14. The integrated circuit packaging structure according to any one of claims 2 to 4, characterized in that, The integrated circuit packaging structure (100) also includes a housing, in which the lead frame (110), the high-voltage side chip (130) and the low-voltage side chip (120) are all encapsulated.

15. An electronic device, characterized in that, The device includes a circuit board and an integrated circuit package structure (100) according to any one of claims 1 to 14, wherein a plurality of pads are distributed on the circuit board, and the integrated circuit package structure (100) is connected to the pads by a conductive material.

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