Semiconductor structure, manufacturing method thereof and semiconductor device

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a semiconductor device. The semiconductor structure comprises a first tube core, a connecting structure and a second tube core which are stacked along a first direction, wherein two sides, which are oppositely arranged along the first direction, of the connecting structure are respectively in bonding connection with the first tube core and the second tube core; the connection structure includes: a base layer; the conductive structure is positioned in the substrate layer and extends along a first direction, the conductive structure comprises a first end part and a second end part which are oppositely arranged along the first direction, the first end part is coupled with the first tube core, and the second end part is coupled with the second tube core; wherein in the first direction, the thickness of the connecting structure is smaller than the thickness of the first tube core and / or the second tube core.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor structure, its manufacturing method, and a semiconductor device. Background Technology

[0002] To improve the integration of semiconductor devices, multiple dies can be stacked vertically within the same package structure. This expands the one-dimensional semiconductor device layout into a three-dimensional layout, thereby significantly increasing the integration of semiconductor devices.

[0003] However, current semiconductor devices still require further improvement. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a semiconductor device.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: a first die stacked along a first direction, a connection structure, and a second die, wherein two sides of the connection structure disposed opposite to each other along the first direction are respectively bonded to the first die and the second die; the connection structure comprises: a substrate layer; a conductive structure located in the substrate layer and extending along the first direction, the conductive structure comprising a first end and a second end disposed opposite to each other along the first direction, the first end being coupled to the first die, and the second end being coupled to the second die; wherein, along the first direction, the thickness of the connection structure is less than the thickness of the first die and / or the second die.

[0006] In some embodiments, along the first direction, the ratio between the thickness of the connecting structure and the thickness of the first die ranges from 1 / 2 to 1 / 4; and / or, the ratio between the thickness of the connecting structure and the thickness of the second die ranges from 1 / 2 to 1 / 4.

[0007] In some embodiments, along a plane perpendicular to the first direction, the projected area of ​​the connection structure is greater than the projected area of ​​the first die and / or the second die.

[0008] In some embodiments, the semiconductor structure further includes: a first dielectric layer located on the side of the first die opposite to the connection structure; the projected area of ​​the first dielectric layer being larger than the projected area of ​​the first die along a plane perpendicular to the first direction; and / or, a second dielectric layer located on the side of the second die opposite to the connection structure; the projected area of ​​the second dielectric layer being larger than the projected area of ​​the second die along a plane perpendicular to the first direction.

[0009] In some embodiments, the semiconductor structure further includes: a first filling layer located on at least one side of the first die along a second direction, wherein the two sides of the first filling layer disposed opposite to each other along the first direction are in contact with the first dielectric layer and the connection structure, respectively; and / or, a second filling layer located on at least one side of the second die along the second direction, wherein the two sides of the second filling layer disposed opposite to each other along the first direction are in contact with the second dielectric layer and the connection structure, respectively; wherein the first direction and the second direction intersect.

[0010] In some embodiments, the coefficient of thermal expansion of the first dielectric layer is greater than that of the first filler layer, and the coefficient of thermal expansion of the second dielectric layer is greater than that of the second filler layer.

[0011] In some embodiments, the first die includes a first device layer; the second die includes a second device layer; wherein the first device layer and the second device layer are respectively disposed on two sides of the connection structure that are disposed opposite to each other along the first direction.

[0012] In some embodiments, the connection structure further includes: a first insulating layer located between the base layer and the first die; a first pad located in the first insulating layer, the first end being coupled to the first die via the first pad; a second insulating layer located between the base layer and the second die; and a second pad located in the second insulating layer, the second end being coupled to the second die via the second pad.

[0013] In some embodiments, the connection structure and the first die are connected by hybrid bonding, and the connection structure and the second die are connected by hybrid bonding.

[0014] Secondly, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a plurality of semiconductor structures as described above stacked along a first direction; wherein, two adjacent semiconductor structures along the first direction are connected by hybrid bonding, or two adjacent semiconductor structures along the first direction are connected by bump bonding.

[0015] Thirdly, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: providing an initial interconnect structure, the initial interconnect structure comprising: a wafer layer; a conductive structure located in the wafer layer and extending along a first direction, the conductive structure comprising a first end and a second end disposed opposite to each other along the first direction; bonding a plurality of first dies to the initial interconnect structure, the first end being coupled to the first die; processing the initial interconnect structure to form an interconnect structure; bonding a plurality of second dies to the interconnect structure, the second end being coupled to the second die; wherein, along the first direction, the thickness of the interconnect structure is less than the thickness of the first die and / or the second die.

[0016] In some embodiments, the method further includes: filling a dielectric material between two adjacent first dies along a second direction to form a first filling layer, wherein the surface of the first die facing away from the initial connection structure is flush with the surface of the first filling layer; forming a first dielectric layer covering the first dies and the first filling layer, wherein the two sides of the first filling layer disposed opposite to each other along the first direction are in contact with the first dielectric layer and the initial connection structure, respectively; wherein the first direction and the second direction intersect.

[0017] In some embodiments, the initial connection structure further includes: a first insulating layer located between the wafer layer and the first die; a first pad located in the first insulating layer, the first end being coupled to the first die via the first pad; the processing of the initial connection structure to form a connection structure includes: performing a thinning process on the surface of the wafer layer opposite to the first die to form an initial base layer; forming a second insulating layer covering the initial base layer; forming a second pad in the second insulating layer, the second end being coupled to the second die via the second pad.

[0018] In some embodiments, the method further includes: filling a dielectric material between two adjacent second dies along the second direction to form a second filling layer, wherein the surface of the second die facing away from the connecting structure is flush with the surface of the second filling layer; forming a second dielectric layer covering the second dies and the second filling layer, wherein the two sides of the second filling layer disposed opposite to each other along the first direction are in contact with the second dielectric layer and the connecting structure, respectively.

[0019] In some embodiments, the method further includes: performing a dicing process along the first direction on the first dielectric layer, the first filling layer, the first insulating layer, the initial substrate layer, the second insulating layer, the second filling layer, and the second dielectric layer to form a semiconductor structure.

[0020] This disclosure provides a semiconductor structure, a method for manufacturing the same, and a semiconductor device. In this embodiment, two sides of a connection structure disposed opposite to each other along a first direction are respectively bonded to a first die and a second die, and the thickness of the connection structure is less than the thickness of the first die and / or the second die. Thus, by stacking the first die and the second die along the first direction using the connection structure, the thickness of the semiconductor structure along the first direction can be reduced, and the integration density of the semiconductor structure can be improved. Attached Figure Description

[0021] Figure 1 This is a cross-sectional structural schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0022] Figure 2 A schematic cross-sectional view of a semiconductor device provided in some embodiments of this disclosure;

[0023] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure;

[0024] Figures 4 to 24 This is a cross-sectional structural diagram of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Detailed Implementation

[0025] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0026] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0027] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0032] Before introducing the embodiments of this disclosure, the various directions that may be involved in the following text are defined. The stacking direction of multiple dies is defined as the first direction (i.e., the Z direction), which can also be called the vertical direction. Any direction in the plane perpendicular to the first direction is defined as the second direction (i.e., the X direction), which can also be called the horizontal direction. The following description will use the X direction and the Z direction as examples.

[0033] In some examples, a three-dimensional semiconductor device layout can be achieved by wafer-on-wafer (WOW) stacking, which can then be diced to form a semiconductor structure.

[0034] In other examples, a three-dimensional semiconductor device layout can be achieved through chip-on-wafer (COW) stacking, which can then be diced to form a semiconductor structure.

[0035] However, the following problems still exist in the current WOW and COW processes.

[0036] Firstly, the thickness of the donor die is limited by the capabilities of the equipment. When the donor die thickness is small, die chipping and increased die warpage may occur during the die clamping process. Die chipping refers to the phenomenon of breakage or chipping at the edge or corner of the die during the wafer dicing process. Die warpage refers to the bending or twisting caused by thermal stress or uneven material shrinkage during die manufacturing. For example, comparing dies with thicknesses of 40μm and 130μm, clamping a 40μm thick die may lead to die chipping, and the die warpage of a 40μm thick die is greater than that of a 130μm thick die. Furthermore, the number of air bubbles in a 40μm thick die is also greater than that in a 130μm thick die.

[0037] Secondly, the bonding effect of the die with a thickness of 130μm is better than that of the die with a thickness of 40μm.

[0038] Thirdly, the multiple dies stacked vertically need to meet the bonding overlay (Bonding OVL) accuracy, for example, less than 0.5 μm. After wafer stacking, a cube dicing process is performed. The dicing area includes both metal and dielectric materials, making the dicing process more difficult.

[0039] Fourthly, the dimensions of structures such as solder balls and molded underfill (MUF) in semiconductor devices severely restrict their performance.

[0040] In view of this, in order to solve at least one of the above-mentioned technical problems, this disclosure provides a semiconductor structure, a method for manufacturing the same, and a semiconductor device.

[0041] refer to Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments of this disclosure. For example... Figure 1 As shown, in a first aspect, embodiments of this disclosure provide a semiconductor structure 100, comprising: a first die 102 stacked along the Z direction, a connection structure 134, and a second die 118, wherein the two sides of the connection structure 134 disposed opposite each other along the Z direction are respectively bonded to the first die 102 and the second die 118; the connection structure 134 comprises: a first substrate layer 136; and a first conductive structure 138 located in the first substrate layer 136 and extending along the Z direction, the first conductive structure 138 comprising a first end 140 and a second end 142 disposed opposite each other along the Z direction, the first end 140 being coupled to the first die 102, and the second end 142 being coupled to the second die 118; wherein, along the Z direction, the thickness of the connection structure 134 is less than the thickness of the first die 102 and / or the second die 118. To illustrate the connection structure 134 more clearly, Figure 1 The thickness of the connecting structure 134 is appropriately increased.

[0042] In this embodiment of the present disclosure, the two sides of the connection structure 134, which are arranged opposite each other along the Z direction, are respectively bonded to the first die 102 and the second die 118, and the thickness of the connection structure 134 is less than the thickness of the first die 102 and / or the second die 118. In this way, by stacking the first die 102 and the second die 118 along the Z direction through the connection structure 134, the thickness of the semiconductor structure 100 along the Z direction can be reduced, and the integration density of the semiconductor structure 100 can be improved.

[0043] In some embodiments, the connection structure 134 further includes: a first insulating layer 144 located between a first base layer 136 and a first die 102; a first pad 146 located in the first insulating layer 144, with a first end 140 coupled to the first die 102 via the first pad 146; a second insulating layer 148 located between the first base layer 136 and a second die 118; and a second pad 150 located in the second insulating layer 148, with a second end 142 coupled to the second die 118 via the second pad 150. Here, the first pad 146 and the second pad 150 can be used as bonding pads in a hybrid bonding connection, and can also be referred to as a hybrid bond large pad (HLP).

[0044] It should be noted that the term "coupled" in this document refers to the operative connection between multiple conductive elements, including but not limited to the following: In the first case, two conductive elements are directly connected, for example, the first conductive structure 138 and the first pad 146 are coupled, that is, the first conductive structure 138 and the first pad 146 are electrically connected; In the second case, two conductive elements are indirectly connected, for example, the first end 140 and the first die 102 are coupled, that is, the first end 140 is electrically connected to the first die 102 through the first pad 146; the second end 142 and the second die 118 are coupled, that is, the second end 142 is electrically connected to the second die 118 through the second pad 150.

[0045] In some embodiments, the first conductive structure 138 may extend along the Z direction and the surface of the first end 140 may be substantially flush with the surface of the first base layer 136; the first pad 146 may extend along the Z direction and penetrate the first insulating layer 144. That is, the contact interface between the first end 140 and the first pad 146 is substantially flush with the contact interface between the first base layer 136 and the first insulating layer 144.

[0046] It should be noted that the term "basically flush" in this article refers to the height difference of multiple film surfaces along the Z direction being 0 or the height difference meeting the process error range requirements.

[0047] In some embodiments, the first conductive structure 138 may extend along the Z-direction and the surface of the second end 142 may be substantially flush with the surface of the first base layer 136; the second pad 150 may extend along the Z-direction and penetrate the second insulating layer 148. That is, the contact interface between the second end 142 and the second pad 150 is substantially flush with the contact interface between the first base layer 136 and the second insulating layer 148. Here, the surfaces of the first end 140 and the first base layer 136 that are relatively close to the first insulating layer 144 are substantially flush, and the surfaces of the second end 142 and the first base layer 136 that are relatively close to the second insulating layer 148 are substantially flush, i.e., the first conductive structure 138 may extend along the Z-direction and penetrate the first base layer 136.

[0048] In other embodiments, the first conductive structure 138 may extend along the Z-direction and the surface of the second end 142 may be located within the first base layer 136. The second pad 150 may extend along the Z-direction, penetrating the second insulating layer 148 and extending into the first base layer 136. That is, the contact interface between the second end 142 and the second pad 150 is located within the first base layer 136. Thus, even if a backside thinning process is performed on the first wafer layer to form the initial first base layer, the initial first base layer does not expose the second end 142. In other words, the first conductive structure 138 is not removed by grinding during the backside thinning process, thus avoiding metal contamination caused by the removal of part of the first conductive structure 138 by grinding. Figure 1 This case will be used as an example for illustration.

[0049] In some embodiments, the connection structure 134 further includes: a dummy first pad located in the first insulating layer 144; and a dummy second pad located in the second insulating layer 148. Here, the dummy first pad can be formed in the same process as the first pad 146, the difference being that the dummy first pad is not coupled to the first end 140 of the first conductive structure 138; the dummy second pad can be formed in the same process as the second pad 150, the difference being that the dummy second pad is not coupled to the second end 142 of the first conductive structure 138. Here, the dummy first pad can be used to balance the stress during the formation of the first pad 146, and the dummy second pad can be used to balance the stress during the formation of the second pad 150.

[0050] In some embodiments, other elements may also be formed in the first substrate layer 136, the first insulating layer 144, and the second insulating layer 148. For example, redistribution layers (RDLs) and decoupling elements, such as inductors, resistors, or capacitors. In this way, the vacant space in the first substrate layer 136, the first insulating layer 144, and the second insulating layer 148 can be fully utilized, improving the performance of the semiconductor structure 100 without increasing its thickness.

[0051] Here, the first substrate layer 136 may include a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, or silicon-germanium substrates, etc.

[0052] Here, the first insulating layer 144 and the second insulating layer 148 may include a single insulating layer or multiple sub-insulating layers. Figure 1 The illustration shows that both the first insulating layer 144 and the second insulating layer 148 include four sub-insulating layers for illustrative purposes. The first insulating layer 144 and the second insulating layer 148 may be, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0053] Here, the first conductive structure 138, the first pad 146, and the second pad 150 may include conductive materials, including but not limited to tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), metal silicides, or any combination thereof.

[0054] In some embodiments, along the Z direction, the ratio between the thickness of the connecting structure 134 and the thickness of the first die 102 ranges from 1 / 2 to 1 / 4; and / or, the ratio between the thickness of the connecting structure 134 and the thickness of the second die 118 ranges from 1 / 2 to 1 / 4.

[0055] Here, since the connection structure 134 serves to couple the first die 102 and the second die 118, and no other device structures similar to those in the first die 102 or the second die 118 are disposed in the connection structure 134, the thickness of the connection structure 134 is less than the thickness of the first die 102 and / or the second die 118. Thus, by stacking the first die 102 and the second die 118 along the Z-direction using the connection structure 134, the thickness of the package structure along the Z-direction can be reduced.

[0056] In some specific embodiments, the thickness of the connection structure 134 may be, for example, 20 μm, and the thickness of the first die 102 and the second die 118 may be, for example, 40 μm.

[0057] In some embodiments, along a plane perpendicular to the Z direction, the projected area of ​​the connecting structure 134 is greater than the projected area of ​​the first die 102 and / or the second die 118.

[0058] Here, the cross-sectional area of ​​the connecting structure 134 perpendicular to the Z-direction is greater than the cross-sectional area of ​​the first core 102 perpendicular to the Z-direction. In other words, the cross-sectional area of ​​the connecting structure 134 perpendicular to the Z-direction is greater than the contact area between the first core 102 and the connecting structure 134. Similarly, the cross-sectional area of ​​the connecting structure 134 perpendicular to the Z-direction is greater than the cross-sectional area of ​​the second core 118 perpendicular to the Z-direction. This means that the cross-sectional area of ​​the connecting structure 134 perpendicular to the Z-direction is greater than the contact area between the second core 118 and the connecting structure 134.

[0059] In some embodiments, the semiconductor structure 100 further includes: a first dielectric layer 112 located on the side of the first die 102 opposite to the connection structure 134; the projected area of ​​the first dielectric layer 112 is larger than the projected area of ​​the first die 102 along a plane perpendicular to the Z direction; and / or, a second dielectric layer 128 located on the side of the second die 118 opposite to the connection structure 134; the projected area of ​​the second dielectric layer 128 is larger than the projected area of ​​the second die 118 along a plane perpendicular to the Z direction.

[0060] Here, the cross-sectional area of ​​the first dielectric layer 112 perpendicular to the Z-direction is greater than the cross-sectional area of ​​the first die 102 perpendicular to the Z-direction. In other words, the cross-sectional area of ​​the first dielectric layer 112 perpendicular to the Z-direction is greater than the contact area between the first die 102 and the first dielectric layer 112. Similarly, the cross-sectional area of ​​the second dielectric layer 128 perpendicular to the Z-direction is greater than the cross-sectional area of ​​the second die 118 perpendicular to the Z-direction. In other words, the cross-sectional area of ​​the second dielectric layer 128 perpendicular to the Z-direction is greater than the contact area between the second die 118 and the second dielectric layer 128.

[0061] Here, the first dielectric layer 112 and the second dielectric layer 128 may include a single dielectric layer or multiple sub-dielectric layers. Figure 1 The diagram illustrates that both the first dielectric layer 112 and the second dielectric layer 128 include four sub-dielectric layers for illustrative purposes. The first dielectric layer 112 and the second dielectric layer 128 may be, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0062] In some embodiments, the semiconductor structure 100 further includes: a first filling layer 116 located on at least one side of the first die 102 along the X direction, the two sides of the first filling layer 116 disposed opposite to each other along the Z direction being in contact with the first dielectric layer 112 and the connection structure 134 (more specifically, the first insulating layer 144 in the connection structure 134); and / or, a second filling layer 132 located on at least one side of the second die 118 along the X direction, the two sides of the second filling layer 132 disposed opposite to each other along the Z direction being in contact with the second dielectric layer 128 and the connection structure 134 (more specifically, the second insulating layer 148 in the connection structure 134). Figure 1 The following example illustrates the situation with the first filling layer 116 located on both sides of the first core 102 along the X direction and the second filling layer 132 located on both sides of the second core 118 along the X direction.

[0063] Here, because the cross-sectional areas of the first insulating layer 144 and the first dielectric layer 112 are both larger than the cross-sectional area of ​​the first die 102, the first filler layer 116 and the first die 102 are both located between the first insulating layer 144 and the first dielectric layer 112, and are adjacent to each other along the X direction. Similarly, because the cross-sectional areas of the second insulating layer 148 and the second dielectric layer 128 are both larger than the cross-sectional area of ​​the second die 118, the second filler layer 132 and the second die 118 are both located between the second insulating layer 148 and the second dielectric layer 128, and are adjacent to each other along the X direction. During the dicing process, both the first filler layer 116 and the second filler layer 132 are diced to form the semiconductor structure 100. Thus, retaining a portion of the first filler layer 116 and the second filler layer 132 in the dicing area avoids damage to the first die 102 and the second die 118 during the dicing process.

[0064] In some embodiments, the first filling layer 116 and the second filling layer 132 may include a dielectric material, including but not limited to silicon oxide.

[0065] In some embodiments, the coefficient of thermal expansion of the first dielectric layer 112 is greater than that of the first filler layer 116, and the coefficient of thermal expansion of the second dielectric layer 128 is greater than that of the second filler layer 132.

[0066] Here, the coefficient of thermal expansion of the first dielectric layer 112 is greater than that of the first filler layer 116. This is beneficial in mitigating the deformation of the first dielectric layer 112 caused by thermal expansion of the first filler layer 116 during the manufacturing process of the semiconductor structure 100. Similarly, the coefficient of thermal expansion of the second dielectric layer 128 is greater than that of the second filler layer 132. This is also beneficial in mitigating the deformation of the second dielectric layer 128 caused by thermal expansion of the second filler layer 132 during the manufacturing process of the semiconductor structure 100.

[0067] In some embodiments, the first die 102 includes a first device layer 108; the second die 118 includes a second device layer 124; wherein the first device layer 108 and the second device layer 124 are respectively disposed on opposite sides of the connection structure 134 along the Z direction.

[0068] In some embodiments, the first die 102 includes: a second substrate layer 104, a first device layer 108, and a first bonding layer 110 stacked along the Z direction; and a second conductive structure 106 located in the second substrate layer 104 and extending along the Z direction. The first device layer 108 may include: a plurality of first conductive layers; a first conductive contact located between two adjacent first conductive layers along the Z direction; and a third dielectric layer for isolating the first conductive layers and the first conductive contact.

[0069] In some embodiments, the second die 118 includes: a third substrate layer 120, a second device layer 124, and a second bonding layer 126 stacked along the Z direction; and a third conductive structure 122 located in the third substrate layer 120 and extending along the Z direction. The second device layer 124 may include: a plurality of second conductive layers; a second conductive contact located between two adjacent second conductive layers along the Z direction; and a fourth dielectric layer for isolating the second conductive layers and the second conductive contact.

[0070] Here, the materials of the second substrate 104 and the third substrate 120 can be referenced from the material of the first substrate 136, and will not be described again here.

[0071] In some embodiments, the semiconductor structure 100 further includes a third pad 114 located in the first dielectric layer 112. Here, the second conductive structure 106 includes a third end and a fourth end disposed opposite to each other along the Z direction, the third end being coupled to the first device layer 108, and more specifically, the third end being coupled to the first conductive layer in the first device layer 108, and the fourth end being coupled to the third pad 114.

[0072] In some embodiments, the second conductive structure 106 may extend along the Z direction and the surface of the fourth end is substantially flush with the surface of the second base layer 104, that is, the second conductive structure 106 penetrates the second base layer 104; the third pad 114 may extend along the Z direction and penetrate the first dielectric layer 112. In other words, the contact interface between the fourth end and the third pad 114 is substantially flush with the contact interface between the second base layer 104 and the first dielectric layer 112.

[0073] In other embodiments, the second conductive structure 106 may extend along the Z-direction and its fourth end surface may be located within the second base layer 104. The third pad 114 may extend along the Z-direction, penetrating the first dielectric layer 112 and extending into the second base layer 104. That is, the contact interface between the fourth end and the third pad 114 is located within the second base layer 104. Thus, even if a backside thinning process is performed on the initial second base layer, the fourth end is not exposed. In other words, the second conductive structure 106 is not removed by grinding during the backside thinning process, avoiding metal contamination caused by the removal of part of the second conductive structure 106. Figure 1 This case will be used as an example for illustration.

[0074] In some embodiments, the semiconductor structure 100 further includes a fourth pad 130 located in the second dielectric layer 128. Here, the third conductive structure 122 includes a fifth end and a sixth end disposed opposite to each other along the Z direction, the fifth end being coupled to the second device layer 124, and more specifically, the fifth end being coupled to the second conductive layer in the second device layer 124, and the sixth end being coupled to the fourth pad 130.

[0075] In some embodiments, the third conductive structure 122 may extend along the Z direction and the sixth end surface may be substantially flush with the surface of the third base layer 120, that is, the third conductive structure 122 penetrates the third base layer 120; the fourth pad 130 may extend along the Z direction and penetrate the second dielectric layer 128. In other words, the contact interface between the sixth end and the fourth pad 130 is substantially flush with the contact interface between the third base layer 120 and the second dielectric layer 128.

[0076] In other embodiments, the third conductive structure 122 may extend along the Z-direction and the sixth end surface may be located within the third base layer 120, and the fourth pad 130 may extend along the Z-direction, penetrating the second dielectric layer 128 and extending into the third base layer 120. That is, the contact interface between the sixth end and the fourth pad 130 is located within the third base layer 120. Thus, even if a backside thinning process is performed on the initial third base layer, the sixth end is not exposed. In other words, the third conductive structure 122 is not removed by grinding during the backside thinning process, thus avoiding metal contamination caused by the partial removal of the third conductive structure 122. Figure 1 This case will be used as an example for illustration.

[0077] In some embodiments, the semiconductor structure 100 further includes: a dummy third pad located in the first dielectric layer 112; and a dummy fourth pad located in the second dielectric layer 128. Here, the dummy third pad can be formed in the same process as the third pad 114, the difference being that the dummy third pad is not coupled to the fourth end of the second conductive structure 106; the dummy fourth pad can be formed in the same process as the fourth pad 130, the difference being that the dummy fourth pad is not coupled to the sixth end of the third conductive structure 122. Here, the dummy third pad can be used to balance the stress during the formation of the third pad 114, and the dummy fourth pad can be used to balance the stress during the formation of the fourth pad 130.

[0078] In some embodiments, the connection structure 134 and the first die 102 are connected by hybrid bonding (HB), and the connection structure 134 and the second die 118 are connected by hybrid bonding.

[0079] In some embodiments, the first bonding layer 110 includes a fifth dielectric layer and first bonding contacts located in the fifth dielectric layer; wherein the fifth dielectric layer is used to isolate the first bonding contacts from each other. The first bonding contacts are bonded to a first pad 146 to form a metal-metal bond, and the fifth dielectric layer is bonded to a first insulating layer 144 to form a dielectric-dielectric bond.

[0080] In some embodiments, the second bonding layer 126 includes a sixth dielectric layer and second bonding contacts located in the sixth dielectric layer; wherein the sixth dielectric layer is used to isolate the second bonding contacts from each other. The second bonding contacts are bonded to a second pad 150 to form a metal-metal bond, and the sixth dielectric layer and a second insulating layer 148 are bonded to form a dielectric-dielectric bond.

[0081] Here, the third, fourth, fifth, and sixth dielectric layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0082] Here, the first bonding contact, the second bonding contact, the first conductive layer, the second conductive layer, the first conductive contact, the second conductive contact, the second conductive structure 106, the third conductive structure 122, the third pad 114, and the fourth pad 130 may include conductive materials, including but not limited to tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), metal silicides, or any combination thereof.

[0083] refer to Figure 2 , Figure 2This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this disclosure. For example... Figure 2 As shown, in a second aspect, embodiments of this disclosure provide a semiconductor device 200 comprising: a plurality of semiconductor structures 100 as described above stacked along the Z direction; wherein, two adjacent semiconductor structures 100 along the Z direction are connected by hybrid bonding, or two adjacent semiconductor structures 100 along the Z direction are connected by bump bonding.

[0084] Here, hybrid bonding includes metal-metal bonding and dielectric-dielectric bonding.

[0085] Here, bump bonding connection includes forming bumps made of metallic material on the surface of semiconductor structure 100 to achieve electrical connection between adjacent semiconductor structures 100.

[0086] In some embodiments, the semiconductor device 200 further includes: a logic die located on one side of the plurality of semiconductor structures 100 along the Z direction, the logic die being used to control the first die 102 and the second die 118 in the plurality of semiconductor structures 100 stacked along the Z direction; an interposer located on the side of the logic die facing away from the semiconductor structure 100; a central processing unit (CPU) or a graphics processing unit (GPU) located on the interposer; and a package substrate located on the side of the interposer facing away from the semiconductor structure.

[0087] Here, the first die 102 and the second die 118 in the semiconductor structure 100 can be electrically connected to the CPU or GPU through bumps, an interposer, and a package substrate. Furthermore, the interposer can also lead out electrical signals through bumps and a package substrate.

[0088] refer to Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure. Figure 3 As shown, in a third aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising:

[0089] Step S310: Provide an initial connection structure, the initial connection structure including: a wafer layer; a conductive structure located in the wafer layer and extending along a first direction, the conductive structure including a first end and a second end disposed opposite to each other along the first direction;

[0090] Step S320: Bond multiple first dies to the initial connection structure, with the first end coupled to the first die;

[0091] Step S330: Process the initial connection structure to form a connection structure;

[0092] Step S340: Bond multiple second dies and connecting structures together, with the second end and the second die coupled together; wherein, along the first direction, the thickness of the connecting structure is less than the thickness of the first die and / or the second die.

[0093] refer to Figures 4 to 24 , Figures 4 to 24 This is a cross-sectional structural diagram illustrating the semiconductor structure during the manufacturing process, as provided in some embodiments of this disclosure. The following will be combined with... Figure 3 as well as Figures 4 to 24 The present disclosure provides a detailed description of the manufacturing structure of the semiconductor structure provided in some embodiments.

[0094] In this embodiment of the disclosure, a first die 102 is provided. The following will be combined with... Figures 4 to 8 The process of providing the first die 102 is described in detail.

[0095] like Figure 4 As shown, the method includes: providing a second wafer layer 152; a second conductive structure 106 located in the second wafer layer 152 and extending along the Z direction; a third dielectric layer 154 located on the second wafer layer 152, the third dielectric layer 154 including a plurality of first conductive layers 156 and first conductive contacts 158 located between adjacent first conductive layers 156 along the Z direction; and etching the third dielectric layer 154 to form an opening 160 exposing the first conductive layers 156. Here, the second wafer layer 152 includes a front side and a back side disposed opposite to each other along the Z direction, the surface in contact with the third dielectric layer 154 is the front side of the second wafer layer 152, and the surface away from the third dielectric layer 154 is the back side of the second wafer layer 152.

[0096] here, Figure 4 The diagram illustrates that the third dielectric layer 154 may include three first conductive layers 156 stacked along the Z direction, which are, from bottom to top, a bottom first conductive layer, a middle first conductive layer, and a top first conductive layer. Figure 4 The diagram also illustrates that the third dielectric layer 154 may include a bottom first conductive contact and an intermediate first conductive contact stacked along the Z-direction. The bottom first conductive layer and the intermediate first conductive layer are electrically connected through the bottom first conductive contact, and the intermediate first conductive layer and the top first conductive layer are electrically connected through the intermediate first conductive contact. The second conductive structure 106 includes a third end and a fourth end disposed opposite each other along the Z-direction. The third end is coupled to the bottom first conductive layer located in the third dielectric layer 154, and the fourth end is located in the second wafer layer 152. In practice, the number of first conductive layers and first conductive contacts included in the third dielectric layer 154 is not limited to this and can be flexibly selected according to the actual situation.

[0097] like Figure 5 As shown, the method further includes filling the opening 160 with a dielectric material such that the dielectric material covers the top first conductive layer. Here, the first device layer may include a third dielectric layer 154, a plurality of first conductive layers located in the third dielectric layer 154, and a plurality of first conductive contacts. Filling the opening with dielectric material can make the surface of the first device layer away from the second wafer layer 152 flat, thereby improving the frontside flatness of the second wafer layer 152.

[0098] like Figure 6 As shown, the method further includes: etching a third dielectric layer 154 to form a first groove exposing a top first conductive layer; filling the first groove with a conductive material to form a top first conductive contact; forming a fifth dielectric layer 162 covering the third dielectric layer 154 and the top first conductive contact; etching the fifth dielectric layer 162 to form a second groove exposing the top first conductive contact; and filling the second groove with a conductive material to form a first bonding contact 164. The first bonding layer 110 includes the first bonding contact 164 and a fifth dielectric layer 162 for isolating the first bonding contact 164. Here, the top first conductive layer and the first bonding contact 164 are electrically connected through the top first conductive contact.

[0099] In some embodiments, the process for forming the fifth dielectric layer 162 and the first bonding contact 164 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0100] like Figure 7 As shown, the method further includes: fixing the front side of the second wafer layer 152 to the adhesive tape 166, that is, fixing the first bonding layer 110 to the adhesive tape 166; performing a dicing process on the second wafer layer 152 to form a plurality of first dies 102, and the second wafer layer 152 after the dicing process forms an initial second base layer 104S. Here, the surface of the initial second base layer 104S in the first die 102 that faces away from the first bonding layer 110 is the back side. Figure 4 , Figure 5 and Figure 6 The dashed lines in the diagram can be used to indicate, for example, the locations where cutting processes are performed.

[0101] In some embodiments, the dicing process may include, but is not limited to, Stealth Dicing Before Grinding (SDBG). SDBG can include stealth dicing, backside grinding, and die separation. Stealth dicing refers to using a laser to create invisible cracks within the wafer layer, rather than directly cutting the wafer surface. Backside grinding refers to performing backside grinding on the wafer layer to thin it to a target thickness to form the initial substrate layer. Die separation refers to the natural propagation of the invisible cracks during the grinding process, leading to die separation.

[0102] like Figure 8 As shown, the method further includes: cutting the first die 102 (e.g., after the cutting process) Figure 8 (The dashed box in the middle indicates that the tape is separated from the other 166).

[0103] In this embodiment of the disclosure, a second die 118 is provided.

[0104] Here, the process of providing the second die 118 can be referred to the process of providing the first die 102. The process of providing the second die 118 is briefly described below. A fourth dielectric layer is formed on the third wafer layer, the fourth dielectric layer including a plurality of second conductive layers and second conductive contacts located between adjacent second conductive layers along the Z direction; a second bonding layer is formed on the fourth dielectric layer, the second bonding layer including second bonding contacts and a sixth dielectric layer for isolating the second bonding contacts; the second bonding layer is fixedly connected to an adhesive tape; the third wafer layer is diced to form a plurality of second dies; the diced second dies and the adhesive tape are separated.

[0105] It should be noted that the structures of the first die 102 and the second die 118 may be the same or different, and the first die 102 and the second die 118 may be formed on the same wafer layer or on different wafer layers.

[0106] In this embodiment of the present disclosure, in step S310, an initial connection structure 134S is provided. The initial connection structure 134S includes: a first wafer layer 168; a first conductive structure 138 located in the first wafer layer 168 and extending along the Z direction, the first conductive structure 138 including a first end 140 and a second end 142 disposed opposite to each other along the Z direction. The following will be combined with... Figures 9 to 12 The process of providing the initial connection structure 134S is described in detail.

[0107] like Figure 9 As shown, the method further includes providing a first wafer layer 168. Here, the first wafer layer 168 may also be referred to as a contact wafer.

[0108] like Figure 10 As shown, the method further includes: forming a first conductive structure 138 in a first wafer layer 168, exposing a first end 140 of the first conductive structure 138 on the surface of the first wafer layer 168, and a second end 142 of the first conductive structure 138 located in the first wafer layer 168.

[0109] For example, forming the first conductive structure 138 may include: etching the first wafer layer 168 to form a third groove; filling the third groove with a conductive material to form a first conductive material layer covering the first wafer layer 168; and planarizing the first conductive material layer to form the first conductive structure 138 and expose the surface of the first wafer layer 168.

[0110] It should be noted that the term "planarization" in this article may include, but is not limited to, chemical mechanical polishing (CMP) treatment.

[0111] like Figure 11 As shown, the method further includes forming a first insulating layer 144 covering the first wafer layer 168 and the first conductive structure 138. Here, the first wafer layer 168 includes a front side and a back side disposed opposite to each other along the Z direction. The surface in contact with the first insulating layer 144 is the front side of the first wafer layer 168, and the surface facing away from the first insulating layer 144 is the back side of the first wafer layer 168. Forming the first insulating layer 144 improves the flatness of the front side of the first wafer layer 168.

[0112] like Figure 12 As shown, the method further includes: etching a first insulating layer 144 to form a fourth groove exposing the first conductive structure 138; and filling the fourth groove with a conductive material to form a first pad 146. The initial interconnect structure 134S includes: a first wafer layer 168; a first conductive structure 138 located in the first wafer layer 168 and extending along the Z direction; a first insulating layer 144 located on the first wafer layer 168; and a first pad 146 located in the first insulating layer 144, with a first end 140 coupled to the first pad 146. Furthermore, etching the groove to form the dummy first pad does not expose the first conductive structure 138.

[0113] For example, a conductive material is filled in the fourth groove to form a first pad material layer, the first pad material layer filling the fourth groove and covering the first insulating layer 144; a planarization process is performed on the first pad material layer to form a first pad 146 and expose the surface of the first insulating layer 144.

[0114] In this embodiment of the disclosure, such as Figure 13As shown, in step S320, multiple first dies 102 and the initial connection structure 134S are bonded together, with the first end 140 coupled to the first die 102 via the first pad 146. The first bonding layer 110 in the first die 102 and the first insulating layer 144 in the initial connection structure 134S are in contact, aligning the first bonding contact 164 and the first pad 146. For example, when both the first bonding contact 164 and the first pad 146 comprise copper, the bonding connection is achieved through copper thermal diffusion. The first bonding contact 164 and the first pad 146 form a metal-metal bond, and the fifth dielectric layer 162 and the first insulating layer 144 form a dielectric-dielectric bond.

[0115] In some embodiments, such as Figure 14 As shown, the method further includes filling a dielectric material between two adjacent first dies 102 along the X direction to form a first filler layer 116. Here, the surface of the first filler layer 116 may be lower than the surface of the initial second substrate layer 104S in the first die 102, and the thickness of the first filler layer 116 is the thickness reserved for the first die 102 after subsequent back-grinding (BG) processing.

[0116] In some embodiments, the ratio between the thickness of the first filler layer 116 and the distance between two adjacent first dies 102 along the X direction (i.e., the width of the first filler layer 116) is less than 0.5. For example, the thickness of the first filler layer 116 may be, for example, 40 μm, and the distance between two adjacent first dies 102 along the X direction may be, for example, 80 μm. Here, controlling the ratio between the thickness and width of the first filler layer 116 to be less than 0.5 is beneficial for forming the first filler layer 116 in a single filling operation at low cost.

[0117] like Figure 15 As shown, the method further includes: performing a backside thinning process on the initial second substrate layer 104S to form the second substrate layer 104, wherein the surface of the first die 102 facing away from the initial interconnect structure 134S is substantially flush with the surface of the first filler layer 116. Here, a dicing process is performed on the second wafer layer 152 to form the initial second substrate layer 104S; and a backside thinning process is performed on the initial second substrate layer 104S to form the second substrate layer 104. Figure 15 This illustrates that even when the back side is thinned on the initial second substrate 104S, the fourth end of the second conductive structure 106 is not exposed.

[0118] In some embodiments, the back-side thinning process performed on the initial second substrate layer 104S may include, but is not limited to, CMP processing. Here, firstly, before performing the back-side thinning process on the initial second substrate layer 104S, the first die 102 and the initial interconnect structure 134S are bonded together. At this time, a larger thickness of the first die 102 can improve the bonding effect. Secondly, after bonding, performing the back-side thinning process on the initial second substrate layer 104S is beneficial for reducing the thickness of the finally formed semiconductor structure 100 along the Z-direction, thereby improving the integration density of the semiconductor structure 100. For example, before bonding, the thickness of the first die 102 may be 130 μm; after performing the back-side thinning process, the thickness of the first die 102 may be 40 μm.

[0119] In some embodiments, such as Figure 16 As shown, the method further includes: forming a first dielectric layer 112 covering the first die 102 and the first filler layer 116, wherein the two sides of the first filler layer 116 disposed opposite each other along the Z direction are in contact with the first dielectric layer 112 and the initial connection structure 134S, respectively. Here, forming the first dielectric layer 112 can improve the backside flatness of the second substrate layer 104.

[0120] In some embodiments, the process for forming the first filler layer 116 and the first dielectric layer 112 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0121] In this embodiment of the present disclosure, in step S330, the initial connection structure 134S is processed to form the connection structure 134.

[0122] In some embodiments, such as Figure 17 As shown, step S330 includes: performing a thinning process on the surface of the first wafer layer 168 away from the first die 102, that is, performing a back-side thinning process on the first wafer layer 168 to form an initial first substrate layer 136S. Figure 17 This illustrates that even when the back side is thinned on the first wafer layer 168, the initial first substrate layer 136S does not expose the second end 142 of the first conductive structure 138.

[0123] In some embodiments, performing a back-side thinning process on the first wafer layer 168 may include, but is not limited to, CMP processing. Here, performing a back-side thinning process on the first wafer layer 168 is beneficial for reducing the thickness of the final semiconductor structure along the Z direction, thereby improving the integration density of the semiconductor structure.

[0124] In some embodiments, such as Figure 18As shown, step S330 further includes: forming a second insulating layer 148 covering the initial first substrate layer 136S. Here, forming the second insulating layer 148 can improve the flatness of the back surface of the initial first substrate layer 136S.

[0125] In some embodiments, the process for forming the first insulating layer 144 and the second insulating layer 148 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0126] In some embodiments, such as Figure 19 As shown, step S330 further includes: etching the second insulating layer 148 and the initial first base layer 136S to form a fifth groove exposing the first conductive structure 138; filling the fifth groove with conductive material to form a second pad 150, with the second end 142 and the second pad 150 coupled together. Here, the connection structure 134 includes: a first insulating layer 144, an initial first base layer 136S, and a second insulating layer 148 stacked along the Z direction; a first conductive structure 138 located in the initial first base layer 136S; a first pad 146 located in the first insulating layer 144; and a second pad 150 located in the second insulating layer 148. Furthermore, etching the groove used to form the dummy second pad does not expose the first conductive structure 138.

[0127] In this embodiment of the disclosure, such as Figure 20 As shown, in step S340, multiple second dies 118 (such as...) are... Figure 20 (Illustrated by the dashed box) and the connection structure 134 are bonded together, and the second end 142 is coupled to the second die 118 via the second pad 150. The second bonding layer in the second die 118 and the second insulating layer 148 in the connection structure 134 are in contact, aligning the second bonding contact and the second pad 150. For example, when both the second bonding contact and the second pad 150 comprise copper, the bonding connection is achieved through copper thermal diffusion. The second bonding contact and the second pad 150 form a metal-metal bond, and the sixth dielectric layer and the second insulating layer 148 form a dielectric-dielectric bond.

[0128] like Figure 21 As shown, a backside thinning process is performed on the surface of the initial third substrate layer 120S facing away from the connection structure 134 to form the third substrate layer 120. Here, a dicing process is performed on the third wafer layer to form the initial third substrate layer 120S; a backside thinning process is performed on the initial third substrate layer 120S to form the third substrate layer 120. Figure 21 This illustrates that even when the initial third substrate 120S is thinned on the back side, the third substrate 120 does not expose the sixth end of the third conductive structure 122.

[0129] In some embodiments, the back-side thinning process performed on the initial third substrate layer 120S may include, but is not limited to, CMP processing. Here, firstly, before performing the back-side thinning process on the initial third substrate layer 120S, the second die 118 and the connection structure 134 are bonded together. At this time, a larger thickness of the second die 118 can improve the bonding effect. Secondly, after bonding, performing the back-side thinning process on the initial third substrate layer 120S is beneficial for reducing the thickness of the finally formed semiconductor structure 100 along the Z-direction, thereby improving the integration density of the semiconductor structure 100. For example, before bonding, the thickness of the second die 118 may be 130 μm; after performing the back-side thinning process, the thickness of the second die 118 may be 40 μm.

[0130] In some embodiments, such as Figure 22 As shown, the method further includes filling a dielectric material between two adjacent second dies 118 along the X direction to form a second filler layer 132. Here, the surface of the second filler layer 132 is substantially flush with the surface of the third base layer 120 in the second die 118.

[0131] For example, a dielectric material may be filled between two adjacent second dies 118 along the X direction to form a second filler material layer covering the second dies 118; the second filler material layer is planarized to form a second filler layer 132 and expose the second dies 118.

[0132] In some embodiments, the ratio between the thickness of the second filler layer 132 and the distance between two adjacent second dies 118 along the X direction (i.e., the width of the second filler layer 132) is less than 0.5. For example, the thickness of the second filler layer 132 may be, for example, 40 μm, and the distance between two adjacent second dies 118 along the X direction may be, for example, 80 μm. Here, controlling the ratio between the thickness and width of the second filler layer 132 to be less than 0.5 is advantageous for forming the second filler layer 132 in a single filling operation at low cost.

[0133] In some embodiments, such as Figure 23 As shown, the method further includes: forming a second dielectric layer 128 covering the second die 118 and the second filler layer 132, wherein the two sides of the second filler layer 132 disposed opposite to each other along the Z direction are in contact with the second dielectric layer 128 and the connecting structure 134, respectively. Here, forming the second dielectric layer 128 can improve the back surface flatness of the third substrate layer 120.

[0134] In some embodiments, the process for forming the second filler layer 132 and the second dielectric layer 128 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0135] In some embodiments, the first dielectric layer 112 and the second base layer 104 are etched to form a sixth groove exposing the second conductive structure 106; the sixth groove is filled with a conductive material to form a third pad 114, the surface of the third pad 114 being substantially flush with the surface of the first dielectric layer 112. Here, the fourth end of the second conductive structure 106 is coupled to the third pad 114.

[0136] In some embodiments, the second dielectric layer 128 and the third substrate layer 120 are etched to form a seventh groove exposing the third conductive structure 122; the seventh groove is filled with conductive material to form a fourth pad 130, the surface of the fourth pad 130 being substantially flush with the surface of the second dielectric layer 128. Here, the sixth end of the third conductive structure 122 is coupled to the fourth pad 130. Here, the third pad 114 can be an HLP formed on the back side of the first die 102, and the fourth pad 130 can be an HLP formed on the back side of the second die 118.

[0137] In some embodiments, the etching process for forming the first, second, third, fourth, fifth, sixth, and seventh grooves may include, but is not limited to, dry etching processes.

[0138] In some embodiments, such as Figure 24 As shown, the method further includes: performing a dicing process along the Z-direction on the first dielectric layer 112, the first filling layer 116, the first insulating layer 144, the initial first substrate layer 136S, the second insulating layer 148, the second filling layer 132, and the second dielectric layer 128 to form a semiconductor structure. Here, the first wafer layer 168 is thinned on the back side to form the initial first substrate layer 136S, and the initial first substrate layer 136S is diced to form the first substrate layer 136. During the dicing process, the dicing area only includes the first filling layer 116 and the second filling layer 132, that is, it only involves dielectric materials and not metal materials, which can reduce the difficulty and complexity of the dicing process.

[0139] It should be noted that the positions of the first filler layer 116 and the second filler layer 132 can correspond to the cutting channel area. Figure 24 The dashed line indicates the location where the cutting process is performed.

[0140] In some embodiments, the first conductive structure 138, the second conductive structure 106, and the third conductive structure 122 may include through-silicon via (TSV) structures.

[0141] In this embodiment, a first die 102 and a second die 118 are provided, and a first conductive structure 138 is formed in a first wafer layer 168 to form a TSV-like embedded vertical interconnect carrier wafer structure. The first die 102 and the second die 118 are respectively stacked on both sides of the connection structure 134 that are arranged opposite to each other along the Z direction. Under the premise of ensuring the quality of die stacking wafer bonding, a vertical stacking structure of die stacking wafer short-range interconnect is formed to accommodate as many dies as possible, thereby increasing the stacking density, eliminating the need for external wiring, reducing the interconnect length to, for example, below 20 μm, and reducing the resistor-capacitor (RC) delay by more than 40%. It is suitable for wafer process integration of heterogeneous multilayer hybrid bonding and ultra-high density system-in-package. In other words, a carrier wafer with input / output TSV (I / O TSV) structure, signal TSV (Signal TSV) structure and dummy TSV (Dummy TSV) structure is bonded to form a 1-wafer-2-die (1W2C) structure by stacking wafers on both sides. The back of the dies on both sides (i.e., the first die 102 and the second die 118) can also reserve pad structures (i.e., the third pad 114 and the fourth pad 130).

[0142] Firstly, by bonding the two sides of the connecting structure 134, which are respectively arranged opposite each other along the Z direction, to the first die 102 and the second die 118, a high-quality die-stacked wafer bonding structure can be achieved, reducing the thickness of each semiconductor structure and increasing the number of stacked semiconductor layers in the semiconductor device, i.e., increasing the stacking density. Secondly, a first filling layer 116 is provided between any adjacent first dies 102, and a second filling layer 132 is provided between any adjacent second dies 118. Both the first filling layer 116 and the second filling layer 132 are located in the dicing region. Dicing processing is performed on the first filling layer 116 and the second filling layer 132 in the dicing region to reduce the difficulty and complexity of the dicing process. Thirdly, after bonding the first die 102 and the initial interconnect structure 134S, a back-side thinning process is performed on the initial second substrate layer 104S in the first die 102; a back-side thinning process is also performed on the initial first substrate layer 136S in the initial interconnect structure 134S to form the interconnect structure 134; after bonding the second die 118 and the interconnect structure 134, a back-side thinning process is performed on the initial third substrate layer 120S in the second die 118. The overall thickness of the semiconductor structure is controlled by combining the thinning process with die thickness customization. Fourthly, multiple first dies 102 are formed after dicing the second wafer layer 152, and multiple second dies 118 are formed after dicing the third wafer layer. The first dies 102 and the second dies 118 can be tested, and the qualified first dies 102 and the qualified second dies 118 are used for bonding to improve the yield of the semiconductor structure 100.

[0143] This disclosure provides a semiconductor structure, a method for manufacturing the same, and a semiconductor device. In this embodiment, two sides of a connection structure disposed opposite to each other along a first direction are respectively bonded to a first die and a second die, and the thickness of the connection structure is less than the thickness of the first die and / or the second die. Thus, by stacking the first die and the second die along the first direction using the connection structure, the thickness of the semiconductor structure along the first direction can be reduced, and the integration density of the semiconductor structure can be improved.

[0144] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0145] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A first die, a connecting structure, and a second die are stacked along a first direction, wherein the two sides of the connecting structure, which are arranged opposite to each other along the first direction, are respectively bonded to the first die and the second die. The connection structure includes: a base layer; a conductive structure located in the base layer and extending along the first direction, the conductive structure including a first end and a second end disposed opposite to each other along the first direction, the first end being coupled to the first die, and the second end being coupled to the second die; wherein, along the first direction, the thickness of the connection structure is less than the thickness of the first die and / or the second die.

2. The semiconductor structure according to claim 1, characterized in that, Along the first direction, the ratio between the thickness of the connecting structure and the thickness of the first die ranges from 1 / 2 to 1 / 4; and / or, the ratio between the thickness of the connecting structure and the thickness of the second die ranges from 1 / 2 to 1 / 4.

3. The semiconductor structure according to claim 1, characterized in that, Along a plane perpendicular to the first direction, the projected area of ​​the connection structure is greater than the projected area of ​​the first die and / or the second die.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first dielectric layer located on the side of the first die away from the connection structure; along a plane perpendicular to the first direction, the projected area of ​​the first dielectric layer is larger than the projected area of ​​the first die. And / or, a second dielectric layer located on the side of the second die opposite to the connection structure; along a plane perpendicular to the first direction, the projected area of ​​the second dielectric layer is greater than the projected area of ​​the second die.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: A first filling layer located on at least one side of the first die along the second direction, wherein the two sides of the first filling layer disposed opposite to each other along the first direction are in contact with the first dielectric layer and the connecting structure, respectively; And / or, a second filling layer located on at least one side of the second die along the second direction, wherein the two sides of the second filling layer disposed opposite to each other along the first direction are in contact with the second dielectric layer and the connecting structure respectively; wherein the first direction and the second direction intersect.

6. The semiconductor structure according to claim 5, characterized in that, The coefficient of thermal expansion of the first dielectric layer is greater than that of the first filler layer, and the coefficient of thermal expansion of the second dielectric layer is greater than that of the second filler layer.

7. The semiconductor structure according to claim 1, characterized in that, The first die includes a first device layer; the second die includes a second device layer; wherein the first device layer and the second device layer are respectively disposed on two sides of the connection structure that are disposed opposite to each other along the first direction.

8. The semiconductor structure according to claim 1, characterized in that, The connection structure also includes: The first insulating layer is located between the base layer and the first die; The first pad is located in the first insulating layer, and the first end is coupled to the first die through the first pad; The second insulating layer is located between the base layer and the second die; The second pad is located in the second insulating layer, and the second end is coupled to the second die through the second pad.

9. The semiconductor structure according to claim 8, characterized in that, The connection structure and the first die are connected by hybrid bonding, and the connection structure and the second die are connected by hybrid bonding.

10. A semiconductor device, characterized in that, The semiconductor device includes: A plurality of semiconductor structures as described in any one of claims 1 to 9 are stacked along a first direction; wherein two adjacent semiconductor structures along the first direction are connected by hybrid bonding, or two adjacent semiconductor structures along the first direction are connected by bump bonding.

11. A method for manufacturing a semiconductor structure, characterized in that, The method includes: An initial interconnect structure is provided, the initial interconnect structure comprising: a wafer layer; a conductive structure located in the wafer layer and extending along a first direction, the conductive structure comprising a first end and a second end disposed opposite to each other along the first direction; Multiple first dies are bonded to the initial connection structure, with the first end coupled to the first die; The initial connection structure is processed to form a connection structure; Multiple second dies are bonded to the connecting structure, with the second end coupled to the second die; wherein, along the first direction, the thickness of the connecting structure is less than the thickness of the first die and / or the second die.

12. The manufacturing method according to claim 11, characterized in that, The method further includes: A dielectric material is filled between two adjacent first dies along the second direction to form a first filler layer, wherein the surface of the first die facing away from the initial connection structure is flush with the surface of the first filler layer. A first dielectric layer is formed covering the first die and the first filler layer, wherein the two sides of the first filler layer disposed opposite to each other along the first direction are in contact with the first dielectric layer and the initial connection structure, respectively; wherein the first direction and the second direction intersect.

13. The manufacturing method according to claim 12, characterized in that, The initial connection structure further includes: a first insulating layer located between the wafer layer and the first die; a first pad located in the first insulating layer, the first end being coupled to the first die via the first pad; the processing of the initial connection structure to form a connection structure includes: The surface of the wafer layer facing away from the first die is thinned to form an initial substrate layer; A second insulating layer is formed covering the initial substrate layer; A second pad is formed in the second insulating layer, and the second end is coupled to the second die through the second pad.

14. The manufacturing method according to claim 13, characterized in that, The method further includes: A medium material is filled between two adjacent second dies along the second direction to form a second filler layer, wherein the surface of the second die facing away from the connection structure is flush with the surface of the second filler layer. A second dielectric layer is formed covering the second die and the second filler layer, and the two sides of the second filler layer disposed opposite to each other along the first direction are in contact with the second dielectric layer and the connecting structure, respectively.

15. The manufacturing method according to claim 14, characterized in that, The method further includes: A dicing process is performed along the first direction on the first dielectric layer, the first filling layer, the first insulating layer, the initial substrate layer, the second insulating layer, the second filling layer, and the second dielectric layer to form a semiconductor structure.

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