H-bridge power tube driving circuit and control method

Abstract

The invention provides an H-bridge power tube driving circuit and a control method. According to the invention, the high-side driving voltage and the low-side driving voltage are additionally arranged, and a plurality of current sources are adopted as current input, so that the technical effects that the power tube quickly enters a linear region to reduce the on-resistance, the starting speed is improved and the loss is correspondingly reduced are achieved by increasing the current input of the input end of the power tube; each current source is provided with an independent switch, so that the current input of the input end of a power tube can be reduced by disconnecting the switches corresponding to part of the current sources after the gate-source voltage stably reaches a set value, and the technical effects of effectively preventing overshoot and reducing noise are achieved; and the corresponding fourth switch and the seventh switch are directly switched off, so that the whole driving circuit can be quickly switched off, the switching-off speed is greatly improved, and the technical effect of reducing circuit loss is achieved. The technical problems that loss is increased and efficiency is reduced due to the fact that the opening and closing speed is low in the prior art are solved.

Description

Technical Field

[0001] This invention relates to the field of circuit driving technology, and in particular to an H-bridge power transistor driving circuit and control method. Background Technology

[0002] Traditional H-bridge power transistor drive control methods commonly employ push-pull or constant current source drive. When driving large loads, traditional H-bridges typically use a high-side NMOS plus a low-side NMOS structure to reduce the internal resistance of the power transistors. This N+N structure usually requires an additional charge pump to increase the gate-source voltage of the power transistors, ensuring they operate at their optimal state. However, the load-carrying capacity of the charge pump is limited, so a constant current source structure is used to switch the power transistors. This structure suffers from slow turn-on and turn-off speeds, and the influence of Miller capacitance in the power transistors leads to increased circuit losses and reduced efficiency. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides an H-bridge power transistor driving circuit and control method. By adding high-side and low-side driving voltages and employing multiple current sources as current inputs, it increases the current input to the power transistor, enabling it to quickly enter the linear region, reducing on-resistance, improving turn-on speed, and consequently reducing losses. Furthermore, by setting individual switches at each current source, the current input to the power transistor can be reduced by disconnecting some current source switches after the gate-source voltage has stabilized at a set value, effectively preventing overshoot and reducing noise. Moreover, directly shutting down the corresponding fourth and seventh switches allows for rapid shutdown of the entire driving circuit, significantly improving shutdown speed and reducing circuit losses. This solves the technical problems of slow turn-on and shutdown speeds leading to increased losses and reduced efficiency in existing technologies.

[0004] According to an embodiment of the present invention, an H-bridge power transistor driving circuit includes an H-bridge circuit and a driving circuit. The driving circuit includes a high-side driving circuit and a low-side driving circuit. The H-bridge includes power transistors and an inductive load. The power transistors include high-side power transistors and low-side power transistors. Each power transistor is coupled between a power supply voltage and ground. The high-side driving circuit includes two symmetrically arranged sub-high-side driving circuits. Each sub-high-side driving circuit is connected to a corresponding high-side power transistor. Each sub-high-side driving circuit includes a high-side driving voltage, a first current source, a second current source, a third current source, a first switch, a second switch, a third switch, and a fourth switch. The first current source and the first switch are connected in series between the power supply voltage and the input terminal of the corresponding high-side power transistor. The second current source and the second switch are connected in series between the high-side driving voltage and the input terminal of the corresponding high-side power transistor. The high-side drive circuit includes two symmetrically arranged sub-low-side drive circuits. Each sub-low-side drive circuit is connected to a corresponding low-side power transistor. Each sub-low-side drive circuit includes a low-side drive voltage, a fourth current source, a fifth current source, a fifth switch, a sixth switch, and a seventh switch. The fourth current source and the fifth switch are connected in series between the low-side drive voltage and the input terminal of the corresponding low-side power transistor. The fifth current source and the sixth switch are connected in series between the low-side drive voltage and the input terminal of the corresponding low-side power transistor. The seventh switch is connected between the input terminal of the corresponding low-side power transistor and ground.

[0005] In some embodiments, the first current source, the second current source, and the fourth current source are all mirror current sources, wherein the first current source is greater than the second current source, the second current source is greater than the third current source, and the fourth current source is greater than the fifth current source.

[0006] In some embodiments, the first current source, the second current source, and the fourth current source are all proportional mirror current sources.

[0007] In some embodiments, both the high-side power transistor and the low-side power transistor are N-type transistors.

[0008] On the other hand, according to embodiments of the present invention, an H-bridge power transistor drive control method is also provided, based on an H-bridge power transistor drive circuit according to any one of the preceding claims, comprising the following steps: controlling the power transistor to turn on in segments based on the drive circuit; controlling the power transistor to turn off based on the drive circuit in response to a received shutdown signal; wherein the shutdown signal is issued by a terminal.

[0009] In some embodiments, the step of controlling the power transistor to turn on in segments based on the driving circuit further includes: controlling the high-side power transistor to turn on in segments based on the sub-high-side driving circuit; and controlling the low-side power transistor to turn on in segments based on the sub-low-side driving circuit.

[0010] In some embodiments, the step of segmentally controlling the high-side power transistor to turn on based on the sub-high-side driving circuit further includes: turning on the first switch, the second switch, and the third switch, while keeping the fourth switch in the off state; charging the high-side power transistor based on the first current source, the second current source, and the third current source to turn on the high-side power transistor; if it is detected that the voltage of the high-side power transistor transitions from the saturation region to the linear region, then turning off the first switch, and charging the high-side power transistor based on the second current source and the third current source to reduce the charging current of the high-side power transistor; if it is detected that the conduction time of the second switch reaches a preset time, then turning off the second switch, and charging the high-side power transistor based on the third current source to complete the turn-on of the high-side power transistor.

[0011] In some embodiments, the step of controlling the low-side power transistor to turn on in segments based on the sub-low-side driving circuit further includes: turning on the fifth switch and the sixth switch, while keeping the seventh switch in the off state; charging the low-side power transistor based on the fourth current source and the fifth current source to turn on the low-side power transistor; if it is detected that the voltage of the low-side power transistor transitions from the saturation region to the linear region, then turning off the fifth switch and charging the low-side power transistor based on the fifth current source to complete the turn-on of the low-side power transistor.

[0012] In some embodiments, the step of controlling the power transistor to turn off based on the driving circuit in response to the received shutdown signal further includes: controlling the high-side power transistor to turn off based on the high-side driving circuit in response to the received shutdown signal; and controlling the low-side power transistor to turn off based on the low-side driving circuit in response to the received shutdown signal.

[0013] In some embodiments, the step of controlling the high-side power transistor to turn off based on the high-side driving circuit in response to the received shutdown signal further includes: turning on the fourth switch in response to the received shutdown signal to cut off the charging current to the high-side power transistor, thereby completing the shutdown of the high-side power transistor.

[0014] In some embodiments, the step of controlling the low-side power transistor to turn off based on the low-side driving circuit in response to the received shutdown signal further includes: turning on the seventh switch in response to the received shutdown signal to cut off the charging current to the low-side power transistor, thereby completing the shutdown of the low-side power transistor.

[0015] The technical principle of this invention is as follows: a high-side drive voltage and a low-side drive voltage are added, and multiple current sources are used as current inputs to increase the current input at the power transistor input terminal. At the same time, a separate switch is set at each current source. By controlling the opening and closing of the switch, the magnitude of the current input at the power transistor input terminal can be quickly controlled, thereby realizing segmented control of the input current to turn on the power transistor. Furthermore, a switch is set between each power transistor and ground, so that the power transistor can be quickly turned off by closing the switch.

[0016] Compared to existing technologies, this invention offers the following advantages: By adding high-side and low-side drive voltages and employing multiple current sources as current inputs, the current input to the power transistor's input terminal is increased, thereby accelerating the transistor's entry into the linear region, reducing on-resistance, improving turn-on speed, and consequently reducing losses. Furthermore, by setting individual switches at each current source, the current input to the power transistor's input terminal can be reduced by disconnecting some current source switches after the gate-source voltage has stably reached a set value, effectively preventing overshoot and reducing noise. Moreover, directly shutting down the corresponding fourth and seventh switches allows for rapid shutdown of the entire drive circuit, significantly improving shutdown speed and reducing circuit losses. This solves the technical problems of slow turn-on and shutdown speeds leading to increased losses and reduced efficiency in existing technologies. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an H-bridge power transistor driving circuit in one embodiment of the present invention.

[0018] Figure 2 This is a control signal flow diagram in one embodiment of the present invention.

[0019] Figure 3 This is a flowchart of an H-bridge power transistor drive control method according to one embodiment of the present invention.

[0020] Figure 4 This is a flowchart of an H-bridge power transistor drive control method according to one embodiment of the present invention.

[0021] Figure 5 This is a flowchart of an H-bridge power transistor drive control method according to one embodiment of the present invention.

[0022] Figure 6This is a flowchart of an H-bridge power transistor drive control method according to one embodiment of the present invention.

[0023] Figure 7 This is a flowchart of an H-bridge power transistor drive control method according to one embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of the power transistor's on and off signals in one embodiment of the present invention.

[0025] Figure 9 A schematic diagram of the structure of an embodiment of the computer device provided by the present invention.

[0026] In the above figures: VM - power supply voltage; VBST - high-side drive voltage; VCP - low-side drive voltage; MN1, MN3: high-side power transistors; MN2, MN4: low-side power transistors; L1 - inductive load; S1, S8: first switch; S2, S9: second switch; S3, S10: third switch; S4, S11: fourth switch; S5, S12: fifth switch; S6, S13: sixth switch; S7, S14: seventh switch; n×I1: first current source; m×I1: second current source; I1: third current source; m×I3: fourth current source; I3: fifth current source; GND: ground. Detailed Implementation

[0027] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] Traditional H-bridge power transistor drive control methods commonly employ push-pull or constant current source drive. When using a high-side PMOS and low-side NMOS structure, a push-pull drive is often used to switch the power transistors. While simple to control, push-pull drives have significant drawbacks: fast switching speed, susceptibility to overcharging, and high noise. When driving larger loads, traditional H-bridges typically use a high-side NMOS and low-side NMOS structure to reduce the power transistor's internal resistance. This N+N structure usually requires an additional charge pump to increase the gate-source voltage of the power transistors, ensuring optimal operation. However, the charge pump's load-carrying capacity is limited, so a constant current source is used to switch the power transistors. This structure results in slower switching speeds, and the Miller capacitance of the power transistors increases switching losses, reduces efficiency, and increases power transistor heat generation.

[0029] To solve the above-mentioned technical problems, the following embodiments are provided in detail:

[0030] like Figure 1As shown, this embodiment of the invention proposes an H-bridge power transistor driving circuit, including an H-bridge circuit and a driving circuit. The driving circuit includes a high-side driving circuit and a low-side driving circuit. The H-bridge includes power transistors and an inductive load. The power transistors include high-side power transistors MN1 and MN3 and low-side power transistors MN2 and MN4. All power transistors are coupled between the power supply voltage VM and ground GND. Both the high-side power transistors and the low-side power transistors are N-type transistors.

[0031] The high-side drive circuit includes two symmetrically arranged sub-high-side drive circuits; each sub-high-side drive circuit is connected to its corresponding high-side power transistor; the sub-high-side drive circuit includes a high-side drive voltage VBST, a first current source n×I1, a second current source m×I1, a third current source I1, first switches S1, S8, second switches S2, S9, third switches S3, S10, and fourth switches S4, S11; the first current source n×I1 and the first switches S1, S8 are connected in series between the power supply voltage VM and the input terminals of the corresponding high-side power transistors MN1, MN3; the second current source m×I1... I1 and the second switches S2 and S9 are connected in series between the high-side drive voltage and the input terminals of the corresponding high-side power transistors MN1 and MN3; the third current source I1 and the third switches S3 and S10 are connected in series between the high-side drive voltage VBST and the input terminals of the corresponding high-side power transistors MN1 and MN3; the fourth switch m×I3 is connected between the input terminals of the corresponding high-side power transistors MN1 and MN3 and ground GND; VCP and VBST are both charge pump output voltages, VBST is the gate drive voltage of the high-side power transistor, and VCP is the gate drive voltage of the low-side power transistor.

[0032] The low-side drive circuit includes two symmetrically arranged sub-low-side drive circuits; each sub-low-side drive circuit is connected to the corresponding low-side power transistors MN2 and MN4 respectively; the sub-low-side drive circuit includes a low-side drive voltage VCP, a fourth current source m×I3, a fifth current source I3, a fifth switch S5, S12, a sixth switch S6, S13 and a seventh switch S7, S14; the fourth current source m×I3 and the fifth switches S5, S12 are connected in series between the low-side drive voltage VCP and the input terminals of the corresponding low-side power transistors MN2 and MN4; the fifth current source I3 and the sixth switches S6, S13 are connected in series between the low-side drive voltage VCP and the input terminals of the corresponding low-side power transistors MN2 and MN4; the seventh switches S7, S14 are connected between the input terminals of the corresponding low-side power transistors MN2 and MN4 and ground GND.

[0033] Specifically, the H-bridge circuit includes two symmetrically distributed power transistor pairs and an inductive load L1. Each power transistor pair includes a high-side power transistor and a low-side power transistor. Each power transistor pair is coupled between the power supply voltage and ground, and the middle node of each power transistor pair is used to provide a switching voltage to the inductive load L1.

[0034] This invention provides an H-bridge power transistor drive circuit, wherein the control signal is as follows: Figure 2 As shown, this H-bridge power transistor driver circuit is applied to a chip (i.e., a controller). The chip receives input signals (from the user interface or sent by a mobile terminal). These input signals include commands such as turning on the power transistor (starting the circuit to run) or turning off the power transistor (turning off the running circuit). The chip decodes these signals and then controls the H-bridge power transistor driver circuit based on the decoded signals. Figure 2 The charge pump in the middle is used to provide Figure 1 The power supply voltage VM in the circuit allows the signal to flow from the H-bridge to the inductive load, thus enabling the H-bridge power transistors to be driven.

[0035] The technical principle of this invention is as follows: A high-side drive voltage and a low-side drive voltage are added, and multiple current sources are used as current inputs, increasing the current input to the power transistor's input terminal. Simultaneously, a separate switch is provided at each current source, allowing for rapid control of the current input to the power transistor's input terminal through switch opening and closing, thereby achieving segmented control of the input current to turn on the power transistor. Furthermore, a switch is provided between each power transistor and ground, allowing for rapid power transistor shutdown by closing the switch. Detailed workflow instructions are provided in the following method embodiments and will not be repeated here.

[0036] Compared to existing technologies, this invention offers the following advantages: By adding high-side and low-side drive voltages and employing multiple current sources as current inputs, the current input to the power transistor's input terminal is increased, thereby accelerating the transistor's entry into the linear region, reducing on-resistance, improving turn-on speed, and consequently reducing losses. Furthermore, by setting individual switches at each current source, the current input to the power transistor's input terminal can be reduced by disconnecting some current source switches after the gate-source voltage has stably reached a set value, effectively preventing overshoot and reducing noise. Moreover, directly shutting down the corresponding fourth and seventh switches allows for rapid shutdown of the entire drive circuit, significantly improving shutdown speed and reducing circuit losses. This solves the technical problems of slow turn-on and shutdown speeds leading to increased losses and reduced efficiency in existing technologies.

[0037] In some embodiments, such as Figure 1 As shown, the first current source n×I1, the second current source m×I1 and the fourth current source m×I3 are all mirror current sources. Among them, the first current source n×I1 is greater than the second current source m×I1, the second current source m×I1 is greater than the third current source I1, and the fourth current source m×I3 is greater than the fifth current source I3.

[0038] Specifically, this current source configuration results in a larger input current for the power transistor. A mirror current source is a type of constant current source circuit widely used in analog integrated circuits. Its core function is to accurately replicate the reference current, providing a stable bias current for multi-stage amplifier circuits or serving as a high-impedance active load. Due to the requirements of subsequent control methods, the first current source n×I1 is greater than the second current source m×I1, the second current source m×I1 is greater than the third current source I1, and the fourth current source m×I3 is greater than the fifth current source I3. For example... Figure 1 As shown, the third current source is represented by I1, the first current source is n times the third current source, represented by n×I1, the second current source is m times the third current source, represented by m×I1, and n>m. The fifth current source is represented by I3, and the fourth current source is m times the fifth current source, represented by m×I3.

[0039] In some embodiments, the first current source n×I1, the second current source m×I1, and the fourth current source m×I3 are all proportional mirror current sources.

[0040] Specifically, a proportional current mirror is an improved current source circuit that achieves proportional current control by introducing a resistor network at the emitter of the current mirror, thus overcoming the limitations of the basic current mirror in high-current or low-current scenarios. This implementation employs a proportional current mirror to address the technical challenge of requiring high current in low-current scenarios.

[0041] Technical benefits: Since the first current source n×I1, the second current source m×I1, and the fourth current source m×I3 are all proportional mirror current sources, the current flowing into the input terminal of the power transistor can be amplified proportionally. This allows the power transistor to quickly enter the linear region, reduces the on-resistance, improves the turn-on speed, and correspondingly reduces losses.

[0042] On the other hand, such as Figure 3 As shown, this embodiment of the invention also provides an H-bridge power transistor drive control method, based on an H-bridge power transistor drive circuit provided in any of the above embodiments, which includes the following steps:

[0043] Step S110: Based on the driving circuit, control the power transistor to turn on in segments.

[0044] Specifically, both the high-side and low-side power transistors of the H-bridge are NMOS transistors to reduce on-resistance. A charge pump circuit is needed to increase the gate-source voltage of the power transistors, ensuring they operate at their optimal state. By using a drive circuit to control the power transistors' turn-on in stages, losses and heat generation from Miller capacitance are reduced, while noise from overshoot is avoided.

[0045] Step S120: In response to the received shutdown signal, control the power transistor to shut down based on the drive circuit.

[0046] The shutdown signal is sent by the terminal.

[0047] Specifically, the terminal is the user end. The user determines the drive duration of the H-bridge power transistors based on actual needs when the terminal sends a shutdown signal. If no further driving is required, the user sends a shutdown signal based on the terminal. Upon receiving this shutdown signal, the power circuit, based on the drive circuit, responds by shutting down the power transistor.

[0048] Beneficial effects: By adding high-side and low-side drive voltages and using multiple current sources as current inputs, the power transistor's input current is increased, allowing it to quickly enter the linear region, reducing on-resistance, improving turn-on speed, and correspondingly reducing losses. Furthermore, individual switches are installed at each current source, allowing the current input to the power transistor to be reduced by disconnecting some current source switches after the gate-source voltage has stabilized at the set value, effectively preventing overshoot and reducing noise. Moreover, directly shutting down the corresponding fourth and seventh switches quickly shuts down the entire drive circuit, significantly improving turn-off speed and reducing circuit losses. This solves the technical problems of slow turn-on and turn-off speeds leading to increased losses and reduced efficiency in existing technologies.

[0049] In some embodiments, such as Figure 4 As shown, step S110 further includes: Step S111: Based on the sub-high-side driving circuit, segmentally control the high-side power transistor to turn on. Step S112: Based on the sub-low-side driving circuit, segmentally control the low-side power transistor to turn on. Specifically, steps S111 and S112 are performed simultaneously, without distinction in order. Only the turn-on control of the low-side power transistor and the high-side power transistor is considered. The following embodiments describe steps S111 and S112 in detail, and will not be repeated here.

[0050] In some embodiments, such as Figure 5 As shown, step S111 above further includes:

[0051] Step S210: Turn on the first switch, the second switch and the third switch, and keep the fourth switch in the off state. Charge the high-side power transistor based on the first current source, the second current source and the third current source to turn on the high-side power transistor.

[0052] Specifically, in combination Figure 1It can be seen that the first switches S1 and S8, the second switches S2 and S9, and the third switches S3 and S10 are turned on, while the fourth switch S4 and S11 remain in the off state. At this time, the high-side power transistors MN1 and MN3 are charged with a large current of (m+n+1)×I1, specifically charging the Cgs (gate-source capacitance) and Cgd (drain-source capacitance) of the high-side power transistors MN1 and MN3. The duration t1 causes the gate-source voltage of the high-side power transistors to rise, transitioning the power transistors from the turn-on region through the saturation region to the linear region.

[0053] Step S220: If it is detected that the voltage of the high-side power transistor transitions from the saturation region to the linear region, the first switch is turned off, and the high-side power transistor is charged based on the second current source and the third current source to reduce the charging current of the high-side power transistor.

[0054] Specifically, to increase the gate-source voltage of the high-side power transistors, when the power transistors transition from turn-on through the saturation region to the linear region, the first switches S1 and S8 need to be disconnected. The current then decreases to (m+1)×I1, continuing to charge the Cgs (gate-source capacitance) of the high-side power transistors MN1 and MN3. This process, lasting from t2 to t1, allows the gate-source voltage of the power transistors to continue increasing, further reducing the on-resistance of the power transistors.

[0055] Step S230: If the second switch is detected to have been on for a preset duration, the second switch is turned off, and the high-side power transistor is charged based on the third current source to turn on the high-side power transistor.

[0056] Specifically, the preset duration t2 is determined based on user requirements and the parameters of the high-side power transistors. It is determined that after charging to t2, the high-side power transistors are in a relatively optimal state. Therefore, the second switches S2 and S9 are disconnected, reducing the current I1 to charge the Cgs of the high-side power transistors MN1 and MN3, ensuring that MN1 and MN3 operate in their optimal state. Until a shutdown signal is received, the high-side power transistors MN1 and MN3 require a current of I1 to remain in the on state.

[0057] Beneficial effects: The segmented turn-on process of the high-side power transistor is further refined. By turning on and off the switches corresponding to each current source, the segmented control of the high-side power transistor can be achieved quickly. By setting the current magnitude and switching conditions of each stage, the high-side power transistor can achieve better performance in terms of speed, loss and noise during the turn-on process.

[0058] In some embodiments, such as Figure 6 As shown, step S112 further includes:

[0059] Step S310: Turn on the fifth and sixth switches and keep the seventh switch in the off state. Charge the low-side power transistor based on the fourth and fifth current sources to turn on the low-side power transistor.

[0060] Specifically, in combination Figure 1 It can be seen that when the fifth switch S5, S12 and the sixth switch S6, S13 are turned on, and the seventh switch S7, S14 is kept in the off state, the corresponding current (m+1)×I3 is used to charge the Cgs and Cgd of the low-side power transistors MN2 and MN4 for a duration of t4, which increases the gate-source voltage of the low-side power transistors MN2 and MN4, so that the power transistors turn on, pass through the saturation region, and transition to the linear region with a smaller on-resistance.

[0061] Step S320: If it is detected that the voltage of the low-side power transistor transitions from the saturation region to the linear region, the fifth switch is turned off, and the low-side power transistor is charged based on the fifth current source to complete the turn-on of the low-side power transistor.

[0062] Specifically, when the voltage of the low-side power transistor is detected to transition from the saturation region to the linear region, the fifth switches S5 and S12 need to be disconnected to reduce the current to I3 and continue charging the Cgs of the power transistor, so that the low-side power transistor operates in its optimal state. Before receiving a shutdown signal, the high-side power transistors MN1 and MN3 require a current of I1 to ensure they remain in the on state.

[0063] Beneficial effects: The segmented turn-on process of the low-side power transistor has been further refined. By turning on and off the switches corresponding to each current source, the segmented control of the low-side power transistor can be achieved quickly. By setting the current magnitude and switching conditions for each stage, the low-side power transistor can achieve better performance in terms of speed, loss and noise during the turn-on process.

[0064] In some embodiments, such as Figure 7 As shown, step S120 further includes:

[0065] Step S121: In response to the received shutdown signal, control the high-side power transistor to shut down based on the high-side drive circuit.

[0066] Specifically, the shutdown signal is issued by the terminal, which needs to terminate the operation of the H circuit. Therefore, it is necessary to respond to the received shutdown signal and control the high-side power transistor to shut down based on the high-side drive circuit.

[0067] Step S122: In response to the received shutdown signal, control the low-side power transistor to turn off based on the low-side drive circuit.

[0068] Specifically, since it is necessary to respond to the received shutdown signal, the low-side power transistor also needs to be turned off. Therefore, it is necessary to control the low-side power transistor to turn off based on the low-side drive circuit. It should be noted that there is no order between steps S121 and S122; they are performed simultaneously.

[0069] Beneficial effects: The steps for controlling the power transistor to turn off are further refined; by controlling the high-side power transistor to turn off based on the high-side driving circuit and the low-side power transistor to turn off based on the low-side driving circuit, the technical solution of the present invention is enriched.

[0070] In some embodiments, step S121 further includes: responding to the received shutdown signal, turning on the fourth switch to cut off the charging current to the high-side power transistor, thereby completing the shutdown of the high-side power transistor.

[0071] Specifically, turning on the fourth switches S4 and S11 will directly ground the input terminals of the high-side power transistors MN1 and MN3, thereby quickly cutting off the charging current of the high-side power transistors MN1 and MN3, and thus turning off the high-side power transistors MN1 and MN3.

[0072] Beneficial effects: The method for turning off the high-side power transistor has been further refined. By turning on the fourth switch, the input terminal of the high-side power transistor is directly grounded, thereby quickly cutting off the charging current of the high-side power transistor and achieving rapid shutdown of the high-side power transistor, which greatly improves the shutdown efficiency of the high-side power transistor.

[0073] In some embodiments, step S122 further includes: responding to the received shutdown signal, turning on the seventh switch to cut off the charging current to the low-side power transistor, thereby completing the shutdown of the low-side power transistor.

[0074] Specifically, turning on the seventh switches S7 and S14 will directly ground the input terminals of the low-side power transistors MN2 and MN4, thereby quickly cutting off the charging current of the low-side power transistors MN2 and MN4, and thus turning off the low-side power transistors MN2 and MN4.

[0075] Beneficial effects: The method for turning off the low-side power transistor has been further refined. By turning on the seventh switch, the input terminal of the low-side power transistor is directly grounded, thereby quickly cutting off the charging current of the low-side power transistor and achieving rapid shutdown of the low-side power transistor, which greatly improves the shutdown efficiency of the low-side power transistor.

[0076] In some embodiments, such as Figure 8 As shown, a schematic diagram of the power transistors' on and off signals is provided. Based on the method in the above embodiments, the H-bridge power transistor drive circuit is controlled. The specific switching signals of each high-side power transistor and low-side power transistor are as follows: Figure 8As shown in the figure, combined with the above-described embodiments of segmented power transistor activation and deactivation, the activation process of the high-side power transistor is as follows:

[0077] The first stage: A large current (m+n+1)×I1 is used to charge the Cgs and Cgd of the high-side power transistor for a duration of t1, increasing the gate-source voltage of the power transistor. This causes the transistor to turn on, pass through the saturation region, and transition to the linear region. Correspondingly... Figure 8 During the t1 period of the switching signal of the high-side power transistor, the first switches S1 and S8, the second switches S2 and S9, and the third switches S3 and S10 are simultaneously turned on.

[0078] The second stage: Reduce the current to (m+1)×I1 to continue charging the Cgs of the high-side power transistor for a duration of t2-t1, causing the gate-source voltage of the power transistor to continue to rise, further reducing the on-resistance of the power transistor. Corresponding to... Figure 8 During the t2-t1 period of the switching signal of the high-side power transistor, the first switches S1 and S8 are disconnected, while the second switches S2 and S9 and the third switches S3 and S10 are continuously turned on.

[0079] The third stage: Continue to reduce the current until I1 charges the Cgs of the power transistor, allowing the high-side power transistor to operate in its optimal state, until a power transistor shutdown signal is received. Figure 8 During the t3-t2 period of the switching signal of the high-side power transistor, the first switches S1 and S8 and the second switches S2 and S9 are disconnected, while the third switches S3 and S10 remain connected. Here, t3 is the duration of the entire turn-on process.

[0080] Because the current is large in the first stage of the high-side power transistor turn-on process, the power transistor quickly enters the linear region, reducing the on-resistance and reducing losses; the current decreases slightly in the second stage, but is still large, which quickly increases the gate-source voltage and reduces the on-resistance; the current is smaller in the third stage, which allows the gate-source voltage to reach the set value smoothly, effectively preventing overshoot and reducing noise.

[0081] For the high-side power transistor turn-off process:

[0082] Directly turn on the fourth switch S4 and S11 to turn off the high-side power transistor. The turn-off phase is... Figure 8 The "Switch S4 on / off signal" is at a high level (conduction signal) during this stage.

[0083] The turn-on process for the low-side power transistor is as follows:

[0084] The first stage: A relatively large current (m+1)×I3 is used to charge the Cgs and Cgd of the low-side power transistor for a duration of t4, causing the gate-source voltage of the power transistor to rise, transitioning it from the power transistor's turn-on state through the saturation region to a state with low on-resistance in the linear region. Correspondingly... Figure 8During the t4 period of the switching signal of the low-side power transistor, the fifth switch S5 and S12 and the sixth switch S6 and S13 are turned on.

[0085] The second stage: Reduce the current to I3 to continue charging the Cgs of the low-side power transistor, keeping the power transistor operating in its optimal state until a power transistor shutdown signal is received. (Corresponding...) Figure 8 During the t5-t4 period of the switching signal of the low-side power transistor, the fifth switches S5 and S12 are turned off, while the sixth switches S6 and S13 remain on. Here, t5 is the duration of the entire turn-on process.

[0086] Because the current is large in the first stage of the low-side power transistor's turn-on process, the power transistor quickly enters the linear region, reducing the on-resistance and losses; the current is smaller in the second stage, which allows the gate-source voltage to reach the set value smoothly, effectively preventing overshoot and reducing noise.

[0087] For the low-side power transistor turn-off process:

[0088] Directly turn on the seventh switch S7 and S14 to turn off the low-side power transistor. The turn-off phase is... Figure 8 The "Switch S7 on / off signal" is at a high level (conduction signal) during this stage.

[0089] Figure 9 The diagram illustrates a structural schematic of an embodiment of the computer device of the present invention, which shows a structural schematic of a computer system suitable for implementing the computer device of the present invention. The specific embodiments of the present invention do not limit the specific implementation of the computer device.

[0090] Please see Figure 9 As shown, the computer device includes: a controller; and a memory for storing one or more programs, which, when executed by the controller, perform the aforementioned H-bridge power transistor drive control method.

[0091] Please continue reading. Figure 9As shown, the computer system 400 of this computer device includes a Central Processing Unit (CPU) 401, which can perform various appropriate actions and processes, such as executing the methods described in the above embodiments, based on programs stored in Read-Only Memory (ROM) 402 or programs loaded from storage portion 408 into Random Access Memory (RAM) 403. The RAM 403 also stores various programs and data required for system operation. The CPU 401, ROM 402, and RAM 403 are interconnected via a bus 404. An Input / Output (I / O) interface 405 is also connected to the bus 404.

[0092] The following components are connected to I / O interface 405: an input section 406 including a keyboard, mouse, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to I / O interface 405 as needed. A removable medium 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 410 as needed so that computer programs read from it can be installed into storage section 408 as needed.

[0093] In particular, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 409, and / or installed from removable medium 411. When the computer program is executed by central processing unit (CPU) 401, it performs various functions defined in the system of the present invention.

[0094] Another aspect of the present invention provides a computer-readable storage medium storing at least one executable instruction that, when executed on a computer device / equipment, causes the computer device / equipment to perform an H-bridge power transistor drive circuit and control method as described in any of the above embodiments.

[0095] Beneficial effects: By adding high-side and low-side drive voltages and using multiple current sources as current inputs, the power transistor can quickly enter the linear region by increasing the current input at its input terminal, reducing on-resistance, improving turn-on speed, and correspondingly reducing losses. Furthermore, by setting individual switches at each current source, the current input at the power transistor's input terminal can be reduced by disconnecting some current source switches after the gate-source voltage has stably reached the set value, effectively preventing overshoot and reducing noise. Moreover, directly shutting down the corresponding fourth and seventh switches allows for rapid shutdown of the entire drive circuit, significantly improving shutdown speed and reducing circuit losses. This solves the technical problems of slow turn-on and shutdown speeds leading to increased losses and reduced efficiency in existing technologies.

[0096] It should be noted that the computer-readable medium shown in the embodiments of this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0097] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0099] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0100] According to one aspect of the embodiments of this application, a computer system is also provided, including a Central Processing Unit (CPU), which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) or a program loaded from storage into random access memory (RAM), such as performing the methods described above. Various programs and data required for system operation are also stored in the RAM. The CPU, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0101] The following components are connected to the I / O interface: input components including keyboards, mice, etc.; output components including cathode ray tubes (CRTs), liquid crystal displays (LCDs), and speakers; storage components including hard drives; and communication components including network interface cards such as LAN (Local Area Network) cards and modems. The communication components perform communication processing via networks such as the Internet. Drives are also connected to the I / O interface as needed. Removable media, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on the drive as needed so that computer programs read from them can be installed into the storage components as required.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An H-bridge power transistor driving circuit, characterized in that, The system includes an H-bridge circuit and a driving circuit, wherein the driving circuit includes a high-side driving circuit and a low-side driving circuit; the H-bridge includes power transistors and an inductive load; wherein the power transistors include high-side power transistors and bottom-side power transistors; and all power transistors are coupled between the power supply voltage and ground. The high-side drive circuit includes two symmetrically arranged sub-high-side drive circuits; each sub-high-side drive circuit is connected to a corresponding high-side power transistor; each sub-high-side drive circuit includes a high-side drive voltage, a first current source, a second current source, a third current source, a first switch, a second switch, a third switch, and a fourth switch; the first current source and the first switch are connected in series between the power supply voltage and the input terminal of the corresponding high-side power transistor; the second current source and the second switch are connected in series between the high-side drive voltage and the input terminal of the corresponding high-side power transistor; the third current source and the third switch are connected in series between the high-side drive voltage and the input terminal of the corresponding high-side power transistor; the fourth switch is connected between the input terminal of the corresponding high-side power transistor and ground. The low-side drive circuit includes two symmetrically arranged sub-low-side drive circuits; each sub-low-side drive circuit is connected to a corresponding low-side power transistor; each sub-low-side drive circuit includes a low-side drive voltage, a fourth current source, a fifth current source, a fifth switch, a sixth switch, and a seventh switch; the fourth current source and the fifth switch are connected in series between the low-side drive voltage and the input terminal of the corresponding low-side power transistor; the fifth current source and the sixth switch are connected in series between the low-side drive voltage and the input terminal of the corresponding low-side power transistor; the seventh switch is connected between the input terminal of the corresponding low-side power transistor and ground.

2. The H-bridge power transistor driving circuit according to claim 1, characterized in that, The first current source, the second current source, and the fourth current source are all mirror current sources, wherein the first current source is greater than the second current source, the second current source is greater than the third current source, and the fourth current source is greater than the fifth current source.

3. The H-bridge power transistor driving circuit according to claim 2, characterized in that, The first current source, the second current source, and the fourth current source are all proportional mirror current sources.

4. A method for driving and controlling H-bridge power transistors, characterized in that, An H-bridge power transistor driving circuit according to any one of claims 1-3 includes: Based on the driving circuit, the power transistor is controlled to turn on in segments; In response to the received shutdown signal, the power transistor is controlled to shut down based on the drive circuit; wherein the shutdown signal is issued by the terminal.

5. The method according to claim 4, characterized in that, The step of controlling the power transistor to turn on in segments based on the driving circuit further includes: Based on the aforementioned high-side driving circuit, the high-side power transistor is controlled to turn on in segments; Based on the aforementioned low-side drive circuit, the low-side power transistor is turned on in segments.

6. The method according to claim 5, characterized in that, The step of controlling the high-side power transistor to turn on in segments based on the sub-high-side driving circuit further includes: The first switch, the second switch, and the third switch are turned on, while the fourth switch is kept in the off state. The high-side power transistor is charged based on the first current source, the second current source, and the third current source to turn on the high-side power transistor. If the voltage of the high-side power transistor is detected to transition from the saturation region to the linear region, the first switch is disconnected, and the high-side power transistor is charged based on the second current source and the third current source to reduce the charging current of the high-side power transistor. If the second switch is detected to have been on for a preset duration, the second switch is turned off, and the high-side power transistor is charged based on the third current source to turn on the high-side power transistor.

7. The method according to claim 5, characterized in that, The step of controlling the low-side power transistor to turn on in segments based on the sub-low-side driving circuit further includes: The fifth and sixth switches are turned on, while the seventh switch is kept off. The low-side power transistor is charged based on the fourth and fifth current sources to turn on the low-side power transistor. If the voltage of the low-side power transistor is detected to transition from the saturation region to the linear region, the fifth switch is disconnected, and the low-side power transistor is charged based on the fifth current source to complete the turn-on of the low-side power transistor.

8. The method according to claim 4, characterized in that, The step of controlling the power transistor to turn off based on the received shutdown signal and the driving circuit further includes: In response to the received shutdown signal, the high-side power transistor is controlled to shut down based on the high-side drive circuit; In response to the received shutdown signal, the low-side power transistor is controlled to shut down based on the low-side drive circuit.

9. The method according to claim 8, characterized in that, The step of controlling the high-side power transistor to turn off based on the high-side drive circuit in response to the received shutdown signal further includes: In response to the received shutdown signal, the fourth switch is turned on to cut off the charging current to the high-side power transistor, thereby shutting down the high-side power transistor.

10. The method according to claim 8, characterized in that, The step of controlling the low-side power transistor to turn off based on the low-side drive circuit in response to the received shutdown signal further includes: In response to the received shutdown signal, the seventh switch is turned on to cut off the charging current to the low-side power transistor, thereby shutting down the low-side power transistor.

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