Multi-channel acquisition synchronization method and system for closed-loop calibration
By using a closed-loop calibration method, the synchronization deviation problem of the multi-channel acquisition system under environmental changes and chip aging was solved, thereby improving the stability and accuracy of multi-channel synchronous acquisition and adapting to delay deviation changes caused by various environments.
Patent Information
- Application Number
- CN202511017047.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-11-18
AI Technical Summary
Traditional multi-channel acquisition systems, under conditions of environmental changes and chip aging, cannot adapt to changes in clock distribution and acquisition signal link deviations due to fixed calibration values. This leads to loss of synchronization in acquisition, affecting receiver sensitivity and beam pointing accuracy.
A closed-loop calibration method is adopted, which ensures synchronous acquisition by matching clock traces and using the same clock source. The frequency synthesizer board inputs a sinusoidal signal with the same phase, calculates the synchronization delay difference between each channel, and adjusts the channel delay through coarse and fine adjustment to achieve multi-channel synchronization.
It realizes synchronous status perception of multi-board and multi-channel acquisition systems, improves synchronization accuracy and system stability, adapts to environmental changes, and reduces adjustment errors between channels.
Smart Images
Figure CN120979441A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-channel acquisition technology, and more specifically, to a closed-loop calibration method and system for multi-channel acquisition synchronization. Background Technology
[0002] Traditional multi-channel acquisition calibration is typically a single, fixed calibration, requiring high consistency between the board layout and the clock chip. Once the calibration value is written to the firmware, it cannot be modified. Due to open-loop control, it's impossible to know whether synchronous sampling accuracy is met after each power-on. In engineering applications, environmental factors, chip aging, and other factors can cause deviations in clock distribution and the acquisition signal link. Fixed calibration values cannot adapt to these changes, leading to asynchronous acquisition, decreased antenna DBF (Digital Beam Forming) gain, and severely impacting receiver sensitivity and beam pointing accuracy.
[0003] Therefore, it is very necessary and of great engineering significance to study a closed-loop calibration method for multi-channel acquisition synchronization. Summary of the Invention
[0004] This invention aims to provide a closed-loop calibration method for multi-channel acquisition synchronization, in order to solve the problem that the power-on acquisition synchronization deviation caused by various delays due to differences in clock distribution and acquisition signal links caused by hardware wiring in multi-board and multi-channel acquisition synchronization systems cannot be solved by conventional fixed compensation.
[0005] This invention provides a multi-channel acquisition synchronization method for closed-loop calibration, comprising: Step 1: Ensure synchronous sampling of each channel's ADC in the multi-channel synchronous acquisition system by matching clock traces and ensuring clock coherence. Step 2: Input a sinusoidal signal with frequency F1 to the ARM control calibration terminal of the frequency synthesizer board; Step 3: The frequency synthesizer board sends a synchronization acquisition request. The acquisition board samples the in-phase sine wave signal according to the synchronization acquisition request and transmits the sampled data to the frequency synthesizer board. Step 4: The frequency synthesizer board reads the sampled data and calculates the synchronization delay difference between each channel based on the sampled data; Step 5: Using one channel as a reference, adjust the delay of each channel in turn to eliminate the synchronization delay difference between channels; Step 6: Determine whether the synchronization delay difference between each channel meets the error requirements. If it does, stop reading the signal and complete the calibration; otherwise, return to step 2 to re-perform the calibration.
[0006] In a preferred embodiment, step 1 specifically includes: Reset the general SYSREF timer of each HMC7044 clock chip in the clock tree to perform phase alignment on the output of the HMC7044 clock chip. Alignment of LMFCs between receiving acquisition boards is achieved through the SYSREF signal of JESD204B protocol subclass 1.
[0007] In a preferred embodiment, in step 2, the frequency F1 is selected as the lowest frequency mirrored to the first Nyquist zone.
[0008] In a preferred embodiment, step 3 specifically includes: The frequency synthesis board simultaneously initiates a synchronous acquisition request for ADC sampling data to the acquisition board via GPIO; After receiving the synchronous acquisition request, the acquisition board generates a request enable based on the rising edge of the synchronous acquisition request. When rx_start_multf of the JESD204B protocol is 1, it enables the ADC sampling data of the 4 channels to be written to the FIFO. The acquisition board sends the buffered data in the FIFO to the frequency synthesis board via the UART protocol.
[0009] In a preferred embodiment, in step 4, the synchronization delay difference between channels is calculated using FFT and CORDIC.
[0010] In a preferred embodiment, when calculating the synchronization delay difference between channels, the three adjacent sampling points with the largest amplitude are selected, and a second-order polynomial is used for curve fitting. The derivative is used to obtain the value of the sampling point corresponding to the largest amplitude. The difference between the sampling point values corresponding to the largest amplitude between channels is the synchronization delay difference between channels.
[0011] In a preferred embodiment, in step 5, different methods are used to eliminate the synchronization delay difference between channels according to the delay step.
[0012] In a preferred embodiment, step 5 specifically includes: For large step delays with an integer number of sampling points difference, the synchronization delay difference is coarsely adjusted by shifting the sampling sequence. For small step delays that differ by several sampling points, the synchronization delay difference can be finely adjusted by adjusting the ADC delay register.
[0013] In a preferred embodiment, a set number of recalibration cycles is provided, and calibration is stopped when the number of recalibration cycles is reached.
[0014] The present invention also provides a multi-channel acquisition synchronization system for closed-loop calibration, the multi-channel acquisition synchronization system comprising multiple multi-channel acquisition boards, a frequency synthesis board, a power supply board and a backplane; The acquisition board and frequency synthesizer board use the aforementioned closed-loop calibration multi-channel acquisition synchronization method to perform multi-channel synchronous acquisition.
[0015] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention achieves synchronization status perception through a multi-board, multi-channel acquisition synchronization method with closed-loop calibration, ensuring normal acquisition synchronization and providing the necessary conditions for system-wide synchronization.
[0016] 2. This invention combines a polynomial curve fitting algorithm, which can improve the accuracy of reference point selection and reduce reference error.
[0017] 3. This invention combines "coarse calibration" and "fine calibration", which can improve the calibration speed between channels and reduce the adjustment error between channels.
[0018] 4. This invention can adapt to delay deviations caused by various environments, thus improving the stability of the system. Attached Figure Description
[0019] Figure 1 This is a flowchart of a closed-loop calibration multi-channel acquisition synchronization method proposed in an embodiment of the present invention.
[0020] Figure 2 A schematic diagram of the two-level clock tree design in a multi-channel acquisition synchronization system for implementing the above closed-loop calibration multi-channel acquisition synchronization method.
[0021] Figure 3 To implement the above-mentioned closed-loop calibration multi-channel acquisition synchronization method, a schematic diagram is shown in which the high-speed ADC on the acquisition board acquires data, the on-board FPGA processes and frames the data, and then transmits it to the frequency synthesizer board FPGA for parameter point estimation and error calibration. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0024] The multi-channel synchronous acquisition system mainly consists of multiple multi-channel acquisition boards, frequency synthesizer boards, power supply boards, and backplanes. Key components include the AD9689 analog-to-digital converter chip with a JESD204B interface, the HMC7044 high-performance clock chip, an FPGA, and PCB wiring for the clock tree.
[0025] The acquisition board is mainly responsible for configuring ADC chip parameters and clock chip parameters, receiving intermediate frequency signals, reading ADC data streams, and transmitting synchronous data streams to the frequency synthesizer board.
[0026] The frequency integration board is mainly responsible for receiving synchronization data transmitted from each acquisition board, performing synchronization detection and control, and distributing and synchronizing the clock for the entire system.
[0027] The backplane completes the interconnection of signals throughout the entire system.
[0028] The power board performs DC-DC conversion to supply power to each board.
[0029] like Figure 1 As shown in the figure, this invention proposes a multi-channel acquisition synchronization method for closed-loop calibration, comprising the following steps: Step 1: Ensure synchronous sampling of each channel's ADC in the multi-channel synchronous acquisition system by matching clock traces and ensuring clock coherence. Reset the general SYSREF timer of each HMC7044 clock chip in the clock tree to perform phase alignment on the output of the HMC7044 clock chip. Alignment of LMFCs between receiving acquisition boards is achieved through the SYSREF signal of JESD204B protocol subclass 1.
[0030] Step 2: Input a sinusoidal signal with frequency F1 to the ARM control calibration terminal of the frequency synthesizer board; For broadband systems, undersampling is generally used, and frequency F1 is selected as the lowest frequency mirrored to the first Nyquist zone.
[0031] Step 3: The frequency synthesizer board sends a synchronization acquisition request. The acquisition board samples the in-phase sine wave signal according to the synchronization acquisition request and transmits the sampled data to the frequency synthesizer board. The frequency synthesizer board sends a synchronous acquisition request for ADC sampling data (2048 continuous sampling point signals) to the acquisition board via GPIO.
[0032] After receiving the synchronous acquisition request, the acquisition board generates an enable request based on the rising edge of the synchronous acquisition request. When rx_start_multf of the JESD204B protocol is 1, it enables the writing of 4-channel ADC sampling data (2048 points) to the FIFO.
[0033] The acquisition board sends the buffered data in the FIFO to the frequency synthesis board via the UART protocol.
[0034] Step 4: The frequency synthesizer board reads the sampling data (2048 continuous sampling points signal) and calculates the synchronization delay difference between each channel based on the sampling data; In this step, the synchronization delay difference between each channel is calculated using FFT (Fast Fourier Transform) and CORDIC (Coordinate Rotation Digital Computer). When calculating the synchronization delay difference between channels, the three adjacent sampling points with the largest amplitude are selected, and a second-order polynomial is used for curve fitting. The derivative is then used to obtain the value of the sampling point corresponding to the largest amplitude. The difference between the sampling point values corresponding to the largest amplitude in each channel is the synchronization delay difference between channels. Combining this with a polynomial curve fitting algorithm can improve the accuracy of the selection of reference sampling points and reduce errors.
[0035] Step 5: Using one channel (e.g., channel 1) as a reference, adjust the delay of each channel in turn to eliminate the synchronization delay difference between channels; In this step, different methods are used to eliminate the synchronization delay difference between channels based on the delay step. Specifically: For large step delays with an integer number of sampling points difference, the synchronization delay difference is coarsely adjusted by shifting the sampling sequence. For small step delays that differ by a few sampling points, the synchronization delay difference can be finely adjusted by adjusting the ADC delay register (in 15ps steps).
[0036] This step, combining "coarse calibration" and "fine calibration," can improve the calibration speed between channels and reduce the adjustment error between channels.
[0037] Step 6: Determine if the synchronization delay difference between channels meets the error requirements. If it does, stop reading signals and complete the calibration; otherwise, return to Step 2 to re-perform the calibration. The number of re-calibrations can be set, and calibration will stop when the required number of re-calibrations is reached. Typically, the number of re-calibrations, K, can be set according to needs or actual circumstances, for example, K≤5.
[0038] Figure 2 , Figure 3 This paper presents a solution design for a multi-channel acquisition synchronization system based on the aforementioned closed-loop calibration multi-channel acquisition synchronization method. Specifically, Figure 2 A schematic diagram of the two-level clock tree design in a multi-channel acquisition synchronization system for implementing the above closed-loop calibration multi-channel acquisition synchronization method.
[0039] Figure 3 To implement the above-mentioned closed-loop calibration multi-channel acquisition synchronization method, a schematic diagram is shown in which the high-speed ADC on the acquisition board acquires data, the on-board FPGA processes and frames the data, and then transmits it to the frequency synthesizer board FPGA for parameter point estimation and error calibration.
[0040] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A multi-channel acquisition synchronization method for closed-loop calibration, characterized in that, include: Step 1: Ensure synchronous sampling of each channel's ADC in the multi-channel synchronous acquisition system by matching clock traces and ensuring clock coherence. Step 2: Input a sinusoidal signal with frequency F1 to the ARM control calibration terminal of the frequency synthesizer board; Step 3: The frequency synthesizer board sends a synchronization acquisition request. The acquisition board samples the in-phase sine wave signal according to the synchronization acquisition request and transmits the sampled data to the frequency synthesizer board. Step 4: The frequency synthesizer board reads the sampled data and calculates the synchronization delay difference between each channel based on the sampled data; Step 5: Using one channel as a reference, adjust the delay of each channel in turn to eliminate the synchronization delay difference between channels; Step 6: Determine whether the synchronization delay difference between each channel meets the error requirements. If it does, stop reading the signal and complete the calibration; otherwise, return to step 2 to re-perform the calibration.
2. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 1, characterized in that, Step 1 specifically includes: Reset the general SYSREF timer of each HMC7044 clock chip in the clock tree to perform phase alignment on the output of the HMC7044 clock chip. Alignment of LMFCs between receiving acquisition boards is achieved through the SYSREF signal of JESD204B protocol subclass 1.
3. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 1, characterized in that, In step 2, the frequency F1 is selected as the lowest frequency mirrored to the first Nyquist zone.
4. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 1, characterized in that, Step 3 specifically includes: The frequency synthesis board simultaneously initiates a synchronous acquisition request for ADC sampling data to the acquisition board via GPIO; After receiving the synchronous acquisition request, the acquisition board generates a request enable based on the rising edge of the synchronous acquisition request. When rx_start_multf of the JESD204B protocol is 1, it enables the ADC sampling data of the 4 channels to be written to the FIFO. The acquisition board sends the buffered data in the FIFO to the frequency synthesis board via the UART protocol.
5. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 1, characterized in that, In step 4, the synchronization delay difference between each channel is calculated using FFT and CORDIC.
6. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 5, characterized in that, When calculating the synchronization delay difference between channels, select the three adjacent sampling points with the largest amplitude, and use a second-order polynomial for curve fitting. The derivative is used to obtain the value of the sampling point corresponding to the largest amplitude. The difference between the sampling point values corresponding to the largest amplitude between channels is the synchronization delay difference between channels.
7. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 1, characterized in that, In step 5, different methods are used to eliminate the synchronization delay difference between channels according to the delay step.
8. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 7, characterized in that, Step 5 specifically includes: For large step delays with an integer number of sampling points difference, the synchronization delay difference is coarsely adjusted by shifting the sampling sequence. For small step delays that differ by several sampling points, the synchronization delay difference can be finely adjusted by adjusting the ADC delay register.
9. The multi-channel acquisition synchronization method for closed-loop calibration according to claim 1, characterized in that, The number of times to re-perform calibration is set, and calibration stops when the number of re-performations is reached.
10. A multi-channel acquisition and synchronization system for closed-loop calibration, characterized in that, The multi-channel acquisition synchronization system includes multiple multi-channel acquisition boards, frequency synthesis boards, power supply boards, and backplanes; The acquisition board and frequency synthesizer board use the closed-loop calibration multi-channel acquisition synchronization method as described in any one of claims 1-9 to perform multi-channel synchronous acquisition.