Universal BMS gateway circuit

Abstract

The invention discloses a universal BMS (Battery Management System) gateway circuit, which comprises a sending signal conditioning circuit, the input end of which is connected with an FPGA (Field Programmable Gate Array), and the sending signal conditioning circuit is used for converting a first digital signal and a second digital signal output by the FPGA into a first differential signal and a second differential signal which are compatible with a BMS, the phase difference between the first digital signal and the second digital signal is 90 degrees; the input end of the receiving signal conditioning circuit is connected with a secondary coil of the transformer T1, and the receiving signal conditioning circuit is used for converting the first differential signal and the second differential signal into a first phase pulse signal and a second phase pulse signal which can be identified by the FPGA; a primary coil of the transformer T1 is connected with the output end of the sending signal conditioning circuit, and a secondary coil of the transformer T1 is connected with the input end of the receiving signal conditioning circuit, so that signal coupling and electrical isolation are realized. According to the circuit, the test efficiency is improved, and meanwhile, high-fidelity signal transmission and system safety are ensured.

Description

Technical Field

[0001] This invention relates to the field of BMS gateway circuit technology, and more particularly to a general-purpose BMS gateway circuit. Background Technology

[0002] Traditional BMS daisy-chain testing methods rely on specific gateway chips. For example, a BMS designed with NXP's AFE relies on NXP's MC33664, whose standard daisy-chain differential signals are as follows: Figure 1 As shown, existing gateway chips (such as NXP's MC33664 and TI's BQ79600) require customized hardware, leading to frequent board replacements when testing different manufacturers' BMS, resulting in poor compatibility and high signal distortion. There is an urgent need for a fully isolated universal gateway circuit to overcome this technical bottleneck. Summary of the Invention

[0003] To address the technical problems existing in the background art, this invention proposes a universal BMS gateway circuit.

[0004] This invention proposes a universal BMS gateway circuit, comprising:

[0005] The signal conditioning circuit is connected to the FPGA at its input terminal. It converts the first digital signal and the second digital signal output by the FPGA into BMS-compatible first differential signal and second differential signal, wherein the phase difference between the first digital signal and the second digital signal is 90°.

[0006] The receiving signal conditioning circuit has its input terminal connected to the secondary coil of transformer T1, and is used to convert the first differential signal and the second differential signal into a first phase pulse signal and a second phase pulse signal that can be recognized by the FPGA.

[0007] Transformer T1 has its primary coil connected to the output of the transmitting signal conditioning circuit and its secondary coil connected to the input of the receiving signal conditioning circuit, thus achieving signal coupling and electrical isolation.

[0008] Preferably, the transmitting signal conditioning circuit specifically includes: a level conversion chip U1, a π-type filter network, and a transformer T1; the input terminal of the level conversion chip U1 is connected to a first digital signal and a second digital signal, the output terminal of the level conversion chip U1 is electrically connected to the input terminal of the π-type filter network, the output terminal of the π-type filter network is electrically connected to the primary coil of the transformer T1, and the secondary coil of the transformer T1 is electrically connected to the input terminal of the receiving signal conditioning circuit.

[0009] Preferably, the π-type filter network comprises resistance R1, resistance R2, resistance R8, resistance R12, resistance R13, resistance R2, capacitor C1, capacitor C3, transient suppression tube D1 and transient suppression tube D2; wherein the first end of the resistance R2 is connected with the first output end of the level conversion chip U1, the second end of the resistance R2 is connected with the first end of the capacitor C1, the second end of the capacitor C1 is grounded; the first end of the capacitor C1 is connected with the first end of the resistance R1, the second end of the resistance R1 is connected with the first input end of the primary coil of the transformer T1; the first end of the resistance R13 is connected with the first end of the capacitor C1, the second end of the resistance R13 is connected with a 2.5V power supply; the first end of the resistance R8 is connected with the first end of the capacitor C3, the second end of the resistance R8 is connected with the second input end of the primary coil of the transformer T1; the first end of the resistance R12 is connected with the first end of the capacitor C3, the second end of the resistance R12 is connected with a 2.5V power supply; the cathode of the transient suppression tube D1 is connected with the second end of the resistance R1, the anode of the transient suppression tube D1 is grounded; the cathode of the transient suppression tube D2 is connected with the second end of the resistance R8, the anode of the transient suppression tube D2 is grounded.

[0010] Preferably, the receiving signal conditioning circuit comprises: alternating current capacitors C261 and C262, an operational amplifier U8, a first comparator U9 and a second comparator U10; the first output end of the secondary coil of the transformer T1 is connected with the inverting input end of the operational amplifier U8 through the alternating current capacitor C261, the second output end of the secondary coil is connected with the non-inverting input end of the operational amplifier U8 through the alternating current capacitor C262; the output end RX_TI1 of the operational amplifier U8 is a single-ended signal superimposed with a 2.5V bias; the non-inverting input end of the first comparator U9 is connected with a 3V reference voltage, and the inverting input end is connected with RX_TI1; the inverting input end of the second comparator U10 is connected with a 1V reference voltage, and the non-inverting input end is connected with RX_TI1; the output end of the first comparator U9 outputs a rising edge pulse signal RXB1_P_TEMP, and the output end of the second comparator U10 outputs a falling edge pulse signal RXB1_N_TEMP.

[0011] Preferably, the model of the operational amplifier U8 is ADA4807-1, and the response time of the first comparator U9 and the second comparator U10 is less than 10ns.

[0012] Preferably, the reference voltage of the first comparator U9 is 3V, and the reference voltage of the second comparator U10 is 1V.

[0013] Preferably, the transient suppression tubes D1 and D2 are SMAJ series TVS diodes with a breakdown voltage of 5.5V±10%.

[0014] Preferably, the level conversion chip U1 is SN74LVC8T245PWR, the input end of the level conversion chip U1 supports 3.3V level, and the output end of the level conversion chip U1 provides 5V±5% level.

[0015] In the application, the universal BMS gateway circuit is proposed, the 90° phase digital signal of the FPGA is converted into a standardized daisy chain differential signal through a sending signal conditioning circuit, meanwhile, the receiving signal conditioning circuit utilizes a double-comparator decoding mechanism to accurately restore the BMS differential pulse into an edge signal recognizable by the FPGA, and the electrical isolation is realized by cooperating with a common transformer, so that a single hardware platform is compatible with different AFE chip protocols, the hardware replacement operation in the test process is completely eliminated, the test efficiency is improved, and the high-fidelity signal transmission and system safety are ensured. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a schematic diagram of the standard daisy chain differential signal of the prior art MC33664;

[0017] Figure 2 It is a circuit architecture schematic diagram of the universal BMS gateway circuit proposed in the application;

[0018] Figure 3 It is a structure schematic diagram of an embodiment of the sending signal conditioning circuit of the universal BMS gateway circuit proposed in the application;

[0019] Figure 4 It is a structure schematic diagram of an embodiment of the receiving signal conditioning circuit of the universal BMS gateway circuit proposed in the application;

[0020] Figure 5 It is a signal waveform diagram of the comparator U9 of the universal BMS gateway circuit proposed in the application;

[0021] Figure 6 It is a signal waveform diagram of the comparator U10 of the universal BMS gateway circuit proposed in the application;

[0022] Figure 7 It is a phase comparison diagram of the rising edge pulse RXB1_P_TEMP and the falling edge pulse RXB1_N_TEMP of the universal BMS gateway circuit proposed in the application;

[0023] Figure 8 It is a circuit implementation schematic diagram of the universal BMS gateway circuit proposed in the application. DETAILED DESCRIPTION

[0024] REFERENCE Figures 2-8 The universal BMS gateway circuit proposed in the application comprises:

[0025] The sending signal conditioning circuit is connected with the FPGA at the input end, converts the first digital signal and the second digital signal output by the FPGA into the first differential signal and the second differential signal compatible with the BMS, and the phase difference between the first digital signal and the second digital signal is 90°.

[0026] In the embodiment, the sending signal conditioning circuit specifically comprises a level conversion chip U1, a pi filter network and a transformer T1; the input end of the level conversion chip U1 is connected with the first digital signal and the second digital signal, the output end of the level conversion chip U1 is electrically connected with the input end of the pi filter network, the output end of the pi filter network is electrically connected with the primary coil of the transformer T1, and the secondary coil of the transformer T1 is electrically connected with the input end of the receiving signal conditioning circuit.

[0027] In the embodiment, the pi filter network comprises a resistor R1, a resistor R2, a resistor R8, a resistor R12, a resistor R13, a resistor R2, a capacitor C1, a capacitor C3, a transient suppression tube D1 and a transient suppression tube D2; the first end of the resistor R2 is connected with the first output end of the level conversion chip U1, the second end of the resistor R2 is connected with the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; the first end of the capacitor C1 is connected with the first end of the resistor R1, and the second end of the resistor R1 is connected with the first input end of the primary coil of the transformer T1; the first end of the resistor R13 is connected with the first end of the capacitor C1, and the second end of the resistor R13 is connected with a 2.5V power supply; the first end of the resistor R8 is connected with the first end of the capacitor C3, and the second end of the resistor R8 is connected with the second input end of the primary coil of the transformer T1; the first end of the resistor R12 is connected with the first end of the capacitor C3, and the second end of the resistor R12 is connected with the 2.5V power supply; the cathode of the transient suppression tube D1 is connected with the second end of the resistor R1, and the anode of the transient suppression tube D1 is grounded; the cathode of the transient suppression tube D2 is connected with the second end of the resistor R8, and the anode of the transient suppression tube D2 is grounded.

[0028] In the embodiment, the transient suppression tubes D1 and D2 are SMAJ series TVS diodes with a breakdown voltage of 5.5V±10%.

[0029] Specifically, the level conversion chip U1 is SN74LVC8T245PWR, the input end of the level conversion chip U1 supports a 3.3V level, and the output end of the level conversion chip U1 provides a 5V±5% level.

[0030] Specifically, as Figure 2 and Figure 3As shown, the transmitting signal conditioning circuit converts the digital signal 0 or 1 generated by the FPGA logic into the daisy chain differential signal ISO_P, ISO_N recognized by the measured BMS controller; the receiving signal conditioning circuit converts the daisy chain differential signal ISO_P, ISO_N sent by the measured BMS controller into the digital signal 0 or 1 recognizable by the FPGA logic. F_TXB1_P, F_TXB1_N are common 0 or 1 signals generated by the FPGA according to the timing requirements, which are subjected to U1 SN74LVC8T245PWR level conversion, filtering, and driving transformer T1. Figure 3 The chip U2 shown is used for U1 SN74LVC8T245PWR level conversion.

[0031] The receiving signal conditioning circuit has an input end connected to the secondary coil of the transformer T1 and is used for converting the first differential signal and the second differential signal into the first phase pulse signal and the second phase pulse signal recognizable by the FPGA.

[0032] In this embodiment, the receiving signal conditioning circuit includes: alternating current capacitors C261 and C262, an operational amplifier U8, a first comparator U9, and a second comparator U10; the first output end of the secondary coil of the transformer T1 is connected to the inverting input end of the operational amplifier U8 through the alternating current capacitor C261, and the second output end of the secondary coil is connected to the non-inverting input end of the operational amplifier U8 through the alternating current capacitor C262; the output end RX_TI1 of the operational amplifier U8 is a single-ended signal superimposed with a 2.5V bias; the non-inverting input end of the first comparator U9 is connected to a 3V reference voltage, and the inverting input end is connected to RX_TI1; the inverting input end of the second comparator U10 is connected to a 1V reference voltage, and the non-inverting input end is connected to RX_TI1; the output end of the first comparator U9 outputs the rising edge pulse signal RXB1_P_TEMP, and the output end of the second comparator U10 outputs the falling edge pulse signal RXB1_N_TEMP.

[0033] In this embodiment, the model of the operational amplifier U8 is ADA4807-1, and the response time of the first comparator U9 and the second comparator U10 is less than 10ns.

[0034] In this embodiment, the reference voltage of the first comparator U9 is 3V, and the reference voltage of the second comparator U10 is 1V.

[0035] Specifically, Figure 5 The blue waveform in the figure is the SPI differential signal IP1_TEMP and IM1_TEMP, and the yellow waveform is the differential signal falling pulse RXB1_P_TEMP captured by the comparator U9. Figure 6The blue color in the figure is the SPI differential signal IP1_TEMP and IM1_TEMP, and the yellow color is the differential signal RXB1_N_TEMP captured by the U10 comparator. The measured daisy chain signal is coupled by T1 to obtain IM1_TEMP and IP1_TEMP; the IM1_TEMP and IP1_TEMP are AC coupled by C261 and C262 to convert the differential signal into a single-ended signal RX_TI1 with a 2.5V bias by the high-speed operational amplifier U8 ADA4807-1; the RX_TI1 enters two high-speed comparators U9 and U10, and the thresholds of the comparators are 3V and 1V respectively. Figure 7 The figure is a phase comparison diagram of the rising edge pulse RXB1_P_TEMP and the falling edge pulse RXB1_N_TEMP, as shown in the figure. Figure 7 The blue color is the RXB1_P_TEMP signal entering the FPG, and the yellow color is the RXB1_N_TEMP signal entering the FPG. The U9 and U10 convert the RX_TI1 into the rising edge pulse RXB1_P_TEMP and the falling edge pulse RXB1_N_TEMP with special phase information, and the two signals enter the FPGA; the FPGA identifies 0 or 1 through the received rising edge and falling edge pulses with special phase information; thus, the daisy chain differential signal is converted into the normal 0 or 1 signal.

[0036] The transformer T1 is connected to the output end of the sending signal conditioning circuit and the input end of the receiving signal conditioning circuit, so as to realize signal coupling and electrical isolation.

[0037] In the embodiment, the sending signal conditioning circuit converts the digital signal generated by the FPGA logic into the daisy chain differential signal recognized by the measured BMS controller; the receiving signal conditioning circuit converts the daisy chain differential signal sent by the measured BMS controller into the digital signal recognizable by the FPGA logic; the receiving and sending realize the full-duplex communication function of the specific gateway chip. In essence, the general circuit encodes the normal 0 or 1 signal into the ISO_P and ISO_N differential signal recognizable by the daisy chain, and simultaneously decodes the differential signal ISO_P and ISO_N of the daisy chain into the normal 0 or 1 signal recognizable by the FPGA logic.

[0038] The above is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A universal BMS gateway circuit, characterized by, The application relates to a signal transmission and reception device. The signal transmission and reception device comprises a sending signal conditioning circuit, a receiving signal conditioning circuit and a transformer T1. The sending signal conditioning circuit is connected with the FPGA at the input end, converts the first digital signal and the second digital signal output by the FPGA into BMS compatible first differential signals and second differential signals, and the phase difference between the first digital signal and the second digital signal is 90 degrees. The receiving signal conditioning circuit is connected with the secondary coil of the transformer T1 at the input end, and is used for converting the first differential signals and the second differential signals into first phase pulse signals and second phase pulse signals recognizable by the FPGA.

2. The universal BMS gateway circuit of claim 1, wherein, The primary coil of the transformer T1 is connected with the output end of the sending signal conditioning circuit, and the secondary coil is connected with the input end of the receiving signal conditioning circuit, so that signal coupling and electrical isolation are realized.

3. The universal BMS gateway circuit of claim 2, wherein, The sending signal conditioning circuit specifically comprises a level conversion chip U1, a pi-type filter network and the transformer T1. The input end of the level conversion chip U1 is connected with the first digital signal and the second digital signal, the output end of the level conversion chip U1 is electrically connected with the input end of the pi-type filter network, the output end of the pi-type filter network is electrically connected with the primary coil of the transformer T1, and the secondary coil of the transformer T1 is electrically connected with the input end of the receiving signal conditioning circuit. The pi-type filter network comprises resistors R1, R2, R8, R12, R13, a capacitor C1, a capacitor C3, a transient suppression tube D1 and a transient suppression tube D2. The first end of the resistor R2 is connected with the first output end of the level conversion chip U1, the second end of the resistor R2 is connected with the first end of the capacitor C1, and the second end of the capacitor C1 is grounded. The first end of the capacitor C1 is connected with the first end of the resistor R1, and the second end of the resistor R1 is connected with the first input end of the primary coil of the transformer T1. The first end of the resistor R13 is connected with the first end of the capacitor C1, and the second end of the resistor R13 is connected with a 2.5V power supply. The first end of the resistor R8 is connected with the first end of the capacitor C3, and the second end of the resistor R8 is connected with the second input end of the primary coil of the transformer T1. The first end of the resistor R12 is connected with the first end of the capacitor C3, and the second end of the resistor R12 is connected with the 2.5V power supply. The cathode of the transient suppression tube D1 is connected with the second end of the resistor R1, and the anode of the transient suppression tube D1 is grounded. The cathode of the transient suppression tube D2 is connected with the second end of the resistor R8, and the anode of the transient suppression tube D2 is grounded.

4. The universal BMS gateway circuit of claim 1, wherein, The receiving signal conditioning circuit comprises alternating current capacitors C261 and C262, an operational amplifier U8, a first comparator U9 and a second comparator U10; a first output end of a secondary coil of a transformer T1 is connected to an inverting input end of the operational amplifier U8 through the alternating current capacitor C261, and a second output end of the secondary coil is connected to a non-inverting input end of the operational amplifier U8 through the alternating current capacitor C262; an output end RX_TI1 of the operational amplifier U8 is a single-end signal superimposed with a 2.5V bias; a non-inverting input end of the first comparator U9 is connected to a 3V reference voltage, and an inverting input end of the first comparator U9 is connected to RX_TI1; an inverting input end of the second comparator U10 is connected to a 1V reference voltage, and a non-inverting input end of the second comparator U10 is connected to RX_TI1; an output end of the first comparator U9 outputs a rising edge pulse signal RXB1_P_TEMP, and an output end of the second comparator U10 outputs a falling edge pulse signal RXB1_N_TEMP.

5. The universal BMS gateway circuit of claim 4, wherein, The operational amplifier U8 is of ADA4807-1 type, and the response time of the first comparator U9 and the second comparator U10 is less than 10ns.

6. The universal BMS gateway circuit of claim 4, wherein, The reference voltage of the first comparator U9 is 3V, and the reference voltage of the second comparator U10 is 1V.

7. The universal BMS gateway circuit of claim 3, wherein, The transient voltage suppressors D1 and D2 are SMAJ series TVS diodes, and the breakdown voltage is 5.5V±10%.

8. The universal BMS gateway circuit of claim 2, wherein, The level conversion chip U1 is SN74LVC8T245PWR, the input end of the level conversion chip U1 supports a 3.3V level, and the output end of the level conversion chip U1 provides a 5V±5% level.

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