Image coding method and device, electronic equipment and computer program product
By adding an operation pre-state to the video encoding unit and adopting a lock-free concurrency mechanism, the thread contention problem of multi-threaded video encoders is solved, improving the parallel processing efficiency and real-time performance of the encoder.
Patent Information
- Application Number
- CN202511164255.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-19
- Publication Date
- 2025-11-18
AI Technical Summary
In multi-threaded scenarios, traditional video encoders face intense thread contention, leading to reduced CPU throughput, impacting real-time encoding performance, and making it difficult to meet high parallelism requirements.
The image to be encoded is divided into multiple encoding units, and an operation pre-state is added to each encoding unit. The execution conditions of the encoding unit are judged and transformed through a lock-free concurrency mechanism to avoid the locking process and achieve synchronous and parallel processing of the encoding state.
It effectively reduces thread contention, improves parallel coding efficiency, ensures normal execution of the coding process, avoids resource consumption and delays caused by locking, and improves coding efficiency.
Smart Images
Figure CN120980237A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of video coding technology, and more specifically, to an image coding method, an image coding device, an electronic device, and a computer program product. Background Technology
[0002] With the increase in video resolution and the growing demand for real-time encoding, traditional serial encoding processes are struggling to meet performance requirements. To fully utilize the processing power of multi-core CPUs (Central Processing Units), current mainstream video encoders employ multi-granularity, multi-threaded parallel technologies, including parallel transcoding of video segments, parallel video frames, intra-frame tile-based parallel processing, and WPP (Wavefront Parallel Processing) parallel processing based on CTUs (Coding Tree Units).
[0003] In multi-threaded scenarios, parallel processing to ensure error-free encoding typically requires locking. However, with a large number of encoding threads, the encoder has extremely high requirements for parallelism. Locking can lead to intense thread contention, reduced CPU throughput, and consequently, impacted real-time encoding performance.
[0004] Therefore, there is an urgent need in this field for an image encoding method that can effectively reduce thread contention and improve encoding parallel efficiency.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this disclosure is to provide an image encoding method, an image encoding device, an electronic device, and a computer program product, which can at least to some extent effectively reduce thread contention and improve encoding parallel efficiency.
[0007] According to a first aspect of this disclosure, an image encoding method is provided, comprising:
[0008] The image to be encoded is divided into multiple encoding units, and a corresponding operation pre-state is added for each encoding operation to be performed in each encoding unit;
[0009] When the encoding unit is in the pre-operation state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, it is determined whether the encoding unit meets the execution conditions of the target encoding operation; wherein, the pre-encoding unit is the encoding unit on which the encoding unit depends for executing the target encoding operation;
[0010] If the encoding unit meets the execution conditions of the target encoding operation, the encoding unit is changed from the operation pre-operation state of the target encoding operation to the operation execution state, and the encoding unit is controlled to execute the target encoding operation.
[0011] In one exemplary embodiment of this disclosure, the method further includes:
[0012] If the encoding unit does not meet the execution conditions of the target encoding operation, the encoding unit is controlled to wait for the trigger instruction of the target encoding operation sent by the next pre-encoding unit.
[0013] In one exemplary embodiment of this disclosure, determining whether the encoding unit satisfies the execution conditions of the target encoding operation includes:
[0014] Obtain all the pre-encoding units of the encoding unit, and determine whether all the pre-encoding units have completed the target encoding operation;
[0015] If all the pre-encoding units have completed the target encoding operation, then the encoding unit is determined to meet the execution conditions of the target encoding operation;
[0016] If there is a pre-encoding unit that has not completed the target encoding operation, then the encoding unit is determined to have failed to meet the execution conditions of the target encoding operation.
[0017] In one exemplary embodiment of this disclosure, obtaining all pre-coding units of the encoding unit includes:
[0018] Based on the preset coding unit dependency relationship, obtain the preceding coding units that the coding unit depends on to perform the target coding operation.
[0019] In one exemplary embodiment of this disclosure, the method further includes:
[0020] When the encoding unit completes the target encoding operation, the encoding unit is changed from the operation execution state of the target encoding operation to the operation pre-operation state of the next encoding operation.
[0021] In one exemplary embodiment of this disclosure, each of the encoding units in the image to be encoded is processed in parallel by multiple threads, and all encoding operations of each encoding unit are processed serially by the same thread.
[0022] In one exemplary embodiment of this disclosure, the step of changing the encoding unit from the pre-operation state of the target encoding operation to the operation execution state includes:
[0023] The encoding unit is transformed from the pre-operation state of the target encoding operation to the operation execution state through a lock-free concurrency mechanism.
[0024] According to a second aspect of this disclosure, an image encoding apparatus is provided, comprising:
[0025] The pre-state addition module is configured to divide the image to be encoded into multiple encoding units and add a corresponding operation pre-state for each encoding operation to be performed for each encoding unit.
[0026] The trigger instruction receiving module is configured to, when the encoding unit is in the operation pre-state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, determine whether the encoding unit meets the execution conditions of the target encoding operation; wherein, the pre-encoding unit is the encoding unit on which the encoding unit depends for executing the target encoding operation;
[0027] The pre-state transition module is configured to, if the encoding unit satisfies the execution conditions of the target encoding operation, change the encoding unit from the pre-operation state of the target encoding operation to the operation execution state, and control the encoding unit to execute the target encoding operation.
[0028] In one exemplary embodiment of this disclosure, the image encoding apparatus further includes:
[0029] The trigger instruction waiting module is configured to control the encoding unit to wait for the trigger instruction of the target encoding operation sent by the next pre-encoding unit if the encoding unit does not meet the execution conditions of the target encoding operation.
[0030] In one exemplary embodiment of this disclosure, the trigger instruction receiving module includes:
[0031] The encoding operation judgment unit is configured to obtain all the preceding encoding units of the encoding unit and determine whether all the preceding encoding units have completed the target encoding operation;
[0032] The condition satisfaction determination unit is configured to determine that if all the preceding encoding units have completed the target encoding operation, the encoding unit satisfies the execution condition of the target encoding operation.
[0033] The condition-not-met determination unit is configured to determine that if there is a pre-encoding unit that has not completed the target encoding operation, the encoding unit does not meet the execution condition of the target encoding operation.
[0034] In one exemplary embodiment of this disclosure, the encoding operation determination unit includes:
[0035] The pre-encoding unit acquisition unit is configured to acquire the pre-encoding units that the encoding unit depends on for executing the target encoding operation, based on a preset encoding unit dependency relationship.
[0036] In one exemplary embodiment of this disclosure, the image encoding apparatus further includes:
[0037] The next state transition module is configured to, when the encoding unit completes the target encoding operation, transition the encoding unit from the operation execution state of the target encoding operation to the operation pre-operation state of the next encoding operation.
[0038] In one exemplary embodiment of this disclosure, the image encoding apparatus further includes:
[0039] The lock-free concurrency mechanism execution module is configured to convert the encoding unit from the pre-operation state of the target encoding operation to the operation execution state through the lock-free concurrency mechanism.
[0040] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the image encoding method described in any of the preceding claims.
[0041] According to a fourth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the image encoding method described in any of the preceding claims.
[0042] The exemplary embodiments disclosed herein can have the following beneficial effects:
[0043] In the image encoding method of this exemplary embodiment, by adding a corresponding pre-operation state for each encoding operation to be performed by each encoding unit, when the encoding unit is in the pre-operation state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, it is determined whether the encoding unit meets the execution conditions of the target encoding operation. If the encoding unit meets the execution conditions of the target encoding operation, the encoding unit is changed from the pre-operation state of the target encoding operation to the operation execution state, and the encoding unit is controlled to execute the target encoding operation. The image encoding method in this exemplary embodiment achieves encoding state synchronization in a lock-free manner, ensuring normal execution of the encoding process while avoiding thread contention caused by numerous locking processes, thus improving parallel efficiency. Furthermore, by advancing the encoding operation of each encoding unit to be triggered as soon as the conditions are met, rather than waiting until the last trigger, it further improves encoding efficiency.
[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0046] Figure 1 A flowchart illustrating an example embodiment of the image encoding method of this disclosure is shown;
[0047] Figure 2 A flowchart illustrating a sample implementation of this disclosure is shown to determine whether an encoding unit meets the execution conditions of a target encoding operation.
[0048] Figure 3 A schematic diagram of an image to be encoded according to a specific embodiment of the present disclosure is shown;
[0049] Figure 4 A block diagram of an image encoding apparatus according to an exemplary embodiment of the present disclosure is shown;
[0050] Figure 5 A schematic diagram of the structure of a computer system suitable for implementing the embodiments of the present disclosure is shown. Detailed Implementation
[0051] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.
[0052] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.
[0053] The following exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.
[0054] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0055] In some related embodiments, depending on the video coding standard, CTUs have different spatial dependencies; that is, each row's CTU may depend on the encoding result of the CTU above or to its upper right. Therefore, the CTU of the next row cannot be processed too quickly and needs to be synchronized through a certain mechanism. In the released VVC (Versatile Video Coding), many preprocessing and in-loop filtering operations have been added, including Deblocking Filter, Sample Adaptive Offset (SAO), and Adaptive Loop Filter (ALF). Typically, new encoder designs not only need to perform the CTU's mode decision process in WPP mode, but also the remaining processing in WPP mode to maximize parallel efficiency. This introduces more complex dependencies; not only do different CTUs in the same state have spatial dependencies, but the same CTU also has state domain dependencies. For example, a CTU will sequentially undergo the operations of Mode Decision (ENC), Deblocking Filter (DBK), Sample Adaptive Offset (SAO), and Adaptive Loop Filter (ALF) (a total of 4 states). After each CTU is completed, locking is required to check and process the next CTU or the next state. Each frame of an image requires at least 4 * CTUs of locking. In the case of high-resolution video, there are dozens to hundreds or even thousands of CTUs in the same frame. It is evident that the more times locking is required, the more severe the competition between threads becomes, inevitably leading to a decrease in parallelism.
[0056] Based on the above problems, this example implementation first provides an image encoding method. (Reference) Figure 1 As shown, the above image encoding method may include the following steps:
[0057] Step S110. Divide the image to be encoded into multiple encoding units, and add corresponding operation pre-states for each encoding operation to be performed in each encoding unit.
[0058] Step S120. When the encoding unit is in the pre-operation state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, it is determined whether the encoding unit meets the execution conditions of the target encoding operation.
[0059] Among them, the pre-encoding unit is the encoding unit on which the encoding unit depends for performing the target encoding operation.
[0060] Step S130. If the encoding unit meets the execution conditions of the target encoding operation, the encoding unit is changed from the operation pre-operation state of the target encoding operation to the operation execution state, and the encoding unit is controlled to execute the target encoding operation.
[0061] In the image encoding method of this exemplary embodiment, by adding a corresponding pre-operation state for each encoding operation to be performed by each encoding unit, when the encoding unit is in the pre-operation state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, it is determined whether the encoding unit meets the execution conditions of the target encoding operation. If the encoding unit meets the execution conditions of the target encoding operation, the encoding unit is changed from the pre-operation state of the target encoding operation to the operation execution state, and the encoding unit is controlled to execute the target encoding operation. The image encoding method in this exemplary embodiment achieves encoding state synchronization in a lock-free manner, ensuring normal execution of the encoding process while avoiding thread contention caused by numerous locking processes, thus improving parallel efficiency. Furthermore, by advancing the encoding operation of each encoding unit to be triggered as soon as the conditions are met, rather than waiting until the last trigger, it further improves encoding efficiency.
[0062] Below, in conjunction with Figures 2 to 3 The steps described above in this example implementation will be explained in more detail.
[0063] In step S110, the image to be encoded is divided into multiple encoding units, and a corresponding operation pre-state is added for each encoding operation to be performed in each encoding unit.
[0064] In this example implementation, the coding unit is the basic unit in image coding processing, such as a CTU. Each coded image can be divided into multiple coding units. During image coding processing, each coding unit may perform one or more coding operations. For example, a CTU may sequentially undergo the operations of Mode Decision (ENC), Deblocking Filter (DBK), Sample Adaptive Compensation (SAO), and Adaptive Loop Filter (ALF) to complete the entire coding process.
[0065] In this example implementation, for each encoding operation to be performed by the encoding unit, an operation pre-state can be added. The operation pre-state refers to the preparation state (such as the TODO state) before the encoding unit enters each encoding operation.
[0066] In step S120, when the encoding unit is in the pre-operation state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, it is determined whether the encoding unit meets the execution conditions of the target encoding operation.
[0067] In this example implementation, the pre-encoding unit is the encoding unit that the encoding unit depends on when performing the target encoding operation. For example, if the current CTU depends on the encoding operation result of the CTU above or to its right, then the CTU above or to its right is the pre-encoding unit of the current CTU.
[0068] When an encoding unit is in the pre-operation state of the target encoding operation, it waits for the trigger instruction of the target encoding operation sent by its pre-encoding unit. If a pre-encoding unit sends a trigger instruction, the current encoding unit will determine whether the execution conditions of the target encoding operation are met.
[0069] In this example implementation, as Figure 2 As shown, determining whether an encoding unit meets the execution conditions of the target encoding operation can specifically include the following steps:
[0070] Step S210. Obtain all pre-coding units of the coding unit and determine whether all pre-coding units have completed the target coding operation.
[0071] In this example implementation, the preceding encoding units that the encoding unit depends on to perform the target encoding operation can be obtained based on the preset encoding unit dependency relationship. For example, it can be obtained through the preset encoding unit dependency relationship table.
[0072] When an encoding unit receives a trigger command, the system will iterate through the execution status of the target encoding operation of all its preceding encoding units.
[0073] Step S220. If all pre-encoding units have completed the target encoding operation, then it is determined that the encoding unit meets the execution conditions of the target encoding operation.
[0074] Step S230. If there is a pre-encoding unit that has not completed the target encoding operation, then it is determined that the encoding unit does not meet the execution conditions of the target encoding operation.
[0075] Specifically, when an encoding unit receives a trigger command, the system iterates through the status flag set of all its preceding encoding units. If all flags indicate that the target encoding operation has been completed, the current encoding unit is immediately switched to the operation execution state. For example, in a deblocking filtering operation, the current CTU needs to check whether its two preceding CTUs have completed the filtering process. If any preceding CTU has not completed filtering, the current CTU maintains the operation-preceding state and continues to listen for subsequent trigger events.
[0076] In step S130, if the encoding unit meets the execution conditions of the target encoding operation, the encoding unit is changed from the operation pre-operation state of the target encoding operation to the operation execution state, and the encoding unit is controlled to execute the target encoding operation.
[0077] The operation execution state refers to the running state of the encoding unit when it is executing the target encoding operation. If the encoding unit meets the execution conditions of the target encoding operation, that is, all the preceding encoding units of the encoding unit have completed the target encoding operation, the encoding unit can be changed from the operation preceding state of the target encoding operation to the operation execution state, and the encoding unit can be controlled to execute the target encoding operation.
[0078] In this example implementation, a lock-free concurrency mechanism can be used to change the encoding unit from the pre-operation state of the target encoding operation to the operation execution state.
[0079] When each CTU is triggered, a lock-free concurrency mechanism, such as CAS (Compare And Swap), can be used to update the expected operation pre-do state (TODO) to the operation execution state, so as to ensure the atomicity and thread safety of state transitions.
[0080] In this example implementation, each encoding unit in the image to be encoded is processed in parallel by multiple threads, and all encoding operations of each encoding unit are processed serially by the same thread.
[0081] The encoding units in the image to be encoded are processed in parallel by multiple threads. For example, encoding unit 0 can be processed by thread 1, encoding unit 1 can be processed by thread 1, or it can be processed by thread 2, or it can be processed by thread 0, or one thread can process one CTU row, and so on from left to right. This example implementation does not make a specific limitation. For a single encoding unit, all its encoding operations are processed serially by one thread.
[0082] In this example implementation, if the encoding unit does not meet the execution conditions of the target encoding operation, the control encoding unit waits for the trigger instruction of the target encoding operation sent by the next pre-encoding unit.
[0083] When an encoding unit receives the first trigger instruction but the dependency condition is not met, it can continue to wait for the trigger instructions of the target encoding operation sent by other pre-encoding units through event listening mechanisms or other means. When it receives the trigger instruction of the target encoding operation sent by the next pre-encoding unit, it will re-determine whether the execution condition of the target encoding operation is met.
[0084] Specifically, when an encoding unit receives a trigger instruction from the first preceding encoding unit, it immediately checks the completion status of the target encoding operations of all preceding encoding units. If any preceding encoding unit is found to have incomplete operations, the trigger event is marked as invalid, and an event listening channel is established for the remaining preceding encoding units. This approach allows the encoding unit to passively receive state updates through an asynchronous event notification mechanism, rather than continuously consuming computing resources for state polling. Furthermore, each trigger instruction is encapsulated as an independent event object, carrying the source encoding unit identifier and the target operation type, enabling the receiving unit to quickly match dependencies. This forms a cascading trigger chain, automatically triggering the state checks of subsequent units after the preceding unit completes its operation, avoiding the resource consumption caused by global state synchronization.
[0085] In this example implementation, when the encoding unit completes the target encoding operation, the encoding unit can be changed from the operation execution state of the target encoding operation to the operation pre-operation state of the next encoding operation.
[0086] Specifically, when an encoding unit completes the target encoding operation, its operation execution state is automatically cleared and immediately set to the pre-operation state corresponding to the next encoding operation. For example, after the encoding unit completes the deblocking filtering operation, its state is converted to the pre-operation waiting state for the sample adaptive compensation operation. At this time, the encoding unit only needs to wait for the preceding encoding unit to send a trigger instruction to enter the execution phase of the next operation. Since the state transition is triggered by the encoding unit's own behavior and the transition action is implemented through atomic operations, there is no need to coordinate state changes through locking mechanisms in a multi-threaded environment, thereby avoiding thread contention.
[0087] Figure 3 A schematic diagram of an image to be encoded according to a specific embodiment of the present disclosure is shown, wherein the shaded portion represents the encoded CTU, and T0-T5 represent different threads being executed.
[0088] In the CTU-triggered parallel framework described above, if the CTU ENC in row 2, column 2 depends on the completion of the CTU ENC in row 1, column 3, then when both row 1, column 3 and row 2, column 1 complete their ENCs simultaneously, the CTU ENC in row 2, column 2 will be triggered. Without locking, the ENC condition for row 2, column 2 will already be met, leading to repeated execution of the ENC. To avoid this problem, upon completion of each CTU ENC, the entire state variable can be locked, and the current CTU state can be updated to the next pending state (DBK). This ensures that only one CTU is triggered at a time. If the triggered CTU checks that the second CTU does not meet the condition, the first trigger will fail. When the second CTU attempts to trigger again, its state has been updated to the next state. The triggered CTU then checks that the conditions of all dependent CTUs are met, and the trigger succeeds. This strategy ensures that the same CTU will only be successfully triggered on the last trigger by all dependent CTUs, preventing the same CTU in the same state from being executed multiple times. However, under the locking mechanism, multi-threaded contention is severe, affecting parallelism. Furthermore, after CTU completes encoding, issues such as operating system time slice allocation may cause delayed triggering, resulting in excessively long waiting times for subsequent CTUs and impacting encoding efficiency.
[0089] In the image encoding method of this example implementation, assuming that the two CTUs dependent on the CTU in the second row and second column simultaneously complete ENC, when one CTU triggers, a CAS mechanism can be used to update the TODO ENC to the ENC state. The second CTU will fail to update the TODO ENC to ENC using the CAS mechanism, therefore, the second CTU will not trigger successfully. The entire state update process is an atomic operation, ensuring consistency with the locked state, and the triggering time is advanced to the first time the dependency condition is met, rather than the last time, thus improving parallel efficiency and encoding efficiency.
[0090] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.
[0091] Furthermore, this disclosure also provides an image encoding apparatus. (See reference) Figure 4 As shown, the image encoding device may include a pre-state addition module 410, a trigger instruction receiving module 420, and a pre-state transition module 430. Wherein:
[0092] The pre-state addition module 410 is configured to divide the image to be encoded into multiple encoding units and add corresponding operation pre-states for each encoding operation to be performed for each encoding unit.
[0093] The trigger instruction receiving module 420 is configured to, when the encoding unit is in the operation pre-state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, determine whether the encoding unit meets the execution conditions of the target encoding operation; wherein, the pre-encoding unit is the encoding unit on which the encoding unit depends for executing the target encoding operation;
[0094] The pre-state transition module 430 is configured to, if the encoding unit meets the execution conditions of the target encoding operation, change the encoding unit from the pre-operation state of the target encoding operation to the operation execution state, and control the encoding unit to execute the target encoding operation.
[0095] In some exemplary embodiments of this disclosure, an image encoding apparatus provided by this disclosure may further include a trigger instruction waiting module, configured to control the encoding unit to wait for a trigger instruction for the target encoding operation sent by the next preceding encoding unit if the encoding unit does not meet the execution conditions of the target encoding operation.
[0096] In some exemplary embodiments of this disclosure, the trigger instruction receiving module 420 may include an encoding operation judgment unit, a condition satisfaction judgment unit, and a condition non-satisfaction judgment unit. Wherein:
[0097] The encoding operation judgment unit is configured to execute all the preceding encoding units of the acquisition encoding unit and determine whether all the preceding encoding units have completed the target encoding operation;
[0098] The condition-satisfaction determination unit is configured to determine if the target encoding unit satisfies the execution condition of the target encoding operation if all pre-encoding units have completed the target encoding operation.
[0099] If the condition is not met, the determination unit is configured to execute if there is a pre-encoding unit that has not completed the target encoding operation, then the determination unit does not meet the execution condition of the target encoding operation.
[0100] In some exemplary embodiments of this disclosure, the encoding operation determination unit may include a pre-encoding unit acquisition unit, which is configured to acquire the pre-encoding units on which the encoding unit depends for executing the target encoding operation based on a preset encoding unit dependency relationship.
[0101] In some exemplary embodiments of this disclosure, an image encoding apparatus provided by this disclosure may further include a next state transition module, configured to perform the operation execution state of the encoding unit from the target encoding operation to the operation pre-operation state of the next encoding operation when the encoding unit completes the target encoding operation.
[0102] In some exemplary embodiments of this disclosure, each encoding unit in the image to be encoded is processed in parallel by multiple threads, and all encoding operations of each encoding unit are processed serially by the same thread.
[0103] In some exemplary embodiments of this disclosure, an image encoding apparatus provided by this disclosure may further include a lock-free concurrency mechanism execution module, configured to perform a lock-free concurrency mechanism to convert the encoding unit from the operation pre-operation state of the target encoding operation to the operation execution state.
[0104] The specific details of each module / unit in the above-mentioned image encoding device have been described in detail in the corresponding method embodiment section, and will not be repeated here.
[0105] Figure 5 A schematic diagram of the structure of a computer system suitable for implementing the embodiments of the present disclosure is shown.
[0106] It should be noted that, Figure 5 The computer system 500 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.
[0107] like Figure 5 As shown, the computer system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 502 or programs loaded from storage section 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for system operation. The CPU 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.
[0108] The following components are connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 510 as needed so that computer programs read from it can be installed into storage section 508 as needed.
[0109] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by central processing unit (CPU) 501, it performs various functions defined in the system of this disclosure.
[0110] Exemplary embodiments of this disclosure also provide a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the image encoding method described above.
[0111] In one embodiment, the computer program product can be a tangible product containing a computer program, such as a computer-readable storage medium storing the computer program. The readable storage medium can be a storage medium based on electrical, magnetic, optical, electromagnetic, infrared, or other signals, including but not limited to: random access memory (RAM), read-only memory (ROM), magnetic tape, floppy disk, flash memory, hard disk drive (HDD), solid-state drive (SSD), etc. For example, the computer program product can be implemented as a non-volatile storage medium storing the computer program, such as read-only memory, NAND flash memory, etc.
[0112] In one implementation, the computer program product can be an intangible product containing a computer program. For example, the computer program product can be implemented as a virtual digital product, such as an executable file, installation package, or other digital file storing the computer program.
[0113] Computer program code can be written in one or more programming languages. Examples of programming languages include C, Java, and C++. Program code can execute entirely on the user's computing device, partially on the user's computing device, or as a standalone software package. It can also execute partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, such as a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via an internet connection provided by a mobile network operator).
[0114] Computer programs can be carried or transmitted via signals such as electrical, magnetic, optical, electromagnetic, and infrared rays. Electronic devices can convert signals carrying computer programs into digital signals, thereby running the computer programs. When a computer program runs on an electronic device, its code is used to cause the electronic device to execute (more specifically, the processor of the electronic device to execute) the method steps of various exemplary embodiments of this disclosure, such as the image encoding method described above.
[0115] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0116] It should be noted that although several modules for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.
[0117] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein.
[0118] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. An image encoding method, characterized in that, include: The image to be encoded is divided into multiple encoding units, and a corresponding operation pre-state is added for each encoding operation to be performed in each encoding unit; When the encoding unit is in the pre-operation state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, it is determined whether the encoding unit meets the execution conditions of the target encoding operation; wherein, the pre-encoding unit is the encoding unit on which the encoding unit depends for executing the target encoding operation; If the encoding unit meets the execution conditions of the target encoding operation, the encoding unit is changed from the operation pre-operation state of the target encoding operation to the operation execution state, and the encoding unit is controlled to execute the target encoding operation.
2. The image encoding method according to claim 1, characterized in that, The method further includes: If the encoding unit does not meet the execution conditions of the target encoding operation, the encoding unit is controlled to wait for the trigger instruction of the target encoding operation sent by the next pre-encoding unit.
3. The image encoding method according to claim 1, characterized in that, The step of determining whether the encoding unit meets the execution conditions of the target encoding operation includes: Obtain all the pre-encoding units of the encoding unit, and determine whether all the pre-encoding units have completed the target encoding operation; If all the pre-encoding units have completed the target encoding operation, then the encoding unit is determined to meet the execution conditions of the target encoding operation; If there is a pre-encoding unit that has not completed the target encoding operation, then the encoding unit is determined to have failed to meet the execution conditions of the target encoding operation.
4. The image encoding method according to claim 3, characterized in that, The step of obtaining all pre-coding units of the coding unit includes: Based on the preset coding unit dependency relationship, obtain the preceding coding units that the coding unit depends on to perform the target coding operation.
5. The image encoding method according to claim 1, characterized in that, The method further includes: When the encoding unit completes the target encoding operation, the encoding unit is changed from the operation execution state of the target encoding operation to the operation pre-operation state of the next encoding operation.
6. The image encoding method according to claim 1, characterized in that, Each of the encoding units in the image to be encoded is processed in parallel by multiple threads, and all encoding operations of each encoding unit are processed serially by the same thread.
7. The image encoding method according to claim 1, characterized in that, The step of changing the encoding unit from the pre-operation state of the target encoding operation to the operation execution state includes: The encoding unit is transformed from the pre-operation state of the target encoding operation to the operation execution state through a lock-free concurrency mechanism.
8. An image encoding device, characterized in that, include: The pre-state addition module is configured to divide the image to be encoded into multiple encoding units and add a corresponding operation pre-state for each encoding operation to be performed for each encoding unit. The trigger instruction receiving module is configured to, when the encoding unit is in the operation pre-state of the target encoding operation, if the encoding unit receives a trigger instruction for the target encoding operation sent by any pre-encoding unit, determine whether the encoding unit meets the execution conditions of the target encoding operation; wherein, the pre-encoding unit is the encoding unit on which the encoding unit depends for executing the target encoding operation; The pre-state transition module is configured to, if the encoding unit satisfies the execution conditions of the target encoding operation, change the encoding unit from the pre-operation state of the target encoding operation to the operation execution state, and control the encoding unit to execute the target encoding operation.
9. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the image encoding method as described in any one of claims 1 to 7.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the image encoding method as described in any one of claims 1 to 7.