Semiconductor layout structure with dummy pattern and manufacturing method thereof

Abstract

The invention discloses a semiconductor layout structure with a dummy pattern and a manufacturing method thereof, and the semiconductor layout structure with the dummy pattern comprises a substrate, a semiconductor device includes a substrate having a cell region and a dummy region adjacent to each other, a plurality of fin-shaped structures on the substrate, a plurality of gates on the substrate and crossing the fin-shaped structures, a plurality of slot-shaped contacts on the substrate and between the gates and connected to the fin-shaped structures, a plurality of polysilicon contacts are located on and connected to the gates in the cell region, and a plurality of dummy polysilicon contacts are located on the gate closest to the cell region in the dummy region and are not connected to any interconnect structures, wherein the dummy polycrystalline silicon contacts are in mirror symmetry with the polycrystalline silicon contacts closest to a boundary by taking the boundary between the dummy region and the unit region as a symmetry axis.

Description

Technical Field

[0001] The present invention relates to a semiconductor layout structure, and more particularly, to a semiconductor layout structure having dummy patterns. Background Technology

[0002] To increase functional density, semiconductor devices often integrate logic circuits and embedded static random-access memory (SRAM). These applications are widespread in industrial and scientific subsystems, automotive electronics, mobile phones, digital cameras, and microprocessors. SRAM has the advantage of storing data without needing to be refreshed. Its cells contain different numbers of transistors, commonly referred to as transistor count, such as six-transistor (6T) SRAM, eight-transistor (8T) SRAM, etc. These transistors typically form a data latch to store a single bit of data. Other transistors can be added to control access to these other transistors. SRAM cells are usually arranged in an array with multiple rows and columns. Each column of SRAM cells is connected to a word line, which determines whether the current SRAM cell is selected. Each row of SRAM cells is connected to a bit line (or a pair of complementary bit lines), which is used to write or read data from the SRAM cell.

[0003] With the rise of high-level computing and applications in the semiconductor field, simply miniaturizing the size is no longer sufficient to meet the high-density requirements of SRAM. For example, traditional planar transistor SRAM cell structures experience performance degradation and leakage problems when the semiconductor size is reduced to a certain level. To overcome this challenge, the industry has proposed fin-type or multi-fin three-dimensional transistor architectures, namely FinFETs. FinFETs, when applied in metal-oxide-semiconductor (MOS) MOSFET structures, can effectively control short-channel effects and possess excellent subcritical slope and high voltage gain characteristics.

[0004] While advancements in FinFET transistor technology have enabled the fabrication of high-end FinFET SRAM devices, the extremely small feature sizes required in advanced semiconductor technology can easily lead to problems with semiconductor patterning. For example, semiconductor patterns near the boundary between the memory and dummy regions are prone to anomalies due to uneven pattern density, affecting the normal interconnection between components and consequently reducing product yield. Therefore, addressing these yield issues has become increasingly crucial and urgent to meet the demands of today's high-end application markets for smaller electronic devices. Summary of the Invention

[0005] To address the aforementioned issue of pattern anomalies in FinFET devices, this invention proposes a semiconductor layout structure and method, characterized by the provision of a dummy pattern mirror-symmetrical to the normal pattern near the boundary of the semiconductor cell region, thereby avoiding pattern anomalies caused by uneven pattern feature density during the manufacturing process.

[0006] One aspect of the present invention is to provide a semiconductor layout structure comprising: a substrate having an adjacent cell region and a dummy region; a plurality of fin structures located on the substrate and spaced apart extending in a first direction; a plurality of gates located on the substrate and extending beyond the fin structures, the gates being spaced apart and extending in a second direction orthogonal to the first direction; a plurality of slot-shaped contacts located on the substrate and between the gates and connected to the fin structures; a plurality of polysilicon contacts located on and connected to the gates in the cell region; and a plurality of dummy polysilicon contacts located on the gate closest to the cell region in the dummy region and not connected to any interconnect structure, wherein the dummy polysilicon contacts are mirror-symmetrical about the boundary between the dummy region and the cell region as an axis of symmetry with respect to the polysilicon contacts closest to the boundary.

[0007] Another aspect of the present invention is to provide a method for manufacturing a semiconductor layout structure with a dummy pattern, comprising: providing a substrate having an adjacent cell region and a dummy region; forming a plurality of fin-like structures on the substrate, the fin-like structures being spaced apart and extending in a first direction; forming a plurality of gates on the substrate, the gates extending beyond the fin-like structures and being spaced apart in a second direction, the second direction being orthogonal to the first direction; and forming a plurality of slot-shaped contacts on the substrate, the slot-shaped contacts being located at... These gates are connected to and to the fin-like structures; a plurality of polysilicon contacts are formed on these gates and connected to these gates, wherein the polysilicon contacts located in the dummy region are dummy polysilicon contacts, which are located on the gate closest to the cell region and are not connected to any interconnect structure, and the dummy polysilicon contacts are mirror-symmetrical about the boundary between the dummy region and the cell region with respect to the polysilicon contacts closest to the boundary in the cell region.

[0008] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0009] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0010] Figure 1 This is a schematic diagram of a semiconductor layout structure with a dummy pattern in a preferred embodiment of the present invention;

[0011] Figure 2 In a preferred embodiment of the present invention, Figure 1 A schematic diagram of the cross section drawn along the midsection line A-A';

[0012] Figure 3 This is a schematic diagram of an SRAM layout structure with a dummy pattern according to an embodiment of the present invention; and

[0013] Figure 4 This is a flowchart illustrating the steps involved in fabricating a semiconductor layout structure with a dummy pattern, as described in a preferred embodiment of the present invention.

[0014] Symbol Explanation

[0015] 100 base

[0016] 100a unit area

[0017] 100b Virtual Area

[0018] 200 base

[0019] 200a Unit Area

[0020] 200b Virtual Area

[0021] 200c pull-up area

[0022] B boundary

[0023] C storage unit

[0024] D1 First Direction

[0025] D2 Second Direction

[0026] DF defects

[0027] DP (Dummy) Polysilicon Contact

[0028] F Fin-like structure

[0029] G gate

[0030] M-cutting mask

[0031] P Polycrystalline silicon contact

[0032] P1 position

[0033] P2 position

[0034] P3 position

[0035] PD1, PD2 pull-down transistors

[0036] PG1, PG2 access gate transistors

[0037] PU1, PU2 pull-up transistors

[0038] Steps S1 to S4

[0039] S / D source / drain

[0040] SC slotted contact

[0041] STI Shallow Trench Isolation Structure

[0042] V0 guide hole component Detailed Implementation

[0043] The present invention will be described in detail below with reference to the accompanying drawings, which form part of the invention and illustrate specific embodiments by which the invention can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. For the sake of simplicity and convenience, the scale and proportion of certain parts in the drawings may be deliberately reduced or exaggerated. Other embodiments or structural, logical, and electrical variations may be employed in the invention without departing from its scope. Therefore, the following detailed description should not be viewed in a limiting manner, and the scope of the invention will be defined by the appended claims.

[0044] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly" on something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0045] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0047] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0048] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0049] First, please refer to... Figure 1This is a semiconductor layout structure with a dummy pattern according to a preferred embodiment of the present invention. The semiconductor layout structure of the present invention includes a substrate 100, which serves as the basis for forming various elements, components, or circuits in the layout structure. The substrate 100 is preferably made of a silicon-containing material, including but not limited to silicon, monocrystalline silicon, polycrystalline silicon, silicon-germanium, carbon-doped silicon, amorphous silicon, or a combination of the above materials. The material of the substrate 100 can also be a III-V group semiconductor, such as gallium arsenide (GaAs), or a silicon-on-insulator (SOI) substrate. In a preferred embodiment of the present invention, a cell region 100a and a dummy region 100b are defined on the substrate 100, which are adjacent and have a boundary B. The cell region 100a is used to mount semiconductor elements or circuits, such as memory elements or transistors, which can receive signals or current and output results. In contrast, the dummy region 100b can serve as an intermediary or buffer region between multiple unit regions 100a in terms of manufacturing process or design rules, and the semiconductor pattern set on it does not participate in the actual circuit operation.

[0050] Rereference Figure 1 And can be referenced at the same time. Figure 2 , its purpose is Figure 1 The cross-sectional diagram along line A-A' provides a more detailed understanding of the relative and interconnected relationships of the layout patterns in the vertical direction. Multiple fin structures F are disposed on the substrate 100, spaced apart and extending in a first direction D1. The fin structures F are formed from the substrate 100 and protrude from it using photolithography, and shallow trench isolation structures STI can be filled between them to isolate them from each other, thereby defining multiple active regions on the substrate 100. Multiple gates G are also disposed on the substrate 100, spaced apart and extending in a second direction D2 across the fin structures F, preferably orthogonal to the first direction D1. The gates G can be made of polysilicon or metal, and can together with the fin structures F they cross to form transistor elements, creating a channel switch in the circuit. The fin structures F located on both sides of the gates G can be considered as the source / drain (S / D) of the transistor. In this embodiment of the invention, the gate G formed in the dummy region 100b is a dummy gate, which does not participate in the operation of the circuit.

[0051] Rereference Figure 1Multiple slot contacts SC are also disposed on the substrate 100, spaced apart between the gates G and extending in the first direction D1. The slot contacts SC can be formed by first forming a groove pattern in a dielectric layer (such as a pre-metal deposition dielectric layer) on the substrate 100 and then filling it with a metal material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), tungsten (W), or copper (Cu), etc., without limitation. The slot contacts SC are connected to the fin structures F (i.e., source / drain S / D) on both sides of the gate G to connect these parts to the adjacent fin structures F or to the upper layer circuitry. It should be noted that in actual fabrication processes, a single slot contact SC may be divided into multiple segments. For example, this can be achieved by adding a cutting mask M to the groove pattern during the groove pattern formation step. The area covered by the cutting mask M will not form a groove pattern, and therefore, no slot contact SC will be formed. A single gate G may also be segmented into multiple segments during fabrication using a photolithography process, and is not limited thereto. Similarly, the slot-shaped contact SC formed in the dummy region 100b is a dummy slot-shaped contact SC, which does not participate in the operation of the circuit. In some embodiments, the slot-shaped contact SC in the dummy region 100b may be removed.

[0052] Rereference Figure 1 In this embodiment of the invention, the slot-shaped contact SC is connected to the upper-layer circuitry via a via V0 disposed thereon, for example, to the first metal layer (M1) in the interconnect metal structure of the back-end semiconductor fabrication process (BEOL). The material of the via V0 can be copper (Cu) or tungsten (W). On the other hand, the gate G is also connected to the upper-layer circuitry via a contact structure. Figure 2 As shown, a polysilicon contact P can be disposed above the gate G and contact it therewith. Preferably, the top surface of the polysilicon contact P is flush with the top surface of the aforementioned slot-shaped contact SC. The polysilicon contact P can be formed by forming a groove pattern and filling it with polysilicon material after the slot-shaped contact SC is formed, using a photolithography process. In this embodiment of the invention, for the polysilicon contact P, in locations where slot-shaped contacts SC are not formed around it (such as location P1 covered by the cutting mask M), the polysilicon contact P is formed and connected to the gate G, but does not contact any slot-shaped contact SC. A via V0 is also connected to the polysilicon contact P at this location to connect to the upper-layer circuitry. On the other hand, in locations where slot-shaped contacts SC are formed around it (such as location P2 not covered by the cutting mask M), the polysilicon contact P is formed and connected to the gate G, and simultaneously contacts the adjacent slot-shaped contact SC, such as... Figure 2As shown. The polysilicon contact P and the slotted contact SC here can be connected to the upper circuitry via a common via V0, or they may not be connected via V0 at all.

[0053] In the prior art, the polysilicon contact P (such as...) located near the boundary B between the cell region 100a and the dummy region 100b... Figure 1 The location P3 shown is prone to pattern abnormalities. This is because no polysilicon contacts P are typically placed in the dummy area. Therefore, during the photolithography process of forming the polysilicon contact P pattern, the polysilicon contact P pattern near the boundary B is prone to having a smaller critical dimension due to exposure abnormalities. This causes the formed polysilicon contact P to shorten or even disappear, forming a defect DF. Figure 2 As shown. The presence of this defect DF will cause abnormal connection between the gate G and the adjacent slot-shaped contact SC or the upper via V0, causing the corresponding transistor element to fail and affecting the product yield. This is the existing problem that this invention aims to solve.

[0054] To solve the above problems, such as Figure 1 As shown, the present invention provides a dummy polysilicon contact DP corresponding to the polysilicon contact P on a dummy region 100b adjacent to boundary B. The dummy polysilicon contact DP is mirror-symmetrical with respect to the polysilicon contact P closest to boundary B, with the boundary B between the dummy region 100b and the cell region 100a as the axis of symmetry. With this layout design, the polysilicon contact P at position S2, during its pattern definition stage, will have an exposure atmosphere consistent with the pattern of the polysilicon contact P inside the cell region 100a because of the corresponding pattern around it. Thus, the polysilicon contact P formed near boundary B will not have pattern abnormalities. This is the advantage and progress of the present invention. The dummy polysilicon contact DP is disposed on and connected to the dummy gate G closest to boundary B in the dummy region 100b, but the dummy polysilicon contact DP is not connected to the upper circuit through any via V0, nor does it participate in the operation of the circuit. In other aspects, it is the same as the polysilicon contact P.

[0055] Please refer to now. Figure 3 This is an SRAM layout structure with a dummy pattern according to an embodiment of the present invention. This embodiment will use an SRAM architecture to illustrate the layout design of the aforementioned dummy polysilicon contact DP. Unlike the previous embodiment, in this embodiment, both the gate G and the polysilicon contact P have been cut into segments to form specific transistors and circuits.

[0056] like Figure 3As shown, the entire semiconductor layout structure is designed on a substrate 200. In this embodiment, the substrate 200 defines regions such as cell region 200a, dummy region 200b, and pull-up region (or strip region) 200c, wherein the dummy region 200b is located between cell region 200a and pull-up region 200c. Cell region 200a is used to set semiconductor elements or circuits, such as memory elements or transistors, which can accept signals or current and output results. Dummy region 200b can serve as an intermediary or buffer region between multiple cell regions 200a in terms of manufacturing process or design rules. The semiconductor patterns set therein can be used to balance the pattern density on the layout plane and do not participate in actual circuit operation. Pull-up region 200c can be a well pick-up (WPU) region, which is interspersed between each cell region 200a at intervals of layout length to provide a ground path for the circuit or to provide voltage or bias to the N-type wells and P-type wells in cell region 200a.

[0057] Rereference Figure 3 In this embodiment, cell region 200a is composed of multiple memory cells C. In a 6T SRAM architecture, each memory cell C has six transistors. Each transistor can be composed of an intersecting gate G and a fin structure F, including pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass-gate transistors PG1 and PG2. The pull-up transistors PU1 and PU2 can be PMOS, while the pull-down transistors PD1 and PD2 and the pass-gate transistors PG1 and PG2 can be NMOS. The pull-up transistors PU1 and PU2, together with their corresponding pull-down transistors PD1 and PD2, form inverters, and the two inverters in the cell form a latch-up structure. In memory cell C, the pull-up transistors PU1 and PU2 and the pull-down transistors PD1 and PD2 can respectively realize the high potential state ("1") and low potential state ("0") of the memory node, while the pass-gate transistors PG1 and PG can realize the bit line access.

[0058] Rereference Figure 3In an embodiment, polysilicon contacts P are disposed on a portion of the gate G in cell region 200a, for example, near access gate transistors PG1 and PG2. As described in the prior art, these polysilicon contacts P near the boundary B of cell region 200a are prone to pattern abnormalities due to uneven pattern density during fabrication. To address this, the present invention provides dummy polysilicon contacts DP corresponding to these polysilicon contacts P on a dummy region 200b adjacent to the boundary B. The dummy polysilicon contacts DP are disposed on and connected to the dummy gate G in the dummy region 200b, and are mirror-symmetrical to the polysilicon contacts P closest to the boundary B about the boundary B between the dummy region 200b and cell region 200a. With this layout design, the exposure atmosphere of these polysilicon contacts P during the pattern definition stage will be consistent with the pattern of the polysilicon contacts P inside the unit area 200a because there is a corresponding pattern around them. In this way, the polysilicon contacts P formed near the boundary B will not have pattern abnormality defects, thus avoiding the problem of component failure at that location. This is the advantage and effectiveness of the present invention.

[0059] Based on the above semiconductor layout structure, the present invention also proposes a method for manufacturing a semiconductor layout structure with a dummy pattern, the manufacturing steps of which are as follows: Figure 4 The flowchart is shown, and it can be used in conjunction with Figure 1 To gain a clearer understanding, the layout structure includes:

[0060] In step S1, a substrate 100 is provided as the basis for setting the layout structure. The substrate 100 defines an adjacent unit region 100a and a dummy region 100b. Multiple fin-like structures F are formed on the provided substrate 100, for example, by etching the substrate 100 through a photolithography process. These fin-like structures F are spaced apart and extend in a first direction D1.

[0061] In step S2, a plurality of gates G are formed on the substrate 100. These gates G extend beyond the fin structures F and are spaced apart, extending in a second direction D2, which is preferably orthogonal to the first direction D1. This step may also include dividing these gates into a plurality of gate segments by a photolithography process.

[0062] In step S3, a plurality of slot-shaped contacts SC are formed on the substrate 100. These slot-shaped contacts SC are located between the gates G and connected to the fin structures F. They can be formed by filling metal material into a pre-formed groove pattern. This step may also include setting a cutting mask M on the groove pattern to form multiple segments of slot-shaped contacts SC.

[0063] In step S4, a plurality of polysilicon contacts P and DP are formed on the gate G. These polysilicon contacts are connected to the gate G. Among them, the polysilicon contacts located in the dummy region 100b are dummy polysilicon contacts DP. These dummy polysilicon contacts DP are located on the gate G of the dummy region 100b and are not connected to any interconnect structure. Furthermore, these dummy polysilicon contacts DP are mirror-symmetrical about the boundary B between the dummy region 100b and the cell region 100a and the polysilicon contacts P closest to the boundary B in the cell region 100a.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor layout structure with a dummy pattern, comprising: The base consists of adjacent unit areas and dummy areas; Multiple fin-like structures are located on the base and are spaced apart, extending in a first direction; Multiple gates are located on the substrate and extend beyond the fin structures. These gates are spaced apart and extend in a second direction, which is orthogonal to the first direction. Multiple slotted contacts are located on the substrate and between the gates and connected to the fin structures; Multiple polysilicon contacts are located on and connected to the gates in the cell region; as well as Multiple dummy polysilicon contacts are located on the gate of the dummy region closest to the cell region and are not connected to any interconnect structure. The dummy polysilicon contacts are mirror-symmetrical about the boundary between the dummy region and the cell region with respect to the polysilicon contacts closest to the boundary.

2. The semiconductor layout structure with dummy pattern as described in claim 1 further includes a plurality of vias located on and connected to the slot-shaped contacts and the polysilicon contacts.

3. The semiconductor layout structure with dummy patterns as described in claim 1, wherein a portion of the polysilicon contacts are connected to the slot-shaped contacts.

4. The semiconductor layout structure with dummy pattern as described in claim 1 further includes a plurality of slot-shaped contact cutting masks located above the slot-shaped contacts and between the fin structures.

5. The semiconductor layout structure with dummy patterns as claimed in claim 1, wherein the slotted contacts, the polysilicon contacts, and the dummy polysilicon contacts are located in a layer between the substrate and the semiconductor back-end interconnect metal layer.

6. The semiconductor layout structure with a dummy pattern as claimed in claim 1, wherein the gates located in the dummy region are dummy gates, and the dummy polysilicon contacts are located on and connected to the dummy gates.

7. The semiconductor layout structure with a dummy pattern as claimed in claim 1, wherein the cell region is composed of a plurality of SRAM memory cells, and the substrate further has a pull-up region located on the other side of the dummy region opposite to the cell region.

8. A method for manufacturing a semiconductor layout structure with a dummy pattern, comprising: Provide a base having adjacent cell areas and dummy areas; Multiple fin-like structures are formed on the substrate, and these fin-like structures are arranged at intervals and extend in the first direction; Multiple gates are formed on the substrate, and these gates extend beyond the fin structures and are spaced apart and extend in a second direction, which is orthogonal to the first direction. Multiple slotted contacts are formed on the substrate, and these slotted contacts are located between the gates and connected to the fin structures; Multiple polysilicon contacts are formed on these gates and connected to these gates. The polysilicon contacts located in the dummy region are dummy polysilicon contacts. These dummy polysilicon contacts are located on the gate closest to the cell region and are not connected to any interconnect structure. The dummy polysilicon contacts are mirror-symmetrical about the boundary between the dummy region and the cell region with respect to the polysilicon contacts closest to the boundary in the cell region.

9. The method for manufacturing a semiconductor layout structure with a dummy pattern as described in claim 8 further includes forming a plurality of vias on the slot-shaped contacts and polysilicon contacts in the cell region, the vias being connected to the slot-shaped contacts and polysilicon contacts, while no vias are formed or connected on the dummy polysilicon contacts in the dummy region.

10. The method for manufacturing a semiconductor layout structure with a dummy pattern as described in claim 8 further includes forming a plurality of slot-shaped contact cutting masks on the slot-shaped contacts and between the fin structures.

11. The method of manufacturing a semiconductor layout structure with a dummy pattern as claimed in claim 8, wherein the slot-shaped contacts and the polysilicon contacts are located in a layer between the substrate and the semiconductor back metal layer.

12. The method of manufacturing a semiconductor layout structure with a dummy pattern as claimed in claim 8, wherein the gates located in the dummy region are dummy gates, and the dummy polysilicon contacts are located on and connected to the dummy gates.

13. The method for manufacturing a semiconductor layout structure with a dummy pattern as claimed in claim 8, wherein the cell region is composed of a plurality of SRAM memory cells, and the substrate further has a pull-up region located on the other side of the dummy region opposite to the cell region.

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