Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate which comprises a substrate and an epitaxial layer, the epitaxial layer is located at one side of the substrate, and the substrate is of a first doping type; the doped regions are located in the epitaxial layer at intervals, the surfaces of the sides, away from the substrate, of the doped regions are located in the surface of the side, away from the substrate, of the epitaxial layer, and the doped regions are of the second doping type; the ohmic contact structures are located on the side, away from the substrate, of the epitaxial layer of the cellular region of the semiconductor device at intervals, the ohmic contact structures make contact with the doped region, the ohmic contact structures contain carbon, and the problem that in the prior art, the ohmic contact resistance of the semiconductor device is high is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor device manufacturing, and in particular, to a semiconductor device and a method for manufacturing the same. BACKGROUND

[0002] In the field of semiconductor manufacturing, especially for power diodes, it is crucial to form an ohmic contact with low resistance and high stability. In the traditional process, a metal layer is directly deposited on the active region and an ohmic contact is formed by thermal annealing. Although electrical connection is achieved to some extent, a series of technical problems have not been effectively solved.

[0003] During the Ni-Si alloying process at the ohmic contact of the device, the Ni metal is prone to excessive diffusion under heat. As a fast diffusion element, Ni tends to form an interface during the alloying process. Ni atoms will diffuse from the interface into the metal layer, affecting the morphology and thickness of the contact region, thereby increasing the leakage current and affecting the device performance. At the same time, the thermal stability of NiSi is poor, and it is easy to transform into high-resistivity NiSi2 after rapid thermal annealing, thereby affecting the conductivity of the contact and the working efficiency of the overall device.

[0004] The above information disclosed in the background section is only for the purpose of enhancing the understanding of the background of the technology described herein, therefore, the background section can contain information that is not prior art known in this country to a person of ordinary skill in the art. SUMMARY

[0005] The main purpose of the present application is to provide a semiconductor device and a method for manufacturing the same, to solve the problem of high ohmic contact resistance of the semiconductor device in the prior art.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, comprising: a substrate comprising a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate, the substrate having a first doping type; a plurality of doped regions being spaced apart in the epitaxial layer, and the doped regions being located in the surface of the epitaxial layer away from the substrate, the doped regions having a second doping type; a plurality of ohmic contact structures being spaced apart on the surface of the epitaxial layer of the cell region of the semiconductor device away from the substrate, the ohmic contact structures being in contact with the doped regions, and the ohmic contact structures containing carbon.

[0007] Optionally, the ohmic contact structure comprises a first ohmic contact layer and a second ohmic contact layer, wherein the second ohmic contact layer is located on the side of the first ohmic contact layer away from the epitaxial layer, and the second ohmic contact layer comprises the carbon.

[0008] Optionally, the material of the second ohmic contact layer comprises a metal and a non-metal, the metal comprises nickel, and the non-metal further comprises silicon.

[0009] Optionally, the target material for preparing the first ohmic contact layer comprises nickel-vanadium.

[0010] Optionally, the atomic proportion of the metal in the second ohmic contact layer is 42% to 47%.

[0011] Optionally, the atomic proportion of the carbon in the second ohmic contact layer is 5% to 10%, and the atomic proportion of the silicon is 48% to 52%.

[0012] Optionally, the semiconductor device further comprises a first oxide layer, an insulating layer, a source electrode and a drain electrode, wherein the insulating layer is located on the side of the first oxide layer away from the epitaxial layer of the terminal region of the semiconductor device, the source electrode covers the first oxide layer, the second ohmic contact layer and the doped region, and the drain electrode is located on the side of the substrate away from the epitaxial layer.

[0013] According to another aspect of the present application, a preparation method of a semiconductor device is provided for preparing the semiconductor device, the preparation method comprising: providing a substrate, the substrate comprising a substrate and an epitaxial layer, the substrate having a first doping type; forming a plurality of spaced-apart doped regions in the epitaxial layer, the doped regions being located in the side surface of the epitaxial layer away from the substrate, the doped regions having a second doping type; forming a plurality of spaced-apart ohmic contact structures in the side of the epitaxial layer of the cell region of the semiconductor device, the ohmic contact structures being in contact with the doped regions, and the ohmic contact structures containing carbon.

[0014] Optionally, after the doped regions are formed and before the ohmic contact structures are formed, the preparation method further comprises: sequentially forming a first oxide layer and an insulating layer on the epitaxial layer, and performing a patterning process on the oxide layer and the insulating layer to expose part of the epitaxial layer; forming a second oxide layer on the insulating layer, and performing a patterning process on the second oxide layer to expose part of the epitaxial layer.

[0015] Optionally, the step of forming a plurality of spaced ohmic contact structures on the side of the epitaxial layer of the cell region of the semiconductor device away from the substrate comprises: forming a first ohmic contact layer on the second oxide layer, the epitaxial layer and the first oxide layer; depositing a SiC material on the first ohmic contact layer to form a SiC film layer, and performing surface treatment on the SiC film layer, the surface treatment comprising at least one of annealing treatment and passivation treatment; evaporating a Ni target material on the SiC material by a magnetron sputtering process to form a second ohmic contact layer after the annealing treatment; and removing part of the first ohmic contact layer, part of the second ohmic contact layer and the second oxide layer by an etching process, the remaining first ohmic contact layer and the second ohmic contact layer forming the ohmic contact structure.

[0016] By applying the technical solution of the present application, the semiconductor device comprises a substrate with a first doping type, wherein a plurality of doped regions with a second doping type are spaced in an epitaxial layer and are in contact with a plurality of ohmic contact structures, and the ohmic contact structures contain C. By introducing C atoms at the ohmic contact structures, a composite layer of Si, C and ohmic contact metal, which can be nickel, can be formed in the ohmic contact region, and the excessive diffusion of nickel atoms is effectively inhibited by using carbon atoms, thereby stabilizing the nickel silicide phase state during high-temperature annealing and avoiding the formation of high-resistance NiSi2, ensuring the low resistivity and thermal stability of the contact region. The present technical solution can effectively control the diffusion of Ni atoms to the surrounding during Ni-Si alloying, solving the problems of increased leakage current and high ohmic contact resistance of the semiconductor device caused by Ni diffusion in the prior art. By the above technical means, the present application reduces the contact resistivity of the ohmic contact region, improves the electrical performance and reliability of the device, simplifies the process, widens the process window, improves the manufacturing yield, and especially reduces the conduction loss, optimizes the switching speed and frequency characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings accompanying the specification of the present application serve to provide a further understanding of the present application, the illustrative embodiments of the present application and their descriptions serve to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A cross-sectional structure schematic diagram of a semiconductor device according to an embodiment of the present application is shown;

[0019] Figure 2 A flowchart schematic diagram of a preparation method of a semiconductor device according to an embodiment of the present application is shown;

[0020] Figure 3 For Figure 2 In the preparation method of the semiconductor device, a cross-sectional structure schematic diagram of the substrate after forming the second oxide layer is shown;

[0021] Figure 4 In order to be in Figure 3 A schematic diagram of the cross-sectional structure of the substrate after the formation of the first ohmic contact layer and the second ohmic contact layer on the second oxide layer;

[0022] Figure 5 To Figure 4 A schematic diagram of the cross-sectional structure of the substrate after etching the second oxide layer, the first ohmic contact layer, and the second ohmic contact layer.

[0023] The above figures include the following reference numerals:

[0024] 10. Substrate; 11. Substrate; 12. Epitaxial layer; 20. Doped region; 30. Ohmic contact structure; 31. First ohmic contact layer; 32. Second ohmic contact layer; 40. First oxide layer; 50. Insulating layer; 60. Source electrode; 70. Drain electrode; 80. Second oxide layer. Detailed Implementation

[0025] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it will be understood that when an element is referred to as being "connected" to another element, it can be "directly connected" to the other element or "connected" to the other element through a third element.

[0029] As introduced in the background, in the prior art, Ni atoms will diffuse from the interface into the metal layer, affecting the morphology and thickness of the contact region, thereby causing an increase in leakage current and affecting device performance. At the same time, the thermal stability of NiSi is poor, and it is easy to transform into high-resistivity NiSi2 after rapid thermal annealing, thereby affecting the conductivity of the contact. To solve the problem of high ohmic contact resistance of the semiconductor device in the prior art, embodiments of the present application provide a semiconductor device and a preparation method thereof.

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0031] According to a semiconductor device provided by an embodiment of the present application, as shown in the figure, Figure 1 the semiconductor device includes: a substrate 10 including a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 being located on one side of the substrate 11, the substrate 10 having a first doping type; a plurality of doped regions 20 being spaced apart in the epitaxial layer 12 and located in a side surface of the epitaxial layer 12 away from the substrate 11, the doped regions 20 having a second doping type; and a plurality of ohmic contact structures 30 being spaced apart on a side of the epitaxial layer 12 in a cell region of the semiconductor device away from the substrate 11, the ohmic contact structures 30 being in contact with the doped regions 20, and the ohmic contact structures 30 containing carbon.

[0032] By setting the ohmic contact structure in the semiconductor device as a structure containing carbon C. By introducing C atoms at the ohmic contact structure, a composite layer of Si, C, and an ohmic contact metal can be formed in the ohmic contact region, the ohmic contact metal can be nickel, and the excessive diffusion of nickel atoms is effectively inhibited by using carbon atoms, thereby stabilizing the nickel silicide phase state during high-temperature annealing and avoiding the formation of high-resistance NiSi2, ensuring the low resistivity and thermal stability of the contact region. The present technical solution can effectively control the diffusion of Ni atoms in the Ni-Si alloying process, solving the problems of increased leakage current and high ohmic contact resistance of the semiconductor device caused by Ni diffusion in the prior art. Through the above technical means, the present application reduces the contact resistivity of the ohmic contact region, improves the electrical performance and reliability of the device, simplifies the process, widens the process window, improves the manufacturing yield, and especially reduces the conduction loss, optimizes the switching speed and frequency characteristics.

[0033] In the above embodiments, the substrate can be a silicon carbide wafer, the thickness of the epitaxial layer can be between 5 and 10 μm, and the carrier concentration of the epitaxial layer can be between 1e10 and 1e20 cm⁻¹. -3 Between these. The implantation type of the doped regions is the opposite of that of the epitaxial layers, with a doping concentration of 1e15~1e20 cm⁻¹. -3 The width is between 8 and 11 μm, the depth is between 1 and 3 μm, and the spacing is between 2 and 4 μm.

[0034] In the above embodiments, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). This application does not impose specific limitations.

[0035] In the above embodiments, the doped regions include larger doped regions and smaller doped regions. The larger doped regions optimize conduction and reduce the forward voltage drop (VF). The larger P-region has a higher injection area, injecting more minority carriers (holes) into the drift region (epitaxy layer) during forward conduction, triggering conductance modulation. This reduces the resistivity of the high-resistivity drift region, thus lowering the forward voltage drop (VF) and reducing conduction losses. The smaller doped regions optimize blocking, reducing the forward voltage drop (VF), improving the breakdown voltage (BV) and reliability. The smaller doped regions are areas where small currents preferentially flow; as the voltage increases, the current gradually opens up the larger doped regions, reducing the overall forward voltage drop. Furthermore, the smaller doped regions are located at the edge terminations, forming field-limiting loops that flatten and disperse the equipotential lines at the edges, resulting in a more uniform electric field distribution.

[0036] In some alternative implementations, such as Figure 1 As shown, the ohmic contact structure 30 includes a first ohmic contact layer 31 and a second ohmic contact layer 32. The second ohmic contact layer 32 is located on the side of the first ohmic contact layer 31 away from the epitaxial layer 12, and the second ohmic contact layer 32 comprises carbon. This double-layer ohmic contact structure can significantly optimize the electrical performance of the semiconductor device. The first ohmic contact layer 31 typically contacts the doped region (the region with a second doping type) directly to facilitate current injection and extraction. The second ohmic contact layer 32 is located outside the first ohmic contact layer 31, away from the epitaxial layer, and contains carbon atoms. The C atoms effectively suppress the excessive diffusion of Ni atoms, which not only effectively improves the contact performance with the surface but also makes the ohmic region contact tighter, further improving contact reliability and thermal stability.

[0037] In the above optional embodiments, the first ohmic contact layer can be a Ni-Si layer, wherein Si acts as a reaction matrix, and Si reacts with Ni to form a low-resistance silicide (NiSi) that constitutes the main body of the ohmic contact. Si can diffuse with Ni to achieve mutual solubility.

[0038] In some alternative embodiments, the material of the second ohmic contact layer includes metals and non-metals. The metals include Ni, and the non-metals include Si. Both C and Si are non-metals. Si can not only react with Ni to form a low-resistivity NiSi phase, but also act as a diffusion barrier, limiting the excessive diffusion of Ni atoms. Adding Si to the second ohmic contact layer can, to a certain extent, isolate Ni from other potential metal layers, reduce intermetallic interactions, prevent the formation of high-resistivity compounds, and ensure the stability and consistency of the contact resistance. Based on the property that carbon atoms can effectively suppress the excessive diffusion of nickel (Ni) atoms, the above three elements form a Si-C-Ni composite layer. In the fabrication of the Si-C-Ni composite layer, the property of carbon atoms to effectively suppress the excessive diffusion of Ni atoms is utilized. The Si-C-Ni composite layer (second ohmic contact layer) and the Ni-Si metal layer (first ohmic contact layer) are stacked, which effectively controls the tendency of Ni atoms to diffuse, improves the contact performance in the ohmic region, and controls its morphology, avoiding the uneven distribution of Ni-Si metal in the ohmic region. This not only effectively improves the contact performance with the surface but also makes the contact in the ohmic region tighter. Furthermore, the overall process of the semiconductor device in this application is simple and does not involve many process changes, making it more universal. By introducing a fast-conducting pad layer (Si-C-Ni composite layer) formed of highly conductive metals and other non-metals between the ohmic contact region and the upper main interconnect metal of the semiconductor device, rapid conduction and improved switching speed can be achieved.

[0039] In some alternative embodiments, the target material for fabricating the first ohmic contact layer includes nickel-vanadium. The addition of vanadium (V) helps the ohmic contact operate stably and reliably over long periods at high temperatures. V can increase the phase transition temperature, stabilizing NiSi to 900°C; V can also form a diffusion barrier, suppressing excessive diffusion of nickel (Ni); V can make the NiSi interface smoother and more uniform; and V can improve substrate adhesion.

[0040] In some alternative embodiments, the atomic proportion of the metal in the second ohmic contact layer is 42% to 47%. This metal can be Ni. An appropriate Ni content ensures sufficient conductivity in the composite layer. As the primary conductive metal element, Ni plays a decisive role in the overall conductivity of the composite layer. The aforementioned 42% to 47% Ni content balances conductivity with other properties, such as diffusion control, to achieve optimal conductivity. A Ni content below 50% helps control excessive diffusion of Ni atoms at high temperatures, preventing uneven NiSi layer formation or penetration into other layers, and avoiding junction "piercing" and increased leakage current.

[0041] In some alternative embodiments, the atomic proportion of carbon in the second ohmic contact layer is 5% to 10%, and the atomic proportion of silicon is 48% to 52%. Setting the atomic proportion of C atoms within the above range can significantly improve the thermal stability of NiSi by 150 to 200°C (for example, if it is relatively stable at around 750°C, it can now be increased to about 950°C). Carbon atoms effectively suppress Ni diffusion by forming complexes with Ni or through solid solution effects, especially during high-temperature annealing, which helps maintain the stability and uniformity of the NiSi phase and avoids an increase in contact resistance. Setting the atomic proportion of Si atoms within the above range ensures the formation of sufficient Si-C-Ni alloy in the composite layer, which is the material basis for achieving low contact resistance.

[0042] In some alternative implementations, such as Figure 1 As shown, the semiconductor device also includes a first oxide layer 40, an insulating layer 50, a source electrode 60, and a drain electrode 70. The insulating layer 50 is located on the side of the first oxide layer 40 away from the epitaxial layer 12 of the semiconductor device's terminal region. The source electrode 60 covers the first oxide layer 40, the second ohmic contact layer 32, and the doped region 20. The drain electrode 70 is located on the side of the substrate 11 away from the epitaxial layer 12. The first oxide layer 40 can be 17.5 nm thick and made of silicon dioxide, used for passivation of the epitaxial layer surface. The insulating layer 50 can be 0.8 μm thick and provides insulation shielding for current, preventing short circuits at points in the circuit that should not be connected, thus providing protection and passivation. The source electrode 60, as the current input terminal, can form good contact with the doped region and the second ohmic contact layer, ensuring efficient current injection. The drain electrode 70, as the current output terminal, can form good contact with the substrate 11, ensuring efficient current extraction. The drain electrode 70 also provides mechanical support, especially in flip-chip or high-power devices, helping to maintain the integrity and stability of the device structure. The thickness of the source electrode 60 and the drain electrode 70 can be 3~4μm.

[0043] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example...Figure 2 As shown, the method includes the following steps:

[0044] Step S1, providing a substrate, the substrate including a substrate and an epitaxial layer, the substrate having a first doping type;

[0045] Specifically, the substrate can be a silicon carbide wafer, the thickness of the epitaxial layer can be between 5 and 10 μm, and the carrier concentration of the epitaxial layer can be between 1e10 and 1e20 cm⁻¹. -3 The aforementioned epitaxial layer can be prepared by chemical vapor deposition (CVD).

[0046] Step S2: Multiple spaced doped regions are formed in the epitaxial layer. The side surface of the doped region facing away from the substrate is located in the side surface of the epitaxial layer facing away from the substrate. The doped region has a second doping type.

[0047] Specifically, the implantation type of the doped region is opposite to that of the epitaxial layer, and the doping concentration is 1e15~1e20cm. -3 The width of the P-type region is between 8 and 11 μm, the depth is between 1 and 3 μm, and the spacing is between 2 and 4 μm. The P-type region is designed to achieve the special function of the MPS diode, namely, to achieve different electrical performances in different regions and optimize the balance between conduction loss and breakdown voltage.

[0048] Step S3: A plurality of spaced ohmic contact structures are formed on the side of the epitaxial layer of the cell region of the semiconductor device away from the substrate. The ohmic contact structures are in contact with the doped region and contain carbon.

[0049] Specifically, an ohmic contact structure can be formed above the doped region by magnetron sputtering deposition of a composite material. This composite material can be a metal layer including C. The addition of carbon can effectively suppress excessive diffusion of Ni, improve the thermal stability of the composite layer, and avoid the formation of high-resistivity NiSi2.

[0050] In this embodiment, the ohmic contact structure of the semiconductor device prepared contains carbon. Introducing C atoms into the ohmic contact structure allows the formation of a composite layer of Si, C, and ohmic contact metal in the ohmic contact region. The ohmic contact metal can be nickel. The carbon atoms effectively suppress excessive diffusion of nickel atoms, thereby stabilizing the nickel silicide phase during high-temperature annealing and preventing the formation of high-resistivity NiSi2, ensuring low resistivity and thermal stability of the contact region. This technical solution effectively controls the diffusion of Ni atoms during Ni-Si alloying, solving the problems of increased leakage current and high ohmic contact resistance in semiconductor devices caused by Ni diffusion in previous technologies. Through the above technical means, this application achieves a reduction in contact resistivity in the ohmic contact region, improving the electrical performance and reliability of the device, while simplifying the process, widening the process window, and improving manufacturing yield, especially reducing conduction losses and optimizing switching speed and frequency characteristics.

[0051] In some alternative implementations, such as Figure 3 As shown, after forming the doped region 20 and before forming the ohmic contact structure, the fabrication method further includes: sequentially forming a first oxide layer 40 and an insulating layer 50 on the epitaxial layer 12, and patterning the first oxide layer 40 and the insulating layer 50 to expose a portion of the epitaxial layer 12; forming a second oxide layer 80 on the insulating layer 50, and patterning the second oxide layer 80 to expose a portion of the epitaxial layer 12. A first oxide layer 40 with a thickness of 17.5 nm is grown on the epitaxial layer 12 where the doped region 20 has been formed. Then, an insulating layer 50 with a thickness of 0.8 μm is grown using a CVD process. The first oxide layer 40 and the insulating layer 50 are patterned. Only the portion of the insulating layer 50 located in the semiconductor device termination region is retained, along with the portion of the first oxide layer 40 located in the termination region and a portion of the first oxide layer 40 located in the cell region. Next, silicon dioxide material is deposited on the insulating layer 50 and the epitaxial layer 12 to form a second oxide layer 80, and the second oxide layer 80 is patterned. Only the second oxide layer 80 in the terminal region is retained, and the exposed epitaxial layer 12 is used for subsequent fabrication of ohmic contact structures.

[0052] In the specific implementation process, the step S3 above, which involves forming multiple spaced ohmic contact structures on the side of the epitaxial layer of the semiconductor device's cell region away from the substrate, can be achieved through the following steps:

[0053] like Figure 4 and Figure 5As shown, a first ohmic contact layer 31 is formed on the second oxide layer 80, the epitaxial layer 12, and the first oxide layer 40; SiC material is deposited on the first ohmic contact layer 31 to form a SiC film; the SiC film is subjected to surface treatment, which includes at least one of the following: annealing and passivation; Ni target material is deposited on the SiC material using magnetron sputtering, and a second ohmic contact layer 32 is formed after annealing; a portion of the first ohmic contact layer 31, a portion of the second ohmic contact layer 32, and the second oxide layer 80 are removed using an etching process, and the remaining first ohmic contact layer 31 and second ohmic contact layer 32 form an ohmic contact structure.

[0054] The first ohmic contact layer can be formed by magnetron sputtering Ni metal, with its thickness effectively controlled to around 80 nm. Ni-V (nickel-vanadium) metal can be used as the target material, and controlling the overall evaporation rate effectively controls the density of the Ni metal growth. Ni-V alloy as a target material improves thermal stability, interface reaction control, and device reliability. The second ohmic contact layer can be formed by magnetron sputtering SiC and Ni targets to synthesize a Si-C-Ni composite layer. Carbon atoms effectively suppress excessive diffusion of nickel atoms, resulting in a tighter contact between this layer and the upper and lower interfaces. The atomic ratio of Si-C-Ni can be as follows: Si: 48%~52%, C: 5%~10%, Ni: 42%~47%, with an overall thickness of 90 nm~110 nm. Using multiple Si-C-Ni targets with a evaporation rate controlled at 0.5~5 Å / s ensures a tight bond layer on the substrate.

[0055] The specific growth steps are as follows: First, a thin SiC film (40nm is sufficient) is deposited on the surface of the first ohmic contact layer. Using pure Si and pure C targets, sputtering is performed in a mixed atmosphere of argon and nitrogen. The ratio of Si to C in the film can be adjusted by controlling the sputtering power. The sputtering rate of Si can be approximately 5 Å / s, and the sputtering rate of C can be approximately 0.5 Å / s. The sputtering time of C is also controlled. It is expected that after reaching the desired thickness, sputtering only Si targets will ensure the overall proportions are fully maintained. Next, the SiC surface is surface-treated, and a Ni metal film (50nm is sufficient) is deposited on the SiC wafer surface. Finally, high-temperature annealing (550℃ is sufficient) promotes the reaction between Ni and Si to form a stable compound, ultimately forming a Si-C-Ni composite layer. Since Ni is a fast-diffusion element, an interface will form between Ni and Si, allowing Ni to escape to the upper and lower layers.

[0056] The surface treatments mentioned above can be: pre-hydrogenation (pre-hydrogenation involves passing an argon-hydrogen mixture through a vacuum reaction chamber and using radio frequency (RF) to generate a plasma source, exposing the wafer to hydrogen plasma for 30-60 seconds at a relatively low temperature of 200℃~300℃, where active hydrogen ions effectively passivate the surface and solve most surface defects), high-temperature annealing (high-temperature annealing can repair lattice damage and reduce defect density), plasma-enhanced chemical vapor deposition (PECVD) passivation (PECVD itself generates a large number of hydrogen atoms, which passivate the underlying defects and interfaces in situ during deposition), fluorine passivation (fluorine atoms are larger and more electrically charged, forming stronger Si-F bonds on the original surface. Fluorine can more effectively passivate the interface layer), and chlorine passivation (chlorine-containing gases (such as HCl / TCA / TCE) are introduced during the oxidation process, and chlorine atoms are bound to the interface, which not only passivates the interface states but also removes metal impurities and improves minority carrier lifetime).

[0057] After the formation of the second ohmic contact layer and before wet etching of the second oxide layer, the ohmic contact region undergoes rapid thermal annealing. High temperature activates the diffusion ability of metal and semiconductor atoms, causing them to react at the interface to form a nickel-silicon alloy. Rapid heating and cooling prevents over-reaction leading to junction penetration or the formation of a high-resistivity phase. The rapid annealing temperature is controlled at 420–450°C, and the time is controlled at 30–60 seconds, using a nitrogen and hydrogen gas atmosphere.

[0058] First, photolithography is performed on the first and second ohmic contact layers, retaining the first and second ohmic contact layers in the ohmic contact region. Then, a wet etching process is used to remove the second oxide layer, leaving the remaining first and second ohmic contact layers to form an ohmic contact structure. The solution for removing the second oxide layer can be DHF1%+SC1+SC2+IPA (HF / NH4OH / HCl / H2O2), and the process parameters can include: room temperature for 27 minutes.

[0059] The aforementioned second ohmic contact layer can also be other diffusion barrier layers, such as titanium nitride / titanium. Titanium nitride has a dense columnar crystal structure that can physically block the path of Ni atoms and prevent Ni from being oxidized; tungsten / tungsten nitride layers can also serve as effective barrier layers. Before depositing the second ohmic contact layer, the surface of the epitaxial layer can be bombarded with Ge ions to make it amorphous (the amorphous state lacks regular lattice channels, which further hinders Ni diffusion, resulting in more uniform Ni-Si formation and reducing lateral diffusion and junction penetration).

[0060] After forming the ohmic contact structure, the source electrode and drain electrode are formed on the front and back sides of the device, thus completing the fabrication of the semiconductor device.

[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A substrate, comprising a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate, the substrate having a first doping type; Multiple doped regions are spaced apart in the epitaxial layer, and the side surface of the doped region facing away from the substrate is located in the side surface of the epitaxial layer facing away from the substrate, and the doped region has a second doping type; Multiple ohmic contact structures are spaced apart on the side of the epitaxial layer opposite to the substrate in the cell region of the semiconductor device. The ohmic contact structures are in contact with the doped region and contain carbon.

2. The semiconductor device according to claim 1, characterized in that, The ohmic contact structure includes a first ohmic contact layer and a second ohmic contact layer, wherein the second ohmic contact layer is located on the side of the first ohmic contact layer opposite to the epitaxial layer, and the second ohmic contact layer includes the carbon.

3. The semiconductor device according to claim 2, characterized in that, The material of the second ohmic contact layer includes metals and non-metals, the metals including nickel and the non-metals including silicon.

4. The semiconductor device according to claim 2, characterized in that, The target material for preparing the first ohmic contact layer includes nickel-vanadium.

5. The semiconductor device according to claim 3, characterized in that, The atomic ratio of the metal in the second ohmic contact layer is 42% to 47%.

6. The semiconductor device according to claim 3, characterized in that, The atomic proportion of carbon in the second ohmic contact layer is 5% to 10%, and the atomic proportion of silicon is 48% to 52%.

7. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a first oxide layer, an insulating layer, a source electrode, and a drain electrode, wherein the insulating layer is located on the side of the epitaxial layer opposite to the terminal region of the semiconductor device, the source electrode covers the first oxide layer, the second ohmic contact layer, and the doped region, and the drain electrode is located on the side of the substrate opposite to the epitaxial layer.

8. A method for fabricating a semiconductor device, characterized in that, The method for preparing the semiconductor device according to any one of claims 1 to 7 comprises: A substrate is provided, the substrate comprising a substrate and an epitaxial layer, the substrate having a first doping type; Multiple spaced doped regions are formed in the epitaxial layer, and the side surface of the doped region facing away from the substrate is located in the side surface of the epitaxial layer facing away from the substrate. The doped region has a second doping type. Multiple spaced ohmic contact structures are formed on the side of the epitaxial layer of the cell region of the semiconductor device away from the substrate. The ohmic contact structures are in contact with the doped region and contain carbon.

9. The preparation method according to claim 8, characterized in that, After forming the doped region and before forming the ohmic contact structure, the fabrication method further includes: A first oxide layer and an insulating layer are sequentially formed on the epitaxial layer, and the oxide layer and the insulating layer are patterned to expose a portion of the epitaxial layer. A second oxide layer is formed on the insulating layer, and the second oxide layer is patterned to expose a portion of the epitaxial layer.

10. The preparation method according to claim 9, characterized in that, The step of forming a plurality of spaced ohmic contact structures on the side of the epitaxial layer away from the substrate in the cell region of the semiconductor device includes: A first ohmic contact layer is formed on the second oxide layer, the epitaxial layer, and the first oxide layer; SiC material is deposited on the first ohmic contact layer to form a SiC film layer, and the SiC film layer is subjected to surface treatment, the surface treatment including at least one of the following: annealing treatment and passivation treatment; A Ni target is deposited on the SiC material using a magnetron sputtering process, and a second ohmic contact layer is formed after annealing. An etching process is used to remove part of the first ohmic contact layer, part of the second ohmic contact layer, and the second oxide layer, leaving the remaining first ohmic contact layer and second ohmic contact layer to form the ohmic contact structure.

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