Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the steps that a substrate is provided and provided with active columns and isolation layers which are arranged at intervals in the first direction, and the active columns and the isolation layers extend in the second direction; removing a part of the isolation layer to form a first groove exposing the top surface and a part of the side surface of the active column; forming a filling material layer which at least exposes the top surface of the active column in the first groove; forming a metal layer at least directly covering the top surface of the active pillar; performing heat treatment to form a conductive structure on the active column, wherein the conductive structure extends along a third direction; at least removing the filling material layer to expose the first groove; a first dielectric layer is deposited at least on the side surface of the first groove to form a second groove, and the first dielectric layer covers the side surface and the top surface of the conductive structure; and forming a second dielectric layer filling the second groove. According to the manufacturing method of the semiconductor structure, the performance of a semiconductor device can be improved, and the device yield can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a manufacturing method of semiconductor structure and semiconductor structure. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory, compared with static memory, DRAM memory has the advantages of simple structure, low manufacturing cost and high capacity density. With the development of semiconductor industry, semiconductor devices are becoming highly integrated, i.e. miniaturization. Highly integrated semiconductor devices are changing from planar channel transistors to vertical channel transistors (VCT).

[0003] However, in the manufacturing process of vertical channel transistors, the performance and yield of semiconductor memory devices are still low. How to improve the performance and yield of semiconductor memory devices is a technical problem to be solved at present. SUMMARY

[0004] Embodiments of the present disclosure provide a manufacturing method of semiconductor structure and semiconductor structure, which at least have advantages of improving the performance and yield of semiconductor structure.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a manufacturing method of semiconductor structure, comprising:

[0006] providing a substrate, the substrate has active pillars and isolation layers arranged at intervals along a first direction, the active pillars and the isolation layers both extend along a second direction, the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the second direction is perpendicular to the first direction;

[0007] removing part of the isolation layers to form first recesses, the first recesses expose the top surface and part of the side surface of the active pillars;

[0008] forming a filling material layer in the first recesses, the filling material layer at least exposes the top surface of the active pillars;

[0009] forming a metal layer, the metal layer at least directly covers the top surface of the active pillars;

[0010] performing heat treatment to form a conductive structure on the active pillars, the conductive structure extends along a third direction, and the third direction is perpendicular to the first direction and the second direction;

[0011] at least removing the filling material layer to expose the first recesses;

[0012] depositing a first dielectric layer on at least a side surface of the first recess to form a second recess, the first dielectric layer covering a side surface and a top surface of the conductive structure;

[0013] forming a second dielectric layer, the second dielectric layer filling the second recess.

[0014] In some embodiments, in the step of forming the filling material layer in the first recess, in the second direction, a height of a top surface of the filling material layer is controlled to be not lower than a height at a position of 50% of a thickness of the conductive structure, and the filling material layer exposes a top surface of the active pillar.

[0015] In some embodiments, the step of forming the filling material layer in the first recess comprises:

[0016] forming an initial filling material layer in the first recess, the initial filling material layer filling the first recess and covering a top surface of the active pillar;

[0017] removing at least the initial filling material layer covering the top surface of the active pillar, such that in the second direction, a height of a top surface of the remaining initial filling material layer is not lower than a height at a position of 50% of a thickness of the conductive structure, the remaining initial filling material layer serving as the filling material layer; or

[0018] forming an initial filling material layer in the first recess, such that in the second direction, a height of a top surface of the initial filling material layer is not lower than a height at a position of 50% of a thickness of the conductive structure, and the initial filling material layer exposes a top surface of the active pillar, the initial filling material layer serving as the filling material layer.

[0019] In some embodiments, in the step of removing at least the filling material layer, an etching selectivity ratio of the filling material layer to the conductive structure is not less than 20.

[0020] In some embodiments, a material of the filling material layer comprises at least one of a carbon-based material, a metal material, and a dielectric material, wherein,

[0021] the carbon-based material comprises at least one of a spin-on hard mask, a spin-on organic carbon, a photoresist material, and an amorphous carbon layer; and / or

[0022] the metal material comprises tungsten; and / or

[0023] the dielectric material comprises silicon nitride; and / or

[0024] a material of the conductive structure comprises at least one of NiSi, TiSi, TaSi, and CoSi.

[0025] In some embodiments, the step of depositing a first dielectric layer at least on the side surface of the first recess comprises:

[0026] forming a first dielectric material layer covering the side surface and the bottom surface of the first recess and the top surface of the conductive structure, the first dielectric material layer as the first dielectric layer; or

[0027] forming a first dielectric material layer covering the side surface and the bottom surface of the first recess and the top surface of the conductive structure;

[0028] removing the first dielectric material layer covering the bottom surface of the first recess, the remaining first dielectric material layer as the first dielectric layer.

[0029] In some embodiments, after the step of depositing a first dielectric layer, before the step of forming a second dielectric layer, further comprising:

[0030] forming a third dielectric layer filling the second recess and covering the first dielectric layer;

[0031] the substrate comprises an array region and a peripheral region, the third dielectric layer located within the second recess of the array region is removed;

[0032] the step of forming a second dielectric layer comprises: forming a second dielectric layer filling the second recess of the array region and covering the first dielectric layer.

[0033] In some embodiments, in the second direction, the depth of the first recess is greater than the thickness of the conductive structure.

[0034] In some embodiments, the second dielectric layer has an air gap, in the second direction, the depth of the air gap is greater than the thickness of the conductive structure; and / or

[0035] in the first direction, the maximum width of the air gap is 1 / 3-4 / 5 of the width of the second recess.

[0036] In some embodiments, the conductive structure has a square-shaped orthographic projection on the surface of the substrate; and / or

[0037] in the second direction, the conductive structure has a flat or nearly flat side surface; and / or

[0038] in the second direction, the first recess exposed after removing the filling material layer has a flat or nearly flat side surface; and / or

[0039] In the first direction, the first recesses exposed after the removal of the fill material layer have flat or nearly flat bottom surfaces and the bottom surfaces of the adjacent first recesses have consistent or nearly consistent heights.

[0040] In another aspect, the present disclosure provides a semiconductor structure, comprising: a substrate having active pillars and isolation layers spaced along a first direction, the active pillars and the isolation layers both extending along a second direction, the first direction being parallel to a surface of the substrate, the second direction being parallel to a thickness direction of the substrate, the second direction being perpendicular to the first direction;

[0041] a conductive structure on and connected to the active pillars, the conductive structure extending along a third direction, the third direction being perpendicular to the first direction and the second direction;

[0042] a first recess between adjacent conductive structures;

[0043] a second recess in the first recess;

[0044] a first dielectric layer between the first recess and the second recess, the first dielectric layer covering at least a side surface of the first recess and covering a side surface and a part of a top surface of the conductive structure;

[0045] a second dielectric layer filling the second recess.

[0046] In some embodiments, the substrate comprises an array region and a peripheral region, the second dielectric layer fills the second recess in the array region; the semiconductor structure further comprises:

[0047] a third dielectric layer filling the second recess in the peripheral region.

[0048] In some embodiments, in the second direction, a depth of the first recess is greater than a thickness of the conductive structure.

[0049] In some embodiments, the second dielectric layer has an air gap, in the second direction, a depth of the air gap is greater than a thickness of the conductive structure; and / or

[0050] In the first direction, a maximum width of the air gap is 1 / 3-4 / 5 of a width of the second recess.

[0051] In some embodiments, a normal projection of the conductive structure on a surface of the substrate is a square; and / or

[0052] In the second direction, the conductive structure has flat or nearly flat side surfaces; and / or

[0053] In the second direction, the first recess has a flat or nearly flat side surface; and / or

[0054] In the first direction, the first recess has a flat or nearly flat bottom surface and a consistent or nearly consistent height adjacent to the bottom surface of the first recess.

[0055] The manufacturing method and semiconductor structure provided by the embodiments of the present disclosure first remove part of the isolation layer to form a first recess exposing a top surface and part of a side surface of an active pillar; then form a filling material layer exposing at least the top surface of the active pillar in the first recess; then form a metal layer covering at least the top surface of the active pillar directly, perform heat treatment to form a conductive structure on the active pillar, and then remove at least the filling material layer to expose the first recess; and finally form a first dielectric layer and a second dielectric layer. First, by forming the first recess, then forming the filling material layer in the first recess, and then removing the filling material layer after forming the conductive structure, on one hand, it makes it possible to simultaneously compatible in the manufacturing method of removing part of the isolation layer to form the first recess and preparing the bit line with the conductive structure as a mask, on the other hand, it can also prevent the morphology of the conductive structure from changing, avoid damaging the top and sidewall of the conductive structure, that is, avoid the conductive structure appearing to be thin and round (i.e. necking) in the final formation, so that the orthographic projection of the conductive structure on the substrate surface is square and has a flat or nearly flat side surface in the thickness direction of the substrate (i.e. the sidewall morphology of the conductive structure is vertical or nearly vertical). Therefore, it can reduce the resistance of the conductive structure itself and improve the performance of the conductive structure, thereby improving the yield of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0056] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not limiting to the embodiments, unless otherwise specifically stated, the figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings needed to be used in the embodiments will be briefly introduced below, obviously, the drawings in the following description can only be some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0057] Figures 1A-1F is a structural schematic diagram of each step of the manufacturing method of the semiconductor structure in the related art, Figure 1G shows a structural diagram of the semiconductor structure in the related art;

[0058] Figure 2 is a process flow diagram of each step of a specific embodiment of the manufacturing method of the semiconductor structure of the present disclosure,

[0059] Figures 3A-3N is a structural schematic diagram of each step of a specific embodiment of a method of manufacturing a semiconductor structure of the present disclosure, wherein, Figure 3M and Figure 3N are structural schematic diagrams of a specific embodiment of a semiconductor structure of the present disclosure, respectively;

[0060] Figures 4A-4L is a structural schematic diagram of each step of another specific embodiment of a method of manufacturing a semiconductor structure of the present disclosure, wherein, Figure 4K and Figure 4L are structural schematic diagrams of another specific embodiment of a semiconductor structure of the present disclosure, respectively;

[0061] Figure 5 is a structural schematic diagram of another specific embodiment of a semiconductor structure of the present disclosure;

[0062] Figure 6 is a structural schematic diagram of a memory device including a wafer of a semiconductor structure of the present disclosure and a wafer bonded thereto;

[0063] Figure 7 is a structural schematic diagram of a memory device including a wafer of a semiconductor structure of the present disclosure and another wafer bonded thereto. DETAILED DESCRIPTION

[0064] The technical solutions of the present disclosure will be described in further detail below in conjunction with the accompanying drawings and examples. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0065] The present disclosure will be described in further detail below in conjunction with the accompanying drawings and examples. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0066] It can be understood that the meanings of "on", "over", and "above" of the present disclosure should be interpreted in the broadest way, such that "on" not only means the meaning of "on" with no intervening features or layers therebetween (i.e., directly on), but also includes the meaning of "on" with intervening features or layers therebetween.

[0067] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily mean a specific order or sequence.

[0068] like Figures 1A-1F As shown, in the fabrication process of semiconductor devices using related technologies, such as... Figure 1A As shown, the substrate 1 has active pillars 11 and isolation layers 12 spaced apart along a first direction X. Both the active pillars 11 and the isolation layers 12 extend along a second direction Y. The first direction X is parallel to the surface of the substrate 1, and the second direction Y is parallel to the thickness direction of the substrate 1. The second direction Y is perpendicular to the first direction X. After the active pillars 11 and the isolation layers 12 are processed to be flush, as shown... Figure 1B As shown, a metal layer 2 is formed on the active pillar 11 and the isolation layer 12, and after heat treatment, a layer as shown is formed on the active pillar 11. Figure 1C The conductive structure 3 shown (in one embodiment, the metal layer 2 can be made of Pt-doped Ni (NiPt). During heat treatment, Ni diffuses into the Si lattice of the active pillar 11, and NiSi is formed after Ni is doped into the Si lattice, which constitutes the conductive structure 3 (the conductive structure 3 extends along the third direction Z, which is perpendicular to the first direction X and the second direction Y). The remaining metal layer is removed by acid washing to obtain the conductive structure 3 shown. Figure 1C (The structure shown); secondly, as shown Figure 1D As shown, a portion of the isolation layer 12 is etched back using a wet etching process (such as the Certas process) to form the first trench 21. During this wet etching process, under the action of a mixed gas composed of HF gas, water vapor, and a carrier gas (such as nitrogen or argon), HF reacts with the isolation layer 12 (such as silicon oxide in the isolation layer 12), thus completing the back etching of a portion of the isolation layer 12. Since HF also reacts with Ni, the morphology of the conductive structure 3 changes. That is, HF damages the top and sidewalls of the conductive structure 3, causing the conductive structure 3 to exhibit... The thinning and rounding morphology (i.e., necking) causes the originally thick bit lines to become thinner and lose their flush side surfaces in the second direction Y, thereby increasing the resistance of the bit lines themselves. Correspondingly, the first trench 21 also loses its flush side surface in the second direction Y. At the same time, the presence of HF and oxygen may cause the Ni escaping from the conductive structure 3 to turn into nickel oxide, which can prevent the back etching of the isolation layer 12. This results in uneven back etching heights between adjacent isolation layers 12, and the top surface of the isolation layer 12 in the first direction X after back etching is not flush (it is U-shaped or V-shaped). Figure 1D Not shown in the image; please refer to the following for details. Figure 1G Correspondingly, in the first direction X, the first groove 21 loses its flush bottom surface (the bottom surface is U-shaped or V-shaped). Figure 1D Not shown in the image; please refer to the following for details. Figure 1G Furthermore, the heights of the bottom surfaces of adjacent first grooves 21 are not consistent; this part of the morphology can be seen in detail in [reference needed]. Figure 1D The A structure in the text, and the A structure can also be found in the following examples.Figure 1G The semiconductor structure is shown in FIG. 1. As shown in FIG. 1, a substrate 1 is provided, which has active pillars 2 and isolation layers 3 arranged in a first direction, and the active pillars 2 and the isolation layers 3 extend in a second direction. The first direction is parallel to the surface of the substrate 1, and the second direction is parallel to the thickness direction of the substrate 1, and the second direction is perpendicular to the first direction. Figure 1E As shown in FIG. 2, after the formation of the conductive structure 3, a first dielectric layer 4 is deposited in the first trench 21 in a conformal manner, and a second recess 22 is formed, in which the first dielectric layer 4 covers the side surface and top surface of the conductive structure 3 and the side surface and bottom surface of the first trench 21. Finally, as shown in FIG. 3, a second dielectric layer 5 is formed to fill the second recess 22, Figure 1F As shown in FIG. 3, a semiconductor structure is shown in FIG. 1. As shown in FIG. 3, a substrate 1 is provided, which has active pillars 2 and isolation layers 3 arranged in a first direction, and the active pillars 2 and the isolation layers 3 extend in a second direction. The first direction is parallel to the surface of the substrate 1, and the second direction is parallel to the thickness direction of the substrate 1, and the second direction is perpendicular to the first direction. Figure 1F As shown in FIG. 3, a semiconductor structure is shown in FIG. 1. As shown in FIG. 3, a substrate 1 is provided, which has active pillars 2 and isolation layers 3 arranged in a first direction, and the active pillars 2 and the isolation layers 3 extend in a second direction. The first direction is parallel to the surface of the substrate 1, and the second direction is parallel to the thickness direction of the substrate 1, and the second direction is perpendicular to the first direction. Figure 1G As shown in FIG. 3, a semiconductor structure is shown in FIG. 1. As shown in FIG. 3, a substrate 1 is provided, which has active pillars 2 and isolation layers 3 arranged in a first direction, and the active pillars 2 and the isolation layers 3 extend in a second direction. The first direction is parallel to the surface of the substrate 1, and the second direction is parallel to the thickness direction of the substrate 1, and the second direction is perpendicular to the first direction. Figure 1F The structure B' in FIG. 4 corresponds to the structure B in FIG. 3. In addition, in the semiconductor structure, due to the high dielectric constant of the first dielectric layer 4, the parasitic capacitance between the conductive structures 3 is relatively large. Figure 1G The structure B' in FIG. 4 corresponds to the structure B in FIG. 3. In addition, in the semiconductor structure, due to the high dielectric constant of the first dielectric layer 4, the parasitic capacitance between the conductive structures 3 is relatively large.

[0069] Therefore, the present disclosure provides a semiconductor structure and a manufacturing method thereof, which can protect the topography of the conductive structure, reduce the existence of defects, and reduce the resistance of the conductive structure itself and the parasitic capacitance between the conductive structures.

[0070] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to make the reader better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0071] As shown in FIG. 3, a semiconductor structure is shown in FIG. 1. As shown in FIG. 3, a substrate 1 is provided, which has active pillars 2 and isolation layers 3 arranged in a first direction, and the active pillars 2 and the isolation layers 3 extend in a second direction. The first direction is parallel to the surface of the substrate 1, and the second direction is parallel to the thickness direction of the substrate 1, and the second direction is perpendicular to the first direction. Figure 2 The manufacturing method of the semiconductor structure of the present disclosure includes:

[0072] S1, providing a substrate, the substrate has active pillars and isolation layers arranged in a first direction, and the active pillars and the isolation layers extend in a second direction, the first direction is parallel to the surface of the substrate, and the second direction is parallel to the thickness direction of the substrate, and the second direction is perpendicular to the first direction;

[0073] S2, removing part of the isolation layer to form a first recess, the first recess exposes the top surface and part of the side surface of the active pillar;

[0074] S3, forming a filling material layer in the first recess, the filling material layer at least exposes the top surface of the active pillar;

[0075] S4, forming a metal layer, the metal layer at least directly covers the top surface of the active pillar;

[0076] S5, performing a heat treatment to form a conductive structure on the active pillar, the conductive structure extending along a third direction, the third direction being perpendicular to the first direction and the second direction;

[0077] S6, removing at least the filling material layer to expose the first recess;

[0078] S7, depositing a first dielectric layer at least on a side surface of the first recess to form a second recess, the first dielectric layer covering a side surface and a top surface of the conductive structure;

[0079] S8, forming a second dielectric layer, the second dielectric layer filling the second recess.

[0080] Figures 3A-3N is a structural schematic diagram of each step of a specific embodiment of a manufacturing method of a semiconductor structure of the present disclosure, wherein, Figure 3M and Figure 3N respectively show a structural schematic diagram of a specific embodiment of a semiconductor structure of the present disclosure. Figures 4A-4L is a structural schematic diagram of each step of another specific embodiment of a manufacturing method of a semiconductor structure of the present disclosure, wherein, Figure 4K and Figure 4L respectively show a structural schematic diagram of another specific embodiment of a semiconductor structure of the present disclosure. Wherein, Figures 4A-4L is another specific embodiment of the corresponding step of Figures 3C-3N , as Figure 4A is another specific embodiment of the corresponding step of Figures 3C-3D , and so on. Figure 4B is another specific embodiment of the corresponding step of Figure 3E .

[0081] In an embodiment of the present disclosure, in step S1 of the manufacturing method of the semiconductor structure, as shown in Figure 3A , a substrate 1 is provided, the substrate 1 having active pillars 11 and isolation layers 12 arranged at intervals along a first direction X, the active pillars 11 and the isolation layers 12 both extending along a second direction Y, the first direction X being parallel to a surface of the substrate 1, the second direction Y being parallel to a thickness direction of the substrate 1, and the second direction Y being perpendicular to the first direction X.

[0082] The material of the substrate can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or can also be other materials, such as group III-V compound of gallium arsenide, etc. In the present embodiment, the material of the substrate is silicon. The substrate is doped with a certain impurity ion as needed, and the impurity ion can be an N-type impurity ion or a P-type impurity ion.

[0083] In embodiments of the present disclosure, a method for forming an active pillar 11 is provided, which includes but is not limited to the following steps: forming a plurality of trenches in a substrate by using a lithography etching method; filling an isolation material in the trenches to form an isolation layer 12, the isolation material including but not limited to silicon oxide, silicon nitride, silicon oxynitride or other suitable isolation materials. In the specific embodiment, the isolation material is silicon oxide. The substrate isolated by the isolation layer 12 is the active pillar 11. In the specific embodiment, as shown in Figure 3A , the active pillar 11 and the isolation layer 12 are arranged along a first direction X, the first direction X being parallel to the surface of the substrate 1, and the active pillar 11 and the isolation layer 12 both extend along a second direction Y, the second direction Y being parallel to the thickness direction of the substrate 1.

[0084] In embodiments of the present disclosure, in step S2 of the method for manufacturing a semiconductor structure, as shown in Figure 3B , part of the isolation layer 12 is removed to form a first recess 201, the first recess 201 exposing the top surface 111 and part of the side surface 112 of the active pillar 11. It should be understood by those skilled in the art that in the step shown in Figure 3B , the back etching of part of the isolation layer 12 can be completed by a wet etching process, such as a Certas process, under the action of a mixed gas composed of HF gas, water vapor and a carrier gas (such as nitrogen or argon), the HF reacts with the isolation layer 12 (such as silicon oxide in the isolation layer 12) to complete the back etching of part of the isolation layer 12. Since the etching selectivity of HF to the isolation layer 12 (such as silicon oxide in the isolation layer 12) and the active pillar 11 (such as silicon in the active pillar 11) is extremely high (i.e. the active pillar 11 will not or substantially not be etched when back etching the isolation layer 12), the back etching height of the adjacent isolation layer 12 is uniform, and the top surface of the isolation layer 12 in the first direction X after back etching is flush or close to flush, and the active pillar 11 in the second direction Y has a flush or close to flush side surface (i.e. the side wall morphology of the active pillar is vertical or close to vertical); correspondingly, in the first direction X, the first recess 201 has a flush or close to flush bottom surface (i.e. the bottom surface of the first recess will not be U-shaped or V-shaped) and the bottom surfaces of the adjacent first recesses 201 are consistent in height, and in the second direction Y, the first recess 201 has a flush or close to flush side surface (i.e. the side wall morphology of the first recess is vertical or close to vertical).

[0085] In embodiments of the present disclosure, the depth of the first recess 201 can be set according to specific process requirements. In one embodiment, as shown in Figure 3B and Figure 3G , or as shown in Figure 4D , in the second direction Y, the depth of the first recess 201 is greater than the thickness of the conductive structure 501.

[0086] In the embodiments of this disclosure, in step S3 of the semiconductor structure manufacturing method, a filling material layer is formed in the first groove, the filling material layer exposing at least the top surface of the active pillar. Those skilled in the art will understand that the filling material layer exposing at least the top surface of the active pillar includes two scenarios: the filling material layer exposing only the top surface of the active pillar, and the filling material layer exposing both the top surface and a portion of the side surface of the active pillar. When the filling material layer exposes both the top surface and a portion of the side surface of the active pillar, during subsequent heat treatment, the material of the metal layer can diffuse from the side surface of the active pillar into the active pillar to form a conductive structure.

[0087] In one embodiment, in order to ensure that the conductive structure has a preset thickness, in the step of forming a filling material layer in the first groove, in the second direction Y, the height of the top surface of the filling material layer is controlled to be no less than the height at 50% of the thickness of the conductive structure, and the top surface of the source pillar is exposed in the filling material layer.

[0088] In one embodiment, the step of forming a filling material layer within the first groove includes:

[0089] An initial filling material layer is formed in the first groove, the initial filling material layer filling the first groove and covering the top surface of the active column;

[0090] At least the initial filler material layer covering the top surface of the active post is removed, such that, in the second direction, the height of the top surface of the remaining initial filler material layer is not less than 50% of the thickness of the conductive structure, and the remaining initial filler material layer serves as the filler material layer; or

[0091] An initial filling material layer is formed in the first groove such that, in the second direction, the height of the top surface of the initial filling material layer is not less than the height at 50% of the thickness of the conductive structure, and the initial filling material layer exposes the top surface of the active post, the initial filling material layer serving as the filling material layer.

[0092] In one implementation, such as Figures 3C-3D As shown, the step of forming a filling material layer 13 within the first groove 201 includes:

[0093] like Figure 3C As shown, an initial filling material layer 131 is formed in the first groove 201, and the initial filling material layer 131 fills the first groove 201 and covers the top surface of the source column 11.

[0094] like Figure 3DAs shown, at least the initial filling material layer 131 covering the top surface of the source pillar 11 is removed, such that in the second direction Y, the height of the top surface of the remaining initial filling material layer 131 is not less than the height at 50% of the thickness of the conductive structure 501, and the remaining initial filling material layer 131 serves as the filling material layer 13.

[0095] In another implementation, such as Figure 4A As shown, the step of forming a filling material layer 13 within the first groove 201 includes:

[0096] An initial filling material layer 131 is formed in the first groove 201 such that, in the second direction Y, the height of the top surface of the initial filling material layer 131 is not less than the height at 50% of the thickness of the conductive structure 501, and the initial filling material layer 131 exposes the top surface of the source pillar 11, and the initial filling material layer 131 serves as the filling material layer 13.

[0097] In the embodiments of this disclosure, in step S4 of the semiconductor structure manufacturing method, a metal layer is formed, wherein the metal layer at least directly covers the top surface of the active pillar. Those skilled in the art will understand that the metal layer at least directly covering the top surface of the active pillar includes two cases: the metal layer directly covers the top surface of the active pillar, and the metal layer directly covers both the top surface and a portion of the side surface of the active pillar. When the filler material layer exposes the top surface of the active pillar, it corresponds to the metal layer directly covering the top surface of the active pillar; when the filler material layer exposes both the top surface and a portion of the side surface of the active pillar, it corresponds to the metal layer directly covering both the top surface and a portion of the side surface of the active pillar.

[0098] Specific methods for forming the metal layer include, but are not limited to, the following: The metal layer can be formed using one of the following processes: atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PECVD). The metal layer includes, but is not limited to, the following materials: such as one or more of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), and nickel (Ni). In this embodiment, the metal layer is preferably platinum-doped nickel (NiPt), wherein the mass percentage of Pt in the platinum-doped nickel (NiPt) can be 5%-30%.

[0099] In one implementation, such as Figure 3E As shown, a metal layer 401 is formed, wherein the metal layer 401 directly covers the top surface of the source pillar 11.

[0100] In another implementation, such as Figure 4B As shown, a metal layer 401 is formed, wherein the metal layer 401 directly covers the top surface and part of the side surface of the source pillar 11.

[0101] In an embodiment of the present disclosure, in step S5 of the method for manufacturing a semiconductor structure, a heat treatment is performed to form a conductive structure 501 on the active pillar 11, wherein the conductive structure 501 extends along a third direction Z, and the third direction Z is perpendicular to the first direction X and the second direction Y. Figure 3F and Figure 4C

[0102] The specific process of performing the heat treatment to form the conductive structure includes but is not limited to the following method: the heat treatment can be a high-temperature rapid thermal processing (RTP) process, and by using the RTP process, the metal in the metal layer (such as Pt in NiPt) is diffused into the Si lattice of the active pillar, and after the metal (such as Ni) is doped into the Si lattice, a metal silicide layer (such as NiSi) is formed, the metal silicide layer has good conductive performance to form the conductive structure, and the conductive structure is electrically connected to the active pillar.

[0103] Specifically, the material of the conductive structure 501 can be one or more of titanium silicide (TiSi), tantalum silicide (TaSi), nickel silicide (NiSi), and cobalt silicide (CoSi), and preferably the material of the conductive structure 501 is nickel silicide (NiSi); wherein the resistivity of the NiSi is not greater than 20 μΩ·cm, and the resistivity of the NiSi2 is between 24-30 μΩ·cm.

[0104] In an embodiment of the present disclosure, in step S6 of the method for manufacturing a semiconductor structure, at least the filling material layer is removed to expose the first recess, as shown in Figure 3G and Figure 4D Those skilled in the art can understand that at least removing the filling material layer includes: when it is the structure as shown in Figures 3E-3F , as shown in Figure 3G , the filling material layer 13 and the remaining metal layer 401 are removed, and the first recess 201 is exposed. When it is the structure as shown in Figures 4B-4C , as shown in Figure 4D , the filling material layer 13 and the remaining metal layer 401 are removed, and the first recess 201 is exposed.

[0105] After the conductive structure is formed, the remaining metal layer can be removed by pickling, and due to the high removal selectivity, the conductive structure that has been formed will not be damaged or damaged during the pickling process, so as to obtain the structure as shown in Figure 3F and Figure 4C , so that the performance of the conductive structure 501 is improved.

[0106] ​In the step of removing the filling material layer, the etching selectivity ratio of the filling material layer to the conductive structure is not less than 20. It can be understood that the etching selectivity ratio of the filling material layer to the active pillar and the etching selectivity ratio of the filling material layer to the isolation layer are also not less than 20.

[0107] In the step of removing the filling material layer, the etching selectivity ratio of the filling material layer to the conductive structure, the active pillar and the isolation layer are all not less than 20, so that the conductive structure, the active pillar and the isolation layer formed have not or substantially not been etched or reacted when the filling material layer is removed, that is, the conductive structure, the active pillar and the isolation layer formed have not or substantially not been damaged or damaged, so that the performance of the conductive structure is improved. Therefore, as shown in FIG. 1, the conductive structure 501 does not have a top rounded and necked waist, that is, necking, that is, the orthogonal projection of the conductive structure 501 on the surface of the substrate 1 is a square; in the second direction Y, the conductive structure 501 has a flat or nearly flat side surface (that is, the side wall of the conductive structure 501 is vertical or nearly vertical). In the second direction Y, the first groove 201 exposed after the filling material layer is removed has a flat or nearly flat side surface (that is, the side wall of the first groove 201 is vertical or nearly vertical); in the first direction X, the first groove 201 exposed after the filling material layer is removed has a flat or nearly flat bottom surface (no U-shaped or V-shaped) and the height of the bottom surfaces of adjacent first grooves 201 is consistent or nearly consistent. Figure 3G Figure 4D

[0108] Specifically, the material of the filling material layer includes at least one of a carbon-based material, a metal material and a dielectric material, wherein,

[0109] The carbon-based material includes at least one of a spin-on hard mask (SOH), a spin-on organic carbon (SOC), a photoresist material (PR) and an amorphous carbon layer (ACL); and / or

[0110] The metal material includes tungsten (W); and / or

[0111] The dielectric material includes silicon nitride; and / or

[0112] The material of the conductive structure includes at least one of NiSi, TiSi, TaSi and CoSi, preferably NiSi.

[0113] ​​The forming of the filling material layer of each material described above can be selected by a person skilled in the art according to the different materials, for example, the spin-on hard mask (SOH), the spin-on organic carbon (SOC), and the photoresist material (PR) can be formed by a spin coating process, the amorphous carbon layer (ACL), tungsten (W), and silicon nitride can be formed by a deposition process, and the specific steps are known to a person skilled in the art and will not be described here.

[0114] In the step of removing the filling material layer, if the material of the filling material layer is at least one of carbon-based materials such as the spin-on hard mask (SOH), the spin-on organic carbon (SOC), the photoresist material (PR), and the amorphous carbon layer (ACL), the filling material layer can be removed by an ashing process; if the material of the filling material layer is a metal material such as tungsten, the filling material layer can be removed by cleaning with hydrogen peroxide; and if the material of the filling material layer is a dielectric material such as silicon nitride, the filling material layer can be removed by dry etching. The specific steps of the foregoing removal methods are known to a person skilled in the art and will not be described here. In the step of removing the filling material layer, an etching selectivity of the filling material layer to the conductive structure can be not less than 20. Meanwhile, it can also be satisfied that, in the step of removing at least the filling material layer, an etching selectivity of the filling material layer to the active pillar is not less than 20, and an etching selectivity of the filling material layer to the isolation layer is not less than 20.

[0115] In the step S7 of the method for manufacturing the semiconductor structure in an embodiment of the present disclosure, the first dielectric layer is deposited at least on the side surface of the first recess to form a second recess, and the first dielectric layer covers the side surface and the top surface of the conductive structure.

[0116] In an embodiment of the present disclosure, the dielectric constant of the first dielectric layer is less than the dielectric constant of the active pillar, and the material of the first dielectric layer includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, or other suitable materials. In an embodiment of the present disclosure, the first dielectric layer can be carbon-doped silicon oxide. The main material of the active pillar is silicon, and the dielectric constant of silicon is between 11 and 12. The dielectric constant of carbon-doped silicon oxide is about 4.5. The dielectric constant of the first dielectric layer is less than the dielectric constant of the active pillar, so that the parasitic capacitance of the semiconductor structure is further reduced.

[0117] In an embodiment of the present disclosure, the step of depositing the first dielectric layer at least on the side surface of the first recess includes:

[0118] As shown in FIG. 3A, the first dielectric material layer 3011 is formed, the first dielectric material layer 3011 covers the side surface and the bottom surface of the first recess 201 and the top surface of the conductive structure 501, and the first dielectric material layer 3011 serves as the first dielectric layer 301. Meanwhile, the second recess 202 is formed, and the first dielectric layer 301 covers the side surface and the top surface of the conductive structure 501, thereby protecting the conductive structure 501. Figure 3H As shown in FIG. 3A, the first dielectric material layer 3011 is formed, the first dielectric material layer 3011 covers the side surface and the bottom surface of the first recess 201 and the top surface of the conductive structure 501, and the first dielectric material layer 3011 serves as the first dielectric layer 301. Meanwhile, the second recess 202 is formed, and the first dielectric layer 301 covers the side surface and the top surface of the conductive structure 501, thereby protecting the conductive structure 501.

[0119] In another embodiment of the present disclosure, the step of depositing the first dielectric layer at least on the side surface of the first recess comprises:

[0120] As shown in FIG. 3A, a first dielectric material layer 3011 is formed, which covers the side surface and the bottom surface of the first recess 201 and the top surface of the conductive structure 501. Figure 4E

[0121] As shown in FIG. 3B, the first dielectric material layer 3011 covering the bottom surface of the first recess 201 is removed, and the remaining first dielectric material layer 3011 serves as a first dielectric layer 301, while a second recess 202 is formed, the first dielectric layer 301 covering the side surface and the top surface of the conductive structure 501, which serves to protect the conductive structure 501. Figure 4F Specifically, the first dielectric material layer 3011 can be formed by one of an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a chemical vapor deposition (CVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process.

[0122] In an embodiment of the present disclosure, in the step S8 of the method for manufacturing a semiconductor structure, a second dielectric layer is formed, which fills the second recess.

[0123] Specifically, the second dielectric layer can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials. In a specific embodiment, the second dielectric layer is silicon oxide. Specifically, the second dielectric layer can be formed by one of an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a chemical vapor deposition (CVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process.

[0124] In an embodiment of the present disclosure, in the method for manufacturing a semiconductor structure, after the step of depositing the first dielectric layer, before the step of forming the second dielectric layer, the method further comprises:

[0125] forming a third dielectric layer, which fills the second recess and covers the first dielectric layer;

[0126] the substrate includes an array region and a peripheral region, and the third dielectric layer in the second recess of the array region is removed;

[0127]

[0128] ​​The step of forming the second dielectric layer includes forming the second dielectric layer, which fills the second recess in the array region and covers the first dielectric layer.

[0129] Specifically, the third dielectric layer can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride or other suitable isolation materials. In one specific embodiment, the third dielectric layer is silicon oxide. The specific formation of the third dielectric layer includes, but is not limited to, the following methods: one of an atomic layer deposition (ALD) process, a plasma-enhanced atomic layer deposition (PEALD) process, a chemical vapor deposition (CVD) process, and a plasma-enhanced chemical vapor deposition (PECVD) process can be used to form the third dielectric layer.

[0130] In one embodiment, as shown in Figure 3I and Figure 4G , the third dielectric layer 701 is formed, which fills the second recess 202 and covers the first dielectric layer 301;

[0131] As shown in Figure 3J and Figure 4H , the substrate 1 includes an array region 14 and a peripheral region 15, and the array region 14 and the peripheral region 15 are defined by a photoresist layer 801;

[0132] As shown in Figure 3K and Figure 4I , the third dielectric layer 701 in the second recess 202 in the array region 14 is removed;

[0133] As shown in Figure 3L and Figure 4J , the photoresist layer 801 is removed;

[0134] As shown in Figure 3M and Figure 4K , the step of forming the second dielectric layer 601 includes forming the second dielectric layer 601, which fills the second recess 202 in the array region 14 and covers the first dielectric layer 301.

[0135] Specifically, the second dielectric layer 601 can have an air gap or not have an air gap; preferably, in one embodiment of the present disclosure, as shown in Figure 3M and Figure 4K , the second dielectric layer 601 has an air gap 602, and in the second direction Y, the depth of the air gap 602 is greater than the thickness of the conductive structure 501; and / or

[0136] In the first direction X, the maximum width of the air gap 602 is 1 / 3-4 / 5 of the width of the second recess 202.

[0137] In embodiments of the present disclosure, in the second direction Y, the depth of the first recess 201 is greater than the thickness of the conductive structure 501, so as to make it possible for the depth of the air gap 602 in the second direction Y to be greater than the thickness of the conductive structure 501. The thickness of the conductive structure refers to the depth from the top surface of the conductive structure to the bottom of the conductive structure in the second direction Y. The depth of the air gap in the second direction Y refers to the depth from the top of the air gap to the bottom of the air gap in the second direction Y. As shown in Figure 3M and Figure 4K In the second direction Y, the air gap 602 has a top and a bottom, the top of the air gap 602 is higher than the top surface of the conductive structure 501, and the bottom of the air gap 602 is lower than the bottom surface of the conductive structure 501. Further, the size of the air gap 602 in the second direction Y accounts for 2 / 3-4 / 5 of the depth of the second recess 202, and the maximum size of the air gap in the first direction X accounts for 1 / 3-4 / 5 of the width of the second recess 202. Such arrangement makes the air gap 602 between the conductive structures 501, and reduces the parasitic capacitance between the conductive structures 501.

[0138] In embodiments of the present disclosure, after removing the filling material layer and exposing the first recess, the first dielectric layer is formed conformally, and after forming the second dielectric layer, the conductive structure 501 formed finally does not have a top rounding and necking morphology, i.e., the orthographic projection of the conductive structure 501 formed finally on the surface of the substrate 1 is a square; in the second direction Y, the conductive structure 501 formed finally has flat or nearly flat side surfaces (i.e., the sidewall of the conductive structure 501 formed finally is vertical or nearly vertical). In the second direction Y, the first recess 201 formed finally has flat or nearly flat side surfaces (i.e., the sidewall of the first recess 201 is vertical or nearly vertical), and the first dielectric layer formed correspondingly has flat or nearly flat side surfaces (i.e., the sidewall of the first dielectric layer is vertical or nearly vertical); in the first direction X, the first recess 201 formed finally has flat or nearly flat bottom surfaces (without U-shaped or V-shaped) and the height of the bottom surfaces of adjacent first recesses 201 is consistent or nearly consistent, and the first dielectric layer formed correspondingly has flat or nearly flat bottom surfaces / the second dielectric layer formed has flat or nearly flat bottom surfaces.

[0139] In embodiments of the present disclosure, the method for manufacturing a semiconductor structure further comprises: Figure 3N and Figure 4LAs shown, the peripheral contact 901 is formed, the peripheral contact 901 is directly connected with the partial conductive structure 501, the first dielectric layer 301 covers the side surface and partial top surface of the partial conductive structure directly connected with the peripheral contact 901, and the first dielectric layer 301 covers the side surface and all top surfaces of the remaining conductive structure not directly connected with the peripheral contact 901. In this structure, the second dielectric layer 601 covers the corresponding first dielectric layer 301.

[0140] The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure first removes part of the isolation layer to form a first recess exposing the top surface and part of the side surface of the active pillar; then forms a filling material layer exposing at least the top surface of the active pillar in the first recess; then forms a metal layer covering at least the top surface of the active pillar, performs heat treatment to form a conductive structure on the active pillar, and then removes at least the filling material layer to expose the first recess; and finally forms a first dielectric layer and a second dielectric layer. First, by forming the first recess, then forming the filling material layer in the first recess, and then removing the filling material layer after forming the conductive structure, on the one hand, it makes it possible to simultaneously compatible in the manufacturing method of removing part of the isolation layer to form the first recess and preparing the bit line with the conductive structure as a mask, on the other hand, it can also prevent the morphology of the conductive structure from changing, avoid damaging the top and sidewall of the conductive structure, that is, avoid the conductive structure appearing to be thin and round (i.e. necking) in the final formation, so that the orthogonal projection of the conductive structure on the substrate surface is square and has a flat or nearly flat side surface in the thickness direction of the substrate (i.e. the sidewall morphology of the conductive structure is vertical or nearly vertical). Therefore, the resistance of the conductive structure itself can be reduced, the performance of the conductive structure can be improved, and thus the yield of the semiconductor device can be improved.

[0141] The first dielectric layer with a smaller dielectric constant, such as the dielectric constant of the first dielectric layer being smaller than the dielectric constant of the active pillar, makes the parasitic capacitance of the semiconductor structure further reduced, and through the above improvement, the performance of the semiconductor device can be improved, and the yield of the device can be improved.

[0142] In order to further reduce the parasitic capacitance, an air gap can also be arranged between the conductive structures, since the relative dielectric constant of air is about 1, air can be used as a good dielectric to further reduce the parasitic capacitance between the conductive structures; through the above improvement, the performance of the semiconductor device can be improved, and the yield of the device can be improved.

[0143] The present disclosure provides a semiconductor structure, as shown in Figure 3M and Figure 4K comprises:

[0144] a substrate 1 having active pillars 11 and isolation layers 12 arranged in an array along a first direction X, the active pillars 11 and the isolation layers 12 extending along a second direction Y, the first direction X being parallel to a surface of the substrate 1, the second direction Y being parallel to a thickness direction of the substrate 1, the second direction Y being perpendicular to the first direction X;

[0145] a conductive structure 501 on and connected to the active pillar 11, the conductive structure 501 extending along a third direction Z, the third direction Z being perpendicular to the first direction X and the second direction Y;

[0146] a first recess 201 between adjacent conductive structures 501;

[0147] a second recess 202 in the first recess 201;

[0148] a first dielectric layer 301 between the first recess 201 and the second recess 202, the first dielectric layer 301 covering at least a side surface of the first recess 201 and covering a side surface and a part of a top surface of the conductive structure 501 (as shown in Figure 3N and Figure 4L , the first dielectric layer 301 covering the side surface and the part of the top surface of the conductive structure 501);

[0149] a second dielectric layer 601 filling the second recess 202.

[0150] In an embodiment, as shown in Figure 3M and Figure 4K , in the semiconductor structure provided by the present disclosure, the substrate 1 comprises an array region 14 and a peripheral region 15, the second dielectric layer 601 fills the second recess 202 in the array region 14; the semiconductor structure further comprises: a third dielectric layer 701 filling the second recess 202 in the peripheral region 15.

[0151] In an embodiment, the second dielectric layer 601 fills the second recess 202 in the array region 14 and covers the first dielectric layer 301.

[0152] In an embodiment, the third dielectric layer 701 fills the second recess 202 in the peripheral region 15 and covers the first dielectric layer 301.

[0153] In an embodiment, as shown in Figure 3M and Figure 4K , the second dielectric layer 601 has an air gap 602, in the second direction Y, a depth of the air gap 602 is greater than a thickness of the conductive structure 501; and / or

[0154] In the first direction X, a maximum width of the air gap 602 is 1 / 3-4 / 5 of a width of the second recess 202.

[0155] In one embodiment, the first recess 201 has a depth greater than the thickness of the conductive structure 501 in the second direction Y. The thickness of the conductive structure refers to the depth from the top surface of the conductive structure to the bottom of the conductive structure in the second direction Y. The depth of the air gap in the second direction Y refers to the depth from the top of the air gap to the bottom of the air gap in the second direction Y. As shown in Figure 3M and Figure 4K In one embodiment, the air gap 602 has a top and a bottom in the second direction Y, the top of the air gap 602 is higher than the top surface of the conductive structure 501, and the bottom of the air gap 602 is lower than the bottom surface of the conductive structure 501. Further, the air gap 602 has a dimension in the second direction Y that is 2 / 3-4 / 5 of the depth of the second recess 202, and the air gap has a maximum dimension in the first direction X that is 1 / 3-4 / 5 of the width of the second recess 202. Such arrangement allows the air gap 602 to be between the conductive structures 501, and reduces the parasitic capacitance between the conductive structures 501.

[0156] In one embodiment, as shown in Figure 3M and Figure 4K The first dielectric layer 301 has a dielectric constant less than that of the active pillar, and the first dielectric layer 301 can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, or other suitable materials. In one embodiment of the present disclosure, the first dielectric layer 301 can be carbon-doped silicon oxide. The active pillar is mainly made of silicon, and the dielectric constant of silicon is between 11 and 12. The dielectric constant of carbon-doped silicon oxide is about 4.5. The dielectric constant of the first dielectric layer 301 is less than that of the active pillar, which further reduces the parasitic capacitance of the semiconductor structure. The resistivity of the conductive structure is not greater than 20 μΩ·cm, and the material of the conductive structure can be NiSi. Other same or corresponding parts can refer to the corresponding descriptions in the foregoing embodiments of the manufacturing method of the semiconductor structure, which will not be described here again.

[0157] In one embodiment, as shown in Figure 3N and Figure 4L The conductive structure 501 has a square-shaped orthographic projection on the surface of the substrate 1; and / or

[0158] The conductive structure 501 has a flat or nearly flat side surface in the second direction Y; and / or

[0159] The first recess 201 has a flat or nearly flat side surface in the second direction Y; and / or

[0160] The first recess 201 has a flat or nearly flat bottom surface (not U-shaped or V-shaped) in the first direction X, and the height of the bottom surfaces of adjacent first recesses 201 is consistent or nearly consistent.

[0161] In one embodiment, as shown in Figure 3N andFigure 4L As shown, the semiconductor structure provided by the present disclosure further comprises: a peripheral contact 901, the peripheral contact 901 is directly connected with the partial conductive structure 501, the first dielectric layer 301 covers the side surface and partial top surface of the partial conductive structure 501 directly connected with the peripheral contact 901, and the first dielectric layer 301 covers the side surface and all top surfaces of the remaining conductive structure not directly connected with the peripheral contact 901. It can be understood that only for illustration, in Figure 3M and Figure 3N only one peripheral contact 901 is shown in the above-mentioned figures, and other peripheral contacts are not shown. Under such a structure, the second dielectric layer 601 covers the corresponding first dielectric layer 301.

[0162] Specifically, those skilled in the art can understand that the second dielectric layer 601 fills the second groove 202 and the second dielectric layer 601 covers the first dielectric layer 301. That is, the first dielectric layer 301 and the second dielectric layer 601 cover the side surface and partial top surface of the partial conductive structure 501 directly connected with the peripheral contact 901, and the first dielectric layer 301 and the second dielectric layer 601 cover the side surface and all top surfaces of the remaining conductive structure not directly connected with the peripheral contact 901.

[0163] Specifically, those skilled in the art can understand that the third dielectric layer 701 covers the above-mentioned first dielectric layer 301.

[0164] Further, those skilled in the art can understand that compared with Figure 3N , Figure 3N the peripheral contact 901 is added, the first dielectric layer 301 and the second dielectric layer 601 cover the side surface and partial top surface of the partial conductive structure 501 directly connected with the peripheral contact 901, the first dielectric layer 301 and the second dielectric layer 601 cover the side surface and all top surfaces of the remaining conductive structure not directly connected with the peripheral contact 901, and other structures remain unchanged, and when referring to Figure 3M , the structures not shown by reference numerals in Figure 4K may refer to the corresponding structures shown by reference numerals in Figure 4L ; similarly, compared with Figure 4L , Figure 4L the peripheral contact 901 is added, the first dielectric layer 301 and the second dielectric layer 601 cover the side surface and partial top surface of the partial conductive structure 501 directly connected with the peripheral contact 901, the first dielectric layer 301 and the second dielectric layer 601 cover the side surface and all top surfaces of the remaining conductive structure not directly connected with the peripheral contact 901, and other structures remain unchanged, and when referring to Figure 4K , the structures not shown by reference numerals in Figure 5 may refer to the corresponding structures shown by reference numerals in Figure 5 .

[0165] Figure 3N is a schematic diagram of another embodiment of the semiconductor structure of the present disclosure. As shown in Figure 5 is a schematic diagram of another embodiment of the semiconductor structure of the present disclosure. As shown in Figure 5 The base further comprises a word line structure 10, which is arranged around the active pillar 11, the active pillar 11 is arranged in the first direction X and the third direction Z, and the active pillars 11 are separated by an isolation layer 12; one end of the active pillar 11 is electrically connected to the conductive structure 501, which can be a bit line structure, and the other end of the active pillar 11 is electrically connected to the capacitor structure 20, and the adjacent capacitor structures are separated by the fourth dielectric layer 30. In this embodiment, the semiconductor structure can be a gate-all-around (GAA) structure or a vertical channel transistor (VCT) structure.

[0166] In another embodiment, as Figure 6 In contrast, the first dielectric layer 301 only covers the side surface of the first recess 201 and does not cover the bottom surface of the first recess 201, and the other structures are the same as Figure 7 The structure shown in this embodiment is not shown in the figure.

[0167] The conductive structure of the semiconductor structure of the present disclosure does not have a morphology of thinning and rounding (i.e., necking), so that the orthogonal projection of the conductive structure on the surface of the base is a square and has a flat or nearly flat side surface in the second direction (i.e., the side wall morphology of the conductive structure is vertical or nearly vertical). Therefore, the resistance of the conductive structure itself can be reduced, the performance of the conductive structure can be improved, and thus the yield of the semiconductor device can be improved.

[0168] In one embodiment, the semiconductor structure of the present disclosure uses a first dielectric layer with a smaller dielectric constant, such as a dielectric constant smaller than that of the active pillar, so that the parasitic capacitance of this semiconductor structure is further reduced, and the performance of the semiconductor device can be improved through the above improvement, and the device yield can be improved.

[0169] In one embodiment, the conductive structures are separated by air gaps. Since the relative dielectric constant of air is about 1, it can be used as a good dielectric to further reduce the parasitic capacitance between the conductive structures; through the above improvement, the performance of the semiconductor device can be improved, and the device yield can be improved.

[0170] Figure 6 is a schematic diagram of a memory device formed by bonding a wafer including the semiconductor structure of the present disclosure and another wafer. Figure 7 is a schematic diagram of a memory device formed by bonding a wafer including the semiconductor structure of the present disclosure and another wafer.

[0171] As shown in FIG. 4A, the memory device includes a first wafer 40 having the semiconductor structure described above in the present disclosure (the first wafer 40 can be an Array wafer) and a second wafer 50 including a control circuit (the second wafer 50 can be a CMOS wafer), and the first wafer 40 and the second wafer 50 are bonded to form the memory device. ​

[0172] In an embodiment, the back surface of the first wafer 40 and the second wafer 50 can be bonded to form the memory device by hybrid bonding.

[0173] As shown in FIG. 4B, the memory device includes a first wafer 40 having the semiconductor structure described above in the present disclosure (the first wafer 40 can be an Array wafer) and a third wafer 60 which can be a carrier wafer, and the first wafer 40 and the third wafer 60 are bonded to form the memory device. ​

[0174] In an embodiment, the front surface of the first wafer 40 and the third wafer 60 can be bonded to form the memory device by fusion bonding.

[0175] It is understood by those skilled in the art that the front surface of the first wafer 40 and the third wafer 60 can be bonded first, and then the back surface of the first wafer 40 and the second wafer 50 can be bonded to form the memory device.

[0176] It is understood by those skilled in the art that the above embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.​​

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided having active pillars and isolation layers spaced apart along a first direction, both the active pillars and the isolation layers extending along a second direction, the first direction being parallel to the surface of the substrate, the second direction being parallel to the thickness direction of the substrate, and the second direction being perpendicular to the first direction; A portion of the isolation layer is removed to form a first groove, the first groove exposing the top surface and a portion of the side surface of the active post; A filling material layer is formed within the first groove, the filling material layer exposing at least the top surface of the active post; A metal layer is formed, which at least directly covers the top surface of the active column; Heat treatment is performed to form a conductive structure on the active post, the conductive structure extending along a third direction, the third direction being perpendicular to the first direction and the second direction; At least the filling material layer is removed to expose the first groove; A first dielectric layer is deposited at least on the side surface of the first groove to form a second groove, the first dielectric layer covering the side surface and top surface of the conductive structure; A second dielectric layer is formed, and the second dielectric layer fills the second groove.

2. The manufacturing method as described in claim 1, characterized in that, In the step of forming a filling material layer in the first groove, in the second direction, the height of the top surface of the filling material layer is controlled to be no less than 50% of the thickness of the conductive structure, and the filling material layer exposes the top surface of the active post.

3. The manufacturing method as described in claim 2, characterized in that, The step of forming a filling material layer in the first groove includes: An initial filling material layer is formed in the first groove, the initial filling material layer fills the first groove and covers the top surface of the active column; At least the initial filler material layer covering the top surface of the active post is removed, such that, in the second direction, the height of the top surface of the remaining initial filler material layer is not less than 50% of the thickness of the conductive structure, and the remaining initial filler material layer serves as the filler material layer; or An initial filling material layer is formed in the first groove such that, in the second direction, the height of the top surface of the initial filling material layer is not less than the height at 50% of the thickness of the conductive structure, and the initial filling material layer exposes the top surface of the active post, the initial filling material layer serving as the filling material layer.

4. The manufacturing method as described in claim 1, characterized in that, In the step of at least removing the filler material layer, the etching selectivity ratio of the filler material layer to the conductive structure is not less than 20.

5. The manufacturing method as described in claim 4, characterized in that, The filling material layer comprises at least one of carbon-based materials, metallic materials, and dielectric materials, wherein... The carbon-based material includes at least one of spin-coated hard mask, spin-coated organic carbon, photoresist material, and amorphous carbon layer; and / or The metallic material includes tungsten; and / or The dielectric material includes silicon nitride; and / or The material of the conductive structure includes at least one of NiSi, TiSi, TaSi, and CoSi.

6. The manufacturing method as described in claim 1, characterized in that, The step of depositing a first dielectric layer on at least the side surface of the first groove includes: A first dielectric material layer is formed, which covers the side and bottom surfaces of the first groove and the top surface of the conductive structure, and serves as the first dielectric layer; or A first dielectric material layer is formed, which covers the side and bottom surfaces of the first groove and the top surface of the conductive structure. Remove the first dielectric material layer covering the bottom surface of the first groove, and the remaining first dielectric material layer serves as the first dielectric layer.

7. The manufacturing method as described in claim 1, characterized in that, After the deposition of the first dielectric layer and before the formation of the second dielectric layer, the method further includes: A third dielectric layer is formed, which fills the second groove and covers the first dielectric layer; The substrate includes an array region and a peripheral region, and the third dielectric layer located in the second groove of the array region is removed; The step of forming the second dielectric layer includes: forming a second dielectric layer, wherein the second dielectric layer fills the second groove located in the array region and covers the first dielectric layer.

8. The manufacturing method according to any one of claims 1-7, characterized in that, In the second direction, the depth of the first groove is greater than the thickness of the conductive structure.

9. The manufacturing method according to any one of claims 1-7, characterized in that, The second dielectric layer has an air gap, and in the second direction, the depth of the air gap is greater than the thickness of the conductive structure; and / or In the first direction, the maximum width of the air gap is 1 / 3 to 4 / 5 of the width of the second groove.

10. The manufacturing method according to any one of claims 1-7, characterized in that, The conductive structure has a square orthographic projection onto the surface of the substrate; and / or In the second direction, the conductive structure has a flush or nearly flush side surface; and / or In the second direction, the first groove exposed after the filling material layer is removed has a flush or nearly flush side surface; and / or In the first direction, the first groove exposed after the filling material layer is removed has a flush or nearly flush bottom surface and the bottom surfaces of adjacent first grooves are at the same or nearly the same height.

11. A semiconductor structure, characterized in that, include: A substrate having active pillars and an isolation layer spaced apart along a first direction, the active pillars and the isolation layer both extending along a second direction, the first direction being parallel to the surface of the substrate, the second direction being parallel to the thickness direction of the substrate, and the second direction being perpendicular to the first direction; A conductive structure is located on and connected to the active post, the conductive structure extending along a third direction, the third direction being perpendicular to the first direction and the second direction; The first groove is located between adjacent conductive structures; The second groove is located inside the first groove; A first dielectric layer is located between the first groove and the second groove, and the first dielectric layer at least covers the side surface of the first groove and covers the side surface and part of the top surface of the conductive structure; The second dielectric layer fills the second groove.

12. The semiconductor structure as claimed in claim 11, characterized in that, The substrate includes an array region and a peripheral region, and the second dielectric layer fills the second groove located in the array region; the semiconductor structure further includes: A third dielectric layer fills the second groove located in the peripheral region.

13. The semiconductor structure as described in claim 11 or 12, characterized in that, In the second direction, the depth of the first groove is greater than the thickness of the conductive structure.

14. The semiconductor structure as described in claim 11 or 12, characterized in that, The second dielectric layer has an air gap, and in the second direction, the depth of the air gap is greater than the thickness of the conductive structure; and / or In the first direction, the maximum width of the air gap is 1 / 3 to 4 / 5 of the width of the second groove.

15. The semiconductor structure as described in claim 11 or 12, characterized in that, The conductive structure has a square orthographic projection onto the surface of the substrate; and / or In the second direction, the conductive structure has a flush or nearly flush side surface; and / or In the second direction, the first groove has a side surface that is flush or nearly flush; and / or In the first direction, the first groove has a flat or nearly flat bottom surface and the bottom surfaces of adjacent first grooves are at the same or nearly the same height.

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