MOS for improving withstand voltage of Trench-MOSFET and preparation method

Abstract

The invention discloses an MOS (Metal Oxide Semiconductor) for improving the withstand voltage of a Trench-MOSFET (Metal Oxide Semiconductor Field Effect Relates to the technical field of semiconductors. The bottom of the groove is smoothed, so that the electric field at the bottom of the groove is uniformly distributed; when the gate dielectric layer is grown, a high-K medium (the dielectric constant K is generally greater than 10) is used for replacing conventional silicon oxide, and the electric field intensity at the bottom of the groove is reduced. A lightly doped region (the conductive type is the same as that of the WELL region) is added between the WELL region and the drift region to serve as a buffer layer, the electric field distribution of a contact surface is optimized, and the peak value of the electric field is reduced. The K dielectric layer at the arc-shaped bottom and the three-layer WELL region fundamentally relieve the curvature effect of the bottom of the groove through the action of'reducing the electric field in the dielectric by the shape optimization dispersed electric field line and the high-K material ', avoid the local electric field concentration of the gate oxide layer, and finally improve the voltage endurance capability and the reliability of the device. The design can be realized in an existing production line without relying on a complex process of a super junction technology, and performance improvement and cost control are both considered.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a MOS for improving the breakdown voltage of Trench-MOSFET and its fabrication method. Background Technology

[0002] In the field of power semiconductor devices, trench MOSFETs are power devices that optimize current paths through a vertical trench structure. Their core feature is the formation of three-dimensional conductive channels within the silicon wafer using a deep trench etching process. Compared to traditional planar MOSFETs, trench structures offer lower conduction losses, better switching performance, and avoid the parasitic JFET effect.

[0003] Currently, trench MOSFETs face two key technological bottlenecks: First, due to the curvature effect at the bottom of the trench, the silicon dioxide dielectric layer will generate a severe electric field concentration phenomenon in this region, which will not only significantly reduce the gate oxide quality, but may also cause gate oxide breakdown in severe cases. Secondly, MOSFETs typically have a high WELL region concentration, and the depletion region essentially extends from the drift region. Furthermore, the electric field peak at the boundary between the WELL and drift regions is very high. The width of the depletion region and the peak electric field limit the device's breakdown voltage capability.

[0004] While existing superjunction technology and field plate structures can partially improve these defects, superjunction processes require complex epitaxial processes and are costly, which in turn leads to a decrease in device area utilization.

[0005] As the performance requirements of power devices in electric vehicle drive systems continue to increase, how to maintain device characteristics and improve voltage withstand characteristics while ensuring process compatibility has become a key research and development direction for power semiconductor technology. Summary of the Invention

[0006] To address the above problems, this invention provides a MOS and its fabrication method that maintains device on-resistance, threshold voltage, and improves breakdown voltage characteristics while ensuring process compatibility.

[0007] The technical solution of this invention is: A method for fabricating a MOSFET to improve its breakdown voltage includes the following steps: Step 1: Grow an epitaxial layer on the substrate; Step 2: Trenches of a specific depth are etched into the epitaxial layer, and the bottom of the trenches is processed to make the corners rounded. Step 3: Deposit a K dielectric layer on the surface of the trench; Step 4: Fill the trench with polysilicon and etch it back to horizontal. Step 5: Perform multiple ion implantations on the epitaxial layer to form the WELL region; The WELL zone includes the first WELL zone, the second WELL zone, and the third WELL zone. The total depth of the WELL zone cannot exceed the trench depth. Step 6: Ion implantation is performed on the epitaxial layer to form a heavily doped source region, wherein the doping concentration of the source region is higher than that of the WELL region; Step 7: Etch the CT vias and fill them with metal to finally form a complete MOSFET structure.

[0008] Specifically, the thickness of the epitaxial layer in step one ranges from 4 to 20 μm.

[0009] Specifically, the trench depth in step two ranges from 0.5 to 3 μm.

[0010] Specifically, the thickness of the K dielectric layer in step three ranges from 200 to 1000 Å.

[0011] Specifically, the material of the K dielectric layer mentioned in step three is one or a combination of HfO2, Al2O3, and ZrO2.

[0012] Specifically, the concentrations of the third WELL region, the second WELL region, and the first WELL region decrease sequentially from the surface of the silicon wafer downwards.

[0013] Specifically, the doping concentration of the source region is 1.5e. 20 .

[0014] A MOSFET for improving the breakdown voltage of a Trench MOSFET includes a substrate, an epitaxial layer, a WELL region, and a source region connected sequentially from bottom to top. The source region is equipped with: A metal layer extends downward from the top of the source region to the third WELL region; The K dielectric layer extends downward from the top of the source region to below the WELL region, and the bottom of the K dielectric layer has an arc-shaped structure. Polycrystalline silicon is disposed within the K dielectric layer.

[0015] Specifically, the WELL area includes a first WELL area, a second WELL area, and a third WELL area arranged from bottom to top.

[0016] This invention performs a rounded treatment on the bottom of the trench to make the electric field distribution at the bottom of the trench uniform; when growing the gate dielectric layer, a high-K dielectric (generally dielectric constant K is greater than 10) is used instead of conventional silicon oxide to reduce the electric field intensity at the bottom of the trench.

[0017] A lightly doped region (with the same conductivity type as the Well region) is added between the Well region and the drift region as a buffer layer to optimize the electric field distribution at the contact surface and reduce the electric field peak. The K dielectric layer at the curved bottom and the three Well regions fundamentally alleviate the curvature effect at the bottom of the trench by "shape optimization to disperse electric field lines + high-K material to reduce the electric field within the dielectric," avoiding local electric field concentration in the gate oxide layer, and ultimately improving the device's breakdown voltage and reliability. This design can be implemented in existing production lines without relying on the complex processes of superjunction technology, balancing performance improvement and cost control. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the substrate and epitaxial structure. Figure 2 This is a schematic diagram of the etched grooves; Figure 3 This is a schematic diagram of the formation of the gate dielectric layer; Figure 4 This is a schematic diagram of polycrystalline silicon deposition; Figure 5 This is a schematic diagram of the WELL region formed by step-by-step injection; Figure 6 This is a schematic diagram of the injection forming an active region; Figure 7 This is a schematic diagram of etching through-holes and filling them with metal; In the figure, 1 is the substrate, 2 is the epitaxial layer, 3 is the high-k dielectric layer, 4 is polysilicon, 5 is the first Well region, 6 is the second Well region, 7 is the third Well region, 8 is the source region, and 9 is the metal layer. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0021] A method for fabricating a MOSFET to improve its breakdown voltage includes the following steps: Step 1, as follows Figure 1 As shown, a silicon substrate 1 is provided, and an epitaxial layer 2 of the same conductivity type is grown on the substrate 1, wherein the thickness of the epitaxial layer 2 ranges from 4 to 20 μm.

[0022] Step two, as Figure 2 As shown, a layer of silicon oxide and silicon nitride is deposited on the surface of epitaxial layer 2 to protect the non-trench areas. Using photolithography, silicon nitride, silicon oxide, and epitaxial layer 2 are sequentially etched away in the areas exposed by the photomask to form trenches of a specific depth. Next, the bottom of the trenches is processed to make the corners rounded. After obtaining the trenches, the surface silicon oxide and silicon nitride are removed. The depth of the formed trenches ranges from 0.5 to 3 μm and cannot exceed the thickness of epitaxial layer 2.

[0023] Step 3, as Figure 3 As shown, a K dielectric layer 3 is deposited on the surface of the trench; The thickness of the K dielectric layer (3) ranges from 200 to 1000 Å. The thickness of the dielectric layer 3 at the bottom of the trench is greater than that of the dielectric layer 3 on the sidewall. The material of the high K dielectric layer can be one or a combination of HfO2, Al2O3, and ZrO2.

[0024] Step four, as Figure 4 As shown, polysilicon 4 is filled into the trench and then etched back to the horizontal. Step 5, as Figure 5 As shown, multiple ion implantations are performed on the epitaxial layer 2 to form the first WELL region 5, the second WELL region 6 and the third WELL region 7. The total depth of the WELL region cannot exceed the trench depth. The doping concentration in the WELL regions (from the third WELL region 7, the second WELL region 6, and the first WELL region 5) decreases sequentially downwards from the silicon wafer surface, forming a stepped concentration distribution. The first WELL region 5 and the second WELL region 6 have lower doping concentrations, acting as buffer layers between WELL region 7 and epitaxial layer 2, making the doping change in the PN junction more gradual, forming a gradient junction. The doping concentrations of the first WELL region 5, the second WELL region 6, and the third WELL region 7 are approximately 5e⁻¹. 15 1e 16 5e 16 ~5e 17 cm-3.

[0025] The gradual doping distribution in the WELL region allows the depletion region to extend more smoothly and naturally into the drift region, and the electric field lines are more uniform than before, thus reducing the peak electric field. The synergistic effect of the multilayer WELL region and the high-k dielectric layer effectively suppresses the electric field concentration effect at the bottom of the trench, enabling the device to withstand higher voltages and meet the requirements of applications such as electric drive systems for electric vehicles.

[0026] Step six, as follows Figure 6 As shown, ion implantation is performed on epitaxial layer 2 to form a heavily doped source region 8, wherein the doping concentration of source region 8 is higher than that of WELL region 7; the doping concentration of source region 8 is 1.5e 20 .

[0027] Step seven, as Figure 7 As shown, through-hole 9 is etched and filled with metal to finally form a complete MOSFET structure.

[0028] This invention abandons the complex and expensive superjunction epitaxial process and avoids the waste of device area caused by the field plate structure. Through structural optimization, it achieves compatibility with existing processes, improving performance while controlling costs and maintaining a high area utilization rate. The structural design is compatible with existing MOSFET fabrication processes, enabling mass production without large-scale modifications to production lines, accelerating technology implementation and industrial application, and adapting to the development trend of high performance and low cost in power semiconductor devices.

[0029] A MOSFET for improving the breakdown voltage of a Trench MOSFET includes a substrate 1, an epitaxial layer 2, a WELL region and a source region 8 connected sequentially from bottom to top; The source region 8 is equipped with: Metal layer 9 extends downward from the top surface of source region 8 to third WELL region 7, and is spaced from the bottom surface of third WELL region 7; K dielectric layer 3 extends downward from the top surface of the source region 8 to below the WELL region, and the bottom of the K dielectric layer 3 has an arc structure; The core idea of ​​high-k dielectric is to replace SiO2 with a thicker insulating layer without sacrificing gate control capability (Cox). According to the capacitance formula C = K / d, a greater thickness of high-k dielectric is needed to maintain the capacitance. At the same voltage, the high-k dielectric layer can have a lower electric field strength (E = V / d, where d is the dielectric thickness and K is the dielectric constant). When the high-k dielectric layer covers the curved bottom, even if there is a gradient in the external electric field distribution, the electric field inside the dielectric layer can be effectively "diluted." At the interface between the high-k dielectric and the epitaxial layer (semiconductor), the curved design combined with the high-k characteristics reduces interface charge accumulation, avoiding local electric field distortion caused by charge accumulation. Therefore, the high-k dielectric layer at the curved bottom disperses the electric field strength at the bottom of the trench, significantly reducing the electric field concentration in the gate oxide region, reducing the risk of gate oxide breakdown, and improving the long-term operating stability of the device.

[0030] The K dielectric layer 3 comprises one or a combination of HfO2, Al2O3, and ZrO2 materials. Silica has a relatively low dielectric constant, approximately 3.9. High-K materials have much higher dielectric constants, typically >10, and can even reach tens to hundreds. These materials are generally metal oxides (such as HfO2 and ZrO2) and composite high-titanium minerals (BST), exhibiting characteristics such as high capacitance density, low leakage current, and good thermal stability. Using high-K materials instead of traditional silica can reduce the electric field strength without increasing the physical thickness.

[0031] The breakdown voltage (breakdown field strength Eb) of the dielectric layer in power devices is an inherent property. When the actual electric field strength E in a certain region of the dielectric layer exceeds Eb, breakdown failure will occur. Since the electric field is naturally concentrated at the bottom of the trench, if a uniformly thick K dielectric layer is used, the overall dielectric layer needs to be thickened to prevent bottom breakdown—but this would result in excessively thick sidewall dielectric layers, increasing not only the gate capacitance (affecting switching speed) but also increasing manufacturing costs. In this case, the thickness of the bottom arc-shaped region of the K dielectric layer 3 is greater than the thickness of the trench sidewall region. The optimal ratio of the thickness of the bottom arc-shaped region of the K dielectric layer to the thickness of the trench sidewall region is 1.2:1 - 1.8:1, which increases the gate oxide breakdown voltage by 20%-40%, effectively solving the key problem of "easy gate oxide breakdown at the bottom of the trench" and improving the long-term reliability of the device. Maintaining a relatively thin K-dielectric layer on the sidewall (in this case, the sidewall thickness ranges from 200 to 800 Å) can reduce Cgs and Cgd by 10%-20% compared to the "uniform thick dielectric layer scheme", and reduce switching losses by 12%-18%. While improving withstand voltage, it ensures that the device has excellent switching speed, which is suitable for the "high frequency and low loss" requirements of electric vehicle drive systems.

[0032] Polycrystalline silicon 4 is disposed within the K dielectric layer 3, and a gap is provided between the bottom of the polycrystalline silicon 4 and the bottom of the K dielectric layer 3.

[0033] In this case, there is a gap between the K dielectric layer 3 and the bottom surface of the epitaxial layer 2; the polycrystalline silicon 4 is inside the K dielectric layer 3, which has a U-shaped cross-section.

[0034] The WELL zones are arranged from bottom to top as follows: First WELL Zone 5, Second WELL Zone 6, and Third WELL Zone 7. Traditionally, abrupt PN junctions are formed between uniformly doped body regions (WELL regions) and drift regions (epitaxy layers). The depletion region bends sharply at the PN junction surface, causing electric field spikes at the corners. This invention designs a three-layer WELL region with a gradually doped body, effectively introducing a buffer layer or concentration transition region between the heavily doped WELL region and the lightly doped drift region, forming a gradually changing PN junction. This gradually changing junction allows the depletion region to extend into the drift region more smoothly and naturally, thus "pushing away" the electric field lines that were originally concentrated at the corners and redistributing them over a wider area, significantly reducing the peak electric field.

[0035] This article only uses Trench MOS as an example. Any discrete product with a trench structure can be made to overcome the poor chip voltage due to the electric field at the bottom corner of the trench.

[0036] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET, characterized in that, Includes the following steps: Step 1: Grow an epitaxial layer (2) on the substrate (1); Step 2: Etch trenches of a specific depth in the epitaxial layer (2), and process the bottom of the trenches to make the corners rounded. Step 3: Deposit a K dielectric layer on the surface of the trench (3); Step 4: Fill the trench with polysilicon (4) and etch it back to horizontal; Step 5: Perform multiple ion implantations on the epitaxial layer (2) to form a WELL region; Step 6: Ion implantation is performed on the epitaxial layer (2) to form a heavily doped source region (8), wherein the doping concentration of the source region (8) is higher than that of the WELL region (7); Step 7: Etch the CT vias and fill them with metal to finally form a complete MOSFET structure.

2. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 1, characterized in that, The thickness of the epitaxial layer (2) in step one ranges from 4 to 20 μm.

3. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 1, characterized in that, In step two, the trench depth ranges from 0.5 to 3 μm.

4. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 1, characterized in that, The thickness of the K dielectric layer (3) mentioned in step three ranges from 200 to 1000 Å.

5. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 1, characterized in that, The material of the K dielectric layer (3) mentioned in step three is one or a combination of HfO2, Al2O3, and ZrO2.

6. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 1, characterized in that, Step 5 includes the first Well area (5), the second Well area (6), and the third Well area (7).

7. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 6, characterized in that, The concentrations of the third WELL region (7), the second WELL region (6), and the first WELL region (5) decrease sequentially from the surface of the silicon wafer downwards.

8. The method for fabricating a MOS to improve the breakdown voltage of a Trench-MOSFET according to claim 1, characterized in that, The doping concentration of the source region (8) is 1.5e. 20 .

9. A MOS for improving the breakdown voltage of a Trench-MOSFET, fabricated by the method for fabricating a MOS for improving the breakdown voltage of a Trench-MOSFET as described in claim 1, characterized in that, It includes a substrate (1), an epitaxial layer (2), a WELL region and a source region (8) connected sequentially from bottom to top. The source region (8) is provided with: A metal layer (9) extends downward from the top surface of the source region (8) to the third WELL region (7); The K dielectric layer (3) extends downward from the top surface of the source region (8) to below the WELL region, and the bottom of the K dielectric layer (3) has an arc-shaped structure. Polycrystalline silicon (4) is disposed within the K dielectric layer (3).

10. A MOS for improving the breakdown voltage of a Trench-MOSFET according to claim 9, characterized in that, The WELL area includes a first WELL area (5), a second WELL area (6), and a third WELL area (7) arranged from bottom to top.

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