Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for improving the integration level of the semiconductor device and facilitating the miniaturization of the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of semiconductor structures, and a first isolation structure. The plurality of semiconductor structures are arranged on the semiconductor substrate and are distributed at intervals along a direction parallel to the surface of the semiconductor substrate. Each semiconductor structure comprises a first transistor and a second transistor which are arranged at an interval in the thickness direction of the semiconductor substrate, and the second transistor is located above the first transistor. The first isolation structure is at least disposed on the semiconductor substrate. The first isolation structure is located between at least one pair of two adjacent semiconductor structures, and is in contact with source and drain regions included in the first transistor and the second transistor in the two adjacent semiconductor structures. The first isolation structure is of a stacked structure in the thickness direction of the semiconductor substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] Semiconductor devices are electronic components made from semiconductor materials and are an important part of modern electronic technology. Semiconductor devices have advantages such as small size, low power consumption, and high speed, and are widely used in computers, communications, consumer electronics, medical equipment, and building intelligence.

[0003] However, the low integration of existing semiconductor devices hinders their miniaturization. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, as well as an electronic device, for improving the integration of semiconductor devices and facilitating the miniaturization of semiconductor devices.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: a semiconductor substrate, a plurality of semiconductor structures, and a first isolation structure. The plurality of semiconductor structures are disposed on the semiconductor substrate and spaced apart along a direction parallel to the surface of the semiconductor substrate. Each semiconductor structure includes a first transistor and a second transistor spaced apart along the thickness direction of the semiconductor substrate, with the second transistor positioned above the first transistor. The first isolation structure is disposed at least on the semiconductor substrate. The first isolation structure is located between at least one pair of adjacent semiconductor structures and contacts the source / drain regions included in the first transistor and the second transistor in the adjacent semiconductor structures, respectively. The first isolation structure is stacked along the thickness direction of the semiconductor substrate.

[0006] With the above technical solution, in the semiconductor device provided by the present invention, the first transistor and the second transistor in the same semiconductor structure are spaced apart along the thickness direction of the semiconductor substrate. Obviously, the first transistor and the second transistor in the same semiconductor structure can constitute a three-dimensional stacked transistor (CFET device), which is beneficial for reducing the lateral size of the semiconductor device. Furthermore, the first isolation structure located between at least one pair of adjacent semiconductor structures can be achieved by dividing the same active structure (such as a fin structure) used to manufacture the semiconductor structure into at least two parts, and forming a semiconductor structure based on each part, resulting in a higher density and a smaller area ratio of the semiconductor device, which is beneficial for the miniaturization of the semiconductor device.

[0007] In addition, the first isolation structure not only contacts the source and drain regions of the first transistor and the second transistor in the two adjacent semiconductor structures respectively, but also has a stacked structure along the thickness direction of the semiconductor substrate. At this time, the characteristics (such as material, stress, etc.) of different parts of the first isolation structure along the thickness direction of the semiconductor substrate can be set according to different actual needs to meet the working requirements, improve the working performance of the semiconductor device, and improve the applicability of the semiconductor device provided by the present invention in different application scenarios.

[0008] In one example, the material of the first isolation structure includes tensile stress material and / or compressive stress material.

[0009] In one example, the channel regions of two first transistors adjacent to the same first isolation structure are aligned along the width direction of their sidewalls; and / or, the channel regions of two second transistors adjacent to the same first isolation structure are aligned along the width direction of their sidewalls.

[0010] In one example, in the same semiconductor structure, the sidewalls of the channel region included in the first transistor are aligned with the sidewalls of the channel region included in the second transistor.

[0011] In one example, two first transistors adjacent to the same first isolation structure have the same conductivity type; and / or, two second transistors adjacent to the same first isolation structure have the same conductivity type.

[0012] In one example, within the same semiconductor structure, the first and second transistors have opposite conductivity types.

[0013] In one example, the first isolation structure includes a first material portion and a second material portion located on the first material portion. The first material portion contacts the source / drain regions of two adjacent first transistors, respectively. The second material portion contacts the source / drain regions of two adjacent second transistors, respectively. An interface is provided between the first material portion and the second material portion.

[0014] In one example, the stresses of the first material part and the stresses of the second material part are different; and / or, the materials of the first material part and the second material part are different.

[0015] In one example, in the case where one of the first transistor and the second transistor in the same semiconductor structure is a P-type transistor and the other is an N-type transistor, and at least the P-type transistor is a gate-ring transistor, the first material portion and the second material portion that are in contact with the source-drain region of the P-type transistor have compressive stress; and / or, the first material portion and the second material portion that are in contact with the source-drain region of the N-type transistor have tensile stress or no stress.

[0016] In one example, the first isolation structure further includes a third material portion disposed between the first material portion and the second material portion. The third material portion has interfaces with the first material portion and the second material portion, respectively.

[0017] In one example, the third material section is stress-free.

[0018] In one example, along the length of the channel region included in the first transistor and / or the second transistor, the top of the first isolation structure has isolation sidewalls on both sides, and the top width of the first isolation structure is smaller than the width of the rest of the first isolation structure excluding the top.

[0019] In one example, the first isolation structure further includes a liner layer. The liner layer covers the sidewalls of the first material portion and the second material portion, and is located at least at the bottom of the first material portion.

[0020] In one example, the portion of the padding layer located on the sidewall of the first material portion has an interface with the portion of the padding layer located on the sidewall of the second material portion, and the padding layer is also located between the first material portion and the second material portion.

[0021] In one example, the semiconductor device further includes a second isolation structure located on both sides of the semiconductor structure along the width direction of the channel region included in the first transistor and / or the second transistor; the extension direction of the second isolation structure intersects the extension direction of the first isolation structure to jointly isolate at least one semiconductor structure from other semiconductor structures adjacent to it.

[0022] In a second aspect, the present invention provides an electronic device comprising: the semiconductor device provided in the first aspect and its various implementations described above. The electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0023] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0024] Thirdly, the present invention provides a method for manufacturing a semiconductor device, the method comprising: first, forming a fin-like structure on a semiconductor substrate. The fin-like structure includes a lower fin, a semiconductor isolation portion, and an upper fin, sequentially disposed along the thickness direction of the semiconductor substrate. Next, forming a first mask structure and a second mask structure spanning the fin-like structure. The first mask structure and the second mask structure are spaced apart along a direction parallel to the surface of the semiconductor substrate. Next, etching away the portion of the fin-like structure exposed outside the first mask structure and the second mask structure. Next, forming source / drain regions epitaxially on both sides of the lower fin. Next, protecting the source / drain regions located on both sides of the lower fin; and epitaxially forming source / drain regions on both sides of the upper fin. Next, sequentially removing the first mask structure and the fin-like structure located below the first mask structure to cut the fin-like structure and form a region to be filled. Next, forming a first isolation structure in a stacked structure along the thickness direction of the semiconductor substrate within the region to be filled.

[0025] In one example, a first isolation structure is formed in the region to be filled, forming a stacked structure along the thickness direction of the semiconductor substrate, including: forming a first material portion in the region to be filled. The top height of the first material portion is greater than or equal to the top height of the source / drain regions located on both sides of the lower fin, and less than or equal to the bottom height of the source / drain regions located on both sides of the upper fin. Next, a second material portion is formed on the first material portion.

[0026] In one example, after forming a first material portion in the region to be filled and before forming a second material portion, the method for manufacturing a semiconductor device further includes forming a third material portion on the first material portion. The top height of the third material portion is less than or equal to the bottom height of the source / drain regions located on both sides of the upper fin.

[0027] In one example, after forming the region to be filled and before forming a first material portion within the region to be filled; and / or, after forming a first material portion within the region to be filled and before forming a second material portion on the first material portion, the method of manufacturing a semiconductor device further includes: forming a pad layer on the inner surface of the region to be filled.

[0028] In one example, the method of manufacturing a semiconductor device further includes: using a semiconductor process to form a first transistor based on the remaining lower fin and the source / drain region adjacent to it, and to form a second transistor based on the remaining upper fin and the source / drain region adjacent to it.

[0029] The beneficial effects of the third aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0031] Figure 1 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 1 ;

[0032] Figure 2 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ;

[0033] Figure 3 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 3 ;

[0034] Figure 4 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 4 ;

[0035] Figure 5 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 5 ;

[0036] Figure 6 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 6 ;

[0037] Figure 7 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 7 ;

[0038] Figure 8 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 8 ;

[0039] Figure 9 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 9 ;

[0040] Figure 10 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 ;

[0041] Figure 11 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 one;

[0042] Figure 12A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 two;

[0043] Figure 13 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 three;

[0044] Figure 14 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Four;

[0045] Figure 15 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 five;

[0046] Figure 16 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 six;

[0047] Figure 17 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 seven;

[0048] Figure 18 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 eight;

[0049] Figure 19 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Nine;

[0050] Figure 20 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ten;

[0051] Figure 21 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 eleven;

[0052] Figure 22 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 twelve;

[0053] Figure 23 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 Thirteen;

[0054] Figure 24 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2fourteen;

[0055] Figure 25 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 fifteen;

[0056] Figure 26 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 sixteen;

[0057] Figure 27 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 Seventeen;

[0058] Figure 28 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 eighteen.

[0059] Reference numerals: 11 is a semiconductor substrate, 12 is a first transistor, 13 is a second transistor, 14 is a first isolation structure, 15 is a source / drain region, 16 is a channel region, 17 is a gate stack structure, 18 is a first material portion, 19 is a second material portion, 20 is a third material portion, 21 is a pad layer, 22 is a gate sidewall, 23 is a shallow trench isolation structure, 24 is an insulating dielectric layer, 25 is a third isolation structure, 26 is a fourth isolation structure, 27 is a fin structure, 28 is a lower fin, 29 is a semiconductor isolation portion, 30 is an upper fin, 31 is a first mask structure, 32 is a second mask structure, 33 is the area to be filled, 34 is a sacrificial layer, and 35 is a channel layer. Detailed Implementation

[0060] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0061] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0062] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0064] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0065] Semiconductor devices are electronic components made from semiconductor materials and are an important part of modern electronic technology. Semiconductor devices have advantages such as small size, low power consumption, and high speed, and are widely used in computers, communications, consumer electronics, medical equipment, and building intelligence.

[0066] However, the low integration of existing semiconductor devices hinders their miniaturization.

[0067] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a semiconductor device. In the semiconductor device provided by these embodiments, a first isolation structure is located between at least one pair of adjacent semiconductor structures to facilitate the miniaturization of the semiconductor device. Furthermore, the first isolation structure contacts the source / drain regions of the first transistor and the second transistor in the two adjacent semiconductor structures, respectively, to isolate the source / drain regions of the adjacent semiconductor structures. Simultaneously, it is stacked along the thickness direction of the semiconductor substrate to improve the operating performance of the semiconductor device.

[0068] In a first aspect, embodiments of the present invention provide a semiconductor device. For example... Figures 25 to 28 As shown, the semiconductor device includes a semiconductor substrate 11, a plurality of semiconductor structures, and a first isolation structure 14. The plurality of semiconductor structures are disposed on the semiconductor substrate 11 and spaced apart along a direction parallel to the surface of the semiconductor substrate 11. Each semiconductor structure includes a first transistor 12 and a second transistor 13 spaced apart along the thickness direction of the semiconductor substrate 11, with the second transistor 13 located above the first transistor 12. The first isolation structure 14 is disposed at least on the semiconductor substrate 11. The first isolation structure 14 is located between at least one pair of adjacent semiconductor structures and contacts the source / drain regions 15 included in the first transistor 12 and the second transistor 13 of the adjacent semiconductor structures, respectively. The first isolation structure 14 is stacked along the thickness direction of the semiconductor substrate 11.

[0069] When the above technical solution is adopted, such as Figures 25 to 28 As shown, in the semiconductor device provided in this embodiment of the invention, the first transistor 12 and the second transistor 13 in the same semiconductor structure are spaced apart along the thickness direction of the semiconductor substrate 11. Clearly, the first transistor 12 and the second transistor 13 in the same semiconductor structure can constitute a three-dimensional stacked transistor (CFET device), which facilitates a reduction in the lateral dimension of the semiconductor device. Furthermore, the first isolation structure 14 located between at least one pair of adjacent semiconductor structures can be configured by dividing the same active structure (such as the fin structure 27) used to manufacture the semiconductor structure into at least two parts, and forming a semiconductor structure based on each part, resulting in a higher density and a smaller area ratio of the semiconductor device, which is beneficial for the miniaturization of the semiconductor device. In addition, the first isolation structure 14 not only contacts the source and drain regions 15 of the first transistor 12 and the second transistor 13 in the two adjacent semiconductor structures respectively, but the first isolation structure 14 is also stacked along the thickness direction of the semiconductor substrate 11. At this time, the characteristics (such as materials, stress, etc.) of different parts of the first isolation structure 14 along the thickness direction of the semiconductor substrate 11 can be set according to different actual needs to meet the working requirements, improve the working performance of the semiconductor device, and improve the applicability of the semiconductor device provided by the embodiment of the present invention in different application scenarios.

[0070] In practical applications, the embodiments of the present invention do not specifically limit the structure and material of the semiconductor substrate, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. For example, the semiconductor substrate can be any semiconductor material such as silicon, silicon germanium, or germanium.

[0071] Regarding semiconductor structures, the embodiments of the present invention do not impose specific limitations on the number and distribution of semiconductor structures disposed on the semiconductor substrate, and can be set according to actual needs.

[0072] For example, such as Figures 3 to 28 As shown, the sidewalls of the channel regions 16 of two first transistors 12 adjacent to the same first isolation structure 14 can be aligned along the width direction. In this case, the distribution of the channel regions 16 of the two first transistors 12 adjacent to the same first isolation structure 14 is relatively regular, which can reduce the manufacturing difficulty of semiconductor devices. Meanwhile, in the actual manufacturing process, as... Figures 3 to 28 As shown, the channel regions 16 of two first transistors 12 adjacent to the same first isolation structure 14 can be formed by different portions of the lower fin portion 28 included in the same fin structure 27, which is beneficial to improving the integration of semiconductor devices.

[0073] Optional, such as Figures 3 to 28 As shown, the sidewalls of the channel regions 16 of different first transistors 12 that intersect the same first isolation structure 14 along their own length extension lines can be aligned along the width direction.

[0074] Alternatively, the sidewalls of the channel regions of two first transistors adjacent to the same first isolation structure can be staggered along the width direction in a direction parallel to the surface of the semiconductor substrate. The staggered distance can be set according to the morphology of the fin structure before being isolated by the first isolation structure and actual needs, and is not specifically limited here.

[0075] For example, such as Figures 3 to 28 As shown, the sidewalls of the channel regions 16 of two second transistors 13 adjacent to the same first isolation structure 14 can be aligned along the width direction. In this case, the distribution of the channel regions 16 of the two second transistors 13 adjacent to the same first isolation structure 14 is relatively regular, which can reduce the manufacturing difficulty of semiconductor devices. Meanwhile, in the actual manufacturing process, such as... Figures 3 to 28 As shown, the channel regions 16 of two second transistors 13 adjacent to the same first isolation structure 14 can be formed by different portions of the upper fin portion 30 included in the same fin structure 27, which is beneficial to improving the integration of semiconductor devices.

[0076] Optional, such as Figures 3 to 28 As shown, the sidewalls of the channel regions 16 of different second transistors 13 that intersect the same first isolation structure 14 along their own length extension lines can be aligned along the width direction.

[0077] Alternatively, the sidewalls of the channel regions of two second transistors adjacent to the same first isolation structure can be staggered along the width direction. The staggered distance can be set according to the morphology of the fin structure before being isolated by the first isolation structure and the actual requirements, and is not specifically limited here.

[0078] As for the distribution between the first transistor and the second transistor in the same semiconductor structure, it can be determined according to actual needs and the actual manufacturing process.

[0079] For example, such as Figures 3 to 28 As shown, in the same semiconductor structure, the sidewall of the channel region 16 included in the first transistor 12 can be aligned with the sidewall of the channel region 16 included in the second transistor 13. In this case, the semiconductor structure can be manufactured using a relatively mature monolithic integration method, which can improve the compatibility between the semiconductor device provided in this embodiment of the invention and conventional mature processes, reduce the manufacturing difficulty of the semiconductor device, and also improve the yield of the semiconductor device.

[0080] Alternatively, in the same semiconductor structure, the sidewalls of the channel region included in the first transistor can also be offset from the sidewalls of the channel region included in the second transistor in a direction parallel to the surface of the semiconductor substrate. This facilitates the formation of source-drain contact structures and reduces the risk of device malfunction caused by overlapping of different source-drain contact structures.

[0081] In terms of conductivity type, within the same semiconductor structure, the first transistor and the second transistor can have the same or opposite conductivity types. The specific conductivity types of the first transistor and the second transistor can be set according to actual requirements.

[0082] It is worth noting that in practical applications, stress can be generated in the source / drain regions to alter the band structure of the channel material, thereby increasing the carrier mobility and improving the carrier transport performance of the channel. When the transistors have different conductivity types, the direction of the stress generated in the source / drain regions on the channel needs to differ. Specifically, N-type transistors require tensile stress in the source / drain regions to provide compressive stress to the channel, while P-type transistors require compressive stress to effectively improve the carrier mobility. In the above cases, when the first and second transistors in the same semiconductor structure have different conductivity types, different parts of a first isolation structure stacked along the thickness direction of the semiconductor substrate can provide different stresses to the source / drain regions of the first and second transistors, respectively, to meet the operating requirements of the first and second transistors with different conductivity types, thus improving their performance.

[0083] For example, two first transistors adjacent to the same first isolation structure can have the same conductivity type. This configuration ensures that, because the same first isolation structure contacts the source and drain regions of at least the two adjacent first transistors, the characteristics of the first isolation structure itself will affect these two adjacent first transistors. Therefore, when two first transistors adjacent to the same first isolation structure have the same conductivity type, they have approximately the same characteristics. The same portion of the first isolation structure along the semiconductor substrate thickness direction has roughly the same effect on these two different first transistors. Adjusting the same portion of the first isolation structure along the semiconductor substrate thickness direction can improve the performance of both first transistors, thus enhancing the performance of the semiconductor device. Furthermore, since different first transistors are located in the same layer along the semiconductor substrate thickness direction, when two first transistors adjacent to the same first isolation structure have the same conductivity type, different first transistors can be manufactured simultaneously using the same process. This eliminates the need for doping different first transistors with opposite conductivity types and the need to use different manufacturing materials due to different conductivity types, reducing manufacturing difficulty.

[0084] For example, two second transistors adjacent to the same first isolation structure can have the same conductivity type. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of two first transistors adjacent to the same first isolation structure having the same conductivity type described above, and will not be repeated here.

[0085] For example, the first transistor can be of N-type conductivity, and the second transistor can be of P-type conductivity. Alternatively, the first transistor can be of P-type conductivity, and the second transistor can be of N-type conductivity.

[0086] For example, the first transistor and the second transistor can both be N-type or P-type.

[0087] Furthermore, the device types of the first transistor and the second transistor are not specifically limited in the embodiments of the present invention, as long as they can be applied to the semiconductor devices provided in the embodiments of the present invention. The device types of the first transistor and the second transistor can be the same or different.

[0088] For example, the first transistor and / or the second transistor may be a fin field-effect transistor or a gate-around transistor.

[0089] For example, when the first transistor and / or the second transistor is a finned field-effect transistor, the first transistor and / or the second transistor includes a source / drain region, a channel region, and a gate stack structure. The source / drain regions are located on both sides of the channel region along its length, and the gate stack structure covers the top and both sides of the channel region.

[0090] For example, when the first transistor and / or the second transistor is a gate-to-ring transistor, the first transistor and / or the second transistor includes a source-drain region, a channel region, and a gate stack structure. The source-drain region is disposed on both sides of the channel region along its length. The channel region includes at least one layer of nanostructure suspended between the source-drain region. The gate stack structure surrounds the outer periphery of each nanostructure layer. This embodiment of the invention does not specifically limit the number of nanostructure layers included in the channel region.

[0091] It should be noted that the source region of the second transistor may be located on the same side as the source region of the first transistor along the length of the gate stack structure; or the drain region of the second transistor may be located on the same side as the source region of the first transistor along the length of the gate stack structure.

[0092] In addition, such as Figures 3 to 28 As shown, the extending directions of the gate stack structure 17 of two semiconductor structures adjacent to the same first isolation structure 14 can be arranged in parallel. Furthermore, the extending direction of the gate stack structure 17 can be arranged parallel to the extending direction of the first isolation structure 14.

[0093] In some cases, such as Figures 25 to 28 As shown, the semiconductor device may further include a third isolation structure 25. Along the thickness direction of the semiconductor substrate 11, the third isolation structure 25 is disposed between the source / drain regions 15 of the first transistor 12 and the second transistor 13 to prevent leakage current and device failure. Specifically, the material of the third isolation structure 25 may include any insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The third isolation structure 25 may be a single-layer structure with all parts made of the same material, or it may be a stacked structure including multiple materials (the distribution between different materials can be set according to actual needs and is not specifically limited here).

[0094] As for the thickness of the third isolation structure, it can be determined based on the electrical insulation requirements of the third isolation structure in the actual application scenario, as well as the requirements for the parasitic capacitance and parasitic resistance of the semiconductor device. No specific limit is made here.

[0095] In one example, such as Figure 25 and Figure 28 As shown, the semiconductor device may further include a fourth isolation structure 26. The fourth isolation structure 26 is disposed between the gate stack structure 17 included in the first transistor 12 and the gate stack structure 17 included in the second transistor 13 to reduce electrical interference between the first transistor 12 and the second transistor 13, thereby improving the electrical performance of the semiconductor device. The material of the fourth isolation structure 26 may include any insulating material such as silicon oxide or silicon nitride.

[0096] In some cases, such as Figures 25 to 28As shown, the semiconductor device provided in this embodiment of the invention may further include a gate sidewall 22. The gate sidewall 22 is disposed on both sides along the length of the gate stack structure 17 included in the first transistor 12 and the second transistor 13, serving to separate the gate stack structure 17 from other adjacent conductive structures and reduce the risk of leakage. The material of the gate sidewall 22 may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0097] Furthermore, the semiconductor device provided in this embodiment of the invention may also include isolation sidewalls. Along the length of the channel region included in the first transistor and / or the second transistor, isolation sidewalls are provided on both sides of the top of the first isolation structure, and the width of the top of the first isolation structure is smaller than the width of the remaining portion of the first isolation structure excluding the top. The isolation sidewalls can work together with the first isolation structure to isolate the contact structures used to bring out the source / drain regions and / or the gate, reducing the risk of leakage. In some cases, the isolation sidewalls can be made of the same material and have the same structure as the gate sidewalls, and both can be formed simultaneously to improve the manufacturing efficiency of the semiconductor device and reduce its manufacturing cost.

[0098] Regarding the location of the first isolation structure, it can be disposed solely on the semiconductor substrate. Alternatively, the first isolation structure can extend into a portion of the semiconductor substrate's thickness.

[0099] Alternatively, a first isolation structure may be provided between every pair of adjacent semiconductor structures. Or, at least one pair of adjacent semiconductor structures may exist without a first isolation structure. The distribution density of the first isolation structure between adjacent semiconductor structures can be set according to actual needs and is not specifically limited here.

[0100] Structurally, the specific structure of the stacked structure of the first isolation structure along the thickness direction of the semiconductor substrate can be set according to actual needs. For example, such as... Figures 25 to 28 As shown, the first isolation structure 14 may include a first material portion 18 and a second material portion 19 located on the first material portion 18. The first material portion 18 is in contact with the source / drain regions 15 of two adjacent first transistors 12. The second material portion 19 is in contact with the source / drain regions 15 of two adjacent second transistors 13. An interface is provided between the first material portion 18 and the second material portion 19.

[0101] The top height of the first material portion can be greater than or equal to the top height of the source / drain region included in the first transistor, and less than or equal to the bottom height of the source / drain region included in the second transistor. The bottom height of the second material portion can be less than or equal to the bottom height of the source / drain region included in the second transistor, and greater than the top height of the source / drain region included in the first transistor.

[0102] Alternatively, the first isolation structure may consist only of the first material section and the second material section described above.

[0103] Or, such as Figures 25 to 28 As shown, the first isolation structure 14 may further include a third material portion 20 disposed between the first material portion 18 and the second material portion 19. The third material portion 20 has an interface with the first material portion 18 and the second material portion 19, respectively. The bottom height of the third material portion 20 is greater than or equal to the top height of the source / drain region 15 included in the first transistor 12, and less than or equal to the bottom height of the source / drain region 15 included in the second transistor 13. The thickness of the third material portion 20 can be set according to actual needs, and is not specifically limited here.

[0104] In some cases, such as Figures 25 to 28 As shown, the first isolation structure 14 may further include a padding layer 21. The padding layer 21 covers the sidewalls of the first material portion 18 and the second material portion 19, and is located at least at the bottom of the first material portion 18. With this configuration, the presence of the padding layer 21 can isolate the first material portion 18 and the second material portion 19 from the semiconductor substrate 11, reducing the poor formation quality caused by the material differences between the first material portion 18 and the second material portion 19 and the semiconductor substrate 11, thus improving the yield of the semiconductor device.

[0105] Where the first isolation structure further includes a padding layer, the portion of the padding layer located on the outer periphery of the first material portion and the second material portion can be integrally continuous. In this case, the padding layer is only located below the first material portion, and there is no padding layer between the first material portion and the second material portion. Or, as... Figures 25 to 28 As shown, the portion of the pad layer 21 located on the side wall of the first material portion 18 has an interface with the portion of the pad layer 21 located on the side wall of the second material portion 19, and the pad layer 21 is also located between the first material portion 18 and the second material portion 19. At this time, suitable pad layers 21 can be provided according to the different first material portion 18 and the second material portion 19 to further improve the yield of semiconductor devices.

[0106] Furthermore, when the first isolation structure also includes a third material portion and a liner layer, the specific distribution of the liner layer can be determined according to actual needs. Only a few examples are given below to facilitate better implementation of the invention by those skilled in the art:

[0107] First, such as Figure 25 As shown, the portion of the padding layer 21 located on the sidewalls of the first material section 18, the second material section 19, and the third material section 20 can be integrally continuous. At this time, the padding layer 21 is also located below the first material section 18.

[0108] Second, such as Figure 26As shown, the portion of the padding layer 21 located on the sidewalls of the second material portion 19 and the third material portion 20 is integrally continuous, and has an interface with the portion of the padding layer 21 located on the sidewall of the first material portion 18. Furthermore, the padding layer 21 is also located between the third material portion 20 and the first material portion 18, and this portion of the padding layer 21 is integrally continuous with the padding layer 21 located on the sidewalls of the second material portion 19 and the third material portion 20.

[0109] Third, the portion of the padding layer located on the sidewalls of the first and third material portions is integrally continuous, and has an interface with the portion of the padding layer located on the sidewall of the second material portion. Furthermore, the padding layer is also located between the third and second material portions, and this portion of the padding layer is integrally continuous with the padding layer located on the sidewall of the second material portion.

[0110] Fourth, such as Figure 28 As shown, the padding layer 21 has interfaces between the portions of the first material portion 18, the second material portion 19, and the sidewalls of the third material portion 20. Furthermore, the padding layer 21 is also located between the second material portion 19 and the third material portion 20, and between the third material portion 20 and the first material portion 18. The padding layer 21 located between the second material portion 19 and the third material portion 20 is integrally continuous with the padding layer 21 located on the sidewall of the second material portion 19. The padding layer 21 located between the third material portion 20 and the first material portion 18 is integrally continuous with the padding layer 21 located on the sidewall of the first material portion 18.

[0111] Fifth, such as Figure 27 As shown, the padding layer 21 is only located on the side wall and below the second material section 19 and the side wall and below the first material section 18, and the padding layer 21 is not provided on the outer periphery of the third material section 20.

[0112] The materials used in different parts of the first isolation structure can be set according to actual needs, and no specific restrictions are made here.

[0113] For example, the material of the first isolation structure may include a tensile stress material and / or a compressive stress material. In this case, stress can be generated in the channel region through the first isolation structure and via the source / drain regions in contact with the first isolation structure, thereby improving the carrier mobility of the channel region. In some cases, the material of the first isolation structure may also include a stress-free material.

[0114] As for the material types and stress types of different parts of the first isolation structure, they can be set according to the conductivity type of the first transistor and the second transistor, as well as actual needs, and no specific limitations are made here.

[0115] For example, when the first isolation structure includes a first material part and a second material part, the materials of the first material part and the second material part may be the same or different.

[0116] For example, the stress in the first material part and the stress in the second material part can be different. This difference in stress can mean that the type of stress in the first material part is different from the type of stress in the second material part (e.g., one of the first and second material parts has tensile stress, and the other has compressive stress). Alternatively, it can mean that the type of stress in the first and second material parts is the same, but the magnitude of the stress is different. Or, it can mean that both the type and magnitude of the stress in the first and second material parts are different.

[0117] It should be noted that the crystal orientation of the channel in a gate-around transistor is typically

[100] . In this case, the channel of the gate-around transistor is favorable for electron transport but unfavorable for hole transport. However, the channel carriers of a P-type gate-around transistor are holes. Therefore, in the same semiconductor structure, if one of the first transistor and the second transistor is a P-type transistor and the other is an N-type transistor, and at least the P-type transistor is a gate-around transistor, the hole mobility of the P-type gate-around transistor is disadvantageous. Furthermore, to limit the gate length and improve the yield of the gate-around transistor, inner sidewalls need to be formed before forming the source and drain regions. The presence of these inner sidewalls means that when forming the source and drain regions on both sides of the remaining portion of the channel layer using epitaxial processing, only the remaining portion of the channel layer (which may also include the semiconductor substrate 11) can be used as the seed layer; the remaining portion of the sacrificial layer cannot be used as the seed layer. This results in numerous defects in the formed source and drain regions, making it difficult for them to provide stress to the remaining portion of the channel layer (used to manufacture the channel region). Consequently, it is detrimental to improving the carrier mobility within the channel region, leading to poor performance of the P-type gate-around transistor. In this situation, the specific material of the first isolation structure can be determined according to the conductivity type and device type of the first and second transistors, as well as actual requirements.

[0118] For example, such as Figures 25 to 28As shown, in the case where one of the first transistor 12 and the second transistor 13 in the same semiconductor structure is a P-type transistor and the other is an N-type transistor, and at least the P-type transistor is a gate-around transistor, the first material portion 18 and the second material portion 19 that contacts the source / drain region 15 of the P-type transistor have compressive stress; and / or, the first material portion 18 and the second material portion 19 that contacts the source / drain region 15 of the N-type transistor have tensile stress or no stress. With this configuration, the compressive stress in the first material portion 18 and the second material portion 19 that contacts the P-type transistor allows compressive stress to be provided to the channel region 16 through the contacting source / drain region 15, increasing the carrier mobility of the channel region 16 of the P-type transistor, improving the driving performance of the P-type transistor, and reducing the degree of performance mismatch between the P-type transistor and the N-type transistor in the semiconductor structure. Furthermore, when one of the first material section 18 and the second material section 19 that contacts the source / drain region 15 of the N-type transistor has tensile stress, the source / drain region 15 in contact with the N-type transistor can provide tensile stress to the channel region 16, thereby increasing the carrier mobility of the channel region 16 of the N-type transistor, improving the driving performance of the N-type transistor, and enhancing the operating performance of the semiconductor device. Conversely, when one of the first material section 18 and the second material section 19 that contacts the source / drain region 15 of the N-type transistor is stress-free, the degree of performance mismatch between the P-type transistor and the N-type transistor in the semiconductor structure can be reduced.

[0119] For example, when the first transistor is a P-type transistor, the first material portion has compressive stress; and / or, the second material portion may have tensile stress or no stress.

[0120] For example, when the second transistor is a P-type transistor, the second material portion has compressive stress; and / or, the first material portion may have tensile stress or no stress.

[0121] Furthermore, in this case, the type of N-type transistor can be set according to actual needs, and no specific limitation is made here. For example, an N-type transistor can be a gate-to-ring transistor or a fin field-effect transistor.

[0122] Secondly, if the first isolation structure also includes a third material part disposed between the first material part and the second material part, the third material part can be stress-free to reduce the impact on the first material part and the second material part, which is beneficial for the first material part and / or the second material part to effectively generate stress on the channel region through the source and drain regions in contact with it.

[0123] As for the materials of different parts of the first isolation structure, they can be determined according to the characteristic requirements of different parts, and no specific limitations are made here.

[0124] For example, when the first isolation structure includes the first material portion and the second material portion described above, the material of the first material portion and the second material portion that has compressive stress may include C-SiN. The material of the first material portion and the second material portion that has tensile stress or no stress may include SiN.

[0125] If the first isolation structure also includes a third material section, the material of the third material section may include silicon nitride or silicon oxide, etc.

[0126] If the first isolation structure also includes a liner layer, the material of the liner layer may include materials such as silicon oxide.

[0127] In some cases, such as Figures 25 to 28 As shown, the semiconductor device may further include an insulating dielectric layer 24 to reduce the risk of leakage current in the semiconductor device and improve the yield of the source-drain regions 15 included in the second transistor 13, thereby improving the operating performance of the semiconductor device. The insulating dielectric layer 24 covers the second transistor 13.

[0128] The material of the insulating dielectric layer may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention.

[0129] In some cases, such as Figure 16 As shown, the semiconductor device provided in this embodiment of the invention may further include a shallow trench isolation structure 23. The shallow trench isolation structure 23 is formed on the semiconductor substrate 11 to define the active region of the semiconductor substrate 11, reduce leakage risk, and further improve the yield and performance of the semiconductor device.

[0130] As for the material of the shallow trench isolation structure, it can include any insulating material such as silicon oxide, silicon oxynitride, or silicon oxynitride, without specific limitations here.

[0131] To isolate adjacent semiconductor structures, a second isolation structure (not shown in the figure) is further included between adjacent semiconductor structures in the width direction of the channel region. The extension direction of the second isolation structure intersects the extension direction of the first isolation structure (for example, the extension direction of the second isolation structure is perpendicular to the extension direction of the first isolation structure. The extension direction of the first isolation structure is parallel to the length direction of the channel region, and the extension direction of the second isolation structure is parallel to the width direction of the channel region). This allows the second isolation structure, together with the aforementioned first isolation structure, to form an isolator, isolating at least one semiconductor structure from other surrounding adjacent semiconductor structures, thereby achieving electrical isolation between devices.

[0132] Secondly, embodiments of the present invention provide an electronic device comprising: the semiconductor device provided in the first aspect and its various implementations described above. The electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0133] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0134] Thirdly, embodiments of the present invention provide a method for manufacturing a semiconductor device.

[0135] The following will be based on Figures 1 to 28 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0136] First, such as Figures 1 to 3 As shown, a fin structure 27 is formed on a semiconductor substrate 11. The fin structure 27 includes a lower fin portion 28, a semiconductor isolation portion 29, and an upper fin portion 30 arranged sequentially along the thickness direction of the semiconductor substrate 11.

[0137] In the actual manufacturing process, the lower fin of the fin structure is used to manufacture the first transistor. Therefore, the specific structure of the lower fin of the fin structure can be determined according to the device type and structure of the first transistor.

[0138] For example, when the first transistor is a fin field-effect transistor, the lower fin of the fin structure can be a single-layer elongated semiconductor structure; or it can be an elongated semiconductor structure including multiple semiconductor layers. Furthermore, the material and width of the lower fin of the fin structure are the same as the material and width of the channel region of the first transistor.

[0139] For example, when the first transistor is a gate-to-ring transistor, the lower fin of the fin structure may include alternating layers of sacrificial layers and channel layers. In the alternating layers of sacrificial layers and channel layers, both the bottom layer and the top layer are sacrificial layers. The channel layer included in the lower fin of the fin structure is used to fabricate the nanostructure in the channel region of the first transistor; therefore, the width of the lower fin and the material of the channel layer included in the lower fin can be determined based on the material and width of the channel region of the first transistor. Regarding the sacrificial layer included in the lower fin, the channel region of the first transistor needs to be released by subsequently removing the sacrificial layer of the lower fin covered by the second mask structure. Furthermore, when selectively removing the sacrificial layer included in the lower fin, the upper fin (or the channel layer included in the upper fin) is retained; therefore, the material of the sacrificial layer included in the lower fin can be any semiconductor material different from the channel layer included in the lower fin and the upper fin (or the channel layer included in the upper fin). For example, if the material of the channel layer in both the lower and upper fins is silicon, the material of the sacrificial layer in the lower fin can be germanium-silicon or germanium.

[0140] Similarly, the upper fin of the fin structure is used to manufacture the second transistor, so the specific structure of the upper fin of the fin structure can be determined according to the device type and structure of the second transistor.

[0141] For example, when the second transistor is a fin field-effect transistor, the upper fin portion of the fin structure can be a single-layer elongated semiconductor structure; or it can be an elongated semiconductor structure comprising multiple semiconductor layers. Furthermore, the material and width of the upper fin portion are the same as the material and width of the channel region included in the second transistor.

[0142] For example, when the second transistor is a gate-around transistor, the upper fin of the fin structure may include at least one semiconductor stack. Each semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. The channel layer included in the upper fin is used to fabricate the nanostructure in the channel region included in the second transistor; therefore, the material of the channel layer included in the upper fin of the fin structure can be determined based on the material of the channel region included in the second transistor. Regarding the sacrificial layer included in the upper fin, the channel region included in the second transistor needs to be released by subsequently removing the sacrificial layer of the upper fin covered by the second mask structure. Furthermore, when the sacrificial layer included in the upper fin is selectively removed, the lower fin (or the channel layer included in the lower fin) is retained; therefore, the material of the sacrificial layer included in the upper fin can be any semiconductor material different from that of the channel layer included in the upper fin and the lower fin (or the channel layer included in the lower fin). In addition, when both the first transistor and the second transistor are gate-around transistors, the sacrificial layers included in the lower fin and the upper fin can be made of the same material to reduce the limitation of the epitaxial critical thickness and improve the formation quality of the semiconductor device; of course, the two materials can also be different.

[0143] Regarding the semiconductor isolation portion included in the fin structure, this semiconductor isolation portion serves as a pre-positioning element. Subsequently, by removing the semiconductor isolation portion not covered by the second mask structure, and after forming the source / drain regions included in the first transistor, a third isolation structure is formed on the source / drain regions included in the first transistor and the semiconductor substrate. Therefore, the thickness of the semiconductor isolation portion can be determined according to the thickness requirements of the third isolation structure. As for the material of the semiconductor isolation portion, it can be any semiconductor material different from that of the lower fin and the upper fin; no specific limitation is made here.

[0144] For example, such as Figure 1 As shown, epitaxial growth and other processes can be used to form a channel layer 35 (or the channel layer 35 and the sacrificial layer 34) for manufacturing the lower and upper fins along the thickness direction of the semiconductor substrate 11, and to form a semiconductor isolation layer for manufacturing the semiconductor isolation portion 29. Then, as... Figure 2 As shown, photolithography and etching processes are used to pattern the aforementioned channel layer 35 (or channel layer 35 and sacrificial layer 34), semiconductor isolation layer, and a portion of the semiconductor substrate 11 to form a spaced Fin structure. Next, as... Figure 3 As shown, shallow trench isolation structures 23 for defining active regions can be formed between adjacent Fin structures using processes such as deposition and etching. When the first transistor 12 is a gate-to-ring transistor, the top height of the shallow trench isolation structure 23 is less than or equal to the bottom height of the sacrificial layer 34 located at the bottom layer. The portion of the Fin structure exposed outside the shallow trench isolation structure 23 is a fin structure 27.

[0145] It should be noted that when the manufactured semiconductor device does not include the shallow trench isolation structure mentioned above, only the sacrificial layer, the channel layer, and the semiconductor isolation layer can be patterned; and the fin structure can be directly obtained after the patterning process.

[0146] Next, as Figure 4 and Figure 5 As shown, a first mask structure 31 and a second mask structure 32 spanning the fin structure 27 can be formed using processes such as deposition and etching. The first mask structure 31 and the second mask structure 32 are spaced apart along a direction parallel to the surface of the semiconductor substrate 11.

[0147] The first mask structure serves as a pre-positioning element. Subsequently, by removing the first mask structure and the portion of the fin structure covered by it, the area to be filled for forming the first isolation structure is released. Therefore, the distribution of the first mask structure can be determined based on the formation location of the first isolation structure in the actual application scenario. Similarly, the second mask structure also serves as a pre-positioning element. Subsequently, by at least removing the second mask structure, the gate formation area for forming the gate stack structure is released. Therefore, the distribution of the second mask structure can be determined based on the formation location of the gate stack structure in the actual application scenario. The specific structure and materials of the first and second mask structures can be set according to actual needs and are not specifically limited here.

[0148] For example, such as Figure 4 As shown, the first mask structure 31 may include a sacrificial gate. The material of the sacrificial gate may include easily removable materials such as polysilicon.

[0149] For example, such as Figure 4 As shown, the first mask structure 31 may include a sacrificial gate and isolation sidewalls located at least on both sides of the sacrificial gate along its length. The material of the sacrificial gate may include easily removable materials such as polysilicon. The material of the isolation sidewalls can be referred to above.

[0150] For example, the first mask structure described above may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include silicon oxide or the like.

[0151] In one example, after forming the first mask structure and the second mask structure, the semiconductor device manufacturing method further includes: removing the remaining semiconductor isolation portion using processes such as dry etching or wet etching. Next, as... Figure 4 and Figure 5 As shown, a fourth isolation structure 26 is formed between the remaining lower fin and the remaining upper fin using processes such as deposition and etching.

[0152] It should be noted that, while manufacturing the fourth isolation structure, at least two isolation sidewalls along the length of the first mask structure and at least two gate sidewalls along the length of the second mask structure can be formed simultaneously to improve the manufacturing efficiency of semiconductor devices. Alternatively, the fourth isolation structure can be manufactured using processes such as deposition and etching after the isolation sidewalls and gate sidewalls have been formed.

[0153] Next, as Figure 6 and Figure 7As shown, dry etching or wet etching processes can be used to etch away the portion of the fin structure exposed outside the first mask structure 31 and the second mask structure 32 (if a fourth isolation structure 26 is formed at this time, the fourth isolation structure 26 also needs to be selectively etched).

[0154] Next, as Figure 8 and Figure 9 As shown, source / drain regions 15 are formed on both sides of the lower fin.

[0155] For example, deposition and etching processes can be used to form a third mask structure covering both sides of the lower fin along the length direction of the fin-like structure on a semiconductor substrate. This embodiment of the invention does not specifically limit the material of the third mask structure. The top of the third mask structure needs to be greater than the top height of the lower fin and less than the bottom height of the upper fin. Next, deposition and etching processes can be used to form a fourth mask structure covering both sides of the upper fin along the length direction; the material of the fourth mask structure is different from the material of the third mask structure. This embodiment of the invention does not specifically limit the material of the fourth mask structure, as long as it is different from the material of the third mask structure and is easy to remove. For example, the material of the third mask structure may include silicon oxide, and the material of the fourth mask structure may include silicon nitride. Next, wet etching or dry etching processes can be used to selectively remove the third mask structure to expose the lower fin. Next, as... Figure 6 As shown, under the protection of the fourth mask structure, source / drain regions 15 can be formed on both sides of the remaining lower fin.

[0156] Alternatively, in practical applications, epitaxial growth or other processes can be used to form source / drain regions on both sides of the remaining lower fin. Then, an etching process is used to remove the source / drain regions located on the outer periphery of the remaining upper fin (if a semiconductor isolation portion is formed, the source / drain regions on both sides of the semiconductor isolation portion also need to be removed).

[0157] Next, as Figure 10 and Figure 11 As shown, the source / drain regions 15 located on both sides of the lower fin are protected.

[0158] In the actual manufacturing process, such as Figure 8 As shown, a third isolation structure 25 can be formed on the semiconductor substrate 11 and the source / drain regions 15 located on both sides of the lower fin using processes such as deposition and etching.

[0159] Then, as Figure 12 and Figure 13 As shown, source and drain regions 15 are formed on both sides of the upper fin.

[0160] Next, as Figure 14 and Figure 15As shown, an insulating dielectric layer 24 can be formed on the semiconductor substrate 11 using processes such as deposition and planarization. The top of the insulating dielectric layer 24 is flush with the tops of the first mask structure 31 and the second mask structure 32. The material of the insulating dielectric layer 24 can be referred to the previous text and will not be repeated here.

[0161] Next, as Figures 16 to 19 As shown, the first mask structure and the fin structure located below the first mask structure are removed in sequence to cut the fin structure and form the area to be filled 33.

[0162] In the actual manufacturing process, such as Figures 16 to 18 As shown, dry etching or wet etching processes can be used to remove at least a portion of the first mask structure. It should be noted that the specific structure of the first mask structure determines whether to remove the entire first mask structure or only a portion thereof. For example, if the first and second mask structures are identical, photolithography and etching processes can be used to first form a corresponding mask covering the second mask structure. Then, under the protection of the corresponding mask, at least a portion of the first mask structure is etched away. Where the first mask structure consists only of a sacrificial gate or only of a sacrificial gate and a gate oxide layer, the entire first mask structure needs to be removed. Where the first mask structure includes a sacrificial gate and isolation sidewalls, the isolation sidewalls need to be retained, i.e., only a portion of the first mask structure is removed.

[0163] If the first mask structure and the second mask structure have different structures, the first mask structure can be selectively removed directly based on the differences between the first mask structure and the second mask structure.

[0164] Then, dry etching or wet etching processes are used to remove the exposed parts of the fin structure, thereby cutting off the fin structure and forming the area to be filled.

[0165] Next, as Figures 20 to 23 As shown, processes such as deposition and etching can be used to form a first isolation structure 14 in a stacked structure along the thickness direction of the semiconductor substrate 11 in the area to be filled.

[0166] For example, a deposition and planarization process can be used to form the first material portion 18 in the area to be filled. And as... Figure 20 As shown, the first material section 18 is etched back so that the top height of the first material section 18 is greater than or equal to the top height of the source / drain regions 15 located on both sides of the lower fin, and less than or equal to the bottom height of the source / drain regions 15 located on both sides of the upper fin. Next, as... Figure 21 As shown, a second material section 19 is formed on the first material section 18 using a deposition and planarization process.

[0167] If the manufactured first isolation structure also includes a third material portion, then after the first material portion is formed in the area to be filled and before the second material portion is formed, a deposition and planarization process can be used to form the third material portion 20 on the first material portion 18. And for example... Figure 22 As shown, the third material section 20 is etched back so that the top height of the third material section 20 is less than or equal to the bottom height of the source / drain region 15 located on both sides of the upper fin.

[0168] If the manufactured first isolation structure also includes a liner layer, the formation sequence of the liner layer can be determined based on the formation range of the liner layer. For example, it can be formed after the area to be filled is formed and before the first material portion is formed within the area to be filled; and / or, after the first material portion is formed within the area to be filled and before the second material portion is formed on the first material portion, such as... Figure 23 As shown, a liner layer 21 is formed on the inner surface of the area to be filled using a deposition process.

[0169] Next, as Figures 24 to 28 As shown, a first transistor 12 is formed using semiconductor technology based on the remaining lower fin and the source / drain region 15 adjacent to itself, and a second transistor 13 is formed based on the remaining upper fin and the source / drain region 15 adjacent to itself.

[0170] In the actual manufacturing process, such as Figure 24 As shown, dry etching or wet etching processes can be used to remove at least a portion of the second mask structure. It should be noted that the specific structure of the second mask structure determines whether to remove the entire second mask structure or only a portion thereof. For example, if the second mask structure only includes a sacrificial gate or only includes a sacrificial gate and a gate oxide layer, the entire second mask structure needs to be removed. If the second mask structure includes a sacrificial gate and a gate sidewall 22, then the gate sidewall 22 needs to be retained, i.e., only a portion of the second mask structure needs to be removed. The specific execution method can be set according to the device types of the first transistor 12 and the second transistor 13, as well as actual requirements.

[0171] For example, when the first transistor and the second transistor are finned field-effect transistors, after removing the second mask structure, the remaining lower fin forms the channel region included in the first transistor. The remaining upper fin forms the channel region included in the second transistor.

[0172] For example, in the case where the first transistor and / or the second transistor is a gate-around transistor, after removing the second mask structure, it is also necessary to remove the remaining sacrificial layer to release the channel region.

[0173] Next, as Figures 25 to 28 As shown, a gate stack structure 17 can be formed on the outer periphery of the channel region 16 using processes such as atomic layer deposition.

[0174] It should be noted that the embodiments of the present invention do not specifically limit the formation order of the first isolation structure and the gate stack structure. The first isolation structure can be formed first, followed by the gate stack structure, as described above. Alternatively, the first mask structure and the fin structure located below the first mask structure can be removed after the gate stack structure is formed, and the first isolation structure can be formed in the released area to be filled.

[0175] Furthermore, if the manufactured semiconductor device also includes the aforementioned second isolation structure, after forming the gate stack structure, photolithography and etching processes can be used to etch and cut the gate stack structure at the corresponding locations, and deposition and planarization processes can be used to form the second isolation structure in the released area. Alternatively, the second mask structure can be etched and cut at the corresponding locations before forming the gate stack structure, and the second isolation structure can be formed in the released area.

[0176] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0177] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0178] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple semiconductor structures are disposed on the semiconductor substrate and spaced apart along a direction parallel to the surface of the semiconductor substrate; each semiconductor structure includes a first transistor and a second transistor spaced apart along the thickness direction of the semiconductor substrate, and the second transistor is located above the first transistor; A first isolation structure is disposed at least on the semiconductor substrate; The first isolation structure is located between at least one pair of adjacent semiconductor structures and is in contact with the source and drain regions of the first transistor and the second transistor in the two adjacent semiconductor structures, respectively; the first isolation structure is stacked along the thickness direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, characterized in that, The material of the first isolation structure includes tensile stress material and / or compressive stress material.

3. The semiconductor device according to claim 1, characterized in that, The channel regions of two first transistors adjacent to the same first isolation structure are aligned along the width direction of their sidewalls; And / or, the channel regions of two second transistors adjacent to the same first isolation structure are aligned along the width direction of the sidewalls.

4. The semiconductor device according to claim 1, characterized in that, In the same semiconductor structure, the sidewalls of the channel region included in the first transistor are aligned with the sidewalls of the channel region included in the second transistor.

5. The semiconductor device according to claim 1, characterized in that, The two first transistors adjacent to the same first isolation structure have the same conductivity type; And / or, the two second transistors adjacent to the same first isolation structure have the same conductivity type; And / or, in the same semiconductor structure, the first transistor and the second transistor have opposite conductivity types.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The first isolation structure includes a first material portion and a second material portion located on the first material portion; The first material portion contacts the source and drain regions of two adjacent first transistors respectively; the second material portion contacts the source and drain regions of two adjacent second transistors respectively; There is an interface between the first material section and the second material section.

7. The semiconductor device according to claim 6, characterized in that, The stress in the first material part is different from the stress in the second material part; And / or, the materials of the first material section and the second material section are different.

8. The semiconductor device according to claim 6, characterized in that, In the case where one of the first transistor and the second transistor in the same semiconductor structure is a P-type transistor and the other is an N-type transistor, and at least the P-type transistor is a gate-around transistor, One of the first material portion and the second material portion that contacts the source / drain region of the P-type transistor has compressive stress; and / or, one of the first material portion and the second material portion that contacts the source / drain region of the N-type transistor has tensile stress or no stress.

9. The semiconductor device according to claim 6, characterized in that, The first isolation structure further includes a third material portion disposed between the first material portion and the second material portion; the third material portion has an interface with the first material portion and the second material portion respectively.

10. The semiconductor device according to claim 6, characterized in that, Along the length of the channel region included in the first transistor and / or the second transistor, the top of the first isolation structure has isolation sidewalls on both sides, and the top width of the first isolation structure is smaller than the width of the rest of the first isolation structure excluding the top.

11. The semiconductor device according to claim 6, characterized in that, The first isolation structure further includes a liner layer; the liner layer covers the sidewalls of the first material portion and the second material portion, and is located at least at the bottom of the first material portion.

12. The semiconductor device according to claim 11, characterized in that, The portion of the padding layer located on the side wall of the first material portion has an interface with the portion of the padding layer located on the side wall of the second material portion, and the padding layer is also located between the first material portion and the second material portion.

13. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a second isolation structure located on both sides of the semiconductor structure along the width direction of the channel region included in the first transistor and / or the second transistor; the extension direction of the second isolation structure intersects the extension direction of the first isolation structure to jointly isolate at least one of the semiconductor structures and other adjacent semiconductor structures.

14. An electronic device, characterized in that, include: The semiconductor device as described in any one of claims 1 to 13; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

15. A method for manufacturing a semiconductor device, characterized in that, include: A fin-like structure is formed on a semiconductor substrate; the fin-like structure includes a lower fin, a semiconductor isolation portion, and an upper fin, which are sequentially arranged along the thickness direction of the semiconductor substrate. A first mask structure and a second mask structure are formed that span the fin-like structure; The first mask structure and the second mask structure are spaced apart along a direction parallel to the surface of the semiconductor substrate; Etching removes the portion of the fin structure exposed outside the first mask structure and the second mask structure; Source / drain regions are formed on both sides of the lower fin. The source / drain regions located on both sides of the lower fin are protected; and source / drain regions are formed extending outward on both sides of the upper fin. The first mask structure and the fin structure located below the first mask structure are removed sequentially to cut the fin structure and form the area to be filled. Within the region to be filled, a first isolation structure is formed in a stacked configuration along the thickness direction of the semiconductor substrate.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, Within the region to be filled, a first isolation structure is formed in a stacked structure along the thickness direction of the semiconductor substrate, comprising: A first material portion is formed in the area to be filled; the top height of the first material portion is greater than or equal to the top height of the source / drain regions located on both sides of the lower fin, and less than or equal to the bottom height of the source / drain regions located on both sides of the upper fin; A second material portion is formed on the first material portion.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, After forming the first material portion in the area to be filled and before forming the second material portion, the method for manufacturing the semiconductor device further includes: A third material portion is formed on the first material portion; the top height of the third material portion is less than or equal to the bottom height of the source / drain regions located on both sides of the upper fin portion.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, characterized in that, After forming the region to be filled, and before forming the first material portion within the region to be filled; and / or, after forming the first material portion within the region to be filled, and before forming the second material portion on the first material portion, the method for manufacturing the semiconductor device further includes: A padding layer is formed on the inner surface of the area to be filled.

19. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method for manufacturing the semiconductor device further includes: Using semiconductor technology, a first transistor is formed based on the remaining lower fin and the source / drain region adjacent to itself, and a second transistor is formed based on the remaining upper fin and the source / drain region adjacent to itself.

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