Avalanche photodiode

Abstract

The invention relates to an avalanche photodiode. Provided is an avalanche photodiode having excellent characteristics and reliability. The avalanche photodiode includes a substrate, an n-type contact layer formed over the substrate, and a mesa structure formed over the n-type contact layer. The mesa structure includes a multiplication layer, a light absorption layer, and a p-type contact layer. In plan view, the multiplication layer is larger than the light absorption layer, and in plan view, the light absorption layer is larger than the p-type contact layer.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to Japanese Patent Application No. JP 2024-153278, filed September 5, 2024, and Japanese Patent Application No. JP 2024-080650, filed May 17, 2024. The disclosure of the prior applications is considered part of this patent application and is hereby incorporated by reference into this patent application. TECHNICAL FIELD

[0003] The present disclosure relates generally to avalanche photodiodes. BACKGROUND

[0004] An avalanche photodiode (also referred to herein as an “APD”) is a kind of semiconductor light-receiving element. Generally, an APD includes a light-absorbing layer that absorbs light and generates carriers, and a multiplication layer that multiplies the generated carriers. SUMMARY

[0005] An APD that can be required to operate at high speed is generally preferred to have a mesa structure that enables a small element capacitance. In many cases, an APD is also driven at a higher voltage than a positive-intrinsic-negative photodiode (PiN-PD). For example, when a strong electric field is applied to the multiplication layer, local breakdown can occur at a side surface of the multiplication layer included in the mesa structure. The occurrence of breakdown hinders the APD from operating normally. In the same way, a side surface of the light-absorbing layer included in the mesa structure can also experience an increase in leakage current at the side surface due to a strong electric field, and this increase can adversely affect the characteristics.

[0006] Some embodiments described herein include an avalanche photodiode that suppresses the occurrence of breakdown and supports high-speed operation.

[0007] In some embodiments, an avalanche photodiode includes a substrate, an n-type contact layer formed over the substrate, a multiplication layer formed over the n-type contact layer, a light-absorbing layer formed over the multiplication layer, and a p-type contact layer formed over the light-absorbing layer. The multiplication layer, the light-absorbing layer, and the p-type contact layer form a mesa structure. In plan view, the multiplication layer is larger than the light-absorbing layer, and in plan view, the light-absorbing layer is larger than the p-type contact layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a top view of an avalanche photodiode according to a first example embodiment of the present application.

[0009] Figure 2 is a schematic cross-sectional view taken along line II-II of the avalanche photodiode illustrated in Figure 1 is a schematic cross-sectional view taken along line II-II of the avalanche photodiode illustrated in

[0010] Figure 3A is a schematic cross-sectional view for illustrating a portion of an avalanche photodiode according to Comparative Example 1.

[0011] Figure 3B is a schematic cross-sectional view for illustrating a portion of an avalanche photodiode according to Comparative Example 2.

[0012] Figure 3C is a schematic cross-sectional view for illustrating a portion of an avalanche photodiode according to Comparative Example 3.

[0013] Figure 3D is a schematic cross-sectional view for illustrating a portion of an avalanche photodiode according to the first example embodiment.

[0014] Figure 4 is a schematic cross-sectional view of an avalanche photodiode according to the second example embodiment of the present application.

[0015] Figure 5 is a schematic cross-sectional view of an avalanche photodiode according to a modified example of the second example embodiment.

[0016] Figure 6 is a schematic cross-sectional view of an avalanche photodiode according to the third example embodiment of the present application.

[0017] Figure 7 is a top view of an avalanche photodiode according to the fourth example embodiment of the present application.

[0018] Figure 8 is a schematic cross-sectional view taken along the line VIII-VIII of the avalanche photodiode illustrated in Figure 7 DETAILED DESCRIPTION

[0019] Example embodiments of the present application are explained in detail below with reference to the accompanying drawings. Components that have substantially the same function are denoted with the same reference numerals throughout the drawings and repetitive explanation of these components is omitted. Note that the dimensions of the figures are not always drawn to scale.

[0020] Figure 1 is a top view of an avalanche photodiode (APD) according to the first example embodiment of the present application. The APD according to the first example embodiment can be top-illuminated. The positions of the outer edges of the multiplication layer 5, the light-absorbing layer 9, and the p-type contact layer 11 (not shown in the top view of Figure 1 ) are indicated by dotted lines. Figure 2 is a cross-sectional view for schematically illustrating along the line VII-VII of the APD illustrated in Figure 1 ​cross section taken along line II-II.

[0021] The APD can include semiconductor multilayers on the substrate 1. The substrate 1 can be semi-insulating, insulating, or n-type semiconductor. The semiconductor multilayers can include an n-type contact layer 3, a multiplication layer 5, a p-type electric field control layer 7, a light absorption layer 9, and a p-type contact layer 11. The n-type contact layer 3 can be a semiconductor layer doped with n-type impurities. For example, its impurity concentration can be 1 x 1018cm-3or more. An n-side electrode 17 can be connected to the n-type contact layer 3. The multiplication layer 5 and the light absorption layer 9 can be undoped layers intentionally not doped with impurities. In this case, the undoped layers can be layers having a background level of impurity concentration, and for example, the impurity concentration can be less than 1 x 1018cm-3. In this case, the light absorption layer 9 can be thicker in layer thickness than the multiplication layer 5. The p-type electric field control layer 7 can be a layer for generating a difference between the electric field strength applied to the light absorption layer 9 and the multiplication layer 5. The p-type contact layer 11 can be a semiconductor layer doped with p-type impurities. For example, the impurity concentration can be 1 x 1018cm-3or more. A p-side electrode 15 can be connected to the p-type contact layer 11. The p-side electrode 15 can be a substantially hole ring in a plan view, and an area inside the hole ring serves as a light receiving portion. When the substrate 1 is an n-type semiconductor, the n-type contact layer 3 need not be placed. 18 cm -3 16 cm -3 18 cm -3 The p-side electrode 15 can be a substantially hole ring in a plan view, and an area inside the hole ring serves as a light receiving portion. When the substrate 1 is an n-type semiconductor, the n-type contact layer 3 need not be placed.

[0022] Examples of the respective semiconductor layers are given below. The substrate 1 can be formed of InP doped with Fe. The n-type contact layer 3 can be formed of InP, the multiplication layer 5 can be formed of InAlAs, the electric field control layer 7 can be formed of InP, the light absorption layer 9 can be formed of InGaAs, and the p-type contact layer 11 can be formed of InGaAs. In this case, the band gap of the light absorption layer 9 can be set to support light absorption from 1250 nanometers (nm) to 1600 nm. These are merely examples, and other materials can be used, and the band gap can be set to support another wavelength band.

[0023] In the APD according to the first example embodiment, at least a region from the multiplication layer 5 to the p-type contact layer 11 can have a mesa structure. An insulating film 19 can be placed on the surface of the substrate 1 and on the side surface of the mesa structure. The insulating film 19 can also be placed on the upper portion of the mesa structure. The insulating film 19 on the upper portion of the mesa structure and the insulating film 19 placed on the side surface of the mesa structure can include different materials and can differ in thickness.

[0024] ​​The mesa structure can be circular in plan view. In the mesa structure in the first example embodiment of the present application, the multiplication layer 5 can be the largest in plan view, and the light-absorbing layer 9 can be the second largest. The p-type contact layer 11 can be the smallest. In other words, the mesa structure can be a three-stage structure of a lower stage Ml, an intermediate stage M2, and an upper stage M3. In the first example embodiment, the lower stage Ml can include the multiplication layer 5 and the electric field control layer 7. The intermediate stage M2 can include the light-absorbing layer 9. The upper stage M3 can include the p-type contact layer 11. In Figure 1 particular, the centers of the multiplication layer 5, the light-absorbing layer 9, and the p-type contact layer 11, which are circular in plan view, can be aligned. However, the centers of the multiplication layer 5, the light-absorbing layer 9, and the p-type contact layer 11 need not be aligned.

[0025] The effects of the first example embodiment will be described by using Comparative Examples 1, 2, and 3. Figure 3A Figure 3B Figure 3C are cross-sectional views for illustrating parts of the APD according to Comparative Examples 1, 2, and 3, respectively. In order to simplify the explanation, the insulating film and the electrode are not shown. In this case, the p-type contact layer 11 has the same plan view size between the first example embodiment and Comparative Examples 1, 2, and 3. The multiplication layer 5 and the electric field control layer 7 also have the same plan view size between the first example embodiment and Comparative Examples 2 and 3.

[0026] In Comparative Example 1, the mesa structure does not include a step. Comparative Example 2 is an example in which the mesa structure is a two-stage structure, and the multiplication layer 5 and the electric field control layer 7 are each larger than the light-absorbing layer 9 in the same manner as in the first example embodiment. Comparative Example 3 is an example in which the mesa structure is a two-stage structure, and the multiplication layer 5, the electric field control layer 7, and the light-absorbing layer 9 have the same size in plan view and are each larger than the p-type contact layer 11. In this case, the multiplication layer 5 is provided to have the same plan view size between the first example embodiment and Comparative Examples 2, 3. The phrase "the same plan view size" used here means a state in which the side surfaces of the mesa structure are substantially aligned, as illustrated in Figure 2 Figure 3A to Figure 3D

[0027] ​​​​In the APD, the strongest electric field can be applied to the multiplication layer 5, which can be an undoped layer. A second strongest electric field can be applied to the light-absorbing layer 9. Both layers can be depleted depending on the strength of the electric field and are operated to increase charge carriers and light absorption. The p-type contact layer 11 can be a high-concentration p-type semiconductor layer, and when a reverse bias voltage is applied to the p-side electrode 15, an electric field can be applied to the light-absorbing layer 9, the electric field control layer 7, and the multiplication layer 5 between the p-type contact layer 11 and the n-type contact layer 3. In this case, the electric field control layer 7 can be a high-concentration p-type layer, and the concentration of the electric field control layer 7 can be adjusted such that an appropriate electric field strength is applied to each of the light-absorbing layer 9 and the multiplication layer 5. In Comparative Example 1, the side surfaces of the p-type contact layer 11 and the other semiconductor layers are substantially aligned. Accordingly, the electric field strength distribution at the surface of the multiplication layer 5 on the side of the electric field control layer 7 is approximately uniform. However, the voltage at which breakdown occurs at the side surface of the mesa structure tends to be lower than the voltage at which breakdown occurs in the central portion. Therefore, when the applied voltage increases, breakdown occurs at the side surface of the multiplication layer 5, and the APD no longer operates properly.

[0028] In Comparative Example 2, the side surface of the p-type contact layer 11 is not aligned with the side surface of the multiplication layer 5. Furthermore, the side surface of the p-type contact layer 11 is substantially aligned with the side surface of the light-absorbing layer 9. An electric field can be applied to the light-absorbing layer 9, the electric field control layer 7, and the multiplication layer 5 in the same manner as in Comparative Example 1. The contact point between the side surface of the light-absorbing layer 9 and the electric field control layer 7 is defined here as "edge E1". The electric field in the electric field control layer 7 starts from edge E1 (as the starting point) and diffuses in a first direction D1 perpendicular to the stacking direction of the semiconductor multilayer to be applied to the multiplication layer 5. However, the electric field control layer 7 is thinner than the multiplication layer 5, so the electric field does not diffuse significantly. The electric field also diffuses in the multiplication layer 5 in the same manner. The diffusion of the electric field distribution is indicated by dashed lines. This is merely an illustrative image and does not indicate the exact diffusion of the electric field distribution. By increasing the distance between the side surface of the multiplication layer 5 and the edge E1, the electric field intensity at the side surface of the multiplication layer 5 can be reduced, making it lower compared to the central portion of the multiplication layer 5. For example, in Figure 3BIn Comparative Example 2, the electric field distribution does not reach the side surface of the multiplication layer 5, and no breakdown occurs at the side surface. That is, it can be possible to suppress breakdown by forming the multiplication layer 5 larger than the light absorbing layer 9 in the plan view, so that the electric field strength does not cause breakdown at the side surface of the multiplication layer 5. However, the structure of Comparative Example 2 causes another problem. The electric field distribution in the electric field control layer 7 is non-uniform in the first direction Dl, and is a distribution in which the electric field strength is locally high right under the edge El. This strong electric field right under the edge El is transmitted to the multiplication layer 5, and the electric field distribution in the multiplication layer 5 also exhibits a high electric field strength right under the edge El. Thus, a local breakdown can occur right under the edge El. Therefore, Comparative Example 2 can suppress breakdown at the side surface of the multiplication layer 5, but a breakdown can occur right under the edge El.

[0029] In Comparative Example 3, the mesa structure has two stages of the p-type contact layer 11 and other layers. The side surface of the light absorbing layer 9 is substantially aligned with the side surface of the electric field control layer 7 and the multiplication layer 5. The contact point between the side surface of the p-type contact layer 11 and the light absorbing layer 9 is defined here as "edge E2". The electric field distribution in the light absorbing layer 9 spreads in the first direction Dl from the edge E2 as a starting point. In the same manner as in Comparative Example 2, the image of the electric field distribution is indicated by a broken line. In the same manner as in Comparative Example 2, the electric field distribution does not reach the side surface of the multiplication layer 5, and no breakdown occurs at the side surface of the multiplication layer 5. In addition, there is no region corresponding to the region right under the edge El, and there is no position where the electric field strength is high enough to cause breakdown inside the multiplication layer 5. The electric field is also concentrated right under the edge E2. However, the light absorbing layer 9 is a relatively thick layer, and the effect of such a strong electric field on the multiplication layer 5 does not reach the degree that causes breakdown. Therefore, Comparative Example 3 can suppress breakdown from occurring in the multiplication layer 5. However, in terms of capacitance, Comparative Example 3 is disadvantageous in high-speed operation. The capacitance is proportional to the size of the region in which the electric field spreads in the plan view. As Figure 3C As illustrated in Comparative Example 3, the electric field spreads over a large region of the multiplication layer 5 from the edge E2. Therefore, the capacitance is large, thereby hindering high-speed operation.

[0030] In summary, the parasitic capacitance of Comparative Example 1 is the smallest, but a breakdown can occur at the side surface of the multiplication layer 5. Comparative Example 2 is superior to Comparative Example 3 in terms of parasitic capacitance, but a breakdown can occur inside the multiplication layer 5. Comparative Example 3 is less likely to have a breakdown in the multiplication layer 5, but cannot support high-speed operation in terms of parasitic capacitance.

[0031] For comparison with Comparative Examples 1, 2, and 3, in Comparative Example 4, the p-type contact layer 11 is formed to have a thickness of 0.5 μm, and the light absorbing layer 9 is formed to have a thickness of 0.5 μm. The other structures are the same as in Comparative Example 1. Figure 3DThe diagram illustrates a partial structure of an APD according to a first exemplary embodiment. In the APD according to the first exemplary embodiment, the planar dimensions of the p-type contact layer 11, the light absorption layer 9, and the multiplication layer 5 are different. That is, the side surfaces of the p-type contact layer 11, the light absorption layer 9, and the multiplication layer 5 are not aligned. In the same manner as in comparative examples 2 and 3, in... Figure 3D The dashed line is used to indicate the diffusion of the electric field distribution. For example... Figure 3D As illustrated, the electric field distribution in the light-absorbing layer 9 spreads along the first direction D1 starting from edge E2 (as the starting point), and the electric field is transmitted to the multiplication layer 5 via the electric field control layer 7. In the same manner as in Comparative Examples 2 and 3, the electric field distribution does not reach the side surface of the multiplication layer 5. Therefore, no breakdown occurs at the side surface of the multiplication layer 5. Furthermore, the electric field is concentrated directly below edge E1, making the electric field strength higher than in other areas. However, in Comparative Example 2, the electric field strength is lower than directly below edge E1, and no breakdown occurs inside the multiplication layer 5. The reason is as follows: Comparative Example 2 shows a state where the side surface of the p-type contact layer 11 and the side surface of the light-absorbing layer 9 are aligned, and a strong electric field is also applied to the side surface of the light-absorbing layer 9. Therefore, in Comparative Example 2, the electric field strength concentrated directly below edge E1 is higher. Meanwhile, in the first example embodiment, the side surface of the p-type contact layer 11 and the side surface of the light-absorbing layer 9 are not aligned. Figure 3D As indicated by the dashed line, the electric field diffuses from edge E2 toward the side surface of the light-absorbing layer 9, and the electric field strength decreases with diffusion. Even when the reduced electric field strength is concentrated directly below edge E1, it is not high enough to cause breakdown in the multiplication layer 5. As described above, in the first exemplary embodiment, breakdown in the multiplication layer 5 can be suppressed. Furthermore, in the first exemplary embodiment, compared to Comparative Example 3, the parasitic capacitance can be reduced to a lower level than in Comparative Example 3 because the planar size of the light-absorbing layer 9 is smaller than that of the multiplication layer 5 and the electric field diffusion in the multiplication layer 5 is smaller, thereby enabling high-speed operation. To further illustrate, the electric field diffusion in the light-absorbing layer 9 reaches the side surface of the light-absorbing layer 9 before reaching the interface between the light-absorbing layer 9 and the electric field control layer 7. Therefore, in the first exemplary embodiment, the electric field diffusion from edge E2 to the n-type contact layer 3 is narrower than in Comparative Example 3. The region where parasitic capacitance occurs is the region of electric field diffusion. In the first example embodiment, the multiplication layer 5, which contributes to the generation of parasitic capacitance, is larger than the p-type contact layer 11 and the light-absorbing layer 9 in the planar view, but the electric field does not diffuse over the entire region, thus suppressing the increase of parasitic capacitance. With the configuration mentioned above, an APD that achieves excellent high-speed operation and suppresses breakdown is realized.

[0032] The light-absorbing layer 9 is an important layer that determines the characteristics of the APD, and has a desired size in order to achieve both high-speed operation and a large light-receiving diameter. A larger surface area in the plan view is advantageous in terms of the light-receiving diameter, but the capacitance becomes large, which is not advantageous for high-speed operation. In contrast, a smaller surface area is advantageous in high-speed operation, but is not advantageous in terms of the light-receiving diameter, and optical alignment becomes more difficult. In addition to this point, the size and thickness of the light-absorbing layer 9 are determined in consideration of suppression of breakdown in the multiplication layer 5. For example, the plan view size (here, since the mesa structure is circular, this size is the diameter) of the light-absorbing layer 9 that supports an APD of 25 gigabits per second (Gbps) can preferably be about 20 micrometers (pm). Meanwhile, from the point of view of suppressing breakdown, considering the diffusion of the electric field, it can be desirable for the diameter of the p-type contact layer 11 to be 1 pm or more smaller than the diameter of the light-absorbing layer 9, and for the diameter of the multiplication layer 5 to be 1 pm or more larger than the diameter of the light-absorbing layer 9. In addition, considering manufacturing variations, the diameter of the multiplication layer 5 can preferably be 2 pm or more larger than the diameter of the light-absorbing layer 9. Furthermore, the diameter of the p-type contact layer 11 can preferably be 2 pm or more smaller than the diameter of the light-absorbing layer 9. Furthermore, as illustrated in FIG. 10B, the diameter of the light-absorbing layer 9 can be determined so that the diffusion of the electric field in the light-absorbing layer 9 reaches the side surface of the light-absorbing layer 9 before reaching the interface between the light-absorbing layer 9 and the electric field control layer 7. Figure 3D

[0033] For simplicity of description, the side surface of the mesa structure is illustrated as a vertical surface, but it is not limited thereto. For example, the side surface of the mesa structure can be an inclined surface. When the side surface of the mesa structure is, for example, a positive taper, strictly speaking, the multiplication layer 5 and the electric field control layer 7 cannot be said to have the same plan view size (the multiplication layer 5 can be slightly larger). However, in the present application, as long as the surface of the lower semiconductor layer is not exposed at the interface between the two semiconductor layers (i.e., the side surfaces of the two layers are aligned), the two semiconductor layers are defined as having the same size. In contrast, when the surface of the electric field control layer 7 is exposed from the light-absorbing layer 9 (seen from the interface between the electric field control layer 7 and the light-absorbing layer 9), the two semiconductor layers are defined as having different plan view sizes (i.e., the side surfaces of the two layers are not aligned). Another layer can be included in each stage of the mesa structure. For example, in the upper stage M3, the p-type contact layer 11 can be formed of multiple layers.

[0034] Furthermore, in the example mentioned above, the mesa structure has a circular shape in the plan view, but is not limited thereto. For example, the mesa structure can have an elliptical or polygonal shape.

[0035] Figure 4 ​This is a schematic cross-sectional view of an APD according to a second exemplary embodiment of the present invention. The second exemplary embodiment differs from the first exemplary embodiment in that the light-absorbing layer 209 has a two-level structure. The structure of the other parts in the second exemplary embodiment is the same as that in the first exemplary embodiment.

[0036] In the second example embodiment, the light-absorbing layer 209 may be formed of a first light-absorbing layer 9a and a second light-absorbing layer 9b. The first light-absorbing layer 9a and the second light-absorbing layer 9b may have the same planar dimensions (their side surfaces may be substantially aligned). The first light-absorbing layer 9a may be an InGaAs layer, which may be an undoped layer intentionally undoped of impurities. The second light-absorbing layer 9b may be a low-concentration p-type InGaAs layer doped with p-type impurities, wherein the concentration of the p-type impurities is low enough to form a depletion layer. "Low enough to form a depletion layer" as used herein refers to, for example, an impurity concentration less than 1 × 10⁻⁶. 17 cm -3 More preferably, the impurity concentration of the second light-absorbing layer 9b is 0.5 × 10⁻⁶. 17 cm -3 Or even lower. Semiconductor materials are just one example.

[0037] The APD according to the first exemplary embodiment suppresses the occurrence of breakdown in the multiplication layer 5. However, the electric field is also concentrated below the edge E2 (which is the contact point between the side surface of the p-type contact layer 11 and the light-absorbing layer 9), and breakdown may occur in the light-absorbing layer 9. The APD according to the second exemplary embodiment suppresses the occurrence of breakdown in the light-absorbing layer 9.

[0038] When a low-concentration p-type semiconductor layer (second light-absorbing layer 9b) is sandwiched between the p-type contact layer 11 and the undoped first light-absorbing layer 9a, the location with the highest electric field intensity in the light-absorbing layer 209 can be the interface between the first light-absorbing layer 9a and the second light-absorbing layer 9b. Therefore, the electric field intensity at the interface between the second light-absorbing layer 9b and the p-type contact layer 11 can be lower than the electric field intensity at the interface between the first light-absorbing layer 9a and the second light-absorbing layer 9b. The electric field can be concentrated in the region directly below edge E2, and the electric field intensity can be higher than the electric field intensity near the center of the light-absorbing layer 209. However, the electric field intensity at the interface between the p-type contact layer 11 and the second light-absorbing layer 9b is inherently low, so even if the electric field is concentrated in the region directly below edge E2, it will not reach the breakdown voltage, thereby suppressing breakdown in the light-absorbing layer 209.

[0039] Figure 5is a schematic cross-sectional view of an APD according to a modified example of the second example embodiment. This modified example differs from the second example embodiment in that an etching stopper layer 210 is placed between the second light-absorbing layer 9b and the p-type contact layer 11. In this case, the etching stopper layer 210 can have the same plan view size as the second light-absorbing layer 9b. That is, the etching stopper layer 210 can be placed in the middle stage M2 of the mesa structure. Specifically, the etching stopper layer 210 can be the uppermost layer of the middle stage M2, and can be formed of a different material from the lowermost layer of the upper stage M3 (in this case, the p-type contact layer 11). For example, when the p-type contact layer 11 is formed of InGaAs, the etching stopper layer 210 can be formed of InGaAsP. The etching stopper layer 210 can also be formed of InGaAlAs instead. In addition, the etching stopper layer 210 can be a p-type semiconductor layer.

[0040] By performing multiple etchings after epitaxially growing the semiconductor multilayer on the substrate 1, a mesa structure having multiple stages can be formed. For example, the upper stage M3 can be formed by masking the region that is finally left as the upper stage M3 and removing the other regions. When the etching stopper layer 210 is placed, the middle stage M2 can be prevented from being etched together when the upper stage M3 is formed, and thus a mesa structure having multiple stages can be stably formed. The etching stopper layer 210 can be placed in the first example embodiment.

[0041] The electric field control layer 7 can also function as an etching stopper layer. The electric field control layer 7 can be the uppermost layer of the lower stage M1. Thus, when the uppermost layer of the lower stage M1 and the lowermost layer of the middle stage M2 are formed of different materials, the uppermost layer of the lower stage M1 functions as an etching stopper layer when the middle stage M2 is formed. In this case, the electric field control layer 7 (the uppermost layer of the lower stage M1) can be formed of InP, while the lowermost layer of the middle stage M2 can be the first light-absorbing layer 9a formed of InGaAs. These two layers are formed of different materials, and thus the electric field control layer 7 functions as an etching stopper layer when the middle stage M2 is formed, and the middle stage M2 is stably formed.

[0042] Even if the etching stopper layer is not placed, a mesa structure having multiple stages can be formed by controlling the etching time. Thus, a mesa structure having three stages can also be formed in the first example embodiment. Thus, the electric field control layer 7 can be included in the middle stage M2.

[0043] Figure 6is a schematic cross-sectional view of an APD according to a third example embodiment of the present application. The third example embodiment differs from the second example embodiment in that an electron transport layer 320 and an electric field weakening layer 330 are placed between the n-type contact layer 3 and the multiplication layer 5. In this case, the electron transport layer 320 and the electric field weakening layer 330 have the same plan view size as the multiplication layer 5 (i.e., the side surfaces of the two layers are substantially aligned). That is, the electron transport layer 320 and the electric field weakening layer 330 can be placed in the lower stage Ml of the mesa structure.

[0044] The electron transport layer 320 can be an undoped layer, and can be a layer having a larger band gap than the band gap of the light absorption layer 209. Specifically, the electron transport layer 320 can be a semiconductor layer whose band gap does not absorb light of a wavelength to be received. Meanwhile, the electric field weakening layer 330 can be a high-concentration n-type semiconductor layer, and can be a layer for generating a difference in electric field strength between the electron transport layer 320 and the multiplication layer 5. The electron transport layer can be an undoped layer, and can be depleted during APD operation. This has the effect of reducing the capacitance of the entire APD.

[0045] Also, in the third example embodiment, an APD is implemented that suppresses the occurrence of breakdown at the side surface of the multiplication layer 5 and the light absorption layer 209 and inside thereof and supports high-speed operation, as mentioned above. Further, the electron transport layer 320 and the electric field weakening layer 330 can be placed in the APD described in the first example embodiment.

[0046] Figure 7 is a schematic view of an avalanche photodiode (APD) according to a fourth example embodiment of the present application. The APD of the fourth example embodiment can be back-illuminated, and Figure 7 is a top view, while Figure 8 is a cross-sectional view schematically illustrating a cross section taken along the VIII-VIII line of Figure 7

[0047] The semiconductor multilayer of the APD according to the fourth example embodiment can be the same as in the first example embodiment. The main difference between the two is that a lens 450 can be formed on the back surface of the substrate 401. In addition, the shapes of the n-side electrode 417 and the p-side electrode 415 are different. Furthermore, in addition to the first mesa structure 460 having a light-receiving function, a second mesa structure 470 on which a portion of the n-side electrode 417 is placed is provided.

[0048] ​The lens 450 formed on the back surface of the substrate 401 can have an effect of concentrating incident light on the light absorption layer 9 and improving light sensitivity. The lens 450 can be omitted. The multilayer structure of the first mesa structure 460 can be the same as the multilayer structure of the mesa structure in the first example embodiment, and occurrence of breakdown as described above can be suppressed. The reflective film 440 formed of an insulating film can be placed on the upper surface of the p-type contact layer 11. In addition, the circular p-side electrode 415 can be placed on the uppermost portion of the first mesa structure 460. The insulating film 419 can be placed on the side surface of the first mesa structure 460 and the second mesa structure 470 described later. The reflective film 440 and the insulating film 419 can be formed of the same material.

[0049] The APD according to the fourth example embodiment can include the second mesa structure 470. The semiconductor multilayer included in the second mesa structure 470 can be the same as the semiconductor multilayer of the first mesa structure 460. The second mesa structure 470 can be a mesa structure that does not have a circular step structure in a plan view. The same step structure as the first mesa structure 460 can be formed. The n-side electrode 417 can be placed on the upper surface of the second mesa structure 470. The n-side electrode 417 can be connected to the n-type contact layer 3 via the side surface of the second mesa structure 470.

[0050] As described above, all the mesa structures formed in the APD do not need to have the step structure. As long as the mesa structure having a light receiving function has such a step structure as described above, the effect of the present application can be obtained.

[0051] The present invention provides improvements in high-speed operation and reliability in an avalanche photodiode having a mesa structure. The improvements are achieved by the mesa structure including a multiplication layer, a light absorption layer, and a contact layer, in which, in a plan view, the multiplication layer is larger than the light absorption layer, and the light absorption layer is larger than the contact layer. In other words, in a cross-sectional view of the mesa structure, the mesa structure has a three-stage structure, i.e., a lower stage including the multiplication layer, an intermediate stage including the light absorption layer, and an upper stage including the contact layer. Side surfaces of the multiplication layer, the light absorption layer, and the contact layer are not flush with each other. An electric field control layer can be placed between the multiplication layer and the light absorption layer. The electric field control layer is formed of a material different from that of the light absorption layer. The electric field control layer is included in the lower stage or the intermediate stage of the mesa structure. An uppermost layer of the intermediate stage of the mesa structure can include an etching stop layer. The etching stop layer is formed of a material different from that of a lowermost layer of the upper stage. The light absorption layer can have a two-stage structure, i.e., an undoped absorption layer placed on the multiplication layer side and a low-concentration absorption layer placed on the contact layer side. In this case, when a voltage is applied to the low-concentration absorption layer, the low-concentration absorption layer is depleted. An electron transport layer and an electric field weakening layer can be included between the multiplication layer and the substrate. The electron transport layer and the electric field weakening layer are included in the lower stage of the mesa structure. The avalanche photodiode can be top-illuminated or back-illuminated. In the case of back-illumination, a lens can be formed on a surface of the substrate opposite to a surface on which the mesa structure is formed. The avalanche photodiode supports light of 1250 nm to 1600 nm. The mesa structure has a circular shape in a plan view, and a diameter of the multiplication layer is 1 pm or more larger than a diameter of the light absorption layer in the plan view. The diameter of the light absorption layer is 1 pm or more larger than a diameter of the p-type contact layer in the plan view.

[0052] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit implementations to the precise forms disclosed. Modifications and variations can be made in light of the above disclosure or can be acquired from practice of the implementations. Additionally, other embodiments can be implemented that are within the scope of the claims.

[0053] Even if a particular combination is recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various embodiments. Indeed, many of the features can be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below can directly depend on only one claim, the disclosure of various embodiments includes each dependent claim in combination with every other claim in the claim set. As used in this document, the phrase“at least one of’ followed by a list of two or more items means that any combination of those items can be used, including single members. For example, “at least one of a, b, or c” means that“a” alone, “b” alone, “c” alone, “a-b,” “a-c,” “b-c,” and“a-b-c” are all possible.

[0054] No element, act or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items, and can be used interchangeably with “one or more.” Furthermore, as used herein, the article “the” is intended to include one or more items referenced by the article “the” and can be used interchangeably with “the one or more.” Also, as used herein, the term “set” is intended to include one or more items (for example, related items, unrelated items, or a combination of related and unrelated items) and can be used interchangeably with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. Also, as used herein, the term “or” is intended to mean an inclusive “or” and can be used interchangeably with “and / or,” unless explicitly stated otherwise (for example, if used in a list of items “or” means at least one of the items but not more than one). Moreover, spatial or directional terms, for example “below,” “lower,” “above,” “upper,” and the like can be used herein for ease of describing one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. Spatial and directional terms are used with the intent to be interpreted in the context of the particular application in which the application is utilized. The application can be implemented in either a horizontal or vertical orientation, or a orientation that is different than that depicted in the figures, and the spatial and directional descriptions used herein can similarly be interpreted.

Claims

1. An avalanche photodiode, comprising: Substrate; An n-type contact layer is formed above the substrate; A multiplication layer is formed above the n-type contact layer; A light-absorbing layer is formed above the multiplication layer; as well as A p-type contact layer is formed above the light-absorbing layer. The multiplication layer, the light absorption layer, and the p-type contact layer form a mesa structure. In the planar view, the multiplication layer is larger than the light-absorbing layer, and In the plan view, the light absorption layer is larger than the p-type contact layer.

2. The avalanche photodiode according to claim 1, The light-absorbing layer comprises a first light-absorbing layer and a second light-absorbing layer, wherein the first light-absorbing layer is disposed on the multiplication layer side and the second light-absorbing layer is disposed on the p-type contact layer side. The first light-absorbing layer includes an undoped layer, and The second light-absorbing layer includes a low-concentration p-type layer.

3. The avalanche photodiode according to claim 2, wherein the second light-absorbing layer is depleted when a voltage is applied to the second light-absorbing layer.

4. The avalanche photodiode according to claim 1 further includes an electric field control layer between the multiplication layer and the light absorption layer.

5. The avalanche photodiode according to claim 4, wherein in a plan view, the size of the electric field control layer is the same as the size of the multiplication layer.

6. The avalanche photodiode according to claim 5, wherein the electric field control layer is formed of a material different from the material of the light absorption layer.

7. The avalanche photodiode according to claim 1 further includes an etch stop layer between the light absorption layer and the p-type contact layer.

8. The avalanche photodiode of claim 7, wherein, in a plan view, the size of the etch stop layer is the same as the size of the light absorption layer.

9. The avalanche photodiode of claim 8, wherein the etch stop layer is formed of a material different from the material of the p-type contact layer.

10. The avalanche photodiode according to claim 1, further comprising an electron transport layer and an electric field weakening layer between the multiplication layer and the substrate, wherein the electron transport layer is disposed on the substrate side and the electric field weakening layer is disposed on the multiplication layer side.

11. The avalanche photodiode according to claim 1, further comprising: The p-side electrode is in contact with the p-type contact layer; as well as The n-side electrode is in contact with the n-type contact layer.

12. The avalanche photodiode according to claim 11, The mesa structure includes a first mesa structure having an uppermost surface on which the p-side electrode is placed, and The avalanche photodiode further includes a second mesa structure, which includes a semiconductor multilayer identical to the semiconductor multilayer of the first mesa structure and an uppermost surface on which a portion of the n-side electrode is placed.

13. The avalanche photodiode of claim 12, wherein the second mesa structure has a stepless side surface in a cross-sectional view.

14. The avalanche photodiode of claim 1, wherein the avalanche photodiode is top-illuminated, wherein light is incident from the p-type contact layer side.

15. The avalanche photodiode of claim 1, wherein the avalanche photodiode is back-illuminated, wherein light is incident from the substrate side.

16. The avalanche photodiode of claim 15, wherein the substrate has a lens formed on the surface of the substrate on the light incident side.

17. The avalanche photodiode according to claim 1, The platform structure described herein has a circular shape in the plan view. In the planar view, the diameter of the multiplication layer is 1 μm or more larger than the diameter of the light-absorbing layer, and In the plan view, the diameter of the light-absorbing layer is 1 μm or more larger than the diameter of the p-type contact layer.

18. The avalanche photodiode of claim 4, wherein the diffusion of the electric field applied to the mesa structure reaches the side surface of the light-absorbing layer before reaching the interface between the light-absorbing layer and the electric field control layer.

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