Photoelectric synapse transistor based on graphdiyne / MoS2 Van der Waals heterostructure and preparation method thereof

Abstract

The invention relates to a photoelectric synapse transistor based on a graphdiyne / MoS2 Van der Waals heterostructure and a preparation method thereof. The structure of the transistor comprises a bottom gate electrode / gate dielectric layer, a GDY / MoS2 heterogeneous layer and a metal source drain electrode from bottom to top. According to the GDY / MoS2 heterogeneous layer, the thickness of GDY ranges from 4 nm to 5 nm, the thickness of MoS2 ranges from 2 nm to 3 nm, and the ratio of GDY to MoS2 is (1.3-2.5): 1. The charge capture strategy based on the intrinsic material characteristics has important application value for development of a neuromorphic visual system with high energy efficiency and biological credibility.

Description

TECHNICAL FIELD

[0001] The application relates to the field of semiconductor devices, in particular to a photoelectric synapse transistor based on a graphdiyne / MoS2 van der Waals heterostructure and a preparation method thereof. BACKGROUND

[0002] A visual neural morphic device with a synapse function is crucial for processing exponentially growing complex visual information due to its ability to capture, store and process light signals from the environment. A two-dimensional semiconductor such as a transition metal dichalcogenide (TMD) with an atomic-level thin layer can significantly enhance the electrostatic control of the channel due to the characteristics of a clean interface formed by the surface without dangling bonds and the atomic-level precise stacking, and thus exhibits significant advantages in the construction of multifunctional heterostructures and the miniaturization of reconfigurable electronic components. In addition, a memory window (MW) as a core indicator for measuring the charge storage capacity of a photoelectric synapse device directly determines the dynamic range of synapse weight updating and the information retention capability. The traditional strategy for improving the memory window mainly relies on interface passivation engineering and defect state regulation. However, the use of intrinsic defects or artificially introduced deep level traps to achieve charge trapping faces the bottlenecks of complex implementation process, uncontrollable defect density and poor long-term stability.

[0003] For example, Chinese invention patent CN117769348A discloses a VO2 / MoO3 heterojunction artificial photoelectric synapse device and a preparation method thereof. The VO2 / MoO3 heterojunction artificial photoelectric synapse device is prepared by using a magnetron sputtering method, and the bionic synapse function is realized by using the oxygen vacancy defects of the VO2 / MoO3 material itself. The photoelectric synapse device exhibits short-term synaptic plasticity and long-term synaptic plasticity function under electrical pulse stimulation; Chinese invention patent CN119836018A discloses a bias voltage regulated MoS2 / PbS heterojunction photoelectric device. The MoS2 / PbS heterojunction artificial photoelectric synapse device is prepared by using a hydrothermal method, and the photoelectric synapse function is realized by modulating the interface defects. However, the above-mentioned synapse devices use material defects and interface defects to realize the synapse function, and the uncontrollable defect density leads to poor device stability and complex process, which cannot meet the development needs of the current photoelectric synapse device. SUMMARY

[0004] In view of the deficiencies of the prior art, the application provides a photoelectric synapse transistor based on a graphdiyne / MoS2 van der Waals heterostructure and a preparation method thereof. The transistor uses a GDY / MoS2 hetero-layer as a channel layer, and uses the unique sp-sp 2 hybridization and rich carrier interaction sites provided by the acetylenic bond network in the GDY thin film to realize a nearly 10-fold improvement in the memory window of the transistor. The photoelectric synapse realizes a 5x10 7The super-large on-off ratio and the excellent cycle durability of 70 transfer curve cycles, and the on-off ratio and storage window are not degraded after storing in air environment for 4 weeks. In addition, the device successfully simulates various biological synaptic functions such as excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), short-term potentiation (STP) to long-term potentiation (LTP) and pulse number-dependent plasticity (SNDP). The application based on the charge trapping strategy of intrinsic material characteristics has important application value for the development of neuromorphic visual system with high energy efficiency and biological credibility.

[0005] The technical scheme of the application is:

[0006] A photoelectric synapse transistor based on a graphdiyne / MoS2 van der Waals heterostructure, characterized in that the structure of the transistor is from bottom to top, a bottom gate electrode / gate dielectric layer, a GDY / MoS2 hetero layer and a metal source-drain electrode.

[0007] The GDY / MoS2 hetero layer, wherein the thickness of GDY is 4-5 nm, the thickness of MoS2 is 2-3 nm, and the ratio of GDY to MoS2 is 1.3-2.5:1.

[0008] The bottom gate electrode / gate dielectric layer is Si / SiO2, wherein the thickness of the gate dielectric layer SiO2 is 100-300 nm.

[0009] The metal source-drain electrode is chromium, gold, platinum or palladium, and the thickness is 50-100 nm.

[0010] The preparation method of the photoelectric synapse transistor device based on the graphdiyne / MoS2 van der Waals heterostructure comprises the following steps:

[0011] 1) The bottom gate electrode / gate dielectric layer is sequentially cleaned with deionized water, acetone and anhydrous ethanol for 10-30 minutes, and then the surface is blown dry with nitrogen (N2) for standby;

[0012] 2) Gold Mark is made on the bottom gate electrode / gate dielectric layer by using standard electron beam lithography (EBL), thermal evaporation and peeling process;

[0013] 3) A Cu thin film with a thickness of about 10-50 nm is deposited on the bottom gate electrode / gate dielectric layer by using thermal evaporation process;

[0014] 4) A 3-10 nm GDY thin film is grown by chemical growth method;

[0015] 5) etching the copper foil substrate with the GDY film grown thereon by wet etching, washing with deionized water and drying to obtain the GDY film, wherein the etching time of the copper foil is 2-6 hours, the etching solution is an aqueous solution of ammonium persulfate ((NH4)2S2O8) with a concentration of 0.1-0.3 mol / L;

[0016] 6) transferring the GDY film to the bottom gate electrode / gate dielectric layer with a gold Mark by using a wet transfer process;

[0017] 7) peeling off the MoS2 multilayer nanosheet crystal from the MoS2 crystal using a transparent tape and transferring it to polydimethylsiloxane (PDMS), and using a transfer platform to transfer the nanosheet on the PDMS to the surface of the prepared Si / SiO2 / GDY sample to form a GDY / MoS2 heterostructure;

[0018] 8) patterning the electrode by using a standard EBL process, and then preparing a source-drain electrode by a thermal evaporation and peeling process;

[0019] wherein the thermal evaporation rate involved above is The chamber vacuum degree is 10 -3 ~ 10 -4 Pa.

[0020] The substantial features of the present application are:

[0021] The graphdiyne (GDY) adopted in the present application is a new carbon allotrope, which has a unique sp-sp 2 conjugated backbone and alkyne bond network, and can provide rich two-dimensional distributed charge carrier interaction sites; therefore, the heterostructure based on GDY and TMDs adopted in the present application has excellent interface matching characteristics, and compared with the random distribution characteristics of the interface defect states of the traditional heterostructure, the carrier trapping efficiency can be improved.

[0022] 1) constructing a GDY / MoS2 van der Waals heterostructure, breaking through the traditional two-dimensional material stacking mode, and forming a strong interface coupling between the unique sp-sp 2 conjugated conjugated backbone and alkyne bond network of GDY and MoS2, providing rich two-dimensional distributed charge carrier interaction sites for trapping carriers and realizing quantum-level optimization of the carrier transmission channel;

[0023] 2) using the two-dimensional nanopore structure formed by the alkyne bond network in the GDY film to create high-density carrier interaction sites, so that the memory window is improved by 10 times compared with the pure MoS2 device, and the storage capacity bottleneck of two-dimensional materials is broken through.

[0024] 3) achieving 5*10 7With an ultra-high on / off ratio, the transfer characteristic curve showed almost no drift after 70 cycles of testing, and key parameters stabilized after 28 days of storage in an air environment.

[0025] 4) Successfully simulated various biological synaptic functions, including double-pulse facilitation (PPF), excitatory postsynaptic current (EPSC), short-term to long-term enhancement (STP-LTP), and pulse number-dependent plasticity (SNDP).

[0026] The beneficial effects of this invention are as follows:

[0027] 1. The method for fabricating photoelectric synaptic transistors based on GDY / MoS2 van der Waals heterojunctions provided by this invention achieves simplified processes and breakthroughs in yield through innovative copper film catalysis-transfer technology and molecular-level planar interface engineering. This method can complete the construction of heterostructures without relying on complex vacuum equipment, has broad material applicability, and a simple process. The fabricated devices exhibit excellent cycle durability and air stability, providing a highly stable solution for the development of visual neuromorphic electronics.

[0028] 2. The GDY / MoS2 heterojunction photosynaptic transistor prepared in this invention exhibits a 5×10⁻⁶ Ω·cm² pattern. 7 It boasts an ultra-high on / off ratio and exceptional cycle durability with a 70-cycle transfer curve, as well as outstanding air stability.

[0029] 3. GDY's unique alkyne bond network serves as a natural carrier regulation layer, enabling the device to simultaneously possess the ability to simulate photocurrent memristor behavior and biological synaptic functions, successfully mimicking various neuromorphic characteristics such as PPF, EPSC, STP-LTP, and SNDP. This provides a breakthrough technological path for IoT edge computing and brain-like vision systems. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of the GDY / MoS2 heterojunction photosynaptic transistor in this invention;

[0031] Figure 2 The image shows a projection electron microscope (TEM) image of the GDY / MoS2 heterojunction obtained in Example 1.

[0032] Figure 3 The Raman spectra of the photosynaptic transistors GDY and MoS2 obtained in Example 1 are shown; wherein, Figure 3 a is the Raman spectrum of GDY. Figure 3 b is the Raman spectrum of MoS2;

[0033] Figure 4 A comparison of transfer curves with and without GDY transistors;

[0034] Figure 5The image shows the 70-time transfer curve of the photosynaptic transistor obtained in Example 1.

[0035] Figure 6 The air stability with and without GDY transistor storage window and on / off ratio obtained in Example 1;

[0036] Figure 7 The transfer characteristic curves of the photosynaptic transistor obtained in Example 1 under different drain bias voltages are shown.

[0037] Figure 8 The EPSC behavior of the photosynaptic transistor obtained in Example 1 under light pulse stimulation;

[0038] Figure 9 The photosynaptic transistor obtained in Example 1 exhibits PPF behavior under paired pulse stimulation.

[0039] Figure 10 This is a simulation of the SNDP behavior of the photosynaptic transistor obtained in Example 1; Detailed Implementation

[0040] The present invention will be described below with reference to examples, but this does not limit the invention to the scope of the examples.

[0041] A schematic diagram of the photosynaptic transistor device based on the GDY / MoS2 van der Waals heterostructure in this invention is shown below. Figure 1 As shown, the structure of the device, from bottom to top, consists of a bottom gate electrode, a gate dielectric layer, a GDY layer, a MoS2 layer, and metal source / drain electrodes.

[0042] Example 1:

[0043] 1) A 1×1 cm bottom gate electrode / gate dielectric layer (i.e., substrate) was ultrasonically cleaned sequentially with deionized water, acetone, and anhydrous ethanol for 30 minutes each, and then dried with N2. The bottom gate electrode / gate dielectric layer was a commercially available Si / SiO2 substrate with a SiO2 thickness of 150 nm;

[0044] 2) Gold-plated positioning marks (gold marks) are fabricated on the substrate obtained in the previous step using standard EBL, thermal evaporation and stripping processes. The purpose is to facilitate the positioning of source and drain electrodes when fabricating heterojunctions.

[0045] 3) A Cu thin film with a thickness of approximately 30 nm was deposited on another Si / SiO2 substrate using a thermal evaporation process, with a deposition rate of [missing information].

[0046] 4) The prepared Cu film was immersed in 200 mL of chloroform solvent under argon protection at 25°C. Then 1 mL of pyridine was added to the solvent. Subsequently, 20 mL of hexaethylbenzene solution with a concentration of 5 mol / L was added dropwise to the reaction system for 10 hours. After the synthesis of the graphdiyne was completed, the copper foil with GDY film was washed with acetone and dried with nitrogen. The copper foil with GDY film was heated at 50°C under nitrogen atmosphere for 2 hours.

[0047] 5) The copper foil with GDY film was cut into a square piece with a side length of 1 cm and placed in an aqueous solution of (NH4)2S2O8 with a concentration of 0.1 mol / L for 12 hours. After the etching of the copper foil was completed, the GDY film floated on the surface of the solution. Then the GDY film was cleaned twice with deionized water to remove excess ammonium persulfate salt.

[0048] 6) The GDY film was taken out with a bottom gate electrode / gate dielectric layer containing gold Marks and naturally dried to obtain a GDY layer with a thickness of about 5 nm attached to the bottom gate electrode / gate dielectric layer.

[0049] 7) MoS2 multi-layer nanosheet crystals with a size of about 20 x 20 μm and a thickness of about 2.4 nm were peeled off from a commercially available bulk MoS2 crystal using transparent tape and transferred to polydimethylsiloxane (PDMS). The nanosheet on the PDMS was transferred to the surface of the prepared Si / SiO2 / GDY sample using an E1-G type transfer platform (purchased from Mai Ta Optoelectronics Co., Ltd.) to form a GDY / MoS2 heterostructure.

[0050] 8) A Cr / Au electrode was patterned on the Si / SiO2 / GDY / MoS2 using a standard EBL process, and then a Cr / Au (thickness: 8 nm / 60 nm; electrode spacing distance: 5 μm) source-drain electrode was prepared by thermal evaporation and peeling process to form a photoelectric synaptic transistor with a structure of Si / SiO2 / GDY / MoS2 / Cr / Au.

[0051] 9) FEI Tecnai G2 F20 ST field emission transmission electron microscopy was used to perform cross-sectional transmission electron microscopy imaging of the GDY / MoS2 heterostructure.

[0052] The experimental results are analyzed as follows:

[0053] Figure 2 For the high-resolution TEM cross-sectional image of the GDY / MoS2 heterostructure, the thicknesses of the GDY and MoS2 layers were observed to be 4.5 nm and 2.4 nm, respectively. The interface was clear, flat and smooth, which confirmed that a uniform, flat and clean interface was obtained during the transfer process.

[0054] Example 2:

[0055] Other steps are the same as example 1. The difference is that step 8 Si / SiO2 / GDY / MoS2 is replaced by Si / SiO2 / MoS2; step 9 FEI Tecnai G2 F20 ST field emission transmission electron microscope is replaced by JEOL 4200A-SCS semiconductor analyzer;

[0056] 1) The Cr / Au electrode was patterned on Si / SiO2 / MoS2 using the standard EBL process, and then the Cr / Au (thickness: 8 nm / 60 nm; electrode width: 5 μm) source-drain electrode was prepared by thermal evaporation and peeling process to form a phototransistor with the structure of Si / SiO2 / MoS2 / Cr / Au, which served as a control group to prove the role of GDY in this device structure;

[0057] The performance of the obtained device is as follows:

[0058] Figure 4 To compare the transfer curves of the GDY transistor with and without GDY. The transfer curve of the device was tested by the JEOL 4200A-SCS semiconductor analyzer, and the memory window (MW) of the transistor based on the GDY / MoS2 heterostructure was improved by nearly 10 times, reaching 8 V, compared with the field effect transistor based on MoS2 (MW≈0.8 V). The improvement of MW is due to the unique sp-sp hybridization and alkyne bond in GDY film, which provides rich carrier interaction sites to improve the charge storage capacity of the device. 2 The improvement of MW not only has important significance for the study of charge trapping mechanism in GDY / MoS2 heterostructure, but also has important significance for the actual non-volatile memory application;

[0059] Example 3:

[0060] Other steps are the same as example 1. The difference is that step 9 FEI Tecnai G2 F20 ST field emission transmission electron microscope is replaced by confocal Raman microscope system and Olympus inverted optical microscope and JEOL 4200A-SCS semiconductor analyzer;

[0061] 1) Raman spectrum analysis was performed using confocal Raman microscope system and Olympus inverted optical microscope;

[0062] The performance of the obtained material is as follows:

[0063] Figure 3 a The Raman spectrum characteristic peak of GDY is located at 1388 cm -1 (D band), 1565 cm -1 (G band) corresponding to the in-phase stretching vibration and shear vibration of sp 2 carbon in benzene. Figure 3b is the Raman spectrum of MoS2, the characteristic peak is located at about 380 cm -1 (E 2 g mode) and 405 cm -1 (A 1 g mode) are typical Raman vibration modes of MoS2 crystal structure. The above conclusion further verifies the existence of GDY and MoS2 in the device;

[0064] 2) The GDY / MoS2 heterostructure-based optoelectronic synapse transistor device was tested at room temperature using JTH 4200A-SCS semiconductor analyzer;

[0065] The experimental results are analyzed as follows:

[0066] Figure 5 The 70-cycle repeatability test was carried out based on the GDY / MoS2 heterostructure transistor transfer curve, and all the transfer curves of the cycles remained highly consistent, indicating that the device has excellent cycle stability.

[0067] Figure 6 The air stability of the transistor storage window and the on-off ratio with or without GDY transistor. Every 7 days, the MW and on-off ratio of the transistor device were counted, and it was observed that after 4 weeks, the device had no performance degradation without any packaging, indicating that the device has excellent environmental stability;

[0068] Figure 7 The transfer characteristic curve of the optoelectronic synapse transistor device under different drain bias voltages. Under a drain bias voltage of 1V, the device achieved an ultra-large on-off ratio of 5x10 7 , which laid a foundation for high-performance devices for future visual neural devices;

[0069] Figure 8 The EPSC behavior of the optoelectronic synapse transistor device under light pulse stimulation. Under a drain bias voltage of 1V, a single light pulse (λ = 430nm, pulse width Δt = 500ms) stimulation, the device generated a photocurrent response curve, and the light and dark backgrounds were light and dark stages. It can be seen that the photocurrent presents a transient peak in the initial stage of light, and then presents the excitatory postsynaptic current (EPSC) phenomenon of biological synapse, which indicates that there is a competition process of carrier trapping and de-trapping in the GDY / MoS2 heterostructure;

[0070] Figure 9The PPF behavior of the optoelectronic synapse transistor under paired pulse stimulation is shown in the figure, and the current response of the device is obtained by applying double pulses (pulse width = 500 ms, interval = 1 s) to the device. When the pulse interval is shortened, the memory enhancement effect is more and more obvious, and this characteristic shows high similarity with the synaptic plasticity of the biological nervous system, thereby providing important physical mechanism support for constructing a brain-like computing device.

[0071] Figure 10 The simulation of the SNDP behavior of the optoelectronic synapse transistor is shown in the figure. Under the stimulation of 5-25 light pulses (λ = 430 nm, pulse width Δt = 500 ms) at a drain bias voltage of 1 V, the weight intensity of the synapse is significantly enhanced with the increase of the number of light pulses. The device can realize the transition from short-term plasticity (STP) to long-term plasticity (LTP) under light conditions.

[0072] The above shows and describes the basic principles, main features and advantages of the present application. It should be understood by those skilled in the art that the present application is not limited to the above-mentioned embodiments, and the above-mentioned embodiments and descriptions in the specification are only to illustrate the principles of the present application, and any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.

[0073] The remaining matters of the present application are known technologies.

Claims

1. A photoelectric synaptic transistor based on a graphynetic / MoS2 van der Waals heterostructure, characterized in that, The structure of the transistor, from bottom to top, consists of a bottom gate electrode / gate dielectric layer, a GDY / MoS2 heterolayer, and metal source / drain electrodes. The GDY / MoS2 heterolayer has a thickness of 4-5 nm for GDY and a thickness of 2-3 nm for MoS2.

2. The photoelectric synaptic transistor based on the graphyne / MoS2 van der Waals heterostructure as described in claim 1, characterized in that, The bottom gate electrode / gate dielectric layer is Si / SiO2, wherein the thickness of the gate dielectric layer SiO2 is 100-300 nm; The metal source and drain electrodes are one or two of chromium, gold, platinum and palladium, with a thickness of 50-100 nm.

3. The method for fabricating a photoelectric synaptic transistor based on a graphyne / MoS2 van der Waals heterostructure as described in claim 1, characterized in that, Includes the following steps: 1) Clean the bottom gate electrode / gate dielectric layer sequentially with deionized water, acetone, and anhydrous ethanol using ultrasonic cleaning for 10-30 minutes, and then dry its surface with nitrogen gas for later use. 2) Gold Marks are fabricated on the bottom gate electrode / gate dielectric layer using electron beam lithography, thermal evaporation, and lift-off processes; 3) A Cu thin film with a thickness of approximately 10–50 nm is deposited on the bottom gate electrode / gate dielectric layer using a thermal evaporation process; 4) GDY thin films of 3–10 nm were grown by chemical growth method; 5) The copper foil substrate on which the GDY film is grown is etched by wet etching, washed with deionized water and dried to obtain the GDY film. The etching time of the copper foil is 2 to 6 hours, and the etching solution is an aqueous solution of ammonium persulfate with a concentration of 0.1 to 0.3 mol / L. 6) The GDY thin film is transferred onto the bottom gate electrode / gate dielectric layer with gold mark using a wet transfer process; 7) Use transparent tape to peel off the MoS2 multilayer nanosheet crystals from the MoS2 crystals and transfer them to polydimethylsiloxane PDMS; use a transfer platform to transfer the nanosheets on PDMS to the surface of the prepared Si / SiO2 / GDY sample to form a GDY / MoS2 heterostructure; 8) The electrodes were patterned using the EBL process, and then the source and drain electrodes were prepared by thermal evaporation and stripping processes; The aforementioned thermal evaporation rate is The chamber vacuum level is 10. -3 ~10 -4 Pa.

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