Cadmium zinc telluride pixelated detection module and preparation method thereof

Abstract

The invention belongs to the field of semiconductor detectors, and particularly discloses a cadmium zinc telluride pixelated detection module and a preparation method thereof. According to the invention, the InSb wafer is used as the substrate for growing the CdZnTe thin film, the crystal quality of the CdZnTe thin film is remarkably improved, and the preparation of the wafer-level CdZnTe single crystal thin film is realized, so that the resolution ratio of the detection module is improved, and the size limitation of the detection module is broken through. On the basis, surface treatment of a thin film, pixelated electrode integration and in-situ testing of pixel units are sequentially carried out, and then the whole wafer is cut and divided according to the specification of a module formed by the pixel units, so that a single or multiple high-performance radiation detection modules are obtained. According to the method, high-quality, high-resolution, high-efficiency and standardized mass production of the detection module is realized, and the application suitability of the detection module in the fields of medical CT imaging, nuclear radiation monitoring, industrial nondestructive testing and the like is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor detection devices, and particularly relates to a cadmium zinc telluride pixelated detection module and a preparation method thereof. BACKGROUND

[0002] As a II-VI wide bandgap semiconductor material, cadmium zinc telluride (CdZnTe) is considered as an ideal semiconductor material for X / gamma-ray detectors due to its high atomic number, high carrier mobility and excellent room temperature radiation detection performance, and is widely used in medical CT imaging, nuclear safety monitoring, industrial non-destructive testing and other fields.

[0003] At present, the preparation of cadmium zinc telluride pixelated detection modules mainly uses ingots grown by the melt method as raw materials, and after cutting into blocks, each crystal is ground, polished, electrode prepared and tested to obtain a detection module composed of different arrays. However, the CdZnTe crystal prepared by the melt method must be cut and selected for device construction due to its growth characteristics, while the epitaxially grown CdZnTe thin film can avoid this problem, but the epitaxial growth of large-size CdZnTe thin film usually uses GaAs, GaSb and other substrates with large lattice mismatch, which will form dislocations and stress at the interface, resulting in a significant gap in the quality of the CdZnTe thin film compared with the crystal prepared by the melt method. At the same time, the discrete process flow of the prior art, which is "cutting bulk single crystal first and then constructing pixel electrodes", has many drawbacks: high process complexity, low efficiency and long time-consuming, and the cumulative error introduced by multi-step processing will seriously affect the consistency of module performance; at the same time, a large amount of waste material is generated during repeated processing, resulting in serious material waste and low utilization rate, significantly increasing production costs. In addition, some processes in the traditional process still rely on manual operation, and the degree of automation is insufficient, the production capacity is limited, and it is difficult to meet the market demand for large-scale production.

[0004] Therefore, it is urgent to develop a process technology for cadmium zinc telluride pixelated detection modules with high material utilization, low production cost, suitable for large-scale production, and capable of preparing high-quality CdZnTe thin films, achieving high resolution and high consistency, to break through the bottleneck of the prior art and promote the large-scale application of CdZnTe detectors. SUMMARY

[0005] In view of the problems of the prior art related to the preparation of cadmium zinc telluride pixelated detection modules, the present application provides a cadmium zinc telluride pixelated detection module and a preparation method thereof.

[0006] To achieve the above-mentioned purpose, the following technical solutions are specifically included: In a first aspect, the present application provides a preparation method of a cadmium zinc telluride pixelated detection module, comprising the following steps: (1) taking CdZnTe polycrystal as a growth source, growing a CdZnTe film layer on the front surface of an InSb wafer substrate by a close space sublimation method, and then annealing under a Te annealing source to obtain a wafer-level CdZnTe film layer; the wafer-level CdZnTe film layer comprises an InSb wafer substrate and a CdZnTe film layer deposited on the front surface of the InSb wafer substrate; (2) grinding and polishing the wafer-level CdZnTe film layer to obtain a pretreated wafer-level CdZnTe film layer; (3) depositing a back electrode on the back surface of the InSb wafer substrate in the pretreated wafer-level CdZnTe film layer; (4) spin-coating a photoresist layer on the CdZnTe film layer in the pretreated wafer-level CdZnTe film layer, performing photoetching according to a designed pixelated pattern to obtain a pixelated mask layer; and then depositing a metal film layer on the pixelated mask layer to form a plurality of pixelated top electrodes, thereby obtaining a plurality of pixel units; (5) testing the performance of each pixel unit to determine whether each pixel unit is qualified, and then selecting qualified pixel units to construct a module, and cutting the module to obtain the CdZnTe pixelated detection module.

[0007] In the method, the InSb wafer is used as a substrate for growing the CdZnTe thin film, the good lattice matching relationship between InSb and CdZnTe is utilized to effectively reduce the generation of interface dislocation and stress, improve the crystallization quality of the CdZnTe thin film, and obtain a CdZnTe single crystal thin film, thereby improving the resolution of the detection module. Meanwhile, the size of the grown CdZnTe thin film reaches the wafer level, which breaks through the size limitation in the preparation of the CdZnTe single crystal thin film in the prior art. On the wafer-level CdZnTe thin film, surface treatment, pixelated electrode integration and in-situ testing of pixel units are sequentially performed, and then based on the whole wafer, the module specification composed of the pixel units is cut into a single module or multiple modules, so that high-quality, high-resolution, high-efficiency and standardized mass production of the high-performance radiation detection module are realized, and the high-performance radiation detection module is more suitable for medical CT imaging, nuclear radiation monitoring, industrial nondestructive testing and other fields.

[0008] In some embodiments, in step (1), the crystal orientation of the InSb wafer substrate is (100), and the diameter of the InSb wafer substrate is 1-12 inches. In some embodiments, in step (1), the chemical formula of the CdZnTe polycrystal is Cd 1-x Zn x Te, wherein 0.01≤x≤0.2.

[0009] In some embodiments, in step (1), when growing the CdZnTe film layer, the temperature of the growth source is 480-760℃, the temperature of the InSb wafer substrate is 300-450℃, the growth time is 1-24h, the distance between the growth source and the InSb wafer substrate is 4-15mm, and the vacuum degree is less than or equal to 0.1Pa.

[0010] In some embodiments, in step (1), when growing the CdZnTe film layer, the growth is performed in two times, specifically including the following steps: (1-1) increasing the temperature of the growth source and the InSb wafer substrate to 480-760℃ and 300-450℃ respectively, and growing the CdZnTe film layer at the above-mentioned temperature for 1-24h; (1-2) reducing the temperature of the growth source to 350-450℃, and keeping the temperature for 10-60min; then increasing the temperature of the growth source to 480-760℃, and growing the CdZnTe film layer at the above-mentioned temperature for 1-24h, and cooling to room temperature. The growth of the CdZnTe film layer in two times can prevent the excessive internal stress of the CdZnTe film layer and the cracks of the film layer caused by the continuous growth of the CdZnTe film layer.

[0011] In some embodiments, in step (1), before growing the CdZnTe film layer, the InSb wafer substrate is sequentially subjected to preheating treatment and cooling to room temperature, the temperature of the preheating treatment is 300-400℃, the time of the preheating treatment is 1-10min, and the vacuum of the preheating treatment is <2×10 -3 Pa. The preheating treatment of the InSb wafer substrate can remove the oxide and possible impurities on the surface of the growth substrate.

[0012] In some embodiments, in step (1), before growing the CdZnTe film layer, the CdZnTe polycrystal is sequentially subjected to preheating treatment and cooling to room temperature, the temperature of the preheating treatment is 550-650℃, the time of the preheating treatment is 5-20min, and the vacuum of the preheating treatment is <2×10 -3 Pa. The preheating treatment of the CdZnTe polycrystal can remove the impurities on the surface of the growth source (evaporation source) which are not cleaned.

[0013] In some embodiments, in step (1), the thickness of the CdZnTe film layer in the wafer-level CdZnTe film layer is 0.6-3mm.

[0014] In some embodiments, in step (1), the temperature of the annealing is 300-400℃, the time of the annealing is 2-20h, and the rate of the temperature rising to the annealing is 5-25℃ / min.

[0015] In some embodiments, in step (1), the annealing is performed at a temperature of 380-420℃ for the Te annealing source, at a rate of 5-25℃ / min for the temperature of the Te annealing source, at a temperature of 300-400℃ for the CdZnTe film layer, and at a rate of 5-25℃ / min for the temperature of the CdZnTe film layer.

[0016] In some embodiments, in step (1), the CdZnTe polycrystal wafer is further subjected to grinding, polishing, water washing, ethanol cleaning, acetone cleaning, and drying, each of the water washing, the ethanol cleaning, and the acetone cleaning being independently selected from being performed under ultrasonic condition for 5-20 min.

[0017] In some embodiments, in step (1), the InSb wafer substrate is further subjected to water washing, ethanol cleaning, acetone cleaning, and drying, each of the water washing, the ethanol cleaning, and the acetone cleaning being independently selected from being performed under ultrasonic condition for 5-20 min.

[0018] In some embodiments, in step (1), the wafer-level CdZnTe film layer is a single crystal.

[0019] In some embodiments, in step (2), the grinding is a physical and mechanical grinding of the wafer-level CdZnTe film layer using a grinding material, the grinding material comprising alumina powder with an average particle size of 0.5-3 μm.

[0020] In some embodiments, in step (2), the polishing comprises physical and mechanical polishing and chemical etching polishing, in the physical and mechanical polishing, a polishing powder is used for polishing, the polishing powder comprising alumina powder with an average particle size of 0.01-0.1 μm, and the chemical etching polishing comprises the following steps: first, the wafer-level CdZnTe film layer is immersed in a 1wt%-3wt% aqueous bromoform solution for 1-5 min, then the wafer-level CdZnTe film layer is taken out and ultrasonically cleaned in ethanol, and finally dried to obtain a pretreated wafer-level CdZnTe film layer.

[0021] In some embodiments, in step (2), the pretreated wafer-level CdZnTe film layer has a roughness of <5 nm on the surface of the CdZnTe film layer.

[0022] In some embodiments, in step (3), the deposition method comprises at least one of a magnetron sputtering method or an electron beam evaporation method, the material of the back electrode comprises at least one of titanium, chromium, gold, indium, or platinum, and the thickness of the back electrode is 30-500 nm.

[0023] In some embodiments, in step (4), the photolithography is performed by using ultraviolet light and a mask to transfer the designed pixelated pattern to the photoresist layer, thereby obtaining a pixelated mask layer.

[0024] In some embodiments, in step (4), the deposition method comprises at least one of a magnetron sputtering method or an electron beam evaporation method, the material of the pixelated top electrode comprises at least one of titanium, chromium, gold, indium or platinum, the thickness of the pixelated top electrode is 30-500 nm, the width of the pixelated top electrode is 250 μm-2 mm, the length of the pixelated top electrode is 250 μm-2 mm, and the distance between adjacent pixelated top electrodes is 50 μm-1 mm.

[0025] In some embodiments, in step (5), the performance comprises resistivity, and the resistivity of each pixel unit is >10 9 Ω·cm.

[0026] In some embodiments, in step (5), the module comprises an arrayed module, and the specification of the arrayed module is represented as M×N, wherein M and N respectively represent the number of pixel units in each row (the number of rows) and the number of pixel units in each column (i.e., the number of columns). For example, the arrayed module can comprise at least one of 1×16, 4×4 or 8×8.

[0027] In a second aspect, the present application provides a CdZnTe pixelated detection module, which is prepared by the method for preparing a CdZnTe pixelated detection module, and comprises one or more than two pixel units, wherein each pixel unit comprises a pixelated top electrode, a CdZnTe single crystal film layer, an InSb substrate and a back electrode which are sequentially arranged in a stacked manner.

[0028] Compared with the prior art, the present application has the following beneficial effects: on the one hand, the present application uses InSb which is matched with the CdZnTe crystal lattice as a growth substrate, so that the number of misfit dislocations at the epitaxial interface is small, and the quality of the CdZnTe crystal is improved; on the other hand, the present application uses a wafer-level continuous process to replace discrete processing, thereby improving the overall process integration, reducing the number of repeated processes, reducing cumulative errors, enhancing the performance consistency of the module, and allowing the size of the detection module and the pixel electrode pattern to be customized. In addition, the method of the present application can avoid material loss caused by traditional separate cutting of multiple element units, improve material utilization, reduce the cost of a single detection module, and is suitable for mass production. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 The figure is a preparation flowchart of the CdZnTe pixelated detection module based on wafer production of the present application.

[0030] Figure 2 The figure is a structural schematic diagram of the CdZnTe pixelated detection module of the present application.

[0031] Figure 3 The image shows the XRD rocking curve of the zinc cadmium telluride thin film on the InSb wafer substrate in Example 1.

[0032] Figure 4 The image shows the XRD rocking curve of the zinc cadmium telluride film on the GaAs substrate in Comparative Example 1.

[0033] Figure 5 This is a schematic diagram of the wafer-level cadmium zinc telluride pixelated detection module of the present invention. Detailed Implementation

[0034] To better illustrate the purpose, technical solution, and advantages of this invention, specific embodiments will be used to further explain the invention below. Unless otherwise specified, the test methods used in the embodiments and / or comparative examples are conventional methods; the materials and reagents used, unless otherwise specified, are commercially available.

[0035] Example 1 A method for fabricating a pixelated detector module for zinc cadmium telluride, the process is as follows: Figure 1 As shown, it includes the following steps: (1) Wafer-level CdZnTe thin film preparation: Wafer-level Cd grown using the melt method 0.9 Zn 0.1 Te multi-chips were used as the growth source. After polishing, they were placed in deionized water, anhydrous ethanol and acetone for ultrasonic cleaning for 15 minutes in sequence. Finally, they were dried with nitrogen and vacuum sealed for later use. A 2-inch InSb(100) wafer was used as the growth substrate. The substrate was placed in beakers containing deionized water, anhydrous ethanol and acetone, and sonicated for 15 minutes each. Finally, it was dried with nitrogen and vacuum sealed for later use. The pretreated growth source and wafer substrate were placed on the lower and upper heating stages of the near-space sublimation furnace, respectively. The mechanical pump and vent valve were turned on to evacuate the chamber, and water cooling was activated simultaneously. When the gas pressure inside the chamber dropped below 5 Pa, the molecular pump automatically started, and the vacuum was continued to 1 × 10⁻⁶ Pa. -4 Pa is used to preheat the wafer substrate to 420°C for 5 minutes; at the same time, the growth source is preheated to 600°C for 10 minutes; finally, the wafer substrate and the growth source are cooled to room temperature. High-purity argon gas was introduced to increase the pressure inside the cavity to 0.01 Pa. The distance between the wafer substrate and the growth source was set to 6 mm. The wafer substrate and the growth source were heated to 400 °C and 700 °C, respectively, at a heating rate of 2 °C / s. The growth source Cd... 0.9 Zn 0.1Te sublimates and deposits on the front surface of the wafer substrate to form a CdZnTe thin film, the growth time is 10 h, and the wafer is naturally cooled to room temperature after the growth is completed; The ventilation valve, the molecular pump, the water cooling and the mechanical pump are sequentially closed, the cavity is opened, and the wafer-level thin film product is taken out, and the thickness of the CdZnTe thin film on the wafer is 1.1 mm; The wafer-level thin film product and the Te annealing source are respectively placed in the center of two temperature zones of an annealing furnace, the temperature of the annealing source is increased to 420℃ at a rate of 10℃ / min, the temperature of the wafer-level thin film product is increased to 390℃, and the annealing time is 10 h, so as to obtain a wafer-level CdZnTe thin film; the wafer-level CdZnTe thin film comprises an InSb wafer substrate and a CdZnTe thin film deposited on the front surface of the InSb wafer substrate; The CdZnTe thin film on the InSb wafer substrate is characterized by X-ray diffraction (XRD), and the rocking curve of the characteristic peak of the (004) crystal plane is as shown in Figure 3 The half peak width is only 90'', which is a single crystal phase.

[0036] (2) Wafer-level CdZnTe thin film grinding and polishing: A physical and mechanical grinding method is used to improve the flatness of the CdZnTe thin film, 1μm particle size Al2O3 powder is used as abrasive to perform surface grinding treatment on the CdZnTe thin film, and a thin film with uniform thickness is obtained; A physical and mechanical polishing method is used to remove the micro-damage layer remaining in the grinding process, 0.05μm particle size Al2O3 powder is used as polishing powder to perform surface polishing treatment on the CdZnTe thin film, and a mirror-like smooth surface is obtained.

[0037] (3) Wafer-level CdZnTe thin film surface chemical etching and polishing treatment: The wafer-level CdZnTe thin film is immersed in a 2% bromine methanol solution for 2 min, then taken out and ultrasonically treated with anhydrous ethanol for 10 min, finally dried with nitrogen and vacuum sealed for standby, to obtain a pretreated wafer-level CdZnTe thin film.

[0038] (4) Preparation of back electrode: a gold film is deposited on the back surface of the InSb wafer substrate as a back electrode by a magnetron sputtering method, and the thickness of the back electrode is 200 nm.

[0039] (5) Preparation of pixelated top electrode: First, a 2μm thick layer of photoresist is spin-coated onto the CdZnTe thin film using a spin coater. Next, a pixelated photoresist mask layer is formed by UV exposure and development according to the designed pixelated pattern, transferring the pixelated pattern onto the thin film. Then, a gold thin film is deposited on the pixelated mask layer using magnetron sputtering. Finally, the film is immersed in acetone. At locations with photoresist, the photoresist and the film covering it detach, removing excess metal film. Where there is no photoresist, the metal film remains on the CdZnTe thin film surface, resulting in a batch of pixelated top electrodes on the CdZnTe thin film surface, forming a wafer-level pixelated electrical component. In this embodiment, because a regular array pixelation pattern is used, the multiple pixelated top electrodes are also arranged in an array on the CdZnTe thin film surface, as shown below. Figure 2 As shown, each pixelated top electrode has a thickness of 100 nm and a length and width of 0.9 mm × 0.9 mm. The spacing between two adjacent pixelated top electrodes is 0.2 mm. The product obtained by slicing along the thickness direction at the position corresponding to each pixelated top electrode includes, from top to bottom, a stacked pixelated top electrode, a CdZnTe single crystal film layer, an InSb substrate, and a back electrode. It contains the functional layers necessary for the detection function. Therefore, it can be regarded as the smallest unit for realizing the detection function. This smallest unit is taken as the pixel unit, and the size of the pixelated top electrode is taken as the pixel size.

[0040] (6) Electrical testing of pixel units: A semiconductor parameter analyzer was used to test the resistance of each pixel unit on the wafer-level pixelated electrical component. The resistivity of each unit was calculated based on parameters such as pixel size and CdZnTe film thickness, and the measured resistivity was greater than 10. 9 A pixel unit is considered acceptable if its resistance is within Ω·cm, and the proportion of acceptable pixel units on a single wafer is 96%. Among these, the pixel units in commonly required detection modules have a resistivity greater than 10 Ω·cm. 9 Ω·cm is considered acceptable; therefore, this standard is also adopted in this invention.

[0041] (7) Wafer dicing for pixel units: Based on the requirements of different types of detection modules, qualified pixel units in the wafer-level pixelated electrical components are divided and assembled into modules of different specifications, such as... Figure 5As shown, on the wafer-level pixelated electrical assembly, each small square represents a pixel unit, and the pixel units on the wafer-level pixelated electrical assembly product in this embodiment are divided into seven regions A-G according to linear array and planar array, wherein the A and B regions are planar arrays, and the remaining five regions are linear arrays. The array is represented as MxN, and M and N represent the number of pixel units in each row (the number of rows) and the number of pixel units in each column (the number of columns), respectively. The wafer-level pixelated electrical assembly is divided according to the seven partitions, and finally seven CdZnTe pixelated detection modules are obtained. The structure of a single CdZnTe pixelated detection module is as shown in Figure 2 As shown, from bottom to top, it includes a back electrode, an InSb substrate, a CdZnTe single crystal thin film, and a plurality of pixelated top electrodes. The previously reported CdZnTe pixelated detection module is sequentially arranged from bottom to top as a GaAs or glass substrate, a back electrode, a CdZnTe polycrystalline thin film, and a planar electrode structure. The CdZnTe thin film is deposited on a metal or conductive oxide back electrode, and the thin film is polycrystalline. The CdZnTe thin film of the present application is epitaxially grown on a single crystal substrate with high lattice matching, and is single crystal. The electrical quality of the single crystal thin film is higher, and therefore the electrical performance of the CdZnTe pixelated detection module is better, and the resolution is higher. The electrical device constructed by the module has more excellent electrical performance. In addition, the present application directly cuts each module based on the whole wafer-level product, which has a relatively large size, reduces the impact of errors, and does not need to use the method of cutting first and then constructing modules separately, which can save process, improve efficiency, reduce material loss and reduce cost. The pixel units on the wafer-level pixelated electrical assembly are compatible with linear or planar arrays, and the specifications of the detection module constructed are more flexible and convenient. A single wafer-level pixelated electrical assembly can be divided into hundreds of detection modules, realizing high-quality and efficient mass production of detection modules.

[0042] Embodiment 2 A preparation method of a CdZnTe pixelated detection module is shown in the flowchart as Figure 1 As shown, the method comprises the following steps: (1) Wafer-level CdZnTe thin film preparation: A wafer-level CdZnTe polycrystalline wafer grown by a melt method is used as a growth source, and after polishing and polishing treatment, it is sequentially placed in deionized water, anhydrous ethanol and acetone for ultrasonic cleaning for 15 minutes. Finally, it is dried with nitrogen and vacuum sealed for standby use; 0.9 Zn 0.1 Te polycrystalline wafer grown by a melt method is used as a growth source, and after polishing and polishing treatment, it is sequentially placed in deionized water, anhydrous ethanol and acetone for ultrasonic cleaning for 15 minutes. Finally, it is dried with nitrogen and vacuum sealed for standby use; A 3-inch InSb (100) wafer is used as a growth substrate, and the substrate is sequentially placed in beakers containing deionized water, anhydrous ethanol and acetone for ultrasonic cleaning for 15 minutes. Finally, it is dried with nitrogen and vacuum sealed for standby use; Put the pretreated growth source and wafer substrate into the lower heating table and the upper heating table of the near-space sublimation furnace respectively, open the mechanical pump and the ventilation valve, vacuumize the cavity, and at the same time, open the water cooling. When the air pressure in the cavity is lower than 5 Pa, the molecular pump is automatically opened, and the vacuumization continues until 1x10 -4 Pa. The wafer substrate is preheated, and the heating temperature is 400℃, and the heating time is 5 min. At the same time, the growth source is preheated to 600℃, and the heating time is 10 min. Finally, the wafer substrate and the growth source are cooled to room temperature. The high-purity argon gas is introduced to increase the pressure in the cavity to 0.01 Pa, and the distance between the wafer substrate and the growth source is set to 6 mm. The wafer substrate and the growth source are heated to 400℃ and 700℃ respectively at a heating rate of 2℃ / s. The growth source sublimates and deposits Cd 0.9 Zn 0.1 Te on the front surface of the wafer substrate to form a CdZnTe thin film, and the growth time is 9 h. Then the growth source temperature is reduced to 400℃, and the temperature is kept constant for 30 min. Then the temperature is increased to 700℃, and the growth continues for 9 h. After the growth is completed, it is naturally cooled to room temperature. The ventilation valve, molecular pump, water cooling and mechanical pump are closed in turn, the cavity is opened, and the wafer-level thin film product is taken out. The thickness of the CdZnTe thin film on the wafer is 2 mm. The wafer-level thin film product obtained above and the Te annealing source are respectively put into the center of the two temperature zones of the annealing furnace. The temperature of the annealing source is increased to 420℃ at a rate of 10℃ / min, and the temperature of the wafer-level thin film product is increased to 400℃. The annealing time is 20 h, and a wafer-level CdZnTe thin film is obtained. The wafer-level CdZnTe thin film comprises an InSb wafer substrate and a CdZnTe thin film deposited on the front surface of the InSb wafer substrate. (2) Wafer-level CdZnTe thin film grinding and polishing: The flatness of the CdZnTe thin film is improved by physical and mechanical grinding method. Al2O3 powder with a particle size of 1 μm is used as abrasive to grind the surface of the CdZnTe thin film, and a thin film with uniform thickness is obtained. The physical and mechanical polishing method is used to remove the micro-damage layer remaining in the grinding process. Al2O3 powder with a particle size of 0.05 μm is used as polishing powder to polish the surface of the CdZnTe thin film, and a mirror-like smooth surface is obtained.

[0043] (3) Wafer-level CdZnTe thin film surface chemical etching and polishing treatment: The wafer-level CdZnTe thin film is immersed in a 2% bromine methanol solution for 2 min, taken out and ultrasonically cleaned with anhydrous ethanol for 10 min, and finally dried with nitrogen and vacuum sealed for standby. A pretreated wafer-level CdZnTe thin film is obtained.

[0044] (4) Preparation of back electrode: gold film was deposited on the back of InSb wafer substrate as a back electrode by magnetron sputtering method, and the thickness of the back electrode was 200 nm.

[0045] (5) Preparation of pixelated top electrode: First, a layer of photoresist with a thickness of 2 μm was spin-coated on the surface of the CdZnTe thin film by using a photoresist spinner. Next, a pixelated photoresist mask layer was formed by photolithography according to the designed pixelated pattern through ultraviolet exposure and development, so that the pixelated pattern was transferred to the thin film. Then, a layer of gold thin film was deposited on the pixelated mask layer by magnetron sputtering. Finally, the sample was immersed in acetone, and the photoresist and the thin film covered on the photoresist fell off at the position with photoresist, so as to peel off the excess metal thin film. The metal thin film still covered on the surface of the CdZnTe thin film at the position without photoresist, and a batch of pixelated top electrodes were obtained on the surface of the CdZnTe thin film, which constituted a wafer-level pixelated electrical assembly as a whole. In this embodiment, a regular array pixelated pattern was used, so the obtained multiple pixelated top electrodes were also arranged in an array form on the surface of the CdZnTe thin film, as shown in FIG. 2. The thickness of each pixelated top electrode was 100 nm, the length and width of each pixelated top electrode were 0.9 mm x 0.9 mm, and the distance between two adjacent pixelated top electrodes was 0.2 mm. The product obtained by cutting along the thickness direction at the position corresponding to each pixelated top electrode included, from top to bottom, the pixelated top electrode, the CdZnTe single crystal film layer, the InSb substrate and the back electrode which were arranged in layers, and contained the functional layers necessary for realizing the detection function. Therefore, it could be regarded as the smallest unit for realizing the detection function, and the smallest unit was taken as a pixel unit, and the size of the pixelated top electrode was taken as the pixel size. Figure 2

[0046] (6) Electrical test of pixel unit The resistance of each pixel unit on the wafer-level pixelated electrical assembly was tested by using a semiconductor parameter analyzer, and the resistivity of each unit was calculated according to the pixel size, the thickness of the CdZnTe thin film and other parameters. It was considered that the pixel unit was qualified when the resistivity was greater than 10 9 Ω·cm, and the proportion of the qualified pixel units on a single wafer-level pixelated electrical assembly was 93%. In the market, the resistance of the pixel unit in the detection module was generally required to be greater than 10 9 Ω·cm, and therefore, the present application also adopted this standard.

[0047] (7) Wafer slicing of pixel unit According to the requirements of different types of detection modules, the qualified pixel units in the wafer-level pixelated electrical assembly were divided and composed into different specification modules, the wafer-level pixelated electrical assembly was segmented according to each module partition, and finally multiple cadmium zinc telluride pixelated detection modules were obtained. The structure of a single cadmium zinc telluride pixelated detection module is shown in FIG. 3.​Figure 2 As shown, from bottom to top, it sequentially comprises a back electrode, an InSb substrate, a cadmium zinc telluride single crystal thin film, and a plurality of pixelated top electrodes (constituting a surface electrode).

[0048] Comparative Example 1 In this comparison, a 2-inch GaAs (100) wafer is used as a substrate for epitaxial growth of a CdZnTe thin film, which specifically includes the following steps: (1) A wafer-level CdZnTe polycrystal grown by a melt method is used as a growth source, which is subjected to grinding and polishing, and then sequentially ultrasonically cleaned in deionized water, anhydrous ethanol, and acetone for 15 minutes. Finally, it is dried with nitrogen and vacuum sealed for standby use. A GaAs (100) wafer is used as a growth substrate, which is sequentially placed in beakers containing deionized water, anhydrous ethanol, and acetone for ultrasonic cleaning for 15 minutes each. Finally, it is dried with nitrogen and vacuum sealed for standby use; 0.9 Zn 0.1 Te polycrystal as a growth source, and the wafer substrate is sequentially placed in beakers containing deionized water, anhydrous ethanol, and acetone for ultrasonic cleaning for 15 minutes each. Finally, it is dried with nitrogen and vacuum sealed for standby use; (2) The pretreated growth source and wafer substrate are placed in the lower and upper heating stages of a close-spaced sublimation furnace, respectively. The mechanical pump and vent valve are turned on to vacuum the cavity, and the water cooling is turned on at the same time. When the gas pressure in the cavity is lower than 5 Pa, the molecular pump is automatically turned on, and the vacuum is continued to 1 × 10 -4 Pa. The wafer substrate is preheated to 550℃ for 10 minutes. At the same time, the growth source is preheated to 600℃ for 10 minutes. Finally, the wafer substrate and the growth source are cooled to room temperature; (3) High-purity argon gas is introduced to increase the pressure in the cavity to 0.01 Pa. The distance between the wafer substrate and the growth source is set to 6 mm. The wafer substrate and the growth source are heated to 400℃ and 700℃, respectively, at a heating rate of 2℃ / s. The CdZnTe source sublimates and deposits on the front surface of the wafer substrate to form a CdZnTe thin film. The growth time is 10 hours, and the product is naturally cooled to room temperature after the growth is completed. The vent valve, molecular pump, water cooling, and mechanical pump are turned off in sequence. The cavity is opened, and the product is taken out. The thickness of the CdZnTe thin film on the wafer is 1.1 mm; 0.9 Zn 0.1 Te sublimates and deposits on the front surface of the wafer substrate to form a CdZnTe thin film. The growth time is 10 hours, and the product is naturally cooled to room temperature after the growth is completed. The vent valve, molecular pump, water cooling, and mechanical pump are turned off in sequence. The cavity is opened, and the product is taken out. The thickness of the CdZnTe thin film on the wafer is 1.1 mm; (4) The above-mentioned product and Te annealing source are placed in the center of the two temperature zones of an annealing furnace, respectively. The temperature of the annealing source is increased to 420℃ at a rate of 10℃ / min, and the temperature of the above-mentioned product is increased to 390℃. The annealing time is 10 hours, and a CdZnTe thin film is obtained. The CdZnTe thin film comprises a GaAs substrate and a CdZnTe thin film deposited on the front surface of the GaAs substrate.

[0049] The CdZnTe thin film on the GaAs substrate is characterized by XRD, and the results are as follows: Figure 4As shown, the rocking curve half-peak width of the characteristic peak of the thin film (004) crystal plane is 161".

[0050] Compared with the CdZnTe thin film in Example 1, the CdZnTe thin film prepared on the InSb substrate has a smaller half-peak width, indicating that the crystalline quality thereof is better. This is mainly due to the fact that the lattice mismatch between the InSb substrate and CdZnTe is only 0.5%, which is significantly lower than 13.9% of the GaAs substrate; the smaller lattice mismatch effectively reduces the interface mismatch dislocation density and residual stress, thereby significantly improving the crystal quality of the epitaxial thin film.

[0051] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application and not to limit the protection scope of the present application. Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced equivalently without departing from the essence and scope of the technical solutions of the present application.

Claims

1. A method for fabricating a pixelated detection module for cadmium zinc telluride, characterized in that, Includes the following steps: (1) Using a CdZnTe multi-wafer as the growth source, a CdZnTe film is grown on the front side of an InSb wafer substrate using a near-space sublimation method, and then annealed under a Te annealing source to obtain a wafer-level CdZnTe film; the wafer-level CdZnTe film includes an InSb wafer substrate and a CdZnTe film deposited on the front side of the InSb wafer substrate; (2) Grind and polish the wafer-level CdZnTe film to obtain a pre-treated wafer-level CdZnTe film; (3) Deposit a back electrode on the back side of the InSb wafer substrate in the pretreated wafer-level CdZnTe film layer; (4) A photoresist layer is prepared by spin-coating on the CdZnTe film layer in the pretreated wafer-level CdZnTe film layer, and photolithography is performed according to the designed pixelated pattern to obtain a pixelated mask layer. A metal film is then deposited on the pixelated mask layer to form multiple pixelated top electrodes, thereby obtaining multiple pixel units; (5) Perform performance testing on each pixel unit to determine whether each pixel unit is qualified, then select qualified pixel units to construct a module, and divide the module to obtain the cadmium zinc telluride pixelated detection module.

2. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, Includes at least one of the following: A. In step (1), the chemical formula of the CdZnTe multi-crystal is Cd 1-x Zn x Te, where 0.01 ≤ x ≤ 0.2; B. In step (1), when growing the CdZnTe film, the temperature of the growth source is 480-760℃, the temperature of the InSb wafer substrate is 300-450℃, the growth time is 1-24h, the distance between the growth source and the InSb wafer substrate is 4-15mm, and the vacuum degree is less than or equal to 0.1Pa.

3. The method for preparing the pixelated detection module for zinc cadmium telluride as described in claim 1, characterized in that, In step (1), the InSb wafer substrate has a crystal orientation of (100) and a diameter of 1-12 inches.

4. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, Includes at least one of the following: C. In step (1), the thickness of the CdZnTe film layer at the wafer level is 0.6-3 mm; D. In step (1), the annealing temperature is 300-400℃ and the annealing time is 2-20h.

5. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, Includes at least one of the following: E. In step (1), the CdZnTe multi-crystal wafers are further subjected to grinding, polishing, water washing, ethanol cleaning, acetone cleaning and drying. The water washing, ethanol cleaning and acetone cleaning are each independently selected to be performed under ultrasonic conditions for 5-20 minutes. F. In step (1), the InSb wafer substrate is further subjected to water washing, ethanol cleaning, acetone cleaning and drying. The water washing, ethanol cleaning and acetone cleaning are each independently selected to be performed under ultrasonic conditions for 5-20 minutes.

6. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, In step (1), the CdZnTe film layer at the wafer level is a single crystal.

7. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, Includes at least one of the following: G. In step (2), the grinding is to use an abrasive to perform physical and mechanical grinding on the wafer-level CdZnTe film, wherein the abrasive includes alumina powder with an average particle size of 0.5-3μm; H. In step (2), the polishing includes physical mechanical polishing and chemical etching polishing. In the physical mechanical polishing, polishing powder is used for polishing. The polishing powder includes alumina powder with an average particle size of 0.01-0.1μm. The chemical etching polishing includes the following steps: first, the wafer-level CdZnTe film is immersed in a 1wt%-3wt% bromomethanol aqueous solution for 1-5 minutes, the wafer-level CdZnTe film is taken out, then ultrasonically cleaned in ethanol, and finally dried to obtain the pretreated wafer-level CdZnTe film.

8. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, Includes at least one of the following: I. In step (2), the surface roughness of the CdZnTe film layer after pretreatment is <5nm. J. In step (3), the deposition method includes at least one of magnetron sputtering or electron beam evaporation, the material of the back electrode includes at least one of titanium, chromium, gold, indium or platinum, and the thickness of the back electrode is 30-500 nm. K. In step (4), during photolithography, the light source is ultraviolet light, and a mask is used to transfer the designed pixelated pattern to the photoresist layer to obtain a pixelated mask layer. L. In step (4), the deposition method includes at least one of magnetron sputtering or electron beam evaporation. M. The pixelated top electrode is made of at least one of titanium, chromium, gold, indium or platinum. The pixelated top electrode has a thickness of 30-500nm, a width of 250μm-2mm, a length of 250μm-2mm, and a spacing of 50μm-1mm between adjacent pixelated top electrodes.

9. The method for preparing the pixelated detection module for cadmium zinc telluride as described in claim 1, characterized in that, Includes at least one of the following: N. In step (5), the performance includes resistivity, with a resistivity of 10 for each pixel unit. 9 Ω·cm; O. In step (5), the module includes an array module, and the specifications of the array module include at least one of 1×16, 4×4 or 8×8.

10. A pixelated detection module for cadmium zinc telluride, characterized in that, The pixelated detection module is prepared by any one of claims 1-9. The pixelated detection module includes one or more pixel units, and the pixel unit includes a pixelated top electrode, a CdZnTe single crystal film layer, an InSb substrate and a back electrode stacked sequentially.

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