Image sensor

Abstract

An image sensor is provided. The image sensor includes: a substrate including a first surface and a second surface opposite to each other; a deep partition member in the substrate and defining a first light receiving region; a first light receiving region including first to fourth side surfaces arranged clockwise in a top view; a shallow partition feature in the substrate and adjacent to the first face, the shallow partition feature defining a first active feature in the first light receiving region, and the first active feature having, in a top view, a first active region adjacent to the first side surface and a second active region adjacent to the second side surface; and a reset gate electrode on the first active component.

Description

Technical Field

[0001] The various example embodiments in this article relate to image sensors. Background Technology

[0002] An image sensor is a semiconductor device that converts optical images into electrical signals. Image sensors can be classified into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CMOS image sensors are abbreviated as CIS. A CIS consists of multiple pixels arranged in two dimensions. Each pixel includes a photodiode (PD). The photodiode is used to convert incident light into an electrical signal. Summary of the Invention

[0003] Various example embodiments provide image sensors capable of delivering clear image quality.

[0004] Various exemplary embodiments of the present invention provide an image sensor comprising: a substrate including a first surface and a second surface opposite to each other; a deep partition member located in the substrate and defining a first light-receiving region; the first light-receiving region including a first side surface to a fourth side surface arranged clockwise in a top view; a shallow partition member located in the substrate and adjacent to the first surface, the shallow partition member defining a first active component in the first light-receiving region, and the first active component having a first active region adjacent to the first side surface and a second active region adjacent to the second side surface in a top view; and a reset gate electrode located on the first active component. The reset gate electrode includes a first gate portion located on the first active region and a second gate portion located on the second active region, and the first gate portion and the second gate portion are connected to each other.

[0005] In various exemplary embodiments of the present invention, an image sensor includes: a substrate having a first surface and a second surface opposite to each other; a deep separating member located in the substrate and defining a first light-receiving region; a shallow separating member located in the substrate and adjacent to the first surface, the shallow separating member defining a first active member and a second active member in the first light-receiving region, and the first active member having an "L" shape in a top view; a reset gate electrode located on the first active member; a transfer gate electrode located on the second active member; and a floating diffusion region located in the second active member adjacent to the transfer gate electrode. The first active member includes a channel region overlapping the reset gate electrode and a first impurity region not overlapping the reset gate electrode; and a first distance between the second active member and the first impurity region is greater than a second distance between the second active member and the channel region.

[0006] In various exemplary embodiments of the present invention, an image sensor includes: a substrate including a first surface and a second surface opposite to each other; a deep partition member located in the substrate and separating a first group of regions and a second group of regions arranged side-by-side along a first direction, such that the deep partition member is located in the first group of regions and the second group of regions and separates a first light-receiving region to an eighth light-receiving region, the first light-receiving region to the fourth light-receiving region being arranged clockwise and forming the first group of regions, and the fifth light-receiving region to the eighth light-receiving region being arranged clockwise and forming the second group of regions; a shallow partition member located in the substrate and adjacent to the first surface in the first light-receiving region to the eighth light-receiving region, the shallow partition member defining a first active component and a second active component in each of the first light-receiving region to the eighth light-receiving region; and a reset gate electrode located in the first light-receiving region to the eighth light-receiving region. The first active component in any of the fourth light receiving regions and having an "L" shape in a top view; a transfer gate electrode, the transfer gate electrode being disposed on the second active components of the first light receiving region to the eighth light receiving region respectively; a first floating diffusion region, the first floating diffusion region being located at the center of the first group of regions; a second floating diffusion region, the second floating diffusion region being located at the center of the second group of regions; a first line, the first line connecting the first floating diffusion region to the second floating diffusion region; an interlayer insulating layer, the interlayer insulating layer covering the first surface, the reset gate electrode, the transfer gate electrode and the first line; a first color filter, the first color filter being located on the second surface and covering the first group of regions; a second color filter, the second color filter being located on the second surface and covering the second group of regions; and a microlens, the microlens being disposed on the first color filter and the second color filter and overlapping the first light receiving region to the eighth light receiving region respectively. Attached Figure Description

[0007] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and form part of this specification. The drawings illustrate various exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings: Figure 1 This is a schematic layout of an image sensor according to various exemplary embodiments of the present invention; Figure 2 It is along Figure 1 A sectional view taken by line A-A'; Figure 3 It is along Figure 1 A sectional view taken by line B-B'; Figure 4 yes Figure 1 and Figure 3 A three-dimensional view of the transfer gate electrode; Figure 5 This is the layout of an image sensor according to various exemplary embodiments of the present invention; Figure 6 It is along Figure 5 A sectional view taken by line B-B'; Figure 7 This is the layout of an image sensor according to various exemplary embodiments of the present invention; Figure 8 This is a top view of an image sensor according to various exemplary embodiments of the present invention; Figure 9 This is the layout of an image sensor according to various exemplary embodiments of the present invention; Figure 10 These are various exemplary embodiments conceived according to the present invention. Figure 9 A sectional view taken by line C-C'; Figure 11 yes Figure 9 and Figure 10 The circuit diagram of the image sensor; Figure 12 This is the layout of an image sensor according to various exemplary embodiments of the present invention; Figure 13 This is a cross-sectional view of an image sensor according to various exemplary embodiments of the present invention; Figure 14 These are cross-sectional views of image sensors according to various exemplary embodiments of the present invention; and Figure 15 This is a cross-sectional view of an image sensor according to various exemplary embodiments conceived in accordance with the present invention. Detailed Implementation

[0008] In the following, various exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings in order to provide a more detailed description of the inventive concept. Throughout this document, terms such as first, second, etc., indicating order, are used to distinguish elements having the same / similar functions, and the ordinal numbers can be interchanged depending on the order in which the terms are mentioned. The term "impurity" may also be referred to as "dopant".

[0009] Figure 1 This is a schematic diagram of an image sensor according to various exemplary embodiments of the present invention. Figure 2 It is along Figure 1 A sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'. Figure 4 yes Figure 1and Figure 3 A three-dimensional view of the transfer gate electrode.

[0010] refer to Figures 1 to 4 The image sensor 100 of various exemplary embodiments of the present invention is provided with a substrate 1. The substrate 1 may include a plurality of light-receiving regions PX arranged in two dimensions along a first direction D1 and a second direction D2 that intersect each other. Figure 1 A light-receiving region PX is shown as an example. The substrate 1 may include a first surface 1a and a second surface 1b that are opposite to each other. Figure 10 Light can be incident on substrate 1 through the second surface 1b. Substrate 1 may be a silicon-on-insulator (SOI) substrate, an epitaxial layer, or a single-crystal wafer comprising silicon and / or germanium. However, the example embodiment is not limited thereto. Substrate 1 may be doped with an impurity of a first conductivity type. The first conductivity type may be, for example, p-type. The first conductivity type impurity may be, for example, boron. However, the example embodiment is not limited thereto.

[0011] Deep partition members 10 that isolate and define light-receiving regions PX from each other can be disposed in the substrate 1. In a top view, the deep partition members 10 may have a grid shape. The deep partition members 10 may include an isolation conductive pattern 14 disposed therein, an isolation insulating pattern 12 located between the isolation conductive pattern 14 and the substrate 1, and a first buried insulating pattern 16 located on the isolation conductive pattern 14. The deep partition members 10 may penetrate the substrate 1. The isolation conductive pattern 14 may be formed of doped polycrystalline silicon or metal. The isolation insulating pattern 12 and the first buried insulating pattern 16 may be formed of an insulating material such as silicon oxide. However, the exemplary embodiments are not limited thereto.

[0012] A photoelectric conversion component PD can be disposed in the light-receiving region PX within the substrate 1. The photoelectric conversion component PD can be doped with an impurity of a second conductivity type opposite to the first conductivity type. The second conductivity type can be, for example, N-type. The second conductivity type impurity can be, for example, phosphorus or arsenic. However, the example embodiment is not limited to this. The N-type impurity region of the photoelectric conversion component PD can form a PN junction with the peripheral P-type impurity region of the substrate 1, thereby constituting a photodiode, and electron-hole pairs can be generated through the PN junction when light is incident.

[0013] A shallow partition 20 may be disposed in the light-receiving region PX adjacent to a first surface 1a of the substrate 1, and defines a first active component ACT1 and a second active component ACT2. The shallow partition 20 may be formed using a shallow trench isolation (STI) method. The shallow partition 20 may include a first insulating pad 21, a second insulating pad 23, and a second buried insulating pattern 25 stacked sequentially. The second insulating pad 23 may include a material different from the material of the first insulating pad 21 and the second buried insulating pattern 25. For example, the second insulating pad 23 may be formed of silicon nitride, and the first insulating pad 21 and the second buried insulating pattern 25 may be formed of silicon oxide. A deep partition 10 may penetrate the shallow partition 20. No interface is observed between the deep partition 10 and the shallow partition 20.

[0014] In the top view, the light receiving area PX may have first sidewalls SW1 to fourth sidewalls SW4 arranged clockwise in sequence. The third sidewall SW3 and the fourth sidewall SW4 may be disconnected and not connected to each other.

[0015] In a top view, the first active component ACT1 may have an "L" shape or a rotated "L" shape. Specifically, the first active component ACT1 includes a first active region AR1 that is elongated in the first direction D1 and adjacent to the first sidewall SW1, and a second active region AR2 that is elongated in the second direction D2 and adjacent to the second sidewall SW1. The first active region AR1 is connected to the second active region AR2.

[0016] refer to Figure 1 and Figure 2 A reset gate electrode RG is disposed on the first active component ACT1. The reset gate electrode RG can be formed of, for example, doped polysilicon. However, the example embodiment is not limited thereto. The lower surface of the reset gate electrode RG is located on the first surface 1a. The sidewalls of the reset gate electrode RG can be covered by a gate spacer SP. The gate spacer SP can be formed of, for example, silicon nitride. However, the example embodiment is not limited thereto. A gate insulating layer Gox can be disposed between the reset gate electrode RG and the substrate 1. The gate insulating layer Gox can comprise a single layer or multiple layers of at least one of silicon oxide, metal oxide, silicon nitride, or silicon oxynitride. However, the example embodiment is not limited thereto.

[0017] In a top view, the reset gate electrode RG can have an "L" shape or a rotated "L" shape. The reset gate electrode RG includes a first gate portion GP1 located on a first active region AR1 and a second gate portion GP2 located on a second active region AR2. The first gate portion GP1 is connected to the second gate portion GP2. The planar shape of the reset gate electrode RG with a bent structure can increase the channel length, thereby limiting or preventing short-channel effects. As the size of the light-receiving region PX decreases, this planar shape of the reset gate electrode RG can very effectively improve the performance of the image sensor.

[0018] The first active region AR1 may include a first channel region CH1 that overlaps with the first gate portion GP1 and a first impurity region IM1 that does not overlap with the first gate portion GP1. The first channel region CH1 may overlap with a gate spacer SP that extends laterally from the first gate portion GP1 and covers the sidewall of the first gate portion GP1.

[0019] The second active region AR2 may include a second channel region CH2 overlapping with the second gate portion GP2 and a second impurity region IM2 not overlapping with the second gate portion GP2. The second channel region CH2 may overlap with a gate spacer SP that extends laterally from the second gate portion GP2 and covers the sidewall of the second gate portion GP2. The second channel region CH2 is connected to the first channel region CH1.

[0020] The second channel region CH2 may have a first width W1 in the first direction D1. The second impurity region IM2 may have a second width W2 in the first direction D1. In various example embodiments, the first width W1 is equal to the second width W2.

[0021] The first channel region CH1 may have a third width W3 in the second direction D2. The first impurity region IM1 may have a fourth width W4 in the second direction D2. In various example embodiments, the third width W3 is equal to the fourth width W4.

[0022] The first impurity region IM1 and the second impurity region IM2 may be doped with impurities of a second conductivity type that is opposite to the first conductivity type of the impurities doped in the substrate 1. The second conductivity type may be, for example, N-type.

[0023] One of the first impurity region IM1 and the second impurity region IM2 can be connected to the floating diffusion region FD or a capacitor used to store electrons in the floating diffusion region FD. A power supply voltage Vpix can be applied to the other of the first impurity region IM1 and the second impurity region IM2.

[0024] The second active component ACT2 may be adjacent to the third sidewall SW3 and the fourth sidewall SW4. The second active component ACT2 may be adjacent to the first active component ACT1 on a third direction D3 orthogonal to the first direction D1 and the second direction D2.

[0025] In various example embodiments, the first distance DS1 between the second active component ACT2 and the second impurity region IM2 can be equal to the second distance DS2 between the second active component ACT2 and the second channel region CH2. The third distance DS3 between the second active component ACT2 and the first impurity region IM1 can be equal to the fourth distance DS4 between the second active component ACT2 and the first channel region CH1.

[0026] refer to Figure 1 , Figure 3 and Figure 4 A transfer gate electrode TG is disposed on the second active component ACT2. The transfer gate electrode TG can be formed of polysilicon doped with impurities. However, the example embodiment is not limited thereto. The transfer gate electrode TG includes a plurality of insertion components Tp1 and Tp2 inserted into the substrate 1 and a connecting component Tc connecting the plurality of insertion components Tp1 and Tp2. Insertion components Tp1 and Tp2 may include a first insertion component Tp1 and a second insertion component Tp2. The first insertion component Tp1 and the second insertion component Tp2 may be spaced apart from each other in a fourth direction D4 intersecting the first direction D1 to the third direction D3. The connecting component Tc may be disposed on the first surface 1a of the substrate 1 and is elongated in the fourth direction D4. The first insertion component Tp1, the second insertion component Tp2 and the connecting component Tc may be integrated with each other. The upper portions of the first insertion component Tp1 and the second insertion component Tp2 may be wider than their lower portions, respectively.

[0027] The upper portion of each of the first insertion member Tp1 and the second insertion member Tp2 may have a sidewall protrusion Tw that protrudes toward and overlaps with the shallow separator 20. The connecting member Tc may have a fifth width W5 in the first direction D1. The second insertion member Tp2 may have a sixth maximum width W6 in the first direction D1. The sixth maximum width W6 may be greater than the fifth width W5. The sidewall of the connecting member Tc may be covered by a gate spacer SP. The gate spacer SP may contact the upper surfaces of the first insertion member Tp1 and the second insertion member Tp2. Figure 3 In the middle, the upper surface of the shallow partition 20 may have a seventh width W7 in the first direction D1.

[0028] A gate insulating layer Gox may be located between the first insertion member Tp1 and the second insertion member Tp2 and the substrate 1. The gate insulating layer Gox may be formed of, for example, silicon oxide. An insulating pattern RP may be located between the shallow separator 20 and the sidewall protrusion Tw of each of the first insertion member Tp1 and the second insertion member Tp2. The insulating pattern RP may be formed of the same material as the gate spacer SP. The insulating pattern RP may be connected to the gate spacer SP.

[0029] The floating diffusion region FD can be disposed in the second active component ACT2 on one side of the transfer gate electrode TG. The floating diffusion region FD can be doped with an impurity of a second conductivity type opposite to the first conductivity type of the impurity doped in the substrate 1. The second conductivity type can be, for example, N-type.

[0030] The first surface 1a of substrate 1, the transfer gate electrode TG, and the reset gate electrode RG can be covered by an etch stop layer 3. A first interlayer insulating layer IL1 is disposed on the etch stop layer 3. The etch stop layer 3 can be formed of silicon nitride. The first interlayer insulating layer IL1 can be formed of, for example, silicon oxide. However, the example embodiment is not limited thereto. A first contact plug CT1 can penetrate the first interlayer insulating layer IL1 and the etch stop layer 3 and can contact the transfer gate electrode TG. A second contact plug CT2 can penetrate the first interlayer insulating layer IL1 and the etch stop layer 3 and can contact the first impurity region IM1. A third contact plug CT3 can penetrate the first interlayer insulating layer IL1 and the etch stop layer 3 and can contact the second impurity region IM2. Capacitor CC3 ( Figure 11 It can be connected to the second contact plug CT2 or the third contact plug CT3.

[0031] Figure 5 This is the layout of an image sensor according to various exemplary embodiments of the present invention. Figure 6 It is along Figure 5 A sectional view taken along line B-B'. Figure 5 The cross section intercepted by line A-A' can be compared with... Figure 2 The same as shown.

[0032] refer to Figure 5 and Figure 6 The image sensor 101 according to various example embodiments can be related to the shape of the first active component ACT1. Figure 1 The image sensors differ. In various example embodiments, a power supply voltage Vpix can be applied to the first impurity region IM1. A capacitor for storing electrons in the floating diffusion region FD can be connected to the second impurity region IM2. The second impurity region IM2 can have a second width W2. The second channel region CH2 can have a first width W1. The second width W2 can be smaller than the first width W1.

[0033] The first distance DS1 between the second impurity region IM2 and the second active component ACT2 can be greater than the second distance DS2 between the second channel region CH2 and the second active component ACT2. The second impurity region IM2 is separated from the transfer gate electrode TG by a fifth distance DS5. The fifth distance DS5 can be greater than the second distance DS2. Figure 6 In the middle, the upper surface of the shallow partition member 20 may have an eighth width W8 in the first direction D1. The eighth width W8 may be greater than Figure 3 The seventh width, W7.

[0034] Due to the shape of the first active component ACT1, the second impurity region IM2 can be further away from the second active component ACT2 or the transfer gate electrode TG. Therefore, interference between the transfer gate electrode TG and the second impurity region IM2 can be reduced or suppressed, thereby reducing or preventing leakage current in the second impurity region IM2. Thus, the image sensor is able to provide a clear image, thereby reducing or preventing defects such as white spots. Other structures can be referenced. Figures 1 to 4 The structures described are the same or similar.

[0035] Figure 7 This describes the layout of an image sensor according to various exemplary embodiments conceived in accordance with the present invention. Along... Figure 7 The cross section intercepted by line A-A' can be compared with... Figure 2 The same as shown. Along Figure 7 The cross section intercepted by line B-B' can be compared with... Figure 6 The same as shown.

[0036] refer to Figure 7 In the image sensor 102 according to various example embodiments, the fourth width W4 of the first impurity region IM1 may be smaller than the third width W3 of the first channel region CH1. The third distance DS3 between the first impurity region IM1 and the second active component ACT2 may be greater than the fourth distance DS4 between the first channel region CH1 and the second active component ACT2. The sixth distance DS6 between the transfer gate electrode TG and the first impurity region IM1 may be greater than the fourth distance DS4. Other structures may be referenced. Figure 5 and Figure 6 The structures described are the same.

[0037] Due to the shape of the first active component ACT1, and Figure 5 Compared to the previous scenario, the first impurity region IM1 can be farther away from the second active component ACT2 or the transfer gate electrode TG. Therefore, interference between the transfer gate electrode TG and the first impurity region IM1 can be reduced or suppressed. Thus, an image sensor capable of providing a clear image can be realized.

[0038] Figure 8This is a top view of an image sensor according to various exemplary embodiments conceived in accordance with the present invention.

[0039] refer to Figure 8 The image sensor 103 according to various example embodiments may include a first group of regions GRP1, a second group of regions GRP2, and a third group of regions GRP3 arranged in two dimensions along a first direction D1 and a second direction D2. The first group of regions GRP1 and the second group of regions GRP2 may be arranged alternately in odd-numbered rows. The second group of regions GRP2 and the third group of regions GRP3 may be arranged alternately in even-numbered rows. Each of the first group of regions GRP1, the second group of regions GRP2, and the third group of regions GRP3 may include a 2×2 array of light-receiving regions PX. A deep partition 10 may isolate the first group of regions GRP1, the second group of regions GRP2, and the third group of regions GRP3 from each other. In a top view, the deep partition 10 may isolate the light-receiving regions PX from each of the group regions GRP1, GRP2, and GRP3 by being inserted into each of them. However, since the deep partition 10 is cut at the center of each of the group regions GRP1, GRP2, and GRP3, the light-receiving regions PX belonging to one group of regions may be connected to each other. The first group of regions GRP1 can be covered by the first color filter CF1. The second group of regions GRP2 can be covered by the second color filter CF2. The third group of regions GRP3 can be covered by the third color filter CF3. The first color filter CF1 can have one color, for example, red, green, and blue. The second color filter CF2 can have another color, among red, green, and blue. The third color filter CF3 can have the remaining color, among red, green, and blue. Microlenses ML can be arranged on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The microlenses ML can correspond to and overlap with the light receiving regions PX respectively. That is, one microlens ML is set on one light receiving region PX. A 2×2 array of microlenses ML can be arranged on a group of regions GRP1, GRP2, or GRP3. This array of microlenses ML can increase the light collection rate of each light receiving region PX, thereby enabling a clear image.

[0040] Figure 9 This is the layout of an image sensor according to various exemplary embodiments of the present invention. Figure 10 These are various exemplary embodiments conceived according to the present invention. Figure 9 A sectional view taken by line C-C'. Figure 11 yes Figure 9 and Figure 10 Circuit diagram of the image sensor. Figure 9 The top view can correspond to Figure 8 Part of it.

[0041] refer to Figures 9 to 11 The image sensor 104 according to various example embodiments includes three group regions GRP1(1), GRP2, and GRP1(2) arranged along a second direction D2. A second group region GRP2 may be disposed between the first group regions GRP1(1) and GRP1(2). Each group region GRP1(1), GRP2, and GRP1(2) includes a 2×2 array of clockwise arranged light-receiving regions PX. The first group regions GRP1(1) and GRP1(2) each include a first light-receiving region PX(1) to a fourth light-receiving region PX(4) arranged clockwise. The second group region GRP2 includes a fifth light-receiving region PX(5) to an eighth light-receiving region PX(8) arranged clockwise.

[0042] A photoelectric conversion component PD can be disposed in the substrate 1 in each of the first light receiving regions PX(1) to the eighth light receiving regions PX(8). A shallow partition component 20 is disposed adjacent to a first surface 1a of the substrate 1 in each of the first light receiving regions PX(1) to the eighth light receiving regions PX(8) to define active components ACT1 to ACT4. The second light receiving regions PX(2) to the seventh light receiving regions PX(7) each include the first active component ACT1. In a top view, the first active component ACT1 may have an "L" shape or a rotated "L" shape.

[0043] Each of the first optical receiving regions PX(1) to the eighth optical receiving region PX(8) includes a second active component ACT2. The second active component ACT2 may be arranged near the center of each of the group regions GRP1(1), GRP2 and GRP1(2). The second active components ACT2 may be connected to each other at the center of each of the group regions GRP1(1), GRP2 and GRP1(2).

[0044] The first optical receiving region PX(1) and the eighth optical receiving region PX(8) include a third active component ACT3 and a fourth active component ACT4. The third active component ACT3 may have an elongated strip shape in the first direction D1. The fourth active component ACT4 may have an elongated strip shape in the second direction D2. The first active component ACT1, the third active component ACT3 and the fourth active component ACT4 may be arranged adjacent to the edge of each of the group regions GRP1(1), GRP2 and GRP1(2).

[0045] The transfer gate electrode TG and the floating diffusion region FD can be arranged on the second active component ACT2 of the first light receiving region PX(1) to the eighth light receiving region PX(8). The transfer gate electrode TG and the floating diffusion region FD disposed on one side thereon can constitute a transfer transistor TX. The first common floating diffusion region FD1 is disposed at the center of each of the first group regions GRP1(1) and GRP1(2). The first common floating diffusion region FD1 is connected to the floating diffusion regions FD of the first light receiving region PX(1) to the fourth light receiving region PX(4). The second common floating diffusion region FD2 is disposed at the center of the second group region GRP2. The second common floating diffusion region FD2 is connected to the floating diffusion regions FD of the fifth light receiving region PX(5) to the eighth light receiving region PX(8). FD contact plugs FC can be disposed on the first common floating diffusion region FD1 and the second common floating diffusion region FD2, respectively. FD connection lines FDL can be disposed on the first interlayer insulating layer IL1 of the first surface 1a of the substrate 1 to connect two adjacent FD contact plugs FC. Therefore, the first common floating diffusion area FD1 and the second common floating diffusion area FD2 of two adjacent groups of regions in the second direction D2 can be connected to each other. That is, the first common floating diffusion area FD1 of the rear group of regions GRP1(1) and GRP1(2) and the second common floating diffusion area FD2 of the second group of regions GRP2 can be connected to each other through an FD connecting line FDL. The first common floating diffusion area FD1 of the front group of regions GRP1(1) and GRP1(2) is connected to the second common floating diffusion area FD2 of the other group of regions GRP2 through another FD connecting line FDL.

[0046] The selected gate electrode SEL can be disposed on the third active component ACT3 of the first light receiving region PX(1). The fourth active component ACT4 of the eighth light receiving region PX(8) can be doped with a second conductivity type impurity and used as a capacitor. Although not shown, a dummy gate electrode can be disposed on the fourth active component ACT4 of the eighth light receiving region PX(8).

[0047] The grounding region GN can be disposed in the fourth active component ACT4 of the first light receiving region PX(1) and the eighth light receiving region PX(8). The grounding region GN can be disposed in the substrate 1 and doped with impurities of a first conductivity type similar to those in the substrate 1. However, the concentration of the first conductivity type impurities in the grounding region GN can be higher than the concentration of the first conductivity type impurities in the substrate 1.

[0048] The reset gate electrode RG can be disposed on the first active component ACT1 of the second optical receiving region PX(2). The planar shapes of the first active component ACT1 and the reset gate electrode RG can be the same as those of the reference component ACT1. Figure 1 and Figure 2 The description is the same.

[0049] The third source follower gate electrode SF3 is disposed on the first active component ACT1 of the third light receiving region PX (3). The second source follower gate electrode SF2 is disposed on the first active component ACT1 of the fourth light receiving region PX (4). The first source follower gate electrode SF1 is disposed on the first active component ACT1 of the fifth light receiving region PX (5). The first dual-conversion gain gate electrode DCG1 is disposed on the first active component ACT1 of the sixth light receiving region PX (6). The second dual-conversion gain gate electrode DCG2 is disposed on the first active component ACT1 of the seventh light receiving region PX (7). In the top view, the first source follower gate electrode SF1 to the third source follower gate electrode SF3, as well as the first dual-conversion gain gate electrode DCG1 and the second dual-conversion gain gate electrode DCG2, can each have an "L" shape or a rotated "L" shape. Therefore, short-channel effects can be reduced or prevented, and clear images can be achieved in a highly integrated image sensor.

[0050] refer to Figure 9 and Figure 11 The second source follower transistor S2, which includes the second source follower gate electrode SF2 in the first group region GRP1(1) located at the rear, the third source follower transistor S3, which includes the third source follower gate electrode SF3 in the first group region GRP1(1), and the first source follower transistor S1, which includes the first source follower gate electrode SF1 in the second group region GRP2, can be connected in parallel with each other. The first source follower gate electrode SF1, the second source follower gate electrode SF2, and the third source follower gate electrode SF3 can be connected to the FD connection line FDL, which connects the first common floating diffusion region FD1 in the first group region GRP1(1) located at the rear and the second common floating diffusion region FD2 in the second group region GRP2. The FD connection line FDL can extend above the first source follower gate electrode SF1, the second source follower gate electrode SF2, and the third source follower gate electrode SF3 and overlap with the first source follower gate electrode SF1, the second source follower gate electrode SF2, and the third source follower gate electrode SF3.

[0051] One terminal of each of the first source follower transistors S1 to the third source follower transistors S3 can be connected to a terminal of the select transistor SE, which includes the select gate electrode SEL located on the front first group region GRP1(2). Since the first source follower transistors S1 to the third source follower transistors S3 are connected in parallel, thermal noise and flicker noise can be reduced, and thus clear image quality can be achieved.

[0052] The first dual-conversion gain transistor DCX1, including the first dual-conversion gain gate electrode DCG1 located on the second group region GRP2, the second dual-conversion gain transistor DCX2, including the second dual-conversion gain gate electrode DCG2 located on the second group region GRP2, and the reset transistor RX, including the reset gate electrode RG located on the front first group region GRP1(2), can be connected in series with each other. The FD connection line FDL can be connected to the impurity region (or drain region) on one side of the first dual-conversion gain gate electrode DCG1. The FD connection line FDL can extend to the impurity region on one side of the first dual-conversion gain gate electrode DCG1 and overlap with the impurity region.

[0053] The first capacitor CC1 can be connected to the impurity region on one side of the first double-conversion gain gate electrode DCG1. The second capacitor CC2 can be connected to the impurity region on one side of the second double-conversion gain gate electrode DCG2. The third capacitor CC3 can be connected to the impurity region IM1 or IM2 on one side of the reset gate electrode RG. The first capacitor CC1 to the third capacitor CC3 can be, for example, metal-insulator-metal (MIM) type capacitors.

[0054] In the image sensor 104 according to various example embodiments, electrons (charges) corresponding to incident light can be generated and accumulated in the photoelectric conversion component PD. When at least one transfer transistor TX of the first set of regions GRP1(1) located behind is turned on, the voltage level of the first common floating diffusion region FD1 connected thereto can be determined. The reset transistor RX can reset the first common floating diffusion region FD1. For example, with the first dual conversion gain transistor DCX1 and the second dual conversion gain transistor DCX2 turned on, the reset transistor RX can electrically connect the first common floating diffusion region FD1 to the power supply voltage Vpix based on an electrical signal (reset signal) applied to the reset gate electrode RG. The reset transistor RX can remove or discharge electrons stored in the first common floating diffusion region FD1 by setting the voltage level of the first common floating diffusion region FD1 to the power supply voltage Vpix based on the reset signal.

[0055] The gate electrodes SF1 to SF3 of the first source follower transistors S1 to S3 can be connected to the first common floating diffusion region FD1. The first source follower transistors S1 to S3 can output an output signal Vout to the selection transistor SE based on the voltage level of the first common floating diffusion region FD1. The conversion gain can vary in response to the on / off state of the first dual conversion gain transistor DCX1 and the second dual conversion gain transistor DCX2.

[0056] After detecting the optical signal of the optical receiving region PX in the first group of regions GRP1(1) located behind, the optical signal of the optical receiving region PX in the second group of regions GRP2 can be detected by repeating the above process.

[0057] Return to reference Figure 10 The first wire M1 can be arranged on the first interlayer insulation layer IL1. The second interlayer insulation layer IL2 and the third interlayer insulation layer IL3 can be arranged sequentially on the first interlayer insulation layer IL1. The second wire M2 can be arranged between the second interlayer insulation layer IL2 and the third interlayer insulation layer IL3.

[0058] A fixed charge layer 24 may be disposed on and in contact with the second surface 1b. The fixed charge layer 24 may be in contact with the second surface 1b. The fixed charge layer 24 may comprise a metal oxide layer or a metal fluoride layer, comprising oxygen or fluorine in insufficient amounts compared to the stoichiometric ratio. Therefore, the fixed charge layer 24 may have a negative fixed charge. The fixed charge layer 24 may be formed of a metal oxide or metal fluoride comprising at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, lanthanides, and combinations thereof. However, the exemplary embodiment is not limited thereto. Hole accumulation may occur near the fixed charge layer 24. Therefore, the occurrence of dark current and white spots can be effectively reduced. The fixed charge layer 24 may be at least one of an aluminum oxide layer or a hafnium oxide layer.

[0059] An antireflective layer 42 may be disposed on a fixed charge layer 24. The antireflective layer 42 may include, for example, silicon nitride. However, the exemplary embodiment is not limited thereto. A first grid pattern 48a and a second grid pattern 50a may be stacked sequentially on the antireflective layer 42. In a top view, the first grid pattern 48a and the second grid pattern 50a may have a grid shape. The first grid pattern 48a and the second grid pattern 50a may expose the antireflective layer 42. Color filters CF1 and CF2 may be disposed beneath the antireflective layer 42. Microlenses ML may be disposed on the color filters CF1 and CF2.

[0060] The first grid pattern 48a may include an opaque material, such as titanium. However, the example embodiment is not limited thereto. The sidewalls of the second grid pattern 50a may be aligned with the sidewalls of the first grid pattern 48a. The first grid pattern 48a and the second grid pattern 50a may reduce or prevent crosstalk between adjacent light-receiving areas. The second grid pattern 50a may include an organic material. The second grid pattern 50a may have a lower refractive index than color filters CF1 and CF2. For example, the second grid pattern 50a may have a refractive index of approximately 1.3 or less. Other structures may be the same as / similar to those described above.

[0061] Figure 12 This is the layout of an image sensor according to various exemplary embodiments of the present invention.

[0062] refer to Figure 12 In the image sensor 105 according to various example embodiments, the first active component ACT1 in the second light receiving region PX(2), on which a reset gate electrode RG is disposed, can have the same characteristics as... Figure 7 The first active component ACT1 has the same shape. The first active component ACT1, on which the first dual-conversion gain gate electrode DCG1 is disposed in the sixth optical receiving region PX(6), can have... Figure 7 The first active component ACT1 rotated shape. The first active component ACT1 in the seventh light receiving region PX(7), on which the second dual-conversion gain gate electrode DCG2 is disposed, can have Figure 7 The first active component ACT1 rotates to the desired shape. In various example embodiments, due to the first active component ACT1 of the second light receiving region PX(2), the sixth light receiving region PX(6), and the seventh light receiving region PX(7) being rotated... Figure 7 The first active component ACT1 has the same shape, so interference caused by the transfer gate electrode TG can be prevented / reduced, thereby preventing / reducing leakage current of capacitors CC1 to CC3. Therefore, clear image quality can be achieved. At least one of the first active components ACT1 of the second light receiving region PX(2), the sixth light receiving region PX(6), and the seventh light receiving region PX(7) can have Figure 5 The shape of the first active component ACT1.

[0063] Figure 13 This is a cross-sectional view of an image sensor according to various exemplary embodiments conceived in accordance with the present invention.

[0064] refer to Figure 13The image sensor 106 of various exemplary embodiments of the present invention may include a substrate 1 having a main region APS, an optical black region OB and a pad region PR, a wiring layer 200 located on a first surface 1a of the substrate 1 and a base substrate 400 located on the wiring layer 200.

[0065] Routing layer 200 may have an upper routing layer 221 and a lower routing layer 223. The main area APS may include a reference. Figures 1 to 12 The light-receiving region PX is described.

[0066] The first connection structure 250, the first conductive pad 81, and the main color filter 90 can be disposed on the substrate 1 in the optical black region OB. The first connection structure 250 may include a first light-shielding pattern 51, an insulating pattern 53, and a first cover pattern 55. The first light-shielding pattern 51 may be formed of a conductive material. The first light-shielding pattern 51 may include, for example, titanium or tungsten. However, the example embodiment is not limited thereto.

[0067] The first light-shielding pattern 51 can be disposed on the second surface 1b of the substrate 1. The first light-shielding pattern 51 can conformally cover the inner walls of the third trench TR3 and the fourth trench TR4. The first light-shielding pattern 51 can penetrate the photoelectric conversion layer 150 and the upper wiring layer 221, and connect the photoelectric conversion layer 150 to the wiring layer 200.

[0068] The first light-blocking pattern 51 can be combined with Figure 3 The deep-seated component 10 contacts the isolation conductive pattern 14. The first conductive pad 81 can be electrically connected to the isolation conductive pattern 14 of the deep-seated component 10. The first light-shielding pattern 51 can block light incident on the optical black area OB.

[0069] The first conductive pad 81 can be disposed in the third trench TR3 and can fill the remaining portion of the third trench TR3. The first conductive pad 81 can include a metallic material, such as aluminum. However, the example embodiment is not limited thereto. A negative bias voltage can be applied to the isolation conductive pattern 14 through the first conductive pad 81. Therefore, the occurrence of dark current or white spots can be prevented / reduced.

[0070] The insulating pattern 53 can fill the remaining portion of the fourth trench TR4. The insulating pattern 53 can completely or partially penetrate the photoelectric conversion layer 150 and the wiring layer 200. The first cover pattern 55 can be disposed on the upper surface of the insulating pattern 53. The first cover pattern 55 can be disposed on the insulating pattern 53.

[0071] The main color filter 90 can be disposed on the first conductive pad 81, the first light-shielding pattern 51, and the first cover pattern 55. The main color filter 90 can cover the first conductive pad 81, the first light-shielding pattern 51, and the first cover pattern 55. The first protective layer 71 can be disposed on the main color filter 90 and seal the main color filter 90.

[0072] Multiple light-receiving regions PX can also be arranged within an optical black area OB, and a first reference photoelectric conversion component PD' and a second reference region 111 can be arranged within these light-receiving regions PX. The first reference photoelectric conversion component PD' provides a first reference charge amount that can be generated when light is blocked. The first reference charge amount can be used as a relative reference value when calculating the charge amount generated from the light-receiving regions PX. The second reference region 111 provides a second reference charge amount that can be generated when the photoelectric conversion component PD is not present. The second reference charge amount can be used as information for removing process noise.

[0073] The second connection structure 60, the second conductive pad 83, and the second protective layer 73 can be disposed on the substrate 1 in the pad area PR. The second connection structure 60 may include a second light-shielding pattern 61, an insulating pattern 63, and a second cover pattern 65.

[0074] The second light-shielding pattern 61 can be disposed on the second surface 1b of the substrate 1. The second light-shielding pattern 61 can conformally cover the inner walls of the fifth trench TR5 and the sixth trench TR6. The second light-shielding pattern 61 can penetrate the photoelectric conversion layer 150 and the upper wiring layer 221, and connect the photoelectric conversion layer 150 to the wiring layer 200. The second light-shielding pattern 61 can contact the lines in the lower wiring layer 223. The second light-shielding pattern 61 can be electrically connected to the lines in the wiring layer 200. The second light-shielding pattern 61 can include a metallic material, such as titanium or tungsten. However, the example embodiment is not limited thereto.

[0075] The second conductive pad 83 may be disposed in the fifth trench TR5 and may fill the remaining portion of the fifth trench TR5. The second conductive pad 83 may include a metallic material, such as aluminum. However, the example embodiment is not limited thereto. The second conductive pad 83 may serve as an electrical connection path to the outside of the image sensor device. The insulating pattern 63 may fill the remaining portion of the sixth trench TR6. The insulating pattern 63 may completely or partially penetrate the photoelectric conversion layer 150 and the wiring layer 200. The second cover pattern 65 may be disposed on the insulating pattern 63. The second protective layer 73 may cover a portion of the second light-shielding pattern 61 and the second cover pattern 65.

[0076] refer to Figures 1 to 12 The described image sensor structure can also be applied to, for example... Figure 14 and Figure 15The image sensor shown has a 3-chip structure.

[0077] Figure 14 This is a cross-sectional view of an image sensor according to various exemplary embodiments conceived in accordance with the present invention.

[0078] refer to Figure 14 The image sensor 107 according to various example embodiments may have a structure in which first sub-chips DE1 to third sub-chips DE3 are stacked sequentially. In this specification, "sub-chip" may be referred to as "semiconductor chip". The first sub-chip DE1 includes a first substrate SB1 and a first interlayer insulating layer IL1 covering the front side of the first substrate SB1. The first substrate SB1 may be a semiconductor substrate or an insulating substrate. The first interlayer insulating layer IL1 may have a single-layer structure or a multi-layer structure of at least one of SiO2, SiN, SiCN, SiON, or SiOCH. However, the example embodiments are not limited thereto. Logic circuitry may be arranged in the first sub-chip DE1. The logic circuitry may include row drivers, row decoders, column decoders, timing generators, correlated double samplers (CDS), analog-to-digital converters (ADCs), etc. A first peripheral transistor PTR1, a first contact plug CT1, and a first line IT1 may be arranged on the first substrate SB1 to constitute the logic circuitry. A first shallow partition ST1 may be disposed on the first substrate SB1 to define an active region for the first peripheral transistor PTR1. The first conductive pad CP1 can be placed on the upper end of the first interlayer insulating layer IL1.

[0079] The second sub-chip DE2 is bonded to the first sub-chip DE1. The second sub-chip DE2 may include a second substrate SB2. The front side SB2_F of the second substrate SB2 may be covered by a second interlayer insulating layer IL2. The front side SB2_F of the second substrate SB2 may face the first sub-chip DE1. Figure 11 The driving transistors RX, DCX1, DCX2, SX1 to SX3, and SE shown can be arranged on the front side SB2_F of the second substrate SB2 in the main region of the second sub-chip DE2. Each gate electrode RG, DCG1, DCG2, SF1, SF2, SF3, and SEL can have a planar or vertical shape. The driving transistors RX, DCX1, DCX2, SX1 to SX3, and SE can have a FinFET, a multi-bridge FET (MBCFET), or a gate-all-around FET (GAAFET) structure.

[0080] The second peripheral transistor PTR2 can be disposed on the front side SB2_F of the second substrate SB2 in the peripheral region of the second sub-chip DE2. A second shallow partition ST2 can be disposed on the front side SB2_F of the second substrate SB2 to define the active region for driving transistors RX, DCX1, DCX2, SX, and SE, as well as the second peripheral transistor PTR2. A second contact plug CT2 and a second line IT2 can be disposed in the second interlayer insulating layer IL2. A second conductive pad CP2 can be disposed at the lower end of the second interlayer insulating layer IL2. The lower surface of the second interlayer insulating layer IL2 can contact the upper surface of the first interlayer insulating layer IL1. The second conductive pad CP2 can contact the first conductive pad CP1 respectively. There may be no boundary surface between the second conductive pad CP2 and the first conductive pad CP1 that contacts the second conductive pad CP2 respectively, and the corresponding first conductive pads CP1 and second conductive pads CP2 can be integrated.

[0081] The rear side SB2_B of the second substrate SB2 can be sequentially covered by the first rear insulating layer BL1 and the second rear insulating layer BL2. The fourth line IT4 can be disposed in the second rear insulating layer BL2. The third conductive pad CP3 can be disposed at the upper end of the second rear insulating layer BL2. The via TV can penetrate the first rear insulating layer BL1, the second substrate SB2, the second shallow separator ST2, and a portion of the second interlayer insulating layer IL2, and can contact some of the second lines in the second line IT2. The via TV can taper downwards. The via insulating layer TL can be located between the via TV and the second substrate SB2.

[0082] The third sub-chip DE3 is bonded to the second sub-chip DE2. The third sub-chip DE3 includes a third substrate SB3. The third substrate SB3 may include a main region APS and an edge region ER. The main region APS may include multiple light-receiving regions PX. A deep separator 10 may be disposed in the third substrate SB3 and may isolate the light-receiving regions PX from each other. A photoelectric conversion component PD is disposed in each light-receiving region PX in the third substrate SB3. The front side SB3_F of the third substrate SB3 may face the second sub-chip DE2. A third shallow separator ST3 may be disposed on the front side SB3_F of the third substrate SB3 to define an active region for transferring transistor TX. Figure 11 ), and the grounding area GN.

[0083] The transfer gate electrode TG and the floating diffusion region FD can be arranged on the front side SB3_F of the third substrate SB3. The front side SB3_F of the third substrate SB3 can be covered by the third interlayer insulating layer IL3. The third contact plug CT3, FD connection line FDL, third line IT3, etc., can be arranged in the third interlayer insulating layer IL3. The FD connection line FDL can each connect to at least a portion of the floating diffusion region FD of multiple adjacent light receiving regions PX. The floating diffusion region FD of the third sub-chip DE3 can be connected to the source follower transistors SX1 to SX3 of the second sub-chip DE2, specifically the source follower gate electrodes SF1 to SF3.

[0084] The lower surface of the third interlayer insulating layer IL3 can contact the upper surface of the second rear insulating layer BL2 of the second sub-chip DE2. A fourth conductive pad CP4 can be disposed at the lower end of the third interlayer insulating layer IL3. The fourth conductive pad CP4 can contact the third conductive pad CP3. There can be no boundary surface between the fourth conductive pad CP4 and the third conductive pad CP3 that contacts the fourth conductive pad CP4, and corresponding third conductive pads CP3 and fourth conductive pads CP4 can be integrated.

[0085] The rear side SB3_B of the third substrate SB3 may be covered by a third back insulating layer FL. The third back insulating layer FL may include at least one of a fixed charge layer, an anti-reflection layer, a planarization layer, or a protective layer. The grid pattern WG, color filters CF1, CF2, and CF3, and microlens ML may be arranged on the third back insulating layer FL in the main region APS. The first optical black pattern BT, the second optical black pattern CFB, and the lens residue layer MLR may be arranged sequentially on the third back insulating layer FL in the edge region ER. The first optical black pattern BT may have the same material and the same thickness as the grid pattern WG. The second optical black pattern CFB may include a blue color filter. The lens residue layer MLR may have the same material as the microlens ML. Other structures may be the same as / similar to those described above.

[0086] Figure 15 This is a cross-sectional view of an image sensor according to various exemplary embodiments conceived in accordance with the present invention.

[0087] refer to Figure 15 The image sensor 108 according to various example embodiments may have a structure in which first sub-chips DE1 to third sub-chips DE3 are stacked sequentially. The first sub-chip DE1 may be connected to a reference... Figure 14 The first sub-chip described is the same as / similar to the first sub-chip. The second sub-chip DE2 and the third sub-chip DE3 can be compared with the reference. Figure 14The second and third sub-chips are described similarly. The second substrate SB2 can be a semiconductor substrate, an insulating substrate, or a silicon-on-insulator (SOI) substrate. The first conductive pad CP1 can be arranged on top of the first sub-chip DE1.

[0088] A substrate insulating layer SLL can be disposed within the second substrate SB2 of the second sub-chip DE2. A through-contact plug CCT can penetrate the second substrate SB2, a portion of the second interlayer insulating layer IL2, and a portion of the third interlayer insulating layer IL3, and connect the FD connection line FDL to the source follower gate electrodes SF1 to SF3. A through-contact insulating layer CCL can be located between the through-contact plug CCT and the second substrate SB2. A second conductive pad CP2 can be disposed at the lower end of the second sub-chip DE2. The second conductive pad CP2 can contact the first conductive pad CP1 respectively.

[0089] The input / output pad PA can be positioned on the third rear insulating layer FL within the edge region ER of the third sub-chip DE3. The path TV can penetrate the third substrate SB3 and the third interlayer insulating layer IL3 of the third sub-chip DE3, as well as the second substrate SB2 and a portion of the second interlayer insulating layer IL2 of the second sub-chip DE2, and connect the input / output pad PA to the second line IT2. Other structures can be referenced. Figure 14 The structures described are the same or similar.

[0090] In this specification, the concept of individual semiconductor chips (or sub-chips) can be defined by a stacked structure formed by several semiconductor wafers that are different from each other. Due to the bonding shape, bonding method, or bonding material between semiconductor chips, the interface between semiconductor chips may not be clearly observed, and stacked structures with ambiguous interfaces are not excluded from the concept of individual semiconductor chips.

[0091] Image sensors according to various exemplary embodiments conceived in this invention include a reset gate electrode with a bent structure in a top view to increase the channel length, thereby limiting or preventing short-channel effects. Furthermore, the planar shape of the first active component is modified such that the end of the first active component where the reset gate electrode is disposed is positioned further away from the second active component where the transfer gate electrode is disposed, thereby providing an image sensor that offers sharper image quality and can prevent or reduce defects such as white spots by reducing current leakage.

[0092] Although various exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, it will be readily understood by those skilled in the art that the exemplary embodiments may be implemented in other specific forms without altering the technical concept or essential characteristics. Therefore, the above exemplary embodiments should be considered illustrative and not construed as restrictive. Figures 1 to 15 The example embodiments can be combined with each other.

Claims

1. An image sensor, the image sensor comprising: The substrate includes a first side and a second side that are opposite to each other; A deep-separating component, the deep-separating component being located in the substrate and defining a first light-receiving region; A first light receiving area, the first light receiving area including a first side surface to a fourth side surface arranged clockwise in a top view; A shallow partition member is located in the substrate and adjacent to the first surface. The shallow partition member defines a first active member in the first light receiving region, and the first active member has a first active region adjacent to the first side surface and a second active region adjacent to the second side surface in a top view. and A reset gate electrode, which is located on the first active component. The reset gate electrode includes a first gate portion located on the first active region and a second gate portion located on the second active region. The first gate portion and the second gate portion are connected to each other.

2. The image sensor according to claim 1, wherein The deep-seated component also defines a second light-receiving area. The image sensor also includes a dual-conversion gain gate electrode located on the second light-receiving region, and The dual-conversion gain gate electrode has an "L" shape in the top view.

3. The image sensor according to claim 1, wherein The shallowly separated component also defines a second active component in the first light receiving region. The image sensor further includes a transfer gate electrode located on the second active component and a floating diffusion region located in the second active component. The second active component is located between the third side surface and the fourth side surface. The second active region includes a first channel region overlapping with the second gate portion and a first impurity region not overlapping with the second gate portion, and The first distance between the second active component and the first impurity region is greater than the second distance between the second active component and the first channel region.

4. The image sensor according to claim 3, wherein The first active region includes a second channel region overlapping the first gate portion and a second impurity region not overlapping the first gate portion, and The third distance between the second active component and the second impurity region is greater than the fourth distance between the second active component and the second channel region.

5. The image sensor according to claim 3, wherein, The fifth distance between the transfer gate electrode and the first impurity region is greater than the second distance.

6. The image sensor according to claim 3, wherein, The transfer gate electrode includes: Multiple insertion components, the multiple insertion components being located in the substrate and spaced apart from each other; and A connecting component, which is located on the substrate and connects the insertion components to each other.

7. The image sensor according to claim 6, wherein The upper portion of one of the insertion components has a first width in a first direction. The connecting member has a second width in the first direction, and The first width is greater than the second width.

8. The image sensor according to claim 6, further comprising: A spacer that covers the sidewall of the connecting member; and An insulating pattern is located between the shallow dividing member and the upper portion of one of the insert members. The spacers and the insulating pattern are made of the same material.

9. The image sensor according to claim 1, in, The deep-separation component further defines a second to a fourth light-receiving region adjacent to the first light-receiving region in the substrate. The first light-receiving area to the fourth light-receiving area are arranged clockwise and form a first group of areas. The shallowly spaced component is located in each of the first to fourth light-receiving regions and defines the second active component. The second active components are connected to each other at the center of the first set of regions, and The first active component is adjacent to the edge of the first set of regions.

10. The image sensor according to claim 9, further comprising: A first color filter is located on the second surface and covers the first set of areas; and Microlenses are arranged on the first color filter and overlap with the first light receiving area to the fourth light receiving area, respectively.

11. An image sensor, the image sensor comprising: The substrate includes a first side and a second side that are opposite to each other; A deep-separating component, the deep-separating component being located in the substrate and defining a first light-receiving region; A shallow partition member is located in the substrate and adjacent to the first surface. The shallow partition member defines a first active member and a second active member in the first light receiving region, and the first active member has an "L" shape in a top view. A reset gate electrode, wherein the reset gate electrode is located on the first active component; A transfer gate electrode, wherein the transfer gate electrode is located on the second active component; and A floating diffusion region, wherein the floating diffusion region is adjacent to the transfer gate electrode in the second active component. The first active component includes a channel region overlapping the reset gate electrode and a first impurity region not overlapping the reset gate electrode. The first distance between the second active component and the first impurity region is greater than the second distance between the second active component and the channel region.

12. The image sensor according to claim 11, wherein, The transfer gate electrode includes: Multiple insertion components, the multiple insertion components being located in the substrate and spaced apart from each other; and A connecting component, located on the substrate, connects the insertion components to each other. Wherein, the upper portion of one of the insertion components has a first width in a first direction. The connecting member has a second width in the first direction, and The first width is greater than the second width.

13. The image sensor of claim 12, further comprising: A spacer that covers the sidewall of the connecting member; and An insulating pattern is located between the shallow dividing member and the upper portion of one of the insert members. The spacers and the insulating pattern are made of the same material.

14. The image sensor according to claim 11, wherein, The reset gate electrode has an "L" shape in the top view.

15. The image sensor according to claim 11, in, The deep-seated component also defines a second light-receiving area. The image sensor also includes a dual-conversion gain gate electrode located on the second light-receiving region, and The dual-conversion gain gate electrode has an "L" shape in the top view.

16. An image sensor, the image sensor comprising: The substrate includes a first side and a second side that are opposite to each other; A deep partition component is located in the substrate and separates a first group of regions and a second group of regions arranged side by side along a first direction, such that the deep partition component is located in the first group of regions and the second group of regions and separates a first light receiving region to an eighth light receiving region, the first light receiving region to a fourth light receiving region being arranged clockwise and forming the first group of regions, and the fifth light receiving region to the eighth light receiving region being arranged clockwise and forming the second group of regions. A shallow partition member is located in the substrate and adjacent to the first surface in the first light receiving region to the eighth light receiving region, the shallow partition member defining a first active member and a second active member in each of the first light receiving region to the eighth light receiving region; A reset gate electrode, the reset gate electrode being located on the first active component in any one of the first light receiving regions to the fourth light receiving regions and having an "L" shape in a top view; Transfer gate electrodes are respectively arranged on the second active components in the first light receiving region to the eighth light receiving region; The first floating diffusion area is located at the center of the first group of areas; The second floating diffusion zone is located at the center of the second group of regions; A first line connects the first floating diffusion area to the second floating diffusion area; An interlayer insulating layer covers the first surface, the reset gate electrode, the transfer gate electrode, and the first line; A first color filter is located on the second surface and covers the first set of areas; A second color filter is located on the second surface and covers the second set of areas; and Microlenses are arranged on the first color filter and the second color filter and overlap with the first light receiving area to the eighth light receiving area, respectively.

17. The image sensor according to claim 16, wherein The second active component is arranged near the center of the first group of regions and the center of the second group of regions. The first active component is arranged adjacent to the edges of the first group of regions and the edges of the second group of regions, and At least one or more of the first active components have an "L" shape in a top view.

18. The image sensor according to claim 16, wherein The first active component in any one of the first light receiving region to the fourth light receiving region includes a first channel region overlapping the reset gate electrode and a first impurity region not overlapping the reset gate electrode. The first channel region has a first width in a second direction intersecting the first direction. The first impurity region has a second width in the second direction, and The second width is smaller than the first width.

19. The image sensor of claim 16, further comprising: A dual-conversion gain gate electrode, wherein the dual-conversion gain gate electrode is located on the first active component in any one of the fifth to eighth optical receiving regions; and The dual-conversion gain gate electrode has an "L" shape in the top view.

20. The image sensor of claim 19, wherein The first active component in any of the fifth to eighth optical receiving regions includes a second channel region overlapping the double-conversion gain gate electrode and a second impurity region not overlapping the double-conversion gain gate electrode. The second channel region has a third width in the second direction. The second impurity region has a fourth width in the second direction, and The fourth width is smaller than the third width.

Images