Current limiting circuit

Abstract

When a pulse current is input, the MOSFET for cutting off the current is quickly turned off. A current limiting circuit (1) is provided with: a metal oxide semiconductor field effect transistor (MOSFET) (M1) that is connected between an input terminal (T1) and an output terminal (T2) and that allows and interrupts the passage of a current (I1); a series circuit (SC1) connected between the source of the MOSFET (M1) and the output terminal (T2); and a transistor (Q1), the base of which is connected to a connection point between one end of the series circuit (SC1) and the source of the MOSFET (M1) via a resistor (R3), the collector of which is connected to the gate of the MOSFET (M1) via a resistor (R1), and the emitter of which is connected to the other end of the series circuit (SC1), the transistor (Q1) being connected to the gate of the MOSFET (M1) when a current (I1) exceeding a predetermined current value is supplied. And a current limiting circuit (1) that is driven by a voltage generated at one end of the series circuit (SC1) and limits the current value of the current (I1) passing through the MOSFET (M1), the current limiting circuit (1) being provided with a series circuit (SC2) that allows conduction of the current (I3) from the gate of the MOSFET (M1) toward the output terminal (T2).

Description

TECHNICAL FIELD

[0001] The present application relates to a current limiting circuit which drives a control element when a current exceeding a predetermined current value is supplied, thereby limiting the current value of a current passing through a MOSFET provided in a current supply path. BACKGROUND

[0002] For example, as such a current limiting circuit, there is known a current limiting circuit disclosed in Patent Literature 1. As shown in FIG. 1 of Patent Literature 1, the current limiting circuit 1X is configured to have a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) M1X of enhancement type, a transistor Q1X of bipolar type, a floating power supply PWX, an inductor L1X, and resistors R1X to R3X, a resistor R5X, and a resistor R6X. Figure 2

[0003] Specifically, in the current limiting circuit 1X, a drain of the MOSFET M1X as an element allowing and cutting off the passage of a current is connected to an input terminal side of a current supply path, and a source of the MOSFET M1X is connected to an output terminal side of the current supply path, and a gate of the MOSFET M1X is connected to one end of the resistor R1X, and the MOSFET M1X allows and cuts off the passage of a current supplied to the current supply path according to an application state of a bias voltage from the other end of the resistor R1X to the gate. Further, a series circuit of a parallel circuit of the inductor L1X and the resistor R6X and the resistor R2X is connected between the source of the MOSFET M1X and the output terminal of the current supply path. Further, a base of the transistor Q1X is connected to the source of the MOSFET M1X via the resistor R3X, a collector of the transistor Q1X is connected to the gate of the MOSFET M1X via the resistor R1X and to a positive electrode of the floating power supply PWX via the resistor R5X, and an emitter of the transistor Q1X is connected to a negative electrode of the floating power supply PWX. Further, the negative electrode of the floating power supply PWX is connected to the output terminal of the current supply path.

[0004] In the current limiting circuit 1X, in a normal state, the MOSFET M1X is biased by a bias voltage output from the floating power supply PWX to be kept in an on state. In this state, the current limiting circuit 1X allows the passage of a direct current input to the input terminal of the current supply path toward the output terminal.

[0005] ​On the other hand, when the current value of the supplied direct current exceeds the predetermined current value and rises, the direct current flows, and thus the voltage of the end portion of the resistance R3X side of the resistance R2X rises. At this time, the voltage of the base of the transistor Q1X rises, and thus the transistor Q1X becomes in the on state. In this state, the direct current from the floating power source PWX flows into the transistor Q1X via the resistance R5X, and the gate voltage (bias voltage) of the MOSFET M1X decreases. Thus, the MOSFET M1 is controlled to be in the off state, and thus the current value of the current passing through the MOSFET M1X is controlled. As a result, in the current limiting circuit 1X, the current value of the direct current flowing from the input end of the current supply path toward the output end can be limited to be equal to or less than the predetermined current value.

[0006] Prior Art Documents Patent Documents Patent Document 1: Japanese Patent Application Laid-Open No. 2006-84395 (pages 7-10, FIG. 4) SUMMARY PROBLEMS TO BE SOLVED BY THE INVENTION However, in the existing current limiting circuit 1X, there is a problem that, when a current of an excessively large current value is supplied to the input end side of the current supply path, the supply of the current of the excessively large current value cannot be limited at times. Specifically, for example, when an abnormality occurs in the protected device connected to the output end side of the current supply path, when a direct current voltage of an excessively large voltage value in a pulse shape is instantaneously input to the input end side of the current supply path, and the like, a current of an excessively large current value in a pulse shape (hereinafter, also referred to as "pulse current") that greatly exceeds the predetermined current value can be supplied to the input end side of the current supply path at times. In this case, in the current limiting circuit 1X, the pulse current flows through the resistance R2X, and the voltage difference between both ends of the resistance R2X becomes large, and when the transistor Q1X is to be in the on state, when the frequency of the pulse current is high, the transistor Q1X cannot be brought to the on state at a fast response speed according to the frequency characteristics thereof. Thus, in the current limiting circuit 1X, when the frequency of the pulse current is high, the MOSFET provided to cut off the current of the current supply path cannot be rapidly controlled to be in the off state. As a result, the pulse current is allowed to pass from the input end side of the current supply path toward the output end side, and thus there is a problem that, in the current limiting circuit 1X, the protected device connected to the output end side of the current supply path can be damaged.

[0007] The present application has been achieved in view of the problem, and a main object thereof is to provide a current limiting circuit that can rapidly control a MOSFET to be in the off state even when a pulse current is input, and limit the supply of a current of an excessively large current value.

[0008] SOLUTION TO THE PROBLEM To achieve the above object, the current limiting circuit according to the present application is configured to include: a MOSFET whose current input terminal is connected to an input terminal side of a current supply path, and whose current output terminal is connected to an output terminal side of the current supply path, and whose control terminal is connected to one end of a first resistor, and the MOSFET allows and cuts off the passage of current supplied to the current supply path depending on the application state of a bias voltage applied to the control terminal from the other end of the first resistor; a series circuit of a second resistor and an inductor connected between the current output terminal of the MOSFET and the output terminal; and a control element whose control terminal is connected to a connection point of one end of the series circuit and the current output terminal of the MOSFET via a third resistor, and whose current input terminal is connected to the other end of the first resistor, and whose current output terminal is connected to the other end of the series circuit, and the control element is driven by a voltage generated at the one end of the series circuit to change the application state of the bias voltage applied to the control terminal of the MOSFET via the first resistor when a current exceeding a predetermined current value is supplied to the input terminal of the current supply path, thereby limiting the current value of the current passing through the MOSFET, and the current limiting circuit includes a pulse current conduction circuit configured to include a capacitor and allow the conduction of a pulse current from the control terminal of the MOSFET toward the output terminal.

[0009] In the current limiting circuit, the pulse current conduction circuit is configured to include a capacitor connected in series between the gate of the MOSFET and the output terminal of the current supply path and allow the passage of a pulse current, and thus when the MOSFET is to pass a pulse current of an excessively large current value at a high frequency, the pulse current conduction circuit allows the conduction of a pulse current from the gate of the MOSFET toward the output terminal, and thus the charges accumulated in the static capacitance between the drain and the gate of the MOSFET and the static capacitance between the source and the gate of the MOSFET are instantaneously moved to the capacitor in the series circuit. Therefore, according to the current limiting circuit, the voltage between the gate and the source of the MOSFET is instantaneously reduced and instantaneously dropped (decreased) below the threshold voltage, and as a result, the MOSFET is instantaneously (rapidly) controlled to be in an off state, and the passage of a pulse current from the input terminal toward the output terminal of the current supply path is instantaneously cut off. Thus, in the current limiting circuit, the protected device connected to the output terminal of the current supply path is protected from an overcurrent.

[0010] Further, the current limiting circuit of the present application is characterized in that the pulse current ON circuit is constituted by a series circuit having the capacitor and a fourth resistor.

[0011] According to the current limiting circuit, the pulse current ON circuit can be constituted simply and inexpensively, and further, the current limiting circuit can be constituted simply and inexpensively.

[0012] Further, the current limiting circuit of the present application is provided with: a FET (Field Effect Transistor) control circuit that controls the operation state of the MOSFET by changing the application state of the bias voltage to the control terminal of the MOSFET; and a voltage monitoring circuit that monitors the voltage difference between the input terminal of the current supply path and a reference potential, and causes the FET control circuit to change the application state of the bias voltage applied to the control terminal of the MOSFET when the voltage difference exceeds a predetermined upper limit voltage value, thereby causing the MOSFET to shut off the passage of the current.

[0013] According to the current limiting circuit, the voltage monitoring circuit monitors the voltage difference between the input terminal of the current path and a reference potential, and causes the FET control circuit to change the application state of the bias voltage applied to the control terminal of the MOSFET when the voltage difference exceeds a predetermined upper limit voltage value, thereby causing the MOSFET to shut off the passage of the current, and thus, it is possible to prevent the failure of the protected device caused by the input of a voltage of an excessively large voltage value.

[0014] Further, in the current limiting circuit of the present application, when the voltage difference is within a predetermined prescribed voltage range after exceeding the upper limit voltage value, the voltage monitoring circuit causes the FET control circuit to change the application state of the bias voltage applied to the control terminal of the MOSFET, thereby causing the MOSFET to allow the passage of the current.

[0015] According to the current limiting circuit, the voltage monitoring circuit causes the FET control circuit to change the application state of the bias voltage applied to the control terminal of the MOSFET when the voltage difference is within a predetermined prescribed voltage range after exceeding the upper limit voltage value, thereby causing the MOSFET to allow the passage of the current, and thus, it is possible to automatically supply the current to the current path when recovering from an abnormal state to a normal state.

[0016] Effects of the Invention According to the current limiting circuit of the present application, it is possible to instantaneously control the MOSFET to the off state, and instantaneously shut off the passage of the pulse current from the input terminal toward the output terminal of the current supply path. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a configuration diagram of the current limiting circuit 1.

[0018] Figure 2 is a configuration diagram of the existing current limiting circuit 1X. DETAILED DESCRIPTION

[0019] Hereinafter, an embodiment of the current limiting circuit will be described with reference to the drawings.

[0020] Figure 1 The current limiting circuit 1 illustrated is provided, for example, between a power supply device 2 that generates a direct current and a protected device 3 that is driven by the direct current, and is configured to be able to limit the direct current supplied from the power supply device 2 to the protected device 3 to a predetermined current value or less, and to be able to limit supply (passage) of a pulse current to the protected device 3 when the pulse current is to be supplied from the power supply device 2 to the protected device 3.

[0021] Specifically, as illustrated in Figure 1 The current limiting circuit 1 has an input terminal T1 that is an input end of a current supply path, and an output terminal T2 that is an output end of the current supply path, and is connected (disposed) between the power supply device 2 connected to the input terminal T1 and the protected device 3 such as a constant current circuit or the like that is a load device connected to the output terminal T2.

[0022] Further, the current limiting circuit 1 has a MOSFET M1, a series circuit SC1, a transistor Q1, an FET control circuit 11, and a voltage monitoring circuit 12. In this case, the MOSFET M1 is an enhancement type and N-channel type FET that functions as an element for allowing and cutting off passage of a current supplied to the current supply path, a drain thereof that is a current input terminal is connected to the input terminal T1 side, a source thereof that is a current output terminal is connected to the output terminal T2 side, and a gate thereof that is a control terminal is connected to one end of a resistor R1 that is a first resistor, and the MOSFET M1 allows passage of a current of a predetermined current value or less supplied to the current supply path or cuts off passage of a current of an excessively large current value, according to an application state of a bias voltage Vb from the other end of the resistor R1 to the gate. Specifically, when the bias voltage Vb of a voltage value equal to or higher than a threshold value is applied to the gate via the resistor R1, the MOSFET M1 is controlled to an on state in which a resistance value between the drain and the source is a sufficiently small resistance value, and when the voltage value of the applied bias voltage Vb is less than the threshold value, the MOSFET M1 is controlled to an incomplete on state in which the resistance value between the drain and the source is slightly large, or an off state in which the resistance value between the drain and the source is extremely high.

[0023] The series circuit SC1 has the resistor R2 as a second resistor and the inductor LI, and is connected between the source of the MOSFET Ml and the output terminal T2. Further, the transistor Ql is a transistor of N-channel type, which constitutes one example of the control element. In this case, the base as a control terminal of the transistor Ql is connected to the connection point of one end of the series circuit SC1 (the end portion of the resistor R2 on the MOSFET Ml side) and the source of the MOSFET Ml via the resistor R3 as a third resistor, the collector as a current input terminal of the transistor Ql is connected to the gate of the MOSFET Ml via the resistor Rl by being connected to the other end of the resistor Rl, and the emitter as a current output terminal of the transistor Ql is connected to the other end of the series circuit SC1 (the end portion of the inductor LI on the output terminal T2 side).

[0024] The FET control circuit 11 controls the on / off operation state of the MOSFET Ml by changing the application state of the bias voltage to the gate of the MOSFET Ml. Specifically, the FET control circuit 11 supplies the bias voltage Vb of a voltage value exceeding the threshold value to the gate of the MOSFET Ml via the resistor R5 and the resistor Rl in a normal state in which a voltage in a predetermined voltage range decided in advance is output from the power supply device 2, thereby controlling the MOSFET Ml to the on state. On the other hand, the FET control circuit 11 stops the output of the bias voltage Vb when the control signal S 1 is input from the voltage monitoring circuit 12, thereby controlling the MOSFET Ml to the off state and cutting off the passage of the current supplied to the current supply path.

[0025] The voltage monitoring circuit 12 monitors the voltage VI that is the voltage difference between the input terminal Tl that is the input terminal of the current supply path and the reference potential (ground potential in this case). Further, the voltage monitoring circuit 12 changes the application state of the bias voltage applied to the gate of the MOSFET Ml by the FET control circuit 11, thereby allowing or cutting off the passage of current by the MOSFET Ml. Specifically, the voltage monitoring circuit 12 changes the application state of the bias voltage applied to the gate of the MOSFET Ml when the voltage VI exceeds the upper limit voltage value (the upper limit voltage value of the prescribed voltage range described above), thereby cutting off the passage of current supplied to the current supply path by the MOSFET Ml. More specifically, the voltage monitoring circuit 12 outputs the control signal SI to the FET control circuit 11 to stop the supply of the bias voltage Vb, thereby controlling the MOSFET Ml to the off state to cut off the passage of current supplied to the current supply path. Further, the voltage monitoring circuit 12 changes the application state of the bias voltage applied to the gate of the MOSFET Ml by the FET control circuit 11 when the voltage VI is within the prescribed voltage range after exceeding the upper limit voltage value, thereby allowing the passage of current supplied to the current supply path by the MOSFET Ml. Specifically, the voltage monitoring circuit 12 stops the output of the control signal SI to cause the FET control circuit 11 to resume the supply of the bias voltage Vb, thereby controlling the MOSFET Ml to the on state to allow the passage of current supplied to the current supply path.

[0026] Further, in the current limiting circuit 1, between the gate of the MOSFET Ml and the output terminal T2, specifically, between the other end of the resistor R3 connected to the gate of the MOSFET Ml and the output terminal T2, a series circuit SC2 composed of a capacitor CI and a resistor R4 as a fourth resistor connected in series is provided. The series circuit SC2 functions as a pulse current passing circuit, and allows the passage (passing) of a pulse current from the gate of the MOSFET Ml toward the output terminal T2 when a pulse current of high frequency is to flow in the MOSFET Ml.

[0027] Next, the operation of the current limiting circuit 1 will be described with reference to Figure 1

[0028] ​First, the operation of the current limiting circuit 1 in a normal state in which the voltage value of the direct current supplied to the current supply path is below a predetermined current value, will be described. In the normal state, the voltage value of the voltage Vl between the input terminal Tl and the reference potential is within the predetermined voltage range, and therefore the voltage monitoring circuit 12 stops the output of the control signal Sl. In this state, the FET control circuit 11 outputs the bias voltage Vb to the gate of the MOSFET Ml via the resistor R5 and the resistor Rl. Therefore, the MOSFET Ml is controlled to be in the on state. In this state, the direct current I l output from the power supply device 2 is supplied to the protected device 3 via the current path CP1 (current supply path) composed of the input terminal Tl, the drain of the MOSFET Ml, the source of the MOSFET Ml, the series circuit SC1, and the output terminal T2.

[0029] On the other hand, when the current value of the supplied current I l rises above the predetermined current value, the voltage at the end of the source side (resistor R3 side) of the MOSFET Ml in the resistor R2 rises due to the current I l. At this time, this risen voltage is input to the base of the transistor Ql via the resistor R3, and therefore the base voltage of the transistor Ql rises, as a result of which the transistor Ql becomes in the on state. In this state, the current I2 output from the output section of the FET control circuit 11 flows through the current path CP2 composed of the resistor R5, the collector of the transistor Ql, the emitter of the transistor Ql, and the input section of the FET control circuit 11, and at this time, a voltage drop occurs in the resistor R5, and therefore the voltage value of the bias voltage Vb supplied to the gate of the MOSFET Ml is reduced from the threshold voltage. Therefore, the MOSFET Ml is controlled to be in an incomplete on state or an off state, and as a result of this, the current value of the current I l passing through the MOSFET Ml from the input terminal (in this case, the input terminal Tl) of the current supply path toward the output terminal (in this case, the output terminal T2) is limited to be below the predetermined current value.

[0030] Further, when the current value of the supplied current Ii decreases below the predetermined current value, the voltage at the end of the resistance R3 side of the resistance R2 decreases. At this time, the base voltage of the transistor Ql decreases, and thus the transistor Ql becomes in the off state. In this state, the current I2 does not flow through the current path CP2, and thus no voltage drop occurs in the resistance R5, with the result that the bias voltage Vb of the prescribed voltage exceeding the threshold voltage is output from the FET control circuit 11 to the gate of the MOSFET Ml. Thus, the MOSFET Ml is controlled to be in the on state, and thus the current Ii of the predetermined current value or less is supplied to the current path CPi from the input terminal (in this case, the input terminal Tl) of the current supply path to the output terminal (in this case, the output terminal T2). As a result, in this current limiting circuit 1, the current value of the current Ii input to the input terminal of the current supply path can be controlled to be the prescribed current value or less.

[0031] On the other hand, for example, when an abnormality occurs in the protected device 3, when the power supply device 2 instantaneously outputs a high-frequency pulse-shaped direct-current voltage at an excessively large voltage value, or the like, a pulse current Ip exceeding the predetermined current value is sometimes supplied to the input terminal Tl (refer to FIG. 2). Figure 1 In this case, in this current limiting circuit 1, the pulse current Ip momentarily flows through the current path CPi, but the pulse current Ip becomes slightly difficult to flow due to the inductance of the inductor LI. Thus, at this time, the voltage at the end of the source side (the resistance R3 side) of the MOSFET Ml in the resistance R2 (the voltage across the resistance R2) does not immediately rise, and further, the transistor Ql maintains the off state due to the frequency characteristics of the transistor Ql. In this case, the voltage monitoring circuit 12 cannot sufficiently respond to the high-frequency pulse-shaped direct-current voltage and stops the output of the control signal S l. Thus, in this state, the MOSFET Ml maintains the on state.

[0032] On the other hand, a part of the pulse current Ip input to the input terminal Tl, the current I3 momentarily flows through the current path CP3 constituted by the input terminal Tl, the static capacitance between the drain and the gate of the MOSFET Ml and the static capacitance between the source and the gate of the MOSFET Ml, the resistance Rl, the series circuit SC2, and the output terminal T2. At this time, the charges accumulated in the static capacitance between the drain and the gate of the MOSFET Ml and the static capacitance between the source and the gate of the MOSFET Ml momentarily move to the capacitor CI in the series circuit SC2. Thus, the voltage between the gate and the source of the MOSFET Ml momentarily decreases and momentarily falls below the threshold voltage (decreases), and thus the MOSFET Ml is momentarily controlled to be in the off state. As a result, the passage of the pulse current Ip from the input terminal Tl toward the output terminal T2 is momentarily cut off.

[0033] After that, a part of the pulse current Ip, current I4, flows through a current path CP4 constituted by the input terminal Tl, the drain of the MOSFET Ml, the source of the MOSFET Ml, the resistance R3, the base of the transistor Ql, the emitter of the transistor Ql, and the output terminal T2, and is supplied to the transistor Ql as a bias current. At the same time, a current I5 caused by a counter electromotive force VI generated in the inductor LI by a part of the pulse current Ip flows through a current path CP5 constituted by the inductor LI, the resistance R2, the resistance R3, the base of the transistor Ql, the emitter of the transistor Ql, and the inductor LI, and is supplied to the transistor Ql as a bias current. Thus, the transistor Ql gradually moves (transitions) to an on state in accordance with the frequency characteristic. At this time, the inductor LI is present in the series circuit SCl, and thus the transistor Ql more quickly moves (transitions) to the on state than in the case where only the current I4 is supplied to the base of the transistor Ql.

[0034] On the other hand, at the time point when the charge is sufficiently accumulated in the capacitor CI, a state where the current I3 does not flow through the current path CP3 is attained. However, since the transistor Ql is in the on state, a current I6 flows through a current path CP6 constituted by the input terminal Tl, the drain of the MOSFET Ml, the gate of the MOSFET Ml, the resistance Rl, the collector of the transistor Ql, the emitter of the transistor Ql, and the output terminal T2, and maintains a state where the voltage between the gate and the source of the MOSFET Ml is lower than the threshold voltage (a reduced state), with the result that the MOSFET Ml is reliably maintained in the off state. At this time, a current I7 based on the charge accumulated in the capacitor CI by the current I3 flowing through the current path CP3 flows through a current path CP7 constituted by the capacitor CI, the resistance R4, the collector of the transistor Ql, the emitter of the transistor Ql, and the capacitor CI, and thus the charge accumulated in the capacitor CI is consumed (released). In this case, the resistance R4 functions as a current limiting resistance, and prevents the transistor Ql from being damaged by the current I7 of a large current value flowing when a large amount of charge is accumulated in the capacitor CI.

[0035] On the other hand, the voltage monitoring circuit 12 outputs the control signal SI to the FET control circuit 11 when detecting that the voltage VI between the input terminal Tl and the reference potential exceeds the upper limit voltage value of the prescribed voltage range. Thus, the FET control circuit 11 stops the output of the bias voltage Vb. As a result, the MOSFET Ml is more reliably maintained in the off state, and the passage of the pulse current Ip from the input terminal Tl toward the output terminal T2 is more reliably cut off.

[0036] After that, as the instantaneous value of the pulse current Ip decreases, the current value of the current I4 decreases, and as the energy of the inductor LI decreases, the current value of the current I5 decreases, and thus the transistor Ql moves to the off state.

[0037] Next, at the time when the input of the pulse current Ip is stopped, the voltage monitoring circuit 12 detects that the voltage VI between the input terminal Tl and the reference potential is within the prescribed voltage range, and at this time, the stop control signal SI is output to the FET control circuit 11. Thus, the FET control circuit 11 starts (resumes) the output of the bias voltage Vb. At this time, the gate voltage of the MOSFET Ml rises in accordance with the time constant based on the respective resistance values of the resistor Rl, the resistor R4, the resistor R5, the respective electrostatic capacitances between the drain and the gate and between the source and the gate of the MOSFET Ml, and the electrostatic capacitance of the capacitor Cl. After that, at the time when the gate voltage exceeds the threshold voltage, the MOSFET Ml is controlled to the on state. As a result, the current limiting circuit 1 is maintained in the normal state in which the supply of the current II from the power supply device 2 to the protected device 3 is allowed.

[0038] Thus, in this current limiting circuit 1, the pulse current on circuit (series circuit SC2) which is configured to include the capacitor Cl connected in series between the gate of the MOSFET Ml and the output terminal (output terminal T2) of the current supply path and to allow the passage of the pulse current Ip thereby allows the passage of the pulse current Ip from the gate of the MOSFET Ml toward the output terminal T2 when the MOSFET Ml is to flow the pulse current Ip of an excessively large current value at a high frequency, and thus the charges accumulated in the electrostatic capacitances between the drain and the gate of the MOSFET Ml and between the source and the gate of the MOSFET Ml are instantaneously moved to the capacitor Cl within the series circuit SC2. Therefore, according to this current limiting circuit 1, the voltage between the gate and the source of the MOSFET Ml is instantaneously reduced and instantaneously lowered than the threshold voltage, and as a result, the MOSFET Ml is instantaneously (rapidly) controlled to the off state and the passage of the pulse current Ip from the input terminal Tl of the current supply path toward the output terminal T2 is instantaneously cut off. Thus, in this current limiting circuit 1, the protected device 3 connected to the output terminal of the current supply path can be protected from the excessive current.

[0039] Further, according to this current limiting circuit 1, the voltage monitoring circuit 12 monitors the voltage difference (voltage VI) between the input terminal (input terminal Tl) of the current path CP1 and the reference potential (ground potential), and when the voltage VI exceeds the upper limit voltage value decided in advance, the FET control circuit 11 changes the state of the bias voltage applied to the gate of the MOSFET Ml to cause the MOSFET Ml to cut off the passage of the current II, and thus the failure of the protected device 3 caused by the input of the voltage of an excessively large voltage value can be prevented.

[0040] Further, according to the current limiting circuit 1, the voltage monitoring circuit 12 causes the FET control circuit 11 to change the application state of the bias voltage applied to the gate of the MOSFET Ml to allow the passage of the current II by the MOSFET Ml when the voltage VI exceeds the upper limit voltage value and is within the predetermined prescribed voltage range, thereby automatically supplying the current II to the current path CP1 when recovering from the abnormal state to the normal state in which the voltage within the predetermined prescribed voltage range is output from the power supply device 2.

[0041] Note that the present application is not limited to the above-described configuration of the current limiting circuit 1, and can be appropriately changed. For example, in a configuration in which a small electrostatic capacitor is used as the capacitor CI constituting the series circuit SC2 of the pulse current passing circuit, the current value of the current I7 flowing through the current path CP7 is small. Therefore, the possibility of damage to the transistor Ql is low, and thus the resistance R4 can be omitted. That is, the series circuit SC2 can be constituted only by the capacitor CI. According to the current limiting circuit 1 of this configuration, the pulse current passing circuit can be constituted simply and inexpensively, and further the current limiting circuit 1 can be constituted simply and inexpensively.

[0042] Further, the connection of the resistance R2 and the inductor LI within the series circuit SCI can be reversed, that is, the series circuit SCI can be constituted by arranging the inductor LI on the source side of the MOSFET Ml and arranging the resistance R2 on the output terminal T2 side. Further, the connection of the resistance R4 and the capacitor CI within the series circuit SC2 can be reversed, that is, the series circuit SC2 can be constituted by arranging the capacitor CI on the resistance Rl side and arranging the resistance R4 on the output terminal T2 side.

[0043] Further, a configuration in which the resistance R4 (or the capacitor CI in the above-described reversed connection) is directly connected to the gate of the MOSFET Ml without passing through the resistance Rl can be employed.

[0044] Further, in the above-described current limiting circuit 1, a configuration in which the voltage monitoring circuit 12 is arranged between the input terminal Tl and the reference potential to monitor the voltage VI between the input terminal Tl and the reference potential is employed, but is not limited thereto. For example, a configuration in which the voltage monitoring circuit 12 is arranged between the output terminal T2 and the reference potential to monitor the voltage difference between the output terminal T2 and the reference potential can be employed.

[0045] Industrial Applicability According to the application of the present application, when a pulse current Ip is supplied to the current supply path, the voltage between the gate and the source of the MOSFET M1 is instantaneously reduced and instantaneously lowered than the threshold voltage, as a result, the MOSFET M1 can be instantaneously controlled to be in the off state and instantaneously cut off the passing of the pulse current Ip from the input terminal T1 of the current supply path to the output terminal T2. Thus, the application of the present application can be widely applied to such current limiting circuit.

[0046] Explanation of reference numerals 1: current limiting circuit; 12: voltage monitoring circuit; C1: capacitor; CP1-CP7: current path; Ip: pulse current; L1: inductor; M1: MOSFET; R1-R7: resistor; Q1: transistor; SC1, SC2: series circuit; T1: input terminal; T2: output terminal; V1: voltage.

Claims

1. A current limiting circuit configured to have: A metal-oxide-semiconductor field-effect transistor (MOSFET) has a current input terminal connected to the input side of a current supply path, a current output terminal connected to the output side of the current supply path, and a control terminal connected to one end of a first resistor. The MOSFET allows and cuts off the flow of current supplied to the current supply path by adjusting the state of the control terminal based on the bias voltage from the other end of the first resistor. The series circuit of the second resistor and inductor is connected between the current output terminal and the output terminal of the MOSFET; as well as A control element has its control terminal connected via a third resistor to the connection point between one end of the series circuit and the current output terminal of the MOSFET, and its current input terminal connected to the other end of the first resistor, and its current output terminal connected to the other end of the series circuit. When a current exceeding a predetermined current value is supplied to the input terminal of the current supply path, the control element is driven by the voltage generated at one end of the series circuit to change the bias voltage applied to the control terminal of the MOSFET via the first resistor, thereby limiting the current value through the MOSFET. The current limiting circuit includes a pulse current conduction circuit, which is configured to include a capacitor and allow pulse current to flow from the control terminal of the MOSFET toward the output terminal.

2. The current limiting circuit according to claim 1, wherein, The pulse current conduction circuit is composed of a series circuit having the capacitor and the fourth resistor.

3. The current limiting circuit according to claim 1 or 2, comprising: A field-effect transistor (FET) control circuit controls the operating state of the MOSFET by changing the bias voltage applied to the control terminal of the MOSFET; and A voltage monitoring circuit monitors the voltage difference between the input terminal of the current supply path and a reference potential. When the voltage difference exceeds a predetermined upper limit voltage value, the FET control circuit changes the bias voltage applied to the control terminal of the MOSFET, thereby causing the MOSFET to cut off the current flow.

4. The current limiting circuit according to claim 3, wherein, When the voltage difference exceeds the upper limit voltage value and falls within a predetermined voltage range, the voltage monitoring circuit causes the FET control circuit to change the bias voltage applied to the control terminal of the MOSFET, thereby allowing the current to pass through the MOSFET.

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