Display substrate, display panel and display device

Abstract

The invention relates to a display substrate, a display panel and a display device. The display substrate comprises an interlayer dielectric layer located on one side of a substrate and a plurality of data lines, and the data lines are arranged on the side, away from the substrate, of the interlayer dielectric layer and located in a display area; the multiple first fan-out lines are arranged on the side, away from the substrate, of the interlayer dielectric layer and located in the fan-out area, and the first fan-out lines are electrically connected with the data lines; the planarization layer is located on the side, away from the substrate, of the layer where the data lines are located, and a part of the planarization layer makes contact with the interlayer dielectric layer; wherein the interlayer dielectric layer is provided with a plurality of grooves, at least parts of the first fan-out lines are located in the grooves, and the thickness of the first fan-out lines is different from the depth of the grooves; and / or the display substrate further comprises a protection layer located on the side, away from the substrate, of the first fan-out line, one part of the protection layer makes contact with the interlayer dielectric layer, and the adhesion between the protection layer and the interlayer dielectric layer is larger than the adhesion between the planarization layer and the interlayer dielectric layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display substrate, a display panel and a display device. BACKGROUND

[0002] In the field of display, liquid crystal display (LCD) has become a major subject of display research in recent years due to its advantages of low voltage operation, no radiation scattering, light weight and small size, and has been widely used in display devices such as liquid crystal televisions, mobile phones, personal digital assistants, digital cameras and computer screens. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and proposes a display substrate, a display panel and a display device.

[0004] In order to achieve the above-mentioned purpose, the present disclosure provides a display substrate having a display area, a binding area located on one side of the display area, and a fan-out area located between the display area and the binding area, the display substrate comprising:

[0005] a substrate substrate;

[0006] an interlayer dielectric layer and a plurality of data lines located on one side of the substrate substrate, the data lines being arranged on the side of the interlayer dielectric layer away from the substrate substrate and located in the display area;

[0007] a plurality of first fan-out lines arranged on the side of the interlayer dielectric layer away from the substrate substrate and located in the fan-out area, the first fan-out lines being electrically connected to the data lines;

[0008] a planarization layer located on the side of the layer where the first fan-out lines are located away from the substrate substrate, and part of the planarization layer is in contact with the interlayer dielectric layer;

[0009] wherein the interlayer dielectric layer is provided with a plurality of grooves, at least part of the first fan-out lines is located in the grooves, and the thickness of the first fan-out lines is different from the depth of the grooves;

[0010] And / or, the display substrate further comprises a protective layer located on the side of the first fan-out lines away from the substrate substrate, part of the protective layer is in contact with the interlayer dielectric layer, and the adhesion between the protective layer and the interlayer dielectric layer is greater than the adhesion between the planarization layer and the interlayer dielectric layer.

[0011] In some embodiments, the display substrate further comprises a protective layer;

[0012] The planarization layer is provided with at least one first opening, the first opening exposes at least part of the first fan-out line and a part of the interlayer dielectric layer, the protective layer comprises a first protective portion located in the first opening, part of the first protective portion is arranged in contact with the surface of the interlayer dielectric layer away from the substrate, and the other part of the first protective portion is located on the side of the first fan-out line away from the substrate and arranged in contact with the first fan-out line.

[0013] In some embodiments, the protective layer further comprises a second protective portion located on the side of the planarization layer away from the substrate.

[0014] In some embodiments, the first opening is a plurality of first openings, the plurality of first openings are arranged along a first direction, and the first openings extend along a second direction, the second direction intersects the first direction.

[0015] The second direction is the same as the extension direction of any one of the first fan-out line and the data line, or the display substrate further comprises a gate line located in the display area, the gate line is arranged transversely to the data line, and the second direction is the same as the extension direction of the gate line.

[0016] In some embodiments, the display substrate further comprises a passivation layer located on the side of the planarization layer away from the substrate.

[0017] The protective layer and the passivation layer are arranged in the same layer and are made of the same material.

[0018] In some embodiments, the protective layer and the passivation layer are connected as an integral structure.

[0019] In some embodiments, the display substrate comprises a protective layer, the protective layer is located between the planarization layer and the layer where the first fan-out line is located.

[0020] In some embodiments, the protective layer comprises a plurality of third protective portions arranged at intervals, the third protective portions are the same as the extension direction of the first fan-out line, and the third protective portions cover at least part of the first fan-out line.

[0021] In some embodiments, at least two third protective portions are connected as an integral structure.

[0022] In some embodiments, the fan-out area comprises a plurality of first regions and second regions arranged along a third direction, the first regions are located on opposite sides of the second regions in the third direction, the third direction intersects the arrangement direction of the fan-out area and the binding area, and at least the first regions are provided with the first fan-out line.

[0023] In some embodiments, the fan-out area includes a first area and a second area arranged along a third direction, the first fan-out line is located in the first area, and the display substrate further includes a second fan-out line located in the second area, a distribution density of the first fan-out line in the first area is greater than a distribution density of the second fan-out line in the second area.

[0024] In some embodiments, the material of the interlayer medium layer and the protective layer both includes inorganic material.

[0025] The present disclosure also provides a display panel including the display substrate as described in any one of the above.

[0026] In some embodiments, the display panel further includes:

[0027] A counter-substrate is arranged opposite to the display substrate;

[0028] A sealant is located between the display substrate and the counter-substrate, a normal projection of the sealant on the substrate substrate surrounds the display area, and overlaps with a normal projection of the first fan-out line on the substrate substrate.

[0029] In some embodiments, the display substrate includes a protective layer, the planarization layer is provided with at least one first opening, and a part of the sealant is located in the first opening and in contact with a surface of the protective layer away from the substrate substrate.

[0030] The present disclosure also provides a display device including the display panel as described in any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation on the present disclosure. In the drawings:

[0032] Figure 1 is a schematic diagram of a cross-sectional structure of a display device in some embodiments;

[0033] Figure 2 is Figure 1 is a schematic diagram of a planar structure of a display panel in some embodiments;

[0034] Figure 3 is Figure 2 is a schematic diagram of a cross-sectional structure of a display panel shown in FIG. 8;

[0035] Figure 4 is a schematic diagram of a cross-sectional structure of a display panel in some other embodiments;

[0036] Figure 5 is a schematic diagram of a cross-sectional structure of a display panel in some other embodiments;

[0037] Figure 6 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure;

[0038] Figure 7 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure;

[0039] Figure 8 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure;

[0040] Figure 9 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure;

[0041] Figure 10 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure;

[0042] Figure 11 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure;

[0043] Figure 12 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure;

[0044] Figure 13 is a schematic diagram of a planar structure of a display substrate in some embodiments of the present disclosure;

[0045] Figure 14A is a schematic diagram of a planar structure of a fan-out region in some embodiments of the present disclosure;

[0046] Figure 14B and Figure 14C are respectively Figure 14A schematic diagrams of a planar structure of each single film layer in

[0047] Figure 15A is a schematic diagram of a planar structure of a fan-out region in some embodiments of the present disclosure;

[0048] Figure 15B is a schematic diagram of a planar structure of a planarization layer in Figure 15A

[0049] is a schematic diagram of a planar structure of a fan-out region in some embodiments of the present disclosure; Figure 16A

[0050] is a schematic diagram of a planar structure of a planarization layer in Figure 16B Figure 16A DETAILED DESCRIPTION

[0051] ​​The specific embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be understood that the specific embodiments described herein are merely illustrative and explanatory, and are not intended to limit the present disclosure.

[0052] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0053] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms “include”, “contain”, and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” or similar terms do not mean physical or mechanical connection, but can include electrical connection, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like only represent relative positional relationships, which can change when the absolute positions of the described objects change.

[0054] As used herein, “parallel”, “perpendicular” includes the stated case and the approximately similar case to the stated case, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of a specific quantity (i.e., the limitation of the measurement system). For example, “parallel” includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel can be, for example, within 5° deviation; “perpendicular” includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular can also be, for example, within 5° deviation.

[0055] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0056] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and areas is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] With the continuous development of display technology, the requirements for the drop resistance and reliability of display devices are becoming increasingly stringent. During a drop, due to the violent impact, the film layers contained within the display device may slip or be damaged, rendering the display device unusable.

[0058] Figure 1 These are cross-sectional structural schematic diagrams of the display device in some embodiments.

[0059] like Figure 1 As shown, the display device includes a housing KT, a backlight module BLM, and a liquid crystal display panel. The housing forms a receiving cavity, and the backlight module and the liquid crystal display panel are located within the receiving cavity. The backlight module is located on the backlight side of the liquid crystal display panel, and the backlight module BLM may include, for example, a backlight source and a light guide plate for providing a light source for the display panel.

[0060] like Figure 1 As shown, a liquid crystal display panel generally includes a display substrate (TFT), a cell substrate (CF), and a liquid crystal layer and sealant located between the TFT and the cell. The liquid crystal layer and sealant are not... Figure 1 As shown in the diagram, the sealant seals the liquid crystal layer between the display substrate TFT and the cell substrate CF.

[0061] like Figure 1 As shown, the liquid crystal display panel also includes a first polarizer POL1 located on the side of the display substrate TFT away from the counter substrate CF, a second polarizer POL2 located on the side of the counter substrate CF away from the display substrate TFT, and a cover plate CG located on the side of the second polarizer POL2 away from the counter substrate CF. The cover plate CG and the second polarizer POL2 are bonded together by an optical adhesive layer OCA.

[0062] The display substrate TFT has multiple sub-pixels arranged in an array. Each sub-pixel includes a pixel electrode, and a common electrode is provided on the cell substrate CF. Under the voltage applied between the pixel electrode and the common electrode, the liquid crystal molecules in the liquid crystal layer LCL can be deflected. Furthermore, the liquid crystal display substrate TFT also needs to be provided with a pixel driving circuit electrically connected to the pixel electrode to specifically control the deflection of the liquid crystal molecules between the pixel electrode and the common electrode.

[0063] With the development of full-screen technology, in order to obtain a higher screen ratio, currently mainly adopts COF (chip on film), COP (chip on panel) and COG (Chip on Glass) and other technologies to make liquid crystal display substrate TFT.

[0064] Figure 1 The liquid crystal display panel shown is driven by the sub-pixels in the display substrate TFT using the chip on film COF. The chip on film COF can be electrically connected to the display substrate TFT through a flexible circuit board (FPC, Flexible Printed Circuit).

[0065] Figure 2 is Figure 1 A schematic diagram of the planar structure of the display panel. Figure 3 is Figure 2 A schematic diagram of the cross-sectional structure of the display panel, specifically the cross-sectional structure along the cutting line XX' in Figure 2

[0066] As shown in Figure 2 , the display panel has a display area AA. It should be understood that the display substrate TFT also has a display area AA accordingly.

[0067] Among them, the display area AA is provided with a plurality of gate lines and a plurality of data lines, and the plurality of gate lines and the plurality of data lines cross to define a plurality of pixel areas, and the pixel area is provided with a sub-pixel, the sub-pixel includes a pixel electrode and a driving element electrically connected to the pixel electrode, the driving element can be a thin film transistor for example, the thin film transistor is electrically connected with the gate line and the data line respectively, wherein the gate line can provide a scanning driving signal for the transistor, that is, control the opening and closing of the thin film transistor. The data line can control the pixel electrode through the thin film transistor, for example, in the case of opening of the thin film transistor, the data line can provide a data driving signal for the pixel electrode.

[0068] Specifically, the display substrate TFT also has a non-display area surrounding the display area AA. In one example, the non-display area can be provided with a gate drive circuit such as a GOA (Gate Driver on Array) drive circuit, the gate line is electrically connected with the gate drive circuit, and the gate drive circuit can provide a scanning driving signal for the gate line.

[0069] In one example, as Figure 2 ​As shown, the non-display area includes a bonding area PA1 located at least one side of the display area AA, and a fan-out area FA located between the bonding area PA1 and the display area AA. The bonding area PA1 is provided with a plurality of bonding pads, and the fan-out area FA is provided with a plurality of fan-out lines SD.

[0070] One end of the fan-out line SD is electrically connected with the data line, and the other end is electrically connected with the bonding pad. The bonding pad can be electrically connected with one end of the flexible circuit board, and the other end of the flexible circuit board is electrically connected with the chip on film.

[0071] In the process of falling of the display device, as shown, Figure 1 The force F1 and F4 transmitted by the shell KT to the cover plate CG, wherein the direction of F1 is directed to the light-emitting side of the display device, and the direction of F4 is along the edge of the cover plate CG to the center of the cover plate CG. After the cover plate CG is deformed under stress, the optical adhesive layer OCA generates a pulling force F2 on the cell substrate CF, and the direction of F2 is directed to the light-emitting side of the display device. The flexible circuit board FPC is bent and attached to the display substrate TFT and the chip on film COF respectively, so that the flexible circuit board FPC generates a force F3 towards the backlight module on the display substrate TFT, and generates a pulling force F5 outward on the chip on film COF. The chip on film COF is attached between the backlight module BLM and the shell KT, so that the chip on film COF generates a pulling force on the backlight module BLM and the shell KT. In this case, when the whole display device falls to the bottom, due to the different vibration directions and stress directions of the cover plate CG, the shell KT and the flexible circuit board FPC, the flexible circuit board FPC is easily pulled, which causes the electrical connection position between the flexible circuit board FPC and the display substrate TFT to be pulled, and further causes the film layer of the electrical connection position between the flexible circuit board FPC and the display substrate TFT to be easily separated and displaced.

[0072] As shown, Figure 3 The cell substrate CF includes a second substrate SUB2, and a black matrix layer BM and an organic layer OC arranged in sequence along the direction close to the liquid crystal layer LCL on one side of the second substrate SUB2.

[0073] As shown, Figure 3 The display substrate TFT includes a first substrate SUB1, and a buffer layer BUFFER, a gate insulating layer GI and an interlayer dielectric layer ILD arranged in sequence along the direction away from the first substrate SUB1 on one side of the first substrate SUB1. The display substrate TFT also includes some film layers not shown in the figure, such as a gate metal layer and a semiconductor layer. The gate metal layer can include the gate of a thin film transistor, and the semiconductor layer can include the active layer of a thin film transistor. Figure 3

[0074] ​The display substrate TFT also includes multiple fan-out lines SD located on the side of the interlayer dielectric layer ILD away from the first substrate SUB1 and in the fan-out region FA. The fan-out lines SD are located in the source and drain metal layers. The source and drain metal layers may also include the source and drain of the thin-film transistor.

[0075] Furthermore, the display substrate TFT also includes a planarization layer PLN located on the side of the source / drain metal layer (fan-out line SD) away from the first substrate SUB1, and a passivation layer PVX located on the side of the planarization layer PLN away from the first substrate SUB1. The passivation layer PVX has a via, which exposes a portion of the planarization layer PLN. The orthographic projection of the via onto the first substrate SUB1 does not overlap with the orthographic projection of the liquid crystal layer LCL onto the first substrate SUB1, and a portion of the sealant SEAL is located within the via.

[0076] As mentioned above, during the impact, the flexible printed circuit board (FPC) will stretch the display substrate TFT.

[0077] Specifically, such as Figure 3 As shown, the flexible printed circuit board (FPC) is electrically connected to the display substrate TFT through bonding pads (PADs). In other words, the flexible printed circuit board (FPC) will pull on the bonding pads (PADs), and further, the bonding pads (PADs) will pull on nearby film layers and other structures.

[0078] Depend on Figure 3 As can be seen, the bonding pads (PADs) are relatively close to the planarization layer (PLN) and the fan-out line (SD). Therefore, the bonding pads are prone to causing film separation between the planarization layer (PLN) and the fan-out line (SD), as well as film separation between the planarization layer (PLN) and the interlayer dielectric layer (ILD). Furthermore, because the fan-out line (SD) is densely distributed in the fan-out region (FA), the contact area between the planarization layer (PLN) and the fan-out line (SD) is relatively large. Generally, the planarization layer (PLN) uses an organic insulating material, while the fan-out line (SD) uses a metallic material; therefore, the adhesion between the planarization layer (PLN) and the fan-out line (SD) is relatively poor.

[0079] After the planarization layer PLN separates from the fan-out line SD and the interlayer dielectric layer ILD and vibrates and displaces, the planarization layer PLN can easily scratch the fan-out line SD or cause the fan-out line SD to displace, resulting in short circuits between different fan-out line SDs. Since the polarities of adjacent fan-out line SDs are opposite, the voltage neutralization after the short circuit causes dark lines and dark areas to appear. Therefore, if the display device is dropped, it can easily cause the fan-out line SD to malfunction, leading to display defects.

[0080] Figure 4 This is a cross-sectional structural diagram of the display panel in some other embodiments.

[0081] like Figure 4As shown, the planarization layer PLN is separated from the fan-out lines SD and the interlayer dielectric layer ILD. During the drop vibration process, the planarization layer PLN will vibrate back and forth. In this case, the planarization layer PLN can scratch the fan-out lines SD, causing poor transmission of the fan-out lines SD, or the planarization layer PLN can cause the fan-out lines SD to vibrate. Since the spacing between the fan-out lines SD is small, different fan-out lines SD can be connected together, causing short circuit of the fan-out lines SD.

[0082] Figure 5 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure.

[0083] As shown, the planarization layer PLN can also cause damage to the sealant SEAL, even causing the sealant SEAL to open, resulting in liquid leakage, i.e., leakage of liquid crystal in the liquid crystal layer LCL from the display area AA to the non-display area. Figure 5 Of course, in some embodiments, the problems of poor fan-out lines SD and liquid leakage can also occur simultaneously.

[0084] To at least alleviate one of the above-mentioned technical problems, the present disclosure provides a display substrate, a display panel, and a display device.

[0085] The schematic diagram of the planar structure of the display substrate in some embodiments of the present disclosure can be the same as the schematic diagram of the planar structure of the display substrate shown in

[0086] Figure 2

[0087] As shown, the display substrate TFT provided by the present disclosure has a display area AA, a binding area PA1 located on one side of the display area AA, and a fan-out area FA located between the display area AA and the binding area PA1. Figure 2

[0088] is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure. Figure 6 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure. Figure 7 is a schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present disclosure. Figure 8 In some embodiments, as shown, the display substrate TFT includes a first substrate SUB1, an interlayer dielectric layer ILD, a plurality of gate lines, a plurality of data lines, a plurality of first fan-out lines SD1, and a planarization layer PLN located on one side of the first substrate SUB1.

[0089] Figure 6 to Figure 8

[0090] ​​​​The data line is located on the side of the interlayer dielectric layer (ILD) away from the first substrate (SUB1) and is situated in the display area (AA). Optionally, the data line can be disposed on the same layer as the first fan-out line (SD1).

[0091] In this embodiment of the disclosure, "same-layer setting" means that the two structures are formed by the same material layer through a patterning process, so the two are in the same layer in terms of layering relationship.

[0092] The first fan-out line SD1 is disposed on the side of the interlayer dielectric layer (ILD) away from the first substrate (SUB1) and located in the fan-out region FA. Furthermore, the first fan-out line SD1 is electrically connected to the data line.

[0093] The planarization layer PLN is located on the side of the data line layer away from the first substrate SUB1, or the planarization layer PLN is located on the side of the first fan-out line SD1 layer away from the first substrate SUB1, and a portion of the planarization layer PLN is in contact with the interlayer dielectric layer ILD.

[0094] Furthermore, the interlayer dielectric layer (ILD) has multiple grooves, at least a portion of the first fan-out line SD1 is located in the grooves, and the thickness of the first fan-out line SD1 is different from the depth of the grooves. For example, the thickness of the first fan-out line SD1 is greater than the depth of the grooves, or the thickness of the first fan-out line SD1 is less than the depth of the grooves.

[0095] And / or, the display substrate TFT also includes a protective layer 10 located on the side of the first fan-out line SD1 away from the first substrate SUB1, a portion of the protective layer 10 is in contact with the interlayer dielectric layer ILD, and the adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than the adhesion between the planarization layer PLN and the interlayer dielectric layer ILD.

[0096] Specifically, in Figure 6 In the illustrated embodiment, the interlayer dielectric layer (ILD) has multiple grooves, at least a portion of the first fan-out line SD1 is located within the grooves, and the thickness H1 of the first fan-out line SD1 is different from the depth H2 of the grooves. For example, in this embodiment of the present disclosure, the thickness H1 of the first fan-out line SD1 is greater than the depth H2 of the grooves.

[0097] In this embodiment, a groove is formed by cutting a groove in the interlayer dielectric layer (ILD), and at least a portion of the first sector outgoing line SD1 is located within the groove. This embodiment allows at least a portion of the first sector outgoing line SD1 to be embedded in the ILD. Therefore, even if the planarization layer (PLN) separates from the first sector outgoing line SD1 and the ILD, the damage caused by the PLN to the first sector outgoing line SD1 is reduced. Furthermore, because the first sector outgoing line SD1 is embedded in the ILD, the ILD can fix its position. Therefore, this embodiment at least prevents the PLN from causing the first sector outgoing line SD1 to move, thereby preventing short circuits between different first sector outgoing lines SD1. In summary, this embodiment can alleviate or avoid the problem of malfunctions in the first sector outgoing line SD1.

[0098] exist Figure 7 In the embodiment shown, the display substrate TFT further includes a protective layer 10, a portion of which is in contact with the interlayer dielectric layer ILD. The adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than the adhesion between the planarization layer PLN and the interlayer dielectric layer ILD.

[0099] In this embodiment, the protective layer 10 is located on the side of the first fan-out line SD1 away from the first substrate SUB1, and a portion of the protective layer 10 is in contact with the interlayer dielectric layer ILD. Therefore, at least a portion of the protective line is located between the interlayer dielectric layer ILD and the protective layer 10. In this case, even if the planarization layer PLN separates from the interlayer dielectric layer ILD, the presence of the protective layer 10 prevents the planarization layer PLN from scratching the first fan-out line SD1.

[0100] Furthermore, the adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than that between the planarization layer PLN and the interlayer dielectric layer ILD. That is, the protective layer 10 is not as prone to film detachment as the planarization layer PLN. Therefore, the protective layer 10 can also fix the position of the first outgoing line SD1 and prevent the first outgoing line SD1 from moving.

[0101] Furthermore, by Figure 7 As shown, a portion of the protective layer 10 is also located between adjacent first outgoing lines SD1. Therefore, the protective layer 10 can also isolate adjacent first outgoing lines SD1, thereby preventing short circuits caused by overlapping of adjacent first outgoing lines SD1.

[0102] exist Figure 8In the illustrated embodiment, the interlayer dielectric layer (ILD) has multiple grooves, and at least a portion of the first fan-out line SD1 is located within these grooves. For example, in this embodiment, the thickness H1 of the first fan-out line SD1 is less than the depth H2 of the grooves. Simultaneously, the display substrate TFT further includes a protective layer 10, located on the side of the first fan-out line SD1 away from the first substrate SUB1, and a portion of the protective layer 10 is in contact with the interlayer dielectric layer (ILD). The adhesion between the protective layer 10 and the interlayer dielectric layer (ILD) is greater than the adhesion between the planarization layer PLN and the interlayer dielectric layer (ILD).

[0103] Accordingly, in this embodiment of the present disclosure, the first outgoing line SD1 is embedded in the groove opened in the interlayer dielectric layer ILD, so the interlayer dielectric layer ILD can fix the position of the first outgoing line SD1.

[0104] Meanwhile, since the protective layer 10 is located on the side of the first fan-out line SD1 away from the first substrate SUB1, that is, at least part of the first fan-out line SD1 in this embodiment is located between the interlayer dielectric layer ILD and the planarization layer PLN, or it can also be understood that at least part of the first fan-out line SD1 is covered by the protective layer 10, that is, the first fan-out line SD1 is no longer in contact with the planarization layer PLN. Therefore, in this embodiment, even if the planarization layer PLN and the interlayer dielectric layer ILD separate, the first fan-out line SD1 covered by the protective layer 10 is no longer affected by the planarization layer PLN, that is, it will not be scratched by the planarization layer PLN, nor will it be displaced by the planarization layer PLN.

[0105] Furthermore, the adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than that between the planarization layer PLN and the interlayer dielectric layer ILD. That is, the protective layer 10 in this embodiment will not separate from the interlayer dielectric layer ILD like the planarization layer PLN, which would cause scratches or other effects on the first fan-out line SD1.

[0106] In summary, by creating grooves and / or providing a protective layer 10, the embodiments of this disclosure can prevent the first outgoing line SD1 from being affected by the separation of the planarization layer PLN during a fall or impact.

[0107] In some embodiments, such as Figure 7 As shown, the planarization layer PLN has at least one first opening, which exposes at least a portion of the first fan-out line SD1 and a portion of the interlayer dielectric layer ILD.

[0108] The protection layer 10 includes a first protection part 11 located in the first opening, and a part of the first protection part 11 is in contact with the interlayer dielectric layer ILD away from the surface of the first substrate substrate SUB1, and another part of the first protection part 11 is located on the side of the first fan-out line SD1 away from the substrate and in contact with the first fan-out line SD1.

[0109] In the embodiment of the present disclosure, by opening the first opening in the planarization layer PLN and setting a part of the protection layer 10, i.e. the first protection part 11, in the first opening, the adhesion between the first protection part 11 and the interlayer dielectric layer ILD can weaken the vibration phenomenon of the planarization layer PLN after the film layer separation of the planarization layer PLN and the interlayer dielectric layer ILD, thereby reducing the influence of the planarization layer PLN on some first fan-out lines SD1 not covered by the protection layer 10.

[0110] Further, a part of the first part is in contact with the interlayer dielectric layer ILD, and another part is located on the side of the first fan-out line SD1 away from the first substrate substrate SUB1 and in contact with the first fan-out line SD1, i.e. it can be understood that at least part of the first fan-out line SD1 is surrounded by the first protection part 11 and the interlayer dielectric layer ILD, therefore, the first protection part 11 can avoid the first fan-out line SD1 being affected by the film layer separation of the planarization layer PLN. And the adhesion between the first protection part 11 and the interlayer dielectric layer ILD is large, so the first protection part 11 will not be separated from the interlayer dielectric layer ILD like the planarization layer PLN, and will not affect the first fan-out line SD1.

[0111] Figure 9 is a schematic diagram of the cross-sectional structure of the display substrate in some other embodiments of the present disclosure.

[0112] In some embodiments, as shown in Figure 9 the protection layer 10 in the embodiment of the present disclosure further includes a second protection part 12 located on the side of the planarization layer PLN away from the first substrate substrate SUB1.

[0113] In the embodiment of the present disclosure, the second protection part 12 is located on the side of the planarization layer PLN away from the first substrate substrate SUB1, as shown in Figure 9 the first protection part 11 and the second protection part 12 are connected as a whole protection layer 10, or it can also be understood that the protection layer 10 is continuous, i.e. the first protection part 11 and the second protection part 12 are connected, therefore, a part of the planarization layer PLN is surrounded by the protection layer 10 and the interlayer dielectric layer ILD. The adhesion between the protection layer 10 and the interlayer dielectric layer ILD is large, therefore, the protection layer 10 will not easily separate from the interlayer dielectric layer ILD, therefore, the film layer separation of the planarization layer PLN and the interlayer dielectric layer ILD can also be reduced or avoided in the embodiment of the present disclosure.

[0114] In addition, in the case that the planarization layer PLN not surrounded by the protective layer 10 and the interlayer dielectric layer ILD is separated from the interlayer dielectric layer ILD, the protective layer 10 of the present disclosure can also weaken the vibration degree of the planarization layer PLN after the separation, so as to avoid the impact of the planarization layer PLN on the first fan-out line SD1 of the lower film layer.

[0115] In some embodiments, as shown in FIG. 1, the display substrate TFT further includes a passivation layer PVX located on the side of the planarization layer PLN away from the first substrate substrate SUB1. The protective layer 10 is provided in the same layer as the passivation layer PVX and is made of the same material. Figure 9

[0116] In the present disclosure, the protective layer 10 can be prepared at the same time as the passivation layer PVX, i.e., the protective layer 10 and the passivation layer PVX are formed by using the same preparation process. Therefore, the present disclosure can simplify the preparation process and reduce the difficulty of preparation.

[0117] In some embodiments, the material of the protective layer 10 and the passivation layer PVX can be inorganic matter containing Si, such as at least one of SiO, SiN, and SiON.

[0118] In the present disclosure, SiN is selected as the material of the protective layer, for example. SiN is very dense and can well protect the first fan-out line SD and resist the invasion of water vapor. Further, the material of the protective layer 10 is similar to or the same as that of the passivation layer PVX, which can improve the adhesion of the protective layer 10 and the passivation layer PVX.

[0119] Figure 10 FIG. 2 is a schematic diagram of the cross-sectional structure of the display substrate TFT according to another embodiment of the present disclosure.

[0120] In some embodiments, as shown in FIG. 2, the protective layer 10 and the passivation layer PVX are connected as an integral structure. Figure 10

[0121] In the present disclosure, the protective layer 10 and the passivation layer PVX are connected as an integral continuous film layer, and a part of the protective layer 10 is in contact with the interlayer dielectric layer ILD, and the passivation layer PVX is located on the side of the planarization layer PLN away from the first substrate substrate SUB1. Therefore, the continuous film layer formed by the connection of the protective layer 10 and the passivation layer PVX can protect or fix the position of the planarization layer PLN during falling or impact, so as to avoid or slow down the film layer separation between the planarization layer PLN and the interlayer dielectric layer ILD. In the case that the planarization layer PLN and the interlayer dielectric layer ILD are separated, the position of the planarization layer PLN is limited, so as to avoid large displacement and vibration of the separated planarization layer PLN, thereby avoiding the impact on the first fan-out line SD1 of the accessory or other film layer structures. ​​

[0122] Figure 11 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure. Figure 12 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure.

[0123] As shown in Figure 8 , Figure 11 and Figure 12 , the display substrate TFT includes a protective layer 10 between the planarization layer PLN and the layer where the first fan-out line SD1 is located.

[0124] In embodiments of the present disclosure, a protective layer 10 is directly formed before the planarization layer PLN to protect the first fan-out line SD1. It can be clearly seen that embodiments of the present disclosure need to additionally increase a step of forming the protective layer 10 on the basis of the original display substrate TFT preparation process steps.

[0125] In embodiments shown in Figure 7 , Figure 9 and Figure 10 , the protective layer 10 is formed after the planarization layer PLN, specifically, after the planarization layer PLN is formed, the planarization layer PLN is patterned to form a first opening, and then the protective layer 10 is formed. However, as described in the foregoing embodiments, Figure 7 , Figure 9 , Figure 10 the protective layer 10 in the embodiments shown in Figure 7 , Figure 9 and Figure 10 can be prepared at the same time as the passivation layer PVX, and therefore,

[0126] Specifically, in one example, the original display substrate TFT preparation process steps include: sequentially forming a light shielding layer, a semiconductor layer, a gate metal layer, an interlayer dielectric layer ILD, a source-drain metal layer, a planarization layer PLN, a common electrode layer, a passivation layer PVX, and a pixel electrode layer on one side of the first substrate substrate SUB1.

[0127] In embodiments of the present disclosure, the display substrate TFT preparation process steps include: sequentially forming a light shielding layer, a semiconductor layer, a gate metal layer, an interlayer dielectric layer ILD, a source-drain metal layer, a protective layer 10, a planarization layer PLN, a common electrode layer, a passivation layer PVX, and a pixel electrode layer on one side of the first substrate substrate SUB1.

[0128] Although embodiments of the present disclosure have an additional step of separately preparing the protective layer 10, by Figure 8 , Figure 11 and Figure 12As shown, the protective layer 10 can cover the first fan-out line SD1 well, so as to isolate the planarization layer PLN and the first fan-out line SD1. Therefore, the embodiment of the present disclosure can completely avoid the influence of the planarization layer PLN on the first fan-out line SD1.

[0129] As shown, the protective layer 10 includes a plurality of third protective portions 13 arranged at intervals. The third protective portions 13 are the same as the extension direction of the first fan-out line SD1, and the third protective portions 13 cover at least part of the first fan-out line SD1. Figure 11

[0130] The embodiment of the present disclosure can cover and protect each first fan-out line SD1 by the third protective portion 13, so as to realize accurate protection of the first fan-out line SD1.

[0131] Meanwhile, compared with the embodiment without the protective layer 10, as shown, the depth of the planarization layer PLN embedded between the two adjacent third protective portions 13 in the embodiment of the present disclosure is greater than Figure 3 Figure 3 Therefore, the embodiment of the present disclosure can also limit the displacement and vibration amplitude of the planarization layer PLN which has film separation with the interlayer dielectric layer ILD, so as to reduce the influence caused by the film separation of the planarization layer PLN.

[0132] As shown, at least two third protective portions 13 are connected as an integral structure. Further, all third protective portions 13 are connected as an integral structure. Figure 12

[0133] In the embodiment of the present disclosure, at least two third protective portions 13 are connected as an integral structure, which can increase the contact area of the protective layer 10 and the interlayer dielectric layer ILD, so as to increase the adhesion of the protective layer 10 and the interlayer dielectric layer ILD.

[0134] Further, all third protective portions 13 are connected as an integral structure, which can reduce the step of patterning the protective layer 10, so as to reduce the preparation difficulty.

[0135] Figure 13 is a schematic diagram of a planar structure of a display substrate in another embodiment of the present disclosure.

[0136] In some embodiments, as shown, the fan-out area FA includes a plurality of first areas FA1 and second areas FA2 arranged along a third direction. The first areas FA1 are located on opposite sides of the second areas FA2 in the third direction. Figure 13

[0137] ​​​​For example, the fan-out region FA includes two first regions FA1 and a second region FA2, and the first region FA1 is located on opposite sides of the second region FA2 in the third direction.

[0138] Wherein, the third direction intersects the arrangement direction of the fan-out area FA and the bonding area PA1, and at least the first area FA1 is provided with a first fan-out line SD1, that is, at least the fan-out line SD in the first area FA1 includes the first fan-out line SD1, that is, a corresponding groove or protective layer 10 needs to be provided in the first area FA1. Alternatively, the fan-out lines SD in both the first area FA1 and the second area FA2 include the first fan-out line SD1, that is, a corresponding groove or protective layer 10 needs to be provided in both the first area FA1 and the second area FA2.

[0139] It is understood that in this embodiment of the present disclosure, the first region FA1 is located at the edge of the display substrate TFT compared to the second region FA2. During the drop impact, the film layer in the first region FA1 will be subjected to a greater impact than the film layer in the second region FA2. Therefore, the planarization layer PLN and the first fan-out line SD1 in the first region FA1 will be more affected. Thus, the first fan-out line SD1 is more likely to fail in the first region FA1.

[0140] Therefore, in this embodiment of the present disclosure, at least a corresponding groove and / or protective layer 10 are provided in the first region FA1 to protect the planarization layer PLN and the first fan-out line SD1 in the first region FA1, so as to avoid the problem of the first fan-out line SD1 being faulty in the first region FA1 as much as possible.

[0141] In some embodiments, such as Figure 13 As shown, the fan-out region FA includes a first region FA1 and a second region FA2 arranged along a third direction. The first fan-out line SD1 is located in the first region FA1. The display substrate TFT also includes a second fan-out line SD2SD located in the second region FA2. The distribution density of the first fan-out line SD1 in the first region FA1 is greater than the distribution density of the second fan-out line SD2SD in the second region FA2.

[0142] Obviously, in this embodiment of the present disclosure, the groove and the protective layer 10 are respectively set in the area where the distribution density of the fan-out line SD in the fan-out area FA is relatively large.

[0143] As mentioned above, the denser the fan-out line SD, the more easily the fan-out line SD will be affected and become defective when the planarization layer PLN separates from the interlayer dielectric layer ILD or from the fan-out line SD.

[0144] Therefore, the embodiments of the present disclosure set the corresponding grooves and / or protective layer 10 in the first area FA1 to protect the planarization layer PLN and the first fan-out line SD1 in the first area FA1, so as to avoid the problem of poor first fan-out line SD1 in the first area FA1 with higher distribution density.

[0145] Optionally, as shown in Figure 13 The display substrate TFT further includes pad areas PA2 located on opposite sides of the binding area PA1 in the third direction, and the pad areas PA2 are provided with a plurality of test pads. In one example, some of the test pads can be electrically connected to the binding pads of the binding area PA1, so that when the display substrate TFT is tested, the display substrate TFT can be provided with data driving signals through the test pads.

[0146] In some embodiments, the materials of the interlayer dielectric layer ILD and the protective layer 10 both include inorganic materials. For example, both can include Si-containing inorganic materials, and specifically, for example, can include at least one of SiO, SiN, and SiON.

[0147] In the embodiments of the present disclosure, the interlayer dielectric layer ILD and the protective layer 10 both select inorganic materials, which can increase the adhesion between the interlayer dielectric layer ILD and the protective layer 10. Further, the materials of the interlayer dielectric layer ILD and the protective layer 10 can be the same, so as to maximize the adhesion between the interlayer dielectric layer ILD and the protective layer 10, thereby avoiding film separation between the protective layer 10 and the interlayer dielectric layer ILD.

[0148] Figure 14A is a schematic plan view of the fan-out area in some embodiments of the present disclosure. Specifically, it can be a schematic plan view of the second area FA2. Figure 14B and Figure 14C are respectively Figure 14A schematic plan views of each single film layer in Figure 14B Specifically, it is a schematic plan view of the planarization layer PLN in Figure 14A Figure 14C is a schematic plan view of the first fan-out line SD1 in Figure 14A

[0149] As shown in Figure 14A The plurality of first openings are arranged along the first direction, and the first openings extend along the second direction, which is perpendicular to the first direction.

[0150] In fact, the extension direction of the first opening and the arrangement direction of the plurality of first openings in the embodiments of the present disclosure can be selected at will.

[0151] ​​Optionally, the first opening can have a rectangular, circular, elliptical, polygonal, irregular shape or the like on the first substrate SUB1, and the present disclosure does not limit the shape of the first opening. In order to improve the yield and ensure the exposure of the first opening to the interlayer dielectric layer ILD and the first fan-out line SD1 to ensure the adhesion between the interlayer dielectric layer ILD and the protective layer 10, the present disclosure sets the shape of the first opening on the first substrate SUB1 to be rectangular or circular rectangular.

[0152] Correspondingly, Figure 7 、 Figure 8 The cross-sectional view of the embodiment provided with the first opening is a cross-sectional structure schematic diagram that can be cut along the first direction width direction. For example, it can be a cross-sectional structure schematic diagram cut along the cutting line YY' in Figure 14A .

[0153] In order to improve the yield and reduce the preparation difficulty, the second direction is set to be the same as the extension direction of the data line in the present disclosure.

[0154] Figure 15A is a planar structure schematic diagram of the fan-out area in another embodiment of the present disclosure. Specifically, it can be a planar structure schematic diagram of the second area FA2. Figure 15B is a planar structure schematic diagram of the planarization layer PLN in Figure 15A . Figure 15A The planar structure schematic diagram of the first fan-out line SD1 in the present disclosure can be the same as the planar structure schematic diagram of the first fan-out line SD1 shown in Figure 14C .

[0155] Similarly, in order to improve the yield and reduce the preparation difficulty, the second direction is set to be the same as the extension direction of the gate line in the present disclosure.

[0156] Figure 16A is a planar structure schematic diagram of the fan-out area in another embodiment of the present disclosure. Specifically, it can be a planar structure schematic diagram of the second area FA2. Figure 16B is a planar structure schematic diagram of the planarization layer PLN in Figure 16A . Figure 16A The planar structure schematic diagram of the first fan-out line SD1 in the present disclosure can be the same as the planar structure schematic diagram of the first fan-out line SD1 shown in Figure 14C .

[0157] Similarly, in order to improve the yield and reduce the preparation difficulty, the second direction is set to be the same as the extension direction of the first fan-out line SD1 in the present disclosure.

[0158] In conclusion, the width of the first opening is greater than the width of the first fan-out line SD1, so that the protective layer can have a part located on the side of the first fan-out line SD1 away from the first substrate substrate SUB1, and the protective layer also has a part in contact with the interlayer dielectric layer ILD, thereby ensuring the protective effect of the protective layer 10 on the first fan-out line SD1.

[0159] It should be noted that the first opening in the drawings of the embodiments of the present disclosure does not represent its specific size, and the specific size and position can be adjusted according to different products. For example, in one example, the size of the first region in the third direction is about 8mm wide, and the number of first openings is about 500 or so.

[0160] In some other embodiments, the present disclosure also provides a display panel, including the display substrate TFT as described in any embodiment of the present disclosure.

[0161] In some other embodiments, the display panel further includes: a cell alignment substrate CF arranged opposite to the display substrate TFT, and a sealant SEAL located between the display substrate TFT and the cell alignment substrate CF.

[0162] The normal projection of the sealant SEAL on the first substrate substrate SUB1 surrounds the display area AA, and overlaps with the normal projection of the first fan-out line SD1 on the first substrate substrate SUB1.

[0163] In the embodiments of the present disclosure, the normal projection of the sealant SEAL on the first substrate substrate SUB1 overlaps with the normal projection of the first fan-out line SD1 on the first substrate substrate SUB1, that is, further known that the normal projection of the sealant SEAL on the first substrate substrate SUB1 overlaps with the normal projection of at least one of the groove and the protective layer 10 on the first substrate substrate SUB1.

[0164] Therefore, on the basis of the setting of the protective layer 10 and the groove which can realize the protection of the first fan-out line SD1, that is, on the basis of the vibration and displacement of the planarization layer PLN after the film layer separation, the setting of the protective layer 10 and the groove of the embodiments of the present disclosure can further alleviate or avoid the influence on the sealant SEAL due to the excessive vibration or displacement of the planarization layer PLN, and avoid the generation of the liquid leakage problem.

[0165] Specifically, as shown in Figure 7 and Figure 8 The display substrate TFT includes a protective layer 10, the planarization layer PLN is provided with at least one first opening, and a part of the sealant SEAL is located in the first opening and in contact with the surface of the protective layer 10 away from the first substrate substrate SUB1.

[0166] Obviously, in Figure 3In the illustrated embodiment, a portion of the sealant SEAL is in contact with the planarization layer PLN away from the first substrate substrate SUB1, and thus, in the case of excessive vibration of the planarization layer PLN, the sealant SEAL can be damaged, resulting in liquid leakage.

[0167] In the embodiment of the present disclosure, the sealant SEAL is in contact with the protective layer 10 away from the surface of the first substrate substrate SUB1, and the protective layer 10 can be well attached to the interlayer dielectric layer ILD and does not separate from the film layer, so that the embodiment of the present disclosure can avoid damage to the sealant SEAL caused by large vibration due to film layer separation of the protective layer 10 caused by impact.

[0168] In addition, the embodiment of the present disclosure also increases the contact area of the protective layer 10 and the sealant SEAL, and thus can increase the adhesion between the protective layer 10 and the sealant SEAL.

[0169] Further, the protective layer 10 can also slow down the film layer separation and vibration of the planarization layer PLN, so that the embodiment of the present disclosure can also slow down or avoid damage to the sealant SEAL caused by the planarization layer PLN.

[0170] Therefore, the embodiment of the present disclosure can avoid the problem of liquid leakage of the display panel.

[0171] In summary, the present disclosure proposes a new technical solution according to the problem of display failure caused by falling impact and the like of the display device, for example, one solution is to design a groove in the planarization layer PLN covered by the sealant SEAL in the original process, and use the protective layer 10 to cover the first fan-out line SD1, so that even if the planarization layer PLN is lifted and displaced, it will not scratch the first fan-out line SD1. Another solution is to increase the process of the protective layer 10 based on the original process, which can be covered by SiN or SiO2 alone, and the densely packed area of the first fan-out line SD1 is covered and protected, thereby improving the anti-falling level of the product.

[0172] The present disclosure also provides a display device comprising the display panel as described in any embodiment of the present disclosure.

[0173] In summary, the embodiment of the present disclosure designs a groove and a protective layer in the weak area of the fan-out area, such as the densely packed area of the fan-out line in the fan-out area, so as to protect the fan-out line from being scratched by the planarization layer PLN caused by falling and the like, and to increase the contact area of the sealant to achieve the effect of not deteriorating the adhesion, thereby improving the strength of the display panel in falling and the like. Therefore, the groove and the stacked protective layer structure proposed in the embodiment of the present disclosure can not only prevent the falling line from being scratched, but also improve the local adhesion and the strength of the product.

[0174] The first region in the embodiments of the present disclosure is merely an example region as a problem occurrence region, and there can be slight changes in different actual products. The ultimate purpose of the embodiments of the present disclosure is to protect dense wiring and prevent the separation and displacement of the planarization layer PLN and the lower film layer to cause the fan-out line to be scratched in the process of drop vibration and other strength tests.

[0175] It can be understood that the above implementation is only an exemplary implementation adopted for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A display substrate comprising a display area, a bonding area located on one side of the display area, and a fan-out area located between the display area and the bonding area, characterized in that, The display substrate includes: Substrate; An interlayer dielectric layer and multiple data lines are located on one side of the substrate. The data lines are disposed on the side of the interlayer dielectric layer away from the substrate and are located in the display area. Multiple first fan-out lines are disposed on the side of the interlayer dielectric layer away from the substrate and located in the fan-out region; the first fan-out lines are electrically connected to the data lines. A planarization layer is located on the side of the layer containing the first fan-out line that is away from the substrate, and a portion of the planarization layer is in contact with the interlayer dielectric layer. The interlayer dielectric layer has multiple grooves, at least a portion of the first fan-out line is located in the grooves, and the thickness of the first fan-out line is different from the depth of the grooves. And / or, the display substrate further includes a protective layer located on the side of the first fan-out line away from the substrate, a portion of the protective layer being in contact with the interlayer dielectric layer, and the adhesion between the protective layer and the interlayer dielectric layer being greater than the adhesion between the planarization layer and the interlayer dielectric layer.

2. The display substrate according to claim 1, characterized in that, The display substrate also includes a protective layer; The planarization layer has at least one first opening, the first opening exposing at least a portion of the first fan-out line and a portion of the interlayer dielectric layer. The protective layer includes a first protective portion located within the first opening. A portion of the first protective portion is disposed in contact with the surface of the interlayer dielectric layer away from the substrate. Another portion of the first protective portion is located on the side of the first fan-out line away from the substrate and is disposed in contact with the first fan-out line.

3. The display substrate according to claim 2, characterized in that, The protective layer also includes a second protective portion located on the side of the planarization layer away from the substrate.

4. The display substrate according to claim 2, characterized in that, There are multiple first openings, which are arranged along a first direction and extend along a second direction, which intersects the first direction. Wherein, the second direction is the same as the extension direction of either the first fan-out line or the data line, or the display substrate further includes a gate line located in the display area, the gate line being intersected with the data line, and the second direction being the same as the extension direction of the gate line.

5. The display substrate according to claim 2, characterized in that, The display substrate further includes a passivation layer located on the side of the planarization layer away from the substrate. The protective layer and the passivation layer are disposed in the same layer and are made of the same material.

6. The display substrate according to claim 5, characterized in that, The protective layer and the passivation layer are connected as a single structure.

7. The display substrate according to claim 1, characterized in that, The display substrate includes a protective layer located between the planarization layer and the layer containing the first fan-out line.

8. The display substrate according to claim 7, characterized in that, The protective layer includes a plurality of spaced-apart third protective portions, which extend in the same direction as the first fan-out line and cover at least a portion of the first fan-out line.

9. The display substrate according to claim 8, characterized in that, At least two of the third protection units are connected as a single structure.

10. The display substrate according to any one of claims 1 to 9, characterized in that, The fan-out area includes a plurality of first areas and second areas arranged along a third direction. The first areas are located on opposite sides of the second areas along the third direction. The third direction intersects the arrangement direction of the fan-out area and the binding area. At least the first area is provided with the first fan-out line.

11. The display substrate according to any one of claims 1 to 9, characterized in that, The fan-out area includes a first region and a second region arranged along a third direction. The first fan-out line is located in the first region. The display substrate also includes a second fan-out line located in the second region. The distribution density of the first fan-out line in the first region is greater than the distribution density of the second fan-out line in the second region.

12. The display substrate according to any one of claims 2 to 9, characterized in that, Both the interlayer dielectric layer and the protective layer are made of inorganic materials.

13. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1 to 12.

14. The display panel according to claim 13, characterized in that, The display panel also includes: The cell substrate is disposed opposite to the display substrate; The sealing adhesive is located between the display substrate and the cell substrate. The orthographic projection of the sealing adhesive on the substrate surrounds the display area and overlaps with the orthographic projection of the first fan-out line on the substrate.

15. The display panel according to claim 14, characterized in that, The display substrate includes a protective layer, the planarization layer has at least one first opening, and a portion of the sealing adhesive is located within the first opening and in contact with the surface of the protective layer away from the substrate.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 13 to 15.

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