Data integrity verification method and device and electronic equipment

Abstract

The embodiment of the invention provides a data integrity verification method and device, electronic equipment and a readable storage medium, and the method comprises the steps: writing first data into a first storage area, and calculating a first check code of the first data; determining a storage address corresponding to each check bit in the first check code; writing the first check code into a second storage area according to the storage addresses corresponding to all the check bits; reading the first data from the first storage area, and reading a first check code from the second storage area according to the storage addresses corresponding to all check bits; according to the comparison result of the first check code and the second check code, the integrity of the first data is determined, and the efficiency of verifying the data integrity is improved by improving the speed of writing and reading the check codes.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data integrity verification method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] Static random access memory (SRAM) uses a six-transistor structure to store data, offering advantages such as high-speed access, low power consumption, and no need for refresh, making it widely used in high-performance applications such as processor caches and communication devices. However, as semiconductor processes have advanced to the nanometer scale, the single-event fault rate (SIF) of SRAM has increased significantly, and bit flips caused by high-energy particle impacts have become a major threat to reliability.

[0003] In related technologies, error correction codes are used in static random access memory (SRAM) to add check bits to the original data, enabling the system to detect and correct problems that may occur during transmission or storage. However, when using error correction codes, the encoding and decoding processes introduce additional latency during data reading or writing from SRAM, and frequent read and write operations lead to a significant increase in dynamic power consumption. Summary of the Invention

[0004] This application provides a data integrity verification method, apparatus, electronic device, and readable storage medium, which can improve the efficiency of data integrity verification.

[0005] In a first aspect, embodiments of this application disclose a data integrity verification method, the method comprising:

[0006] Write the first data into the first storage area and calculate the first check code of the first data; the first check code consists of check bits, each check bit being one bit.

[0007] Determine the storage address corresponding to each check bit in the first check code;

[0008] Write the first check code into the second storage area according to the storage address corresponding to all check bits;

[0009] Read the first data from the first storage area, and read the first check code from the second storage area according to the storage address corresponding to all check bits;

[0010] The integrity of the first data is determined based on the comparison result of the first check code and the second check code; the second check code is calculated after the first data is read.

[0011] Secondly, embodiments of this application disclose a data integrity verification device, the device comprising:

[0012] The first write module is used to write the first data into the first storage area and calculate the first check code of the first data; the first check code is composed of check bits, and each check bit is one bit.

[0013] The address determination module is used to determine the storage address corresponding to each check bit in the first check code;

[0014] The second writing module is used to write the first check code into the second storage area according to the storage address corresponding to all check bits.

[0015] The reading module is used to read the first data from the first storage area and read the first check code from the second storage area according to the storage address corresponding to all check bits.

[0016] The verification module is used to determine the integrity of the first data based on the comparison result of the first verification code and the second verification code; the second verification code is calculated after the first data is read out.

[0017] Thirdly, embodiments of this application disclose an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the aforementioned data integrity verification method.

[0018] Fourthly, embodiments of this application disclose a readable storage medium, which, when the instructions in the readable storage medium are executed by the processor of an electronic device, enables the electronic device to perform the aforementioned data integrity verification method.

[0019] The embodiments of this application have the following advantages:

[0020] In this embodiment, each check bit in the checksum is assigned an independent storage address, allowing the processor to directly access each check bit via the storage address. When writing first data to the first storage area, each check bit in the first checksum is written to the second storage area according to its corresponding storage address. When reading first data from the first storage area, the first checksum is automatically read bit by bit from the second storage area, and the second checksum is calculated based on the read data. The first and second checksums are then compared bit by bit. During the reading and writing of first data, the checksum is read and written according to the storage address corresponding to each check bit. Since each check bit has an independent address, a fine-grained verification strategy can be implemented. Furthermore, the address-based method of reading checksums improves the speed of reading and writing checksums, thereby increasing the speed of verifying data integrity by comparing checksums. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating the steps of an embodiment of the data integrity verification method of the present invention;

[0023] Figure 2 This is a flowchart illustrating the steps of another embodiment of the data integrity verification method of the present invention;

[0024] Figure 3 This is an architecture diagram of a data integrity verification system according to the present invention;

[0025] Figure 4 This is a flowchart of the steps for writing data and verification codes according to the present invention;

[0026] Figure 5 This is a flowchart illustrating the steps of reading data and verification codes according to the present invention;

[0027] Figure 6 This is a structural block diagram of a data integrity verification device according to the present invention;

[0028] Figure 7 This is a structural block diagram of an electronic device provided by an example of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0031] Before describing the present invention, the application scenarios of the present invention will be explained first:

[0032] Static Random-Access Memory (SRAM) is widely used in computers, servers, and communication storage devices due to its high integration, high speed, and low power consumption. Reliability and data integrity are crucial factors for storage devices, requiring that the data in the memory not be corrupted by environmental conditions. SRAM is particularly sensitive to single-event upsets (SOME), which can cause unpredictable flips in the data stored in SRAM, leading to changes in the data.

[0033] To improve SRAM reliability, error-correcting code (ECC) mechanisms are used in system and SRAM design to detect data changes and correct them. Specifically, using Hamming codes as an example, 8 parity bits are added to every 64 bits of data in the SRAM. These parity bits are generated based on the data bits and stored in an extra area of ​​the SRAM. When data is read, the parity bits are recalculated, and single-bit errors are located and corrected using an XOR operation, while double-bit errors are detected. The traditional ECC mechanism's process of calculating parity bits, decoding them, and comparing the previously written parity code with the recalculated parity code increases the time spent reading and writing to the SRAM, reducing efficiency. In scenarios with high-frequency SRAM read / write operations, this can degrade overall system performance.

[0034] Method Implementation Examples

[0035] Reference Figure 1The diagram illustrates a flowchart of an embodiment of a data integrity verification method according to the present invention. The method may specifically include the following steps:

[0036] Step 101: Write the first data into the first storage area and calculate the first check code of the first data; the first check code consists of check bits, each check bit being one bit.

[0037] Step 102: Determine the storage address corresponding to each check bit in the first check code;

[0038] Step 103: Write the first check code into the second storage area according to the storage address corresponding to all check bits;

[0039] Step 104: Read the first data from the first storage area, and read the first check code from the second storage area according to the storage address corresponding to all check bits;

[0040] Step 105: Determine the integrity of the first data based on the comparison result of the first check code and the second check code; the second check code is calculated after the first data is read out.

[0041] Regarding steps 101-105, the data integrity verification method provided in this application embodiment can be used in systems requiring high reliability, such as aerospace electronics, medical devices, industrial control systems, server memory, and network equipment. The data stored in Static Random-Access Memory (SRAM) needs to be protected against data corruption due to soft errors, such as bit flips caused by cosmic rays or electromagnetic interference. SRAM is a common type of semiconductor volatile memory, typically read and written in units of bytes or words. When a processor reads or writes data to SRAM, it usually bases its reading on the starting address of a corresponding byte or word. SRAM is characterized by fast read / write speeds, no need for refresh, resulting in stable access time, but also relatively high power consumption and cost.

[0042] The first data refers to the information that needs to be stored in and protected in SRAM. It is the object of computation and manipulation. In SRAM, the first data is represented as a set of binary bits. For example, a 32-bit integer, a piece of program code, or a configuration parameter are stored in the first storage area. The checksum is a redundant information, calculated by applying a specific mathematical algorithm to the first data. The purpose of the checksum is to verify the integrity of the original data. When the first data is read, the checksum is recalculated and compared with the previously stored checksum. If the two checksums match, it means that the data was likely not corrupted during its storage in SRAM; if they do not match, it means that the data in SRAM may have been corrupted. The checksum consists of multiple check bits, each an independent bit, 0 or 1. The first checksum is calculated using a specific mathematical algorithm when the first data is written to SRAM; the second checksum is calculated using the same mathematical algorithm when the first data is read from SRAM. The checksums are calculated at different times: once before storage in SRAM and once after storage in SRAM. These two checksum calculations reflect whether the first data was tampered with during its storage in SRAM.

[0043] It should be noted that the calculation methods for the first and second check bits include: parity check, Hamming code, and cyclic redundancy check. Parity check calculates whether the number of 1s in the first data bit is odd or even, adding a bit to make the total odd or even. Parity check can only detect errors in odd-numbered bits and cannot correct the errors in the first data bit. Hamming code, compared to parity check, is a more powerful encoding method. By inserting multiple check bits into the data bits, it can not only detect single-bit errors but also correct them. The number and position of check bits follow specific rules. Cyclic redundancy check is commonly used in communication and data storage. It generates the check bit through polynomial division and has excellent detection capabilities for burst errors.

[0044] A memory address is a unique identifier for each addressable cell in SRAM. The processor accesses a specific memory location via an address and writes or reads data from that location. Processors typically allocate addresses in bytes. For example, address 0x0000 points to the first byte, address 0x0001 points to the second byte, and so on. In traditional schemes, the entire checksum is packaged and stored in one or more consecutive byte addresses. This scheme, however, assigns an independent, processor-addressable memory address to each individual check bit in the checksum, meaning each check bit, like a data bit, has its own "address."

[0045] The first memory area is a dedicated region in SRAM for storing the initial data. When the processor operates on the first memory area, it accesses the data by addressing bytes (or words). The address points to the starting position of the data byte or word. The second memory area is a dedicated region in the system for storing the initial checksum. The processor assigns a separate byte (or word) address to each check bit in the checksum. It should be noted that the second memory area can be located in SRAM, just like the first memory area, or it can be another type of memory.

[0046] For example, the first data is 0x55, which is 01010101 in binary and occupies 1 byte. Odd parity is used to calculate the checksum. Odd parity requires that the total number of 1s in the data bits and check bits is odd. The data 01010101 has four 1s, so the number of 1s is even. To achieve odd parity, the check bit needs to be set to 1. Thus, the data and check bits are 010101011, with a total of five 1s, which is an odd number of 1s. Therefore, the first checksum is 1, which is one bit.

[0047] The first data is pre-allocated at address 0x1000 in the first storage area, and the parity bit is allocated at address 0x2000 in the second storage area. The first data is written to 0x1000, and the parity calculation circuit performs odd parity calculation on the written data 0x55. The calculation result is that the first parity code = 1, and the parity bit in the first parity code is written to 0x2000. It should be noted that the address corresponding to each parity bit is determined during system configuration or design. In this example, there is only one parity bit, which is allocated to address 0x2000. It should be noted that this address 0x2000 is a byte address that the processor can access. Although only one bit in the address is used to store the parity bit, the processor addresses bytes. The processor needs to write the value 1 to address 0x2000, and because the processor writes bytes, it cannot directly write only a single bit. The entire byte content at address 0x2000 is read, and bit manipulation is used to modify the value of a single bit in the entire byte address to 1, while the other bits remain unchanged.

[0048] When the processor reads the first data, it reads one byte from data address 0x1000. Assume the read value is D_read; the processor knows the parity bit is stored at address 0x2000. The processor reads all bytes corresponding to address 0x2000. Using the just-read data D_read, it recalculates the odd parity bit to obtain the second parity bit. Assuming D_read is 0x55, the recalculated second parity bit should be 1. If D_read becomes 0x54 due to an error, the binary form of 0x54 is 01010100, which has only three 1s, an odd number of 1s. Therefore, the recalculated second parity bit should be 0. The recalculated second parity bit is compared with the first parity bit read from the second storage area. Since D_read = 0x55, the second parity bit = 1, and the first parity bit = 1, the first and second parity bits are the same, indicating that the first data did not change during its storage in SRAM and is complete. When D_read = 0x54, the second check code is 0. The first check code and the second check code are different, which means that the data on which the first check code is calculated is different, indicating that the first data has changed during its storage in SRAM.

[0049] In this embodiment, each check bit in the checksum is assigned an independent storage address, allowing the processor to directly access each check bit via the storage address. Since each check bit has an independent address, a fine-grained verification strategy can be implemented. Furthermore, in this embodiment, the processor accesses the check bits via address addressing. In related technologies, regardless of whether the checksum has one or more bits, it is always stored in a package; for example, eight check bits occupy one complete byte address. Reading the checksum requires reading and writing the entire byte, while the processor reads the checksum bits from the checksum based on the byte address. When the checksum consists of multiple check bits, each check bit needs to be extracted for comparison. In this process, each check bit cannot be directly obtained from its address; bit offset operations are required to extract each individual check bit. However, in this embodiment, the address addressing method for reading check bits improves the speed of reading and writing check bits, thereby increasing the speed of comparison based on check bits and improving the data integrity verification rate.

[0050] Reference Figure 2 The flowchart illustrates another embodiment of the data integrity verification method of the present invention, which may specifically include the following steps:

[0051] Step 201: Write the first data into the first storage area and calculate the first check code of the first data; the first check code consists of check bits, each check bit being one bit;

[0052] Step 202: Determine the memory mapping relationship between the third storage area and the second storage area based on the number of bits of data processed by the processor each time; the second storage area is the mapping region of the third storage area;

[0053] Step 203: Based on the memory mapping relationship, determine the storage address of each check bit in the first check code in the second storage area.

[0054] Regarding steps 201-203, in this embodiment, the number of bits of data processed by the processor refers to the maximum number of bits of data that the processor can process in parallel or transmit via the data bus at one time. The number of bits is typically determined by the processor's word length and the data bus width. Common values ​​for the number of bits are typically 8 bits, 16 bits, 32 bits, and 64 bits. For example, a 32-bit processor typically has 32-bit wide general-purpose registers, and its data bus width is also typically 32 bits, or 4 bytes. A 64-bit processor typically has 64-bit wide general-purpose registers, and its data bus width is also typically 64 bits, or 8 bytes. Processors typically access memory most efficiently when the alignment matches their word length / bus width. For example, a 32-bit processor is fastest at reading and writing a 32-bit (4-byte) aligned word. Forcing the reading and writing of single bits or unaligned bytes requires additional special operations, which reduces the efficiency of data reading.

[0055] Reference Figure 3 This diagram illustrates the architecture of a data integrity verification system according to the present invention. The system includes a data integrity verification device, a memory mapping relationship between a third storage area and a second storage area, and the ability to write first data from and read first data from the first storage area. A checksum is read from the second storage area and written back to the second storage area. When the checksum is written to the second storage area, the checksum in the third storage area changes according to the preset memory mapping relationship. The third storage area is also the storage area for check bits. In the third storage area, check bits are typically stored tightly packed in SRAM cells, just like ordinary data bits. For example, 8 check bits may be tightly stored in one byte (8 bits) of physical address space. 32 check bits may be tightly stored in four consecutive bytes (or one 32-bit word) of physical address space. At the physical layer, the third storage area is stored bit-by-bit, but the processor cannot directly address individual bits.

[0056] The second memory region is another physical area. The content stored in the second memory region is not an independent copy of the parity bit, but rather an "access view" of the third memory region. The second memory region is a physical access area mapped to the third memory region. Memory mapping refers to a hardware mechanism that listens for accesses to specific addresses in the second memory region and translates them into read or write operations to specific single parity bits in the third memory region. This hardware mechanism typically includes a custom memory controller and address decoding logic. Memory mapping is a fixed, hardware-implemented physical address translation rule. It defines which physical address in the second memory region a specific physical parity bit in the third memory region corresponds to, and also defines which bit in the third memory region the hardware should perform and what operation when the processor reads or writes to a certain address in the second memory region. The establishment of memory mapping is usually implemented during system design through hardware circuitry (address decoders, multiplexers, etc.), or set by firmware configuration of dedicated controller registers during system startup.

[0057] For example, if the processor word length is 32 bits, and a specific single parity bit in the third memory area is mapped to an address unit in the second memory area, then accessing a 32-bit physical address in the second memory area actually only operates on one bit in the third memory area, and the processor reads and writes the address in the second memory area as if it were ordinary memory.

[0058] Optionally, step 202 may specifically include:

[0059] Step S11: Determine the correspondence between the number of bits in the third storage area and the number of bits in the second storage area based on the number of bits the processor reads each time;

[0060] Step S12: Determine the memory mapping relationship based on the starting address of the third storage area, the starting address of the second storage area, and the quantity correspondence.

[0061] Regarding steps S11 and S12, it should be noted that the physical memory region where the parity bit is tightly packed and stored is the second memory region, which is an additional physical memory region. A specific single parity bit in the third memory region is mapped to an address in the second region; a processor word-length address unit in the second region is hardware-mapped to a specific single parity bit in the third memory region.

[0062] The quantity mapping relationship refers to the correspondence between the number of bits corresponding to an address in the second memory region and the number of bits corresponding to a single address in the third memory region. For example, if the processor is 32-bit, then a bit in the third memory region maps to a memory address in the second memory region, and that memory address in the second memory region corresponds to 32 bits. The memory mapping relationship is an abstract formula that defines how to uniquely and efficiently read and write a specific parity bit in the third memory region by accessing each specific physical address in the second memory region.

[0063] The correspondence between quantities is the core ratio, defining the space occupied when a bit in the third storage area is mapped to the second storage area. It also defines the interval between each parity bit in the second storage area when parity bits are stored there. The starting addresses of the two storage areas serve as positioning references. The starting address of the third storage area provides the starting point of the mapping region, while the starting address of the second storage area defines the base point for mapping bits from the third storage area to the second storage area. Given the starting address and the space occupied by each bit mapped to the second storage area, the corresponding storage address for each bit in the third storage area mapped to the second storage area can be determined using this calculation formula.

[0064] Optionally, step S12 may specifically include:

[0065] Step S21: Map the first bit of the starting address of the third storage area to the starting address of the second storage area;

[0066] Step S22: Based on the quantity correspondence, determine each bit in the third storage area and map it to the target address in the second storage area.

[0067] Regarding steps S21 and S22, the starting address of the third storage area is the physical memory address of the first byte in the third storage area. The starting address of the second storage area is the physical memory address of the first byte in the second storage area. The target address refers to the starting address of a physical address unit of processor word size within the second storage area that is specifically mapped to a specific bit in the third storage area. Accessing the "target address" of the second storage area allows indirect manipulation of the corresponding specific bit. The starting addresses of the two storage areas define the starting point of the mapping. Based on the correspondence between the quantities and the mapping starting point, the storage address of each bit in the third storage area within the second storage area can be determined. This defines how to calculate the unique target address of each bit in the third storage area within the second storage area. This target address is the "gateway" to accessing that bit. The target address is a physical address in the second storage area. In this embodiment, the target address points to a storage unit of processor word size. Read and write operations on the target address are transparently and atomically converted into operations on specific bits in the third storage area at the hardware level. The actual effects of memory mapping (address translation, bit positioning, atomic operations) are entirely implemented by dedicated hardware (memory controller / custom logic), while the software only needs to follow the mapping rules to access the target address.

[0068] For example, the processor word length is 32 bits, and the byte size is 4. The starting address of the third storage area is PHY_SRC_BASE = 0x2000_0000. The starting address of the second storage area is PHY_MAP_BASE = 0x3000_0000. When it is necessary to access the parity bit with index N=5 in the third storage area, the first bit of the third storage area (N=0, bit 0 at 0x2000_0000) is mapped to the starting address 0x3000_0000 of the second storage area. The quantity correspondence is that one bit in the third storage area corresponds to 32 bits in the second storage area. The target address N=5 is calculated by increasing the number of bits based on the starting address. Accessing the physical address 0x3000_0014 of the second storage area is equivalent to operating on the bit with index 5 in the third storage area. After the target address of bit 5 in the second storage area is determined, writing N=5 bits to 1 may include the following steps: The software writes the value 0x00000001 to address 0x3000_0014. The hardware detects the write to 0x3000_0014, calculates the corresponding operation location in the third storage area according to the memory mapping relationship, locates the starting position of the third storage area with a bit offset of 5, which is reading 0x2000_0000, sets bit 5 at that position to 1, and writes the modified data back to 0x2000_0000. Reading N=5 bits may include the following steps: The software reads from address 0x3000_0014, the hardware calculates N=5 according to the memory mapping relationship, the hardware reads the bit 5 value of byte 0x2000_0000, the hardware returns 0x00000001, the software checks bit 0 of the return value and obtains the check bit value of 1.

[0069] Step 204: For each check bit in the first check code, determine the byte corresponding to the data in the second storage area based on the storage address;

[0070] Step 205: Write the check bit into the least significant bit of the byte.

[0071] For steps 204 and 205, the address is allocated byte-by-byte. However, in the storage unit corresponding to that address, only the least significant bit or a specific bit is used to store that specific parity bit. The other bits are idle and are not used or used for other purposes. Since the parity bit is stored in the least significant bit, it can be read directly based on the address, without needing to perform bit operations to read or write the parity bit when accessing the second storage area.

[0072] For example, the first checksum is a bit sequence: bit0, bit1, bit2, ..., bitM-1, a total of M bits. The storage address corresponding to each checksum bit is stored in a pre-calculated list (e.g., addr_bit0, addr_bit1, addr_bit2, ..., addr_bitM-1). Each address points to a byte in the second storage area. The following operations are performed on each checksum bit_i (i from 0 to M-1) in the first checksum: The storage address addr_i corresponding to the checksum bit_i is obtained. The address addr_i directly indicates which specific byte in the second storage area should contain the checksum bit_i. One byte corresponds to 8 bits. In this embodiment, one byte address points to one byte. Each checksum bit_i determines its target byte position in the second storage area. The processor reads the entire content (8 bits) of the current byte from address addr_i. The processor modifies the least significant bit of the current byte while keeping the high 7 bits of the entire byte unchanged. It then replaces the least significant bit of the entire byte with the value of the current parity bit_i (0 or 1), resulting in the modified byte value. The processor writes the modified byte value back to address addr_i. Processors and memory typically read and write in bytes (or words) as the smallest unit.

[0073] It should be noted that when the ratio of the number of the third storage area to the number of the second storage area is 1:32, that is, one bit in the third storage area maps to a target address in the second storage area, and this target address corresponds to 32 bits, or 4 bytes. Therefore, when writing the parity bit to the target address, the least significant bit of the 4 bytes is modified. The parity bit is written to the least significant bit of the 4 bytes, leaving the other 31 bits unchanged, or leaving the other 31 bits idle.

[0074] Compared to the complex "read-modify-write" operations typically required at the hardware level when directly writing a single bit, assigning each parity bit to an independent byte address and fixing the least significant bit of that byte to be written greatly simplifies the operation. When writing a parity bit to the second storage area, it is only necessary to read the target byte, modify its least significant bit, and write the data back to the entire byte. When reading a parity bit, the byte address is read, and the value of its least significant bit is directly extracted. All parity bits are stored in the same location within their respective bytes, making the read and write logic rules uniform, and simplifying and making the hardware design and software operation simpler and more predictable. Furthermore, each parity bit occupies an independent byte address, meaning that writing a parity bit only affects its own byte, without accidentally overwriting or interfering with other parity bits or other data stored in the second storage area, providing clear isolation and ensuring that the storage of each parity bit is independent. Processors are naturally adept at addressing and manipulating bytes, and the method in this embodiment fully utilizes this fundamental capability of the processor to manage bits, improving the efficiency of reading and writing parity bits, and thus improving the efficiency of verifying data integrity using the same parity bit.

[0075] Step 206: Read the first data from the first storage area, and read the first check code from the second storage area according to the storage address corresponding to all check bits;

[0076] Step 207: Determine the integrity of the first data based on the comparison result of the first verification code and the second verification code; the second verification code is calculated after the first data is read out.

[0077] Steps 206 and 207 can be referred to in detail in steps 104 and 105 above, and will not be repeated here.

[0078] Optionally, step 207 may specifically include:

[0079] Step S31: Compare the first check code and the second check code bit by bit;

[0080] Step S32: If the first verification code and the second verification code are consistent, it is determined that the first data has not been tampered with;

[0081] Step S33: If the first verification code and the second verification code are inconsistent, it is determined that the first data has been tampered with.

[0082] For steps S31-S33, the first checksum is calculated based on the first data during the first data writing process and stored in the second storage area. It represents the "fingerprint" or "digest" of the data at the time of writing. The second checksum is recalculated based on the data read from the first storage area during data reading. It represents the "fingerprint" or "digest" of the data at the time of reading.

[0083] Bit-by-bit comparison refers to comparing each check bit, or every single bit, of the two check codes one by one. A match between the first and second check codes means that all corresponding bits in the two check codes are identical. A discrepancy between the first and second check codes means that at least one corresponding bit differs. Based on the comparison results, it is determined whether the data read from the storage medium is completely consistent with the data originally written, i.e., whether the data has undergone any unexpected changes during storage, such as bit flips, tampering, or corruption.

[0084] For example, the first checksum (Checksum1) is a bit sequence (e.g., bit0_c1, bit1_c1, bit2_c1, ..., bitK-1_c1, a total of K bits), which is the checksum read from the second memory area and stored when it was initially written. The second checksum (Checksum2) is also a bit sequence (e.g., bit0_c2, bit1_c2, bit2_c2, ..., bitK-1_c2, a total of K bits), which is a checksum recalculated based on the data just read from the first memory area. The length of Checksum2 (K bits) must be exactly the same as Checksum1. The bit values ​​of Checksum1 and Checksum2 at the same index positions are compared sequentially from the least significant bit to the most significant bit. Compare Checksum1[0] and Checksum2[0], compare Checksum1[1] and Checksum2[1], ..., compare Checksum1[K-1] and Checksum2[K-1]. If any pair of corresponding bits are found to be different during the comparison process, for example, Checksum1[i] = 0 and Checksum2[i] = 1, then record the difference. If all corresponding bits are the same, then record no difference. Check codes (such as parity check, CRC, Hamming code, hash value) are mathematical summaries of the original data. Ideally, the same data input will necessarily produce the same check code output. Any tiny change in the data, even if only one bit is flipped, is very likely to cause a significant change in the calculated check code. Comparing the first check code calculated when writing with the second check code recalculated when reading is to verify the integrity of the first data. The consistency of the first check code and the second check code means that the input data for calculating the digest when reading is highly consistent with the input data for calculating the digest when writing. Under the premise that the verification algorithm used is effective, it can be highly certain that the data has not been tampered with. A discrepancy between the first and second checksums indicates a difference between the read data and the original data. The checksum algorithm is designed to be extremely sensitive to changes, so even a change of only one bit is easily detected. Therefore, inconsistency is a reliable signal that data integrity has been compromised. Requiring each bit to be identical provides the most stringent comparison standard, ensuring that even the slightest changes detected by the checksum algorithm are captured.

[0085] Verifying data integrity is a crucial mechanism to ensure that data stored in volatile or non-volatile memory is not accidentally or maliciously modified after storage, transmission, or processing. It is essential for scenarios such as financial transactions, security authentication, critical control instructions, and scientific experimental data.

[0086] Optionally, step S33 may specifically include:

[0087] Step S41: If the number of bits where the first check code and the second check code are inconsistent is 1, determine the position in the first data that has been tampered with, and correct the data corresponding to the position that has been tampered with.

[0088] Step S42: If the number of bits in the first check code and the second check code that are inconsistent is greater than 1, an error message is displayed.

[0089] For steps S41 and S42, the first checksum (Checksum1) is the checksum calculated and stored based on the original first data when writing the first data, and the second checksum (Checksum2) is the checksum recalculated based on the read data when reading the first data. The inconsistent number of bits is the number of bit differences found after bit-by-bit comparison. The encoding rule refers to the specific algorithm rule on which the checksum is calculated, and the encoding rule is the basis for locating the error position and decoding. The tampered position refers to the specific bit position in the first data where a bit flip occurs, that is, the position of a 0 changing to a 1 or a 1 changing to a 0. Correction refers to flipping the detected erroneous bits back to the correct value, that is, changing 0 back to 1 or 1 back to 0.

[0090] For example, when it is determined that the first check code and the second check code are inconsistent, let the sequence of inconsistent bits be called Syndrome. Syndrome is obtained by performing a bitwise XOR operation on the first check code and the second check code. Calculating the number of bits with a value of 1 in Syndrome is to determine the number of bits that are inconsistent between the first check code and the second check code.

[0091] Using the same Hamming code encoding rules for calculating Checksum1 and Checksum2, where the Syndrome value directly corresponds to an error location (essentially a binary number), the ECC algorithm defines a mapping table from Syndrome values ​​to error location indices. It can calculate the error bit's position index, Error_Pos, within the entire data and parity block based on the Syndrome value. It's important to note that Error_Pos locates the error position within the entire storage block containing data and parity bits. Therefore, it can verify not only data integrity but also whether the parity bit has changed. An error in the parity bit itself does not affect the correctness of the data area; if the data itself is good, a change in the parity bit does not require correction of the data area. You can choose to recalculate the correct parity code and update the second storage area, or ignore it. It's crucial to distinguish whether this position is a data bit or a parity bit. If using a (7, 4) Hamming code (4 data bits + 3 parity bits), position indices 1, 2, 3, and 4 are data bits, and 5, 6, and 7 are parity bits. If Error_Pos = 3, it indicates a data bit error; if Error_Pos = 6, it indicates a parity bit error.

[0092] It should be noted that different ECC mechanisms have varying error correction capabilities. For example, Hamming codes can only correct single-bit errors and detect double-bit errors. A discrepancy of more than 1 bit indicates the possible occurrence of multiple errors (two or more bits), or a single-bit error where the check bit itself is also faulty. Regardless, the system cannot reliably distinguish specific error modes or safely correct errors. Triggering the error handling process and reporting an uncorrectable error requires the error message to clearly indicate multiple check bit discrepancies, severe data integrity corruption, and the inability to automatically repair the error. When the number of discrepancies between the first and second check codes is greater than 1 (meaning multiple check bits differ between the first and second check codes), an error handling mechanism needs to be triggered. This can include at least one of the following: logging the error, sending an error interrupt / signal / notification; if using error correction codes, attempting to automatically correct the error bits; rereading the data and performing verification again; using backup / redundant data, switching to backup data if available; preventing the propagation of erroneous data by entering safe mode or shutting down the system; and issuing an alert to the user or administrator.

[0093] Optionally, step S42 may specifically include:

[0094] If the bits where the first check code and the second check code are inconsistent are both 1, the position in the first data that has been tampered with is determined according to the encoding rules; the encoding rules are the basis for calculating the first check code and the second check code.

[0095] It should be noted that locating the error position relies entirely on the first and second check codes being calculated using the exact same encoding rules, and the location of the tampered position in the first data is determined based on the corresponding decoding rules. After locating the specific bit in the first storage area based on the tampered position, the cell containing the bit is read, the erroneous bit is flipped, and the data is corrected.

[0096] In summary, the data integrity verification method provided in this application can store data and checksums on the same storage medium or on different storage media. Storing data and checksums on different storage media reduces the frequency of access to the same storage medium. Each check bit in the checksum is assigned a storage address that the processor can directly access, based on the processor's bit width. This allows the processor to access each check bit via address addressing, increasing the access speed of the checksum and thus improving the efficiency of comparing the checksums and verifying the integrity of the first data. During the verification of the first data, the checksums at the same positions in the first and second checksums are compared bit-by-bit. If at least one checksum differs between the two checksums, it indicates that the first and second checksums are different, meaning the first data has been altered during storage, thus improving the rigor of data integrity verification. If the number of different checksums between the first and second checksums is 1, the first data is automatically corrected. If the number of different checksums between the first and second checksums is greater than 1, an error alert is issued to prompt administrator intervention, improving the efficiency of correcting the first data.

[0097] Reference Figure 4 The diagram illustrates a flowchart of the steps for writing data and a verification code according to the present invention, which may specifically include the following steps:

[0098] Step A1: Write the first data to the first storage area;

[0099] Step A2: Calculate the first checksum corresponding to the first data;

[0100] Step A3: Write the first check code bit by bit into the second storage area.

[0101] This method describes the process of writing the first checksum of the first data into its respective storage area. The first checksum is not written to the same byte address in the second storage area, but rather each check bit in the checksum is written to the corresponding address in the second storage area.

[0102] Reference Figure 5 The flowchart illustrates a step-by-step process for reading data and verification codes according to the present invention, which may specifically include the following steps:

[0103] Step B1: Read the first data from the first storage area;

[0104] Step B2: Recalculate the second checksum corresponding to the first data;

[0105] Step B3: Read the first checksum from the second storage area;

[0106] Step B4: Compare the first check code and the second check code bit by bit;

[0107] Step B5: Determine whether the first check code and the second check code are equal;

[0108] Step B6: If the first checksum and the second checksum are equal, the first storage area is confirmed to be normal, and the system continues to run;

[0109] Step B7: If the first check code and the second check code are not equal, an interrupt is generated and error handling is performed.

[0110] This method describes the process of reading first data from a first storage area and reading the first checksum written during the writing of the first data from a second storage area. When reading data from the first storage area, the system automatically reads the first checksum and calculates a second checksum based on the read data, then compares the first and second checksums. If they match, the first storage area is considered normal, and the entire system continues to run; otherwise, an interrupt is generated, and error handling is performed, which involves correcting the first data or issuing an error message.

[0111] Device Examples

[0112] like Figure 6 As shown, Figure 6 The diagram shows a logical block diagram of a data integrity verification device according to an embodiment of the present invention. The device may include:

[0113] The first write module 610 is used to write the first data into the first storage area and calculate the first check code of the first data; the first check code is composed of check bits, and each check bit is one bit.

[0114] Address determination module 620 is used to determine the storage address corresponding to each check bit in the first check code;

[0115] The second writing module 630 is used to write the first check code into the second storage area according to the storage address corresponding to all check bits.

[0116] The reading module 640 is used to read the first data from the first storage area and read the first check code from the second storage area according to the storage address corresponding to all check bits.

[0117] The verification module 650 is used to determine the integrity of the first data based on the comparison result of the first verification code and the second verification code; the second verification code is calculated after the first data is read out.

[0118] Optionally, the address determination module includes:

[0119] The mapping relationship determination module is used to determine the memory mapping relationship between the third storage area and the second storage area based on the number of bits of data processed by the processor each time; the second storage area is the mapping region of the third storage area;

[0120] The address determination submodule is used to determine the storage address of each check bit in the first check code in the second storage area according to the memory mapping relationship.

[0121] Optionally, the mapping relationship determination module includes:

[0122] The quantity correspondence determination module is used to determine the quantity correspondence between the bits in the third storage area and the bits in the second storage area based on the number of bits read by the processor each time.

[0123] The mapping relationship determination submodule is used to determine the memory mapping relationship based on the starting address of the third storage area, the starting address of the second storage area, and the quantity correspondence.

[0124] Optionally, the mapping determination submodule includes:

[0125] The first mapping module is used to map the first bit of the starting address of the third storage area to the starting address of the second storage area;

[0126] The second mapping module is used to determine, based on the quantity correspondence, each bit in the third storage area and map it to the target address in the second storage area.

[0127] Optionally, the second writing module includes:

[0128] A byte determination module is used to determine the byte corresponding to the data in the second storage area for each check bit in the first check code, based on the storage address.

[0129] The first write submodule is used to write the check bit into the least significant bit of the byte.

[0130] Optionally, the verification module includes:

[0131] The comparison module is used to compare the first check code and the second check code bit by bit;

[0132] The first verification module is used to determine that the first data has not been tampered with if the first verification code and the second verification code are consistent.

[0133] The second verification module is used to determine that the first data has been tampered with if the first verification code and the second verification code are inconsistent.

[0134] Optionally, the second verification module includes:

[0135] The correction module is used to determine the tampered position in the first data when the bits where the first check code and the second check code are inconsistent are 1, and to correct the data corresponding to the tampered position.

[0136] The reminder module is used to issue an error reminder when the number of bits in the first check code and the second check code that are inconsistent is greater than 1.

[0137] Optionally, the correction module includes:

[0138] The location determination module is used to determine the location in the first data that has been tampered with, according to the encoding rules, when the bits where the first check code and the second check code are inconsistent are 1; the encoding rules are the basis for calculating the first check code and calculating the second check code.

[0139] In summary, the data integrity verification device provided in this application can store data and checksums on the same storage medium or on different storage media. Storing data and checksums on different storage media reduces the frequency of access to the same storage medium. Each checksum bit in the checksum is assigned a storage address that the processor can directly access, based on the processor's bit width. This allows the processor to access each checksum bit via address addressing, increasing the access speed and thus improving the efficiency of comparing checksums and verifying the integrity of the first data. During the verification of the first data, checksum bits at the same positions in the first and second checksums are compared bit-by-bit. If at least one checksum bit differs between the two checksums, it indicates that the first and second checksums are different, meaning the first data has been altered during storage, thus improving the rigor of data integrity verification. If the number of different checksum bits between the first and second checksums is 1, the first data is automatically corrected. If the number of different checksum bits is greater than 1, an error alert is issued to prompt administrator intervention, improving the efficiency of correcting the first data.

[0140] The data integrity verification device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a GPU BOX, mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0141] The data integrity verification device provided in this application embodiment can achieve... Figure 1 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0142] Optionally, such as Figure 6 As shown, this application embodiment also provides an electronic device 700, including a processor 701 and a memory 702. The memory 702 stores a program or instructions that can run on the processor 701. When the program or instructions are executed by the processor 701, they implement the various steps of the above-described data integrity verification method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0143] In embodiments of this application, memory 702 can be used to store software programs and various data. Memory 702 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback function, image playback function, etc.). Furthermore, memory 702 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 702 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0144] Processor 701 may include one or more processing units; optionally, processor 701 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 701.

[0145] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described data integrity verification method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0146] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0147] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the data integrity verification method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0148] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0149] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0150] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A data integrity verification method, characterized in that, The method includes: Write the first data into the first storage area and calculate the first check code of the first data; the first check code consists of check bits, each check bit being one bit. Determine the storage address corresponding to each check bit in the first check code; Write the first check code into the second storage area according to the storage address corresponding to all check bits; Read the first data from the first storage area, and read the first check code from the second storage area according to the storage address corresponding to all check bits; The integrity of the first data is determined based on the comparison result of the first check code and the second check code; the second check code is calculated after the first data is read.

2. The method according to claim 1, characterized in that, Determining the storage address corresponding to each check bit in the first check code includes: The memory mapping relationship between the third storage area and the second storage area is determined based on the number of bits of data processed by the processor each time; the second storage area is the mapping region of the third storage area. Based on the memory mapping relationship, determine the storage address of each check bit in the first check code in the second storage area.

3. The method according to claim 2, characterized in that, Determining the memory mapping relationship between the third storage area and the second storage area based on the number of bits of data processed by the processor each time includes: The correspondence between the number of bits in the third storage area and the number of bits in the second storage area is determined based on the number of bits read by the processor each time. The memory mapping relationship is determined based on the starting address of the third storage area, the starting address of the second storage area, and the corresponding quantity.

4. The method according to claim 3, characterized in that, Determining the memory mapping relationship based on the starting address of the third storage area, the starting address of the second storage area, and the quantity correspondence includes: Map the first bit of the starting address of the third storage area to the starting address of the second storage area; Based on the quantity correspondence, each bit in the third storage area is determined and mapped to the target address in the second storage area.

5. The method according to claim 1, characterized in that, The step of writing the first check code into the second storage area according to the storage addresses corresponding to all check bits includes: For each check bit in the first check code, the corresponding byte of the data in the second storage area is determined according to the storage address; Write the check bit into the least significant bit of the byte.

6. The method according to claim 1, characterized in that, Determining the integrity of the first data based on the comparison result of the first check code and the second check code includes: Compare the first check code and the second check code bit by bit; If the first verification code and the second verification code match, it is determined that the first data has not been tampered with; If the first verification code and the second verification code are inconsistent, it is determined that the first data has been tampered with.

7. The method according to claim 6, characterized in that, The step of determining that the first data has been tampered with when the first verification code and the second verification code are inconsistent includes: If the bits where the first check code and the second check code are inconsistent are 1, determine the position in the first data that has been tampered with, and correct the data corresponding to the tampered position. An error message will be displayed if the number of bits in the first check code and the second check code that are inconsistent is greater than 1.

8. The method according to claim 7, characterized in that, When the bits in the first checksum that are inconsistent with the second checksum are both 1, determining the location of the tampered data includes: If the bits where the first check code and the second check code are inconsistent are both 1, the position in the first data that has been tampered with is determined according to the encoding rules; the encoding rules are the basis for calculating the first check code and the second check code.

9. A data integrity verification device, characterized in that, The device includes: The first write module is used to write the first data into the first storage area and calculate the first check code of the first data; the first check code is composed of check bits, and each check bit is one bit. The address determination module is used to determine the storage address corresponding to each check bit in the first check code; The second writing module is used to write the first check code into the second storage area according to the storage address corresponding to all check bits. The reading module is used to read the first data from the first storage area and read the first check code from the second storage area according to the storage address corresponding to all check bits. The verification module is used to determine the integrity of the first data based on the comparison result of the first verification code and the second verification code; the second verification code is calculated after the first data is read out.

10. An electronic device, characterized in that, The electronic device includes a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; The memory is used to store executable instructions that cause the processor to perform a data integrity verification method as described in any one of 1 to 8.

11. A readable storage medium, characterized in that, When the instructions or transactions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the data integrity verification method according to any one of claims 1 to 8.

12. A computer program product, characterized in that, Includes instructions or transactions that, when executed by a processor in an electronic device, cause the electronic device to perform the data integrity verification method according to any one of claims 1 to 8.

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