Memory device access control method, program product, device and medium

Abstract

The invention discloses a memory device access control method, a program product, a device and a medium, and relates to the technical field of computers, comprising: respectively configuring a first memory address space and a second memory address space for a dynamic random access memory medium and a flash memory medium of a memory device; dividing the dynamic random access memory medium into a first storage area and a second storage area; the first storage area is mapped to a first memory address space for a host to access and store preset high-access-demand data, and the second storage area is a cache of the flash memory medium and is used for temporarily storing preset low-access-demand data and nonvolatile data; and routing the memory access request to the corresponding storage area. According to the method and the device, the problems that the cost is obviously increased and the nonvolatile characteristic is not supported due to capacity improvement of CXL-DRAM memory extension equipment are solved, and the problems that the access speed of CXL-SSD solid-state storage equipment is slower than that of the CXL-DRAM, and the speed depends on the memory capacity of the equipment side are solved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a memory device access control method, program product, device, and medium. Background Technology

[0002] To expand memory capacity, improve memory utilization, and support cache coherency, Intel led the development of the Compute Express Link (CXL) protocol, which was subsequently open-sourced by several companies. This protocol comprises three sub-protocols: the Compute Express Link Input / Output Subprotocol (CXL.io), the Compute Express Link Cache Subprotocol (CXL.cache), and the Compute Express Link Memory Subprotocol (CXL.mem).

[0003] Based on the CXL sub-protocol adopted, CXL devices are divided into CXL memory extenders, CXL accelerators, and CXL Network Interface Controllers (NICs). Among them, CXL memory extenders adopt the Compute Interconnect Standard Input / Output Sub-protocol (CXL.io) and the Compute Interconnect Standard Memory Sub-protocol (CXL.mem), and are further subdivided into two categories according to the storage medium type: (1) One type is CXL Dynamic Random Access Memory (DRAM) memory extension devices used for host memory expansion. It consists of a CXL interface, a Double Data Rate Physical Layer (DDR PHY) module, and DRAM media. Memory access is achieved through CXL.mem, and device initialization is achieved through CXL.io. It can provide access speed close to host memory, but DRAM media is expensive, and the memory capacity is usually in the hundreds of GB range. Increasing the capacity will significantly increase the cost and does not support non-volatile characteristics; (2) The other type is CXL Solid State Drives (Solid State Drives) used for storage-level memory or persistent memory. Solid-state storage devices (SSDs) use 3D NAND flash memory as the medium. The DRAM contained inside can be used as a cache for the back-end flash memory medium to accelerate data transmission. Although they support both memory access and I / O block data transmission modes and can achieve TB-level memory capacity to reduce expansion costs, their access speed is still slower than CXL-DRAM, and the speed depends on the memory capacity on the device side. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a memory device access control method, program product, device, and medium. This application solves the problem that increasing the capacity of CXL-DRAM memory expansion devices significantly increases costs and does not support non-volatile characteristics, and solves the problem that the access speed of CXL-SSD solid-state storage devices is slower than that of CXL-DRAM, and that the speed depends on the memory capacity on the device side. The specific solutions are as follows: In a first aspect, this application discloses a memory device access control method, including: Initialize the memory device and configure the corresponding first memory address space and the corresponding second memory address space for the dynamic random access memory medium and the flash memory medium of the memory device, respectively; The dynamic random access memory medium is divided into a first storage area and a second storage area; wherein, the first storage area is mapped to a first memory address space for the host to access and store preset high access demand data, and the second storage area is a cache for the flash memory medium, used to temporarily store preset low access demand data and non-volatile data in the host to be written to the flash memory medium; The system receives and parses memory access requests sent by the host to obtain the target address, and routes the memory access request to the corresponding storage area according to the address space range of the target address; the address space range includes the first memory address space and the second memory address space.

[0005] Optionally, a first memory address space and a second memory address space are configured for the dynamic random access memory medium and flash memory medium of the memory device, respectively, including: The transaction layer packet is sent to the memory device through the Computational Interconnect Standard Input / Output Subprotocol of the memory device, so as to read the first base address space capacity information of the dynamic random access memory medium and the second base address space capacity information of the flash memory medium through the transaction layer packet; Based on the read capacity information of the first base address space, configure the first memory address space, and based on the read capacity information of the second base address space, configure the second memory address space.

[0006] Optionally, the address range of the first memory address space does not overlap with the address range of the second memory address space.

[0007] Optionally, the dynamic random access memory medium is divided into a first storage region and a second storage region, including: Two independent dynamic random access memory (DRAM) media are used, with the DRAM media with a larger capacity being designated as the first storage area and the DRAM media with a smaller capacity being designated as the second storage area.

[0008] Optionally, the memory capacity of the memory device is the sum of the capacity of the first storage area and the capacity of the flash memory medium.

[0009] Optionally, the dynamic random access memory medium is divided into a first storage region and a second storage region, including: A single dynamic random access memory (DRAM) medium is used, and the DRAM medium is divided into a first storage area and a second storage area; wherein the capacity of the first storage area is greater than the capacity of the second storage area.

[0010] Optionally, the memory capacity of the memory device is the difference between the target capacity and the capacity of the second storage area, where the target capacity is the sum of the capacity of the dynamic random access memory medium and the capacity of the flash memory medium.

[0011] Optionally, the data read / write process for the first storage area includes: Based on the Compute Interconnect Standard Memory Sub-protocol, a read request is initiated to the first storage area so that the memory device can read preset high access demand data from the first storage area based on the read request, and synchronously feed back the preset high access demand data and the corresponding read status to the host. Based on the compute interconnect standard memory sub-protocol, preset high-access-demand data is written to the first storage area, and after the writing is completed, the corresponding write status is obtained from the memory device.

[0012] Optionally, the data reading process for the flash memory medium includes: Based on the Compute Interconnect Standard Memory Sub-protocol, a read request is initiated to the flash memory medium so that the memory device can determine whether the target data exists in the second storage area; When the target data exists in the second storage area, obtain the target data read from the second storage area by the memory device, and the corresponding read status; When the target data does not exist in the second storage area, the memory device is triggered to start the flash memory medium reading process. After the memory device loads the target data from the flash memory medium into the second storage area, the target data read by the memory device from the second storage area and the corresponding reading status are obtained. The target data includes pre-defined low-access-demand data or non-volatile data.

[0013] Optionally, the memory device is a dual-mode memory expansion device based on computing interconnect standards; wherein, the dual modes include a computing interconnect standard dynamic random access memory mode for storing preset high-access-demand data, and a computing interconnect standard solid-state storage mode for storing preset low-access-demand data and non-volatile data.

[0014] Optionally, the preset high access demand data includes hot zone data and warm zone data, and the preset low access demand data includes cold zone data; wherein, hot zone data is data whose access frequency exceeds a first threshold within a preset time, warm zone data is data whose access frequency is less than the first threshold but greater than a second threshold within a preset time, and cold zone data is data whose access frequency is less than the second threshold within a preset time, and the first threshold is greater than the second threshold.

[0015] Optionally, memory access requests can be routed to the corresponding storage region based on the address space range of the target address, including: If the target address falls within the range of the first memory address space, the memory access request is routed to the first storage region; If the target address falls within the range of the second memory address space, the memory access request is routed to the second storage area.

[0016] Secondly, this application discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the aforementioned memory device access control method.

[0017] Thirdly, this application discloses an electronic device, including: Memory, used to store computer programs; A processor for executing computer programs to implement the aforementioned disclosed memory device access control method.

[0018] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned memory device access control method.

[0019] As can be seen, this application proposes a memory device access control method, including: initializing the memory device and configuring corresponding first memory address spaces and corresponding second memory address spaces for the dynamic random access memory medium and flash memory medium of the memory device, respectively; dividing the dynamic random access memory medium into a first storage area and a second storage area; wherein, the first storage area is mapped to the first memory address space for the host to access and store preset high access demand data, and the second storage area is a cache for the flash memory medium for temporarily storing preset low access demand data and non-volatile data to be written to the flash memory medium from the host; receiving and parsing the memory access request sent by the host, obtaining the target address, and routing the memory access request to the corresponding storage area according to the address space belonging range of the target address; the address space belonging range includes the first memory address space and the second memory address space.

[0020] Beneficial Effects: Addressing the issues of slow access speeds and high costs associated with the need for separate DRAM caches in traditional CXL-SSD solid-state storage devices, this application divides the Dynamic Random Access Memory (DRAM) medium into a first storage region and a second storage region. The first storage region is mapped to a first memory address space, allowing the host to access and store preset high-access-demand data. Since this region is built on DRAM media, it possesses the core characteristic of DRAM's near-host memory access speed, efficiently meeting the fast read / write requirements of high-access-demand data in hot and warm zones, thus directly solving the slow access speed defect of CXL-SSDs. Simultaneously, the second storage region serves as a cache for the flash memory medium, specifically for temporarily storing preset low-access-demand data and non-volatile data to be written to the flash memory in the host. Unlike traditional CXL-SSDs, it does not require separate DRAM caches. This not only significantly reduces the hardware costs associated with separate DRAM caches but also reduces the frequency of direct access to the flash memory medium through the caching mechanism, further improving the transmission efficiency of low-access-demand data and non-volatile data. Building upon this foundation, and addressing the high cost of capacity expansion in traditional CXL-DRAM memory expansion devices, this application first introduces flash memory media supporting terabyte-level capacities. This leverages the low-cost, high-capacity characteristics of flash memory to replace some of the capacity requirements of high-cost DRAM. Subsequently, after receiving and parsing memory access requests sent by the host, the system first obtains the target address in the request, and then, based on the first or second memory address space to which the target address belongs, precisely routes the access request to the corresponding storage area. This design eliminates the need to increase the capacity of high-cost DRAM to expand the overall memory scale, thus directly solving the problem of high capacity expansion costs in traditional CXL-DRAM due to its reliance on DRAM media. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a traditional CXL-DRAM memory expansion device; Figure 2 This is a schematic diagram of a traditional CXL-SSD solid-state storage device; Figure 3 This is a flowchart of a memory device access control method disclosed in this application; Figure 4 This is a schematic diagram of an address arbitration module disclosed in this application; Figure 5 This application discloses a CXL memory device architecture diagram with dual DRAM media. Figure 6 This application discloses a CXL memory device architecture diagram for a single DRAM medium. Figure 7 This is a system architecture diagram of a dual-mode memory device disclosed in this application; Figure 8 This is a schematic diagram of a memory device access control device disclosed in this application; Figure 9 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] (1) CXL-DRAM memory expansion devices use expensive DRAM as the medium, and the capacity is usually in the hundreds of GB range. The cost of increasing the capacity is high and it does not support non-volatile characteristics. See Figure 1 As shown, its architecture includes a CXL interface, which is connected to a DRAM medium composed of multiple double data rate dynamic random access memories through a high-speed serial computer expansion bus physical layer, CXL.mem, double data rate physical layer, etc., and relies on DRAM to realize memory expansion; (2) CXL-SSD solid-state storage devices use 3D NAND flash as the medium, which can achieve TB-level capacity to reduce expansion costs, but the access speed is slower than CXL-DRAM, and the speed depends on the memory capacity on the device side, see Figure 2 As shown, the central processing unit interacts with the CXL controller via the root port. The CXL controller is connected to the DRAM containing data and mapping tables, as well as the controller, through CXL.mem. It is also connected to the flash memory medium through CXL.io, and works together with the DRAM and flash memory medium.

[0025] To address this, this application proposes a memory device access control scheme that solves the problems of significantly increasing costs and not supporting non-volatile characteristics when increasing the capacity of CXL-DRAM memory expansion devices, and also solves the problem that the access speed of CXL-SSD solid-state storage devices is slower than that of CXL-DRAM, and that the speed depends on the memory capacity on the device side.

[0026] This application discloses a memory device access control method. See also... Figure 3 As shown, the method includes: Step S11: Initialize the memory device by configuring the corresponding first memory address space and the corresponding second memory address space for the dynamic random access memory medium and the flash memory medium of the memory device, respectively.

[0027] In this embodiment, the memory device is a dual-mode memory expansion device based on compute interconnect standards. It should be noted that the aforementioned dual modes include a compute interconnect standard dynamic random access memory (CXL-DRAM) mode for storing preset high-access-demand data, and a compute interconnect standard solid-state storage (CXL-SSD) mode for storing preset low-access-demand data and non-volatile data.

[0028] In this embodiment, the memory device is initialized. During initialization, the capacity information of the first base address space of the dynamic random access memory (DRAM) medium and the capacity information of the second base address space of the flash memory medium are acquired. Further, based on the read capacity information of the first base address space, the first memory address space corresponding to the DRAM medium is configured. This address space corresponds to CXL-DRAM mode and is specifically used to store preset high-access-demand data. Simultaneously, based on the capacity information of the second base address space, the second memory address space corresponding to the flash memory medium is configured. This address space corresponds to CXL-SSD mode and is used to store preset low-access-demand data and non-volatile data. Further, after configuration, the memory device will configure the address arbitration module (see...). Figure 4 As shown, the core functional module of the memory device has an input interface of CXL.mem access interface. It contains sub-modules corresponding to the first and second memory address spaces. It can route the request to the DRAM medium corresponding to CXL-DRAM or the flash memory medium corresponding to CXL-SSD according to the target address of the host memory access request, realizing the data routing function in dual mode. The memory address space ranges corresponding to CXL-DRAM and CXL-SSD are included, and it is ensured that the address range of the first memory address space does not overlap with the address range of the second memory address space.

[0029] Step S12: Divide the dynamic random access memory medium into a first storage area and a second storage area; wherein, the first storage area is mapped to the first memory address space for the host to access and store preset high access demand data, and the second storage area is a cache for the flash memory medium, used to temporarily store preset low access demand data and non-volatile data to be written to the flash memory medium from the host.

[0030] See Figure 5 As shown, in one partitioning method, memory devices are accessed via the CXL interface ( Figure 5The CXL interface consists of modules such as the physical layer of the medium- and high-speed serial computer expansion bus, used to establish a connection with the host. It employs two independent dynamic random access memory media (corresponding to...). Figure 5 The memory device uses two dynamic random access memory (DRAM) media (1 and DRAM 2). A larger DRAM media (1) is designated as the first storage region, and a smaller DRAM media (2) is designated as the second storage region. In this partitioning method, the memory capacity of the memory device is the sum of the capacity of the first storage region and the capacity of the flash memory media (2). Figure 5 The total capacity of the CXL-DRAM is the sum of the capacities of the flash memory media. That is, this embodiment can use two independent DRAM media. The DRAM media with the larger capacity is designated as the first storage area, specifically corresponding to the CXL-DRAM mode, used to store intermediate data, status values, and other hot and cold zone data generated during CPU operation. The DRAM media with the smaller capacity is designated as the second storage area, serving as a cache for the NAND Flash memory media to accelerate data transfer. It should be noted that the CXL-DRAM mode relies on the first storage area to ensure near-host memory access speed, while the CXL-SSD mode relies on the second storage area and the flash memory media to achieve high-capacity storage. Furthermore, the CXL-SSD mode only supports memory semantic access.

[0031] See Figure 6 As shown, in another partitioning method, the memory device uses a single dynamic random access memory medium (corresponding to) via the CXL interface. Figure 6 The dynamic random access memory medium (DRAM) is divided into a first storage region and a second storage region (corresponding to...). Figure 6 The cache area in the memory); where the capacity of the first storage area is greater than the capacity of the second storage area. In this partitioning method, the memory capacity of the memory device is the difference between the target capacity and the capacity of the second storage area, and the target capacity is the sum of the capacity of the dynamic random access memory medium and the capacity of the flash memory medium (corresponding to the cache area in the second storage area). Figure 6The sum of the capacities of the flash memory media (in the example) is reduced by the capacity of the second storage area because this area is only used as a cache for the flash memory media and is not directly used as accessible memory space. This ensures that the capacity calculation result matches the actual functional allocation of each medium. That is, this embodiment can use a single DRAM medium and divide it into a first storage area and a second storage area. The first storage area corresponds to the CXL-DRAM mode and is used to store hot and warm zone data, while the second storage area is used as a cache for the flash memory media to temporarily store cold zone data and non-volatile data. It should be noted that the capacity of the first storage area in a single DRAM medium used for CXL-DRAM mode can be configured by the host, thus flexibly adapting to the high-access data storage needs of different scenarios.

[0032] See Figure 7 As shown, the preset high-access-demand data includes hot zone data and warm zone data, while the preset low-access-demand data includes cold zone data. Hot zone data is data whose access frequency exceeds a first threshold within a preset time period; warm zone data is data whose access frequency is less than the first threshold but greater than a second threshold within a preset time period; and cold zone data is data whose access frequency is less than the second threshold within a preset time period, and the first threshold is greater than the second threshold. It should be noted that the host can configure the data partition register set to set the first threshold, the second threshold, and the corresponding hot, warm, and cold zone space capacities. It can also configure the mapping relationship between data partitions and hot / warm / cold zones and non-volatile data areas through registers (e.g., data partition 1 corresponds to hot zone data, data partition 2 corresponds to warm zone data, data partition 3 corresponds to cold zone data, and data partition 4 corresponds to non-volatile data area). Hot and warm zone data are stored in the first memory address space corresponding to CXL-DRAM mode, while cold zone data and non-volatile data are stored in the second memory address space corresponding to CXL-SSD mode. Data requiring long-term storage can be placed in the non-volatile data area by the host according to the application-side identifier.

[0033] In this embodiment, regardless of whether two independent DRAM media or a single DRAM media is used, the data read / write process for the first storage area is implemented based on CXL.mem, including: (1) Data reading process: According to its own data management method, the CPU initiates a read request to the first storage area through the CXL interface and the CXL.mem protocol via the master-to-subordinate (M2S) data read channel. After receiving the request, the memory device reads the preset high access demand data (such as the hot zone data of data partition 1, the warm zone data of data partition 2, etc.) from the first storage area. Then, through the slave-to-master (S2M) data response channel, it synchronously feeds back the preset high access demand data and the corresponding read status to the host to ensure that the host accurately obtains the data and access results. (2) Data writing process: According to its own data management method, the CPU writes the preset high access demand data to the first storage area through the CXL interface and the CXL.mem protocol via the M2S data write channel. After the write operation is completed, the memory device feeds back the corresponding write status to the host through the S2M non-data response channel to inform the host whether the write is successful. If the medium is dual DRAM (two independent DRAM media, also known as Form 1), the first storage area is the large-capacity DRAM medium; if the medium is single DRAM (a single DRAM medium, also known as Form 2), the first storage area is most of the capacity of the DRAM medium. It should be noted that during read and write operations, the CXL.mem protocol's transaction processing follows the timing specifications of the computing interconnect standard to ensure compatibility with the host-side CXL controller.

[0034] In this embodiment, regardless of whether two independent DRAM media or a single DRAM media is used, the data reading process of the flash memory media is also implemented based on the CXL.mem protocol, including: (1) The data reading process of the flash memory medium includes: the host initiates a read request to the flash memory medium through the M2S data read channel based on the CXL.mem protocol. The read request contains the address information of the target data. After receiving the read request, the memory device first determines whether the target data exists in the second storage area (the second storage area is the cache of the flash memory medium). If it is a dual DRAM medium, the second storage area is a small-capacity DRAM medium. If it is a single DRAM medium, the second storage area is the remaining capacity of the DRAM medium, which is used to alleviate the high latency problem of the flash memory medium. When the target data exists in the second storage area, the memory device does not need to access the flash memory medium and directly reads the target data from the second storage area. Then, it feeds back the target data and the corresponding read status to the host through the S2M data response channel to shorten the data read latency. When the target data does not exist in the second storage area, the memory device triggers the flash memory reading process to read the target data from the NAND Flash memory. After the reading is completed, the memory device loads the target data into the second storage area to complete the cache update. Then, through the S2M data response channel, the target data and the corresponding read status are fed back to the host to ensure that subsequent access to the target data can be quickly completed through the cache.

[0035] (2) The data writing process to the flash memory medium includes: The host initiates a data write request to the second storage area via the M2S data write channel, based on the CXL.mem protocol. This write request includes preset low-access-demand data (cold zone data) or non-volatile data, along with corresponding data address information. At this point, the second storage area acts as a cache for the flash memory, first receiving the preset low-access-demand data or non-volatile data sent by the host to avoid direct interaction between the host and the high-latency flash memory. Upon receiving the write request, the memory device writes the preset low-access-demand data or non-volatile data to the second storage area. After completing the data temporary storage, it sends the corresponding write status (e.g., write success / failure) back to the host via the S2M non-data response channel, informing the host that the temporary storage operation is complete. Subsequently, the memory device initiates a background data flushing process, writing the preset low-access-demand data or non-volatile data temporarily stored in the second storage area from the second storage area to the NAND flash memory. In Flash memory media, persistent data storage is achieved through a background process that does not occupy the real-time interaction channel between the host and the memory device, thus avoiding impacting subsequent data access requests initiated by the host. Furthermore, in a dual-DRAM media configuration, the second storage area is a smaller-capacity DRAM medium; data is written from this area to the flash memory medium via an independent data path within the memory device. In a single-DRAM media configuration, the second storage area represents the remaining capacity of the DRAM medium; the data writing process is also implemented through an internal path, and during the writing process, priority is given to ensuring normal data read and write operations in the first storage area (the area corresponding to CXL-DRAM mode) to avoid mutual interference. It should be noted that the background writing process can dynamically adjust the writing rate based on the idle state of the flash memory medium. For example, when the flash memory medium is under high load, the rate is automatically reduced to further minimize the impact on front-end access.

[0036] Step S13: Receive and parse the memory access request sent by the host, obtain the target address, and route the memory access request to the corresponding storage area according to the address space range of the target address; the address space range includes the first memory address space and the second memory address space.

[0037] In this embodiment, the memory device receives memory access requests (including data read requests and data write requests) sent by the host through the M2S direction request channel of CXL.mem. Next, the CXL.mem submodule of the memory device parses the received memory access requests, extracts the target address information from the requests, and then transmits the target address to the address arbitration module of the memory device. The address arbitration module then determines the spatial ownership of the target address according to preset address range determination rules.

[0038] Specifically, memory access requests are routed to the corresponding storage areas based on the address space range of the target address. This includes: if the target address falls within the first memory address space, the address arbitration module directly determines that the request corresponds to a CXL-DRAM mode access requirement and routes the memory access request to the first storage area to match the storage and interaction needs of high-access data. The first storage area is the core area of ​​the DRAM medium. If the memory device is a dual-DRAM medium, the first storage area is the large-capacity DRAM medium; if it is a single-DRAM medium, the first storage area is most of the DRAM medium's capacity. If the target address falls within the second memory address space, the address arbitration module determines that the request requires CXL-SSD mode access and routes the memory access request to the second storage area. The second storage area is a cache area allocated from the DRAM medium. If the memory device uses a dual-DRAM medium, the second storage area is the small-capacity DRAM medium; if it uses a single-DRAM medium, the second storage area is the remaining capacity of the DRAM medium. Its core function is to alleviate the high latency problem of flash memory.

[0039] Furthermore, after completing the routing operation for the memory access request, the address arbitration module generates routing status information (including key fields such as request type, target address, and routing result), and feeds this status information back to the host through the S2M non-data response channel, ensuring that the host can monitor the routing progress of the request in real time. Additionally, if the resolved target address exceeds the preset range of the first and second memory address spaces, the address arbitration module immediately generates an address invalid response, which is also fed back to the host through the S2M non-data response channel, thereby preventing invalid access from consuming device resources and interaction channels.

[0040] Furthermore, to further improve the utilization efficiency of the second storage area, this application can also add a dynamic management mechanism to the second storage area. Specifically, a cache management submodule is added to the memory device. This submodule works in conjunction with the address arbitration module to collect information on the access frequency, recent access time, and data type (cold zone data / non-volatile data) of cached data in the second storage area in real time, and constructs a two-dimensional management model based on access popularity and data attributes. When the capacity occupancy rate of the second storage area reaches a preset threshold (e.g., 85%), the cache management submodule triggers dynamic cleanup and sorting: it prioritizes marking cold zone data with low access frequency and long periods of inactivity as data to be evicted, releasing the cache space it occupies; for non-volatile data, even if the access frequency is low, its retention priority is increased to avoid repeated loading from the flash memory due to frequent evicting. In this way, the cache invalidation problem caused by data accumulation in the second storage area can be avoided, the number of times non-volatile data is repeatedly loaded can be reduced, and the access pressure of flash memory media can be further reduced. Moreover, this mechanism is only implemented through software algorithm upgrades, without the need for additional hardware costs, and is fully compatible with the architecture of the original dual-mode memory device.

[0041] As can be seen, this application proposes a memory device access control method, including: initializing the memory device and configuring corresponding first memory address spaces and corresponding second memory address spaces for the dynamic random access memory medium and flash memory medium of the memory device, respectively; dividing the dynamic random access memory medium into a first storage area and a second storage area; wherein, the first storage area is mapped to the first memory address space for the host to access and store preset high access demand data, and the second storage area is a cache for the flash memory medium for temporarily storing preset low access demand data and non-volatile data to be written to the flash memory medium from the host; receiving and parsing the memory access request sent by the host, obtaining the target address, and routing the memory access request to the corresponding storage area according to the address space belonging range of the target address; the address space belonging range includes the first memory address space and the second memory address space.

[0042] Beneficial Effects: Addressing the issues of slow access speeds and high costs associated with the need for separate DRAM caches in traditional CXL-SSD solid-state storage devices, this application divides the Dynamic Random Access Memory (DRAM) medium into a first storage region and a second storage region. The first storage region is mapped to a first memory address space, allowing the host to access and store preset high-access-demand data. Since this region is built on DRAM media, it possesses the core characteristic of DRAM's near-host memory access speed, efficiently meeting the fast read / write requirements of high-access-demand data in hot and warm zones, thus directly solving the slow access speed defect of CXL-SSDs. Simultaneously, the second storage region serves as a cache for the flash memory medium, specifically for temporarily storing preset low-access-demand data and non-volatile data to be written to the flash memory in the host. Unlike traditional CXL-SSDs, it does not require separate DRAM caches. This not only significantly reduces the hardware costs associated with separate DRAM caches but also reduces the frequency of direct access to the flash memory medium through the caching mechanism, further improving the transmission efficiency of low-access-demand data and non-volatile data. Building upon this foundation, and addressing the high cost of capacity expansion in traditional CXL-DRAM memory expansion devices, this application first introduces flash memory media supporting terabyte-level capacities. This leverages the low-cost, high-capacity characteristics of flash memory to replace some of the capacity requirements of high-cost DRAM. Subsequently, after receiving and parsing memory access requests sent by the host, the system first obtains the target address in the request, and then, based on the first or second memory address space to which the target address belongs, precisely routes the access request to the corresponding storage area. This design eliminates the need to increase the capacity of high-cost DRAM to expand the overall memory scale, thus directly solving the problem of high capacity expansion costs in traditional CXL-DRAM due to its reliance on DRAM media.

[0043] Accordingly, embodiments of this application also disclose a memory device access control device, see [link to relevant documentation]. Figure 8 As shown, the device includes: Address space configuration module 11 is used to initialize the memory device and configure the corresponding first memory address space and the corresponding second memory address space for the dynamic random access memory medium and flash memory medium of the memory device, respectively. The storage area partitioning module 12 is used to divide the dynamic random access memory medium into a first storage area and a second storage area; wherein, the first storage area is mapped to the first memory address space for the host to access and store preset high access demand data, and the second storage area is a cache of the flash memory medium for temporarily storing preset low access demand data and non-volatile data in the host to be written to the flash memory medium; The access request routing module 13 is used to receive and parse the memory access request sent by the host, obtain the target address, and route the memory access request to the corresponding storage area according to the address space belonging range of the target address; the address space belonging range includes the first memory address space and the second memory address space.

[0044] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0045] Furthermore, embodiments of this application also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the aforementioned memory device access control method.

[0046] Furthermore, embodiments of this application also provide an electronic device. Figure 9 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0047] Figure 9 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the memory device access control method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0048] In this embodiment, the power supply 26 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 24 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0049] Furthermore, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored thereon may include computer programs 221, and the storage method may be temporary storage or permanent storage. The computer programs 221 may include, in addition to computer programs capable of performing the memory device access control method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, computer programs capable of performing other specific tasks.

[0050] Furthermore, embodiments of this application also disclose a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned memory device access control method.

[0051] For the specific steps of this method, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0052] The various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. For the same or similar parts between the various embodiments, refer to each other. As for the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to in the method section.

[0053] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0054] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0055] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] The foregoing has provided a detailed description of a memory device access control method, program product, device, and medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A memory device access control method, characterized in that, include: The memory device is initialized, and a first memory address space and a second memory address space are configured for the dynamic random access memory medium and flash memory medium of the memory device, respectively. The dynamic random access memory medium is divided into a first storage area and a second storage area; wherein, the first storage area is mapped to the first memory address space for the host to access and store preset high access demand data, and the second storage area is a cache of the flash memory medium for temporarily storing preset low access demand data and non-volatile data in the host to be written to the flash memory medium; The system receives and parses memory access requests sent by the host to obtain the target address, and routes the memory access request to the corresponding storage area according to the address space range of the target address; the address space range includes the first memory address space and the second memory address space.

2. The memory device access control method according to claim 1, characterized in that, The step of configuring corresponding first memory address spaces and corresponding second memory address spaces for the dynamic random access memory medium and flash memory medium of the memory device includes: The memory device sends a transaction layer packet to the memory device via the Compute Interconnect Standard Input / Output Subprotocol, so as to read the first base address space capacity information of the dynamic random access memory medium and the second base address space capacity information of the flash memory medium through the transaction layer packet; Based on the read first base address space capacity information, configure the first memory address space, and based on the read second base address space capacity information, configure the second memory address space.

3. The memory device access control method according to claim 1, characterized in that, The address range of the first memory address space does not overlap with the address range of the second memory address space.

4. The memory device access control method according to claim 1, characterized in that, The step of dividing the dynamic random access memory medium into a first storage region and a second storage region includes: Two independent dynamic random access memory (DRAM) media are used, with the DRAM media having a larger capacity being designated as the first storage area and the DRAM media having a smaller capacity being designated as the second storage area.

5. The memory device access control method according to claim 4, characterized in that, The memory capacity of the memory device is the sum of the capacity of the first storage area and the capacity of the flash memory medium.

6. The memory device access control method according to claim 1, characterized in that, The step of dividing the dynamic random access memory medium into a first storage region and a second storage region includes: The dynamic random access memory (DRAM) medium is used as a single block, and the DRAM medium is divided into a first storage region and a second storage region; wherein the capacity of the first storage region is greater than the capacity of the second storage region.

7. The memory device access control method according to claim 6, characterized in that, The memory capacity of the memory device is the difference between the target capacity and the capacity of the second storage area, and the target capacity is the sum of the capacity of the dynamic random access memory medium and the capacity of the flash memory medium.

8. The memory device access control method according to claim 4 or 6, characterized in that, The data read / write process for the first storage area includes: Based on the Compute Interconnect Standard Memory Sub-protocol, a read request is initiated to the first storage area so that the memory device can read the preset high access demand data from the first storage area based on the read request, and synchronously feed back the preset high access demand data and the corresponding read status to the host. Based on the compute interconnect standard memory sub-protocol, the preset high-access-requirement data is written to the first storage area, and after the writing is completed, the corresponding write status fed back by the memory device is obtained.

9. The memory device access control method according to claim 4 or 6, characterized in that, The data reading process of the flash memory medium includes: Based on the Compute Interconnect Standard Memory Sub-protocol, a read request is initiated to the flash memory medium so that the memory device can determine whether the target data exists in the second storage area; When the target data exists in the second storage area, the target data read by the memory device from the second storage area and the corresponding read status are obtained; When the target data does not exist in the second storage area, the memory device is triggered to start the reading process of the flash memory medium. After the memory device loads the target data from the flash memory medium into the second storage area, the target data read by the memory device from the second storage area and the corresponding reading status are obtained. The target data includes the preset low-access-requirement data or the non-volatile data.

10. The memory device access control method according to claim 1, characterized in that, The memory device is a dual-mode memory expansion device based on the compute interconnect standard; wherein, the dual modes include a compute interconnect standard dynamic random access memory mode for storing preset high-access-demand data, and a compute interconnect standard solid-state storage mode for storing preset low-access-demand data and non-volatile data.

11. The memory device access control method according to claim 1, characterized in that, The preset high access demand data includes hot zone data and warm zone data, and the preset low access demand data includes cold zone data; wherein, the hot zone data is data whose access frequency exceeds a first threshold within a preset time, the warm zone data is data whose access frequency is less than the first threshold but greater than a second threshold within a preset time, and the cold zone data is data whose access frequency is less than the second threshold within a preset time, and the first threshold is greater than the second threshold.

12. The memory device access control method according to claim 1, characterized in that, The step of routing the memory access request to the corresponding storage region based on the address space range of the target address includes: If the target address falls within the range of the first memory address space, the memory access request is routed to the first storage area; If the target address falls within the range of the second memory address space, the memory access request is routed to the second storage area.

13. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the memory device access control method according to any one of claims 1 to 12.

14. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the memory device access control method as described in any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein, when the computer programs are executed by a processor, they implement the memory device access control method as described in any one of claims 1 to 12.

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