Inverter parallel operation system and upgrading method thereof

Abstract

The invention relates to the technical field of inverters, and discloses an inverter parallel operation system and an upgrading method thereof, and the upgrading method comprises the steps: storing the operation parameters of an operation region to a first storage region under the condition that an upgrading instruction is received in a process of controlling an inverter to work in the operation region; receiving the upgrade firmware sent by the microcontroller, and storing the upgrade firmware in the second storage area; after the upgrade firmware is written, receiving a switching instruction sent by the microcontroller, and switching the running area to the second storage area according to the switching instruction; and after the switching of the operation area is completed, obtaining the operation parameters from the first storage area, and controlling the inverter according to the operation parameters based on the operation environment of the second storage area so as to enable the inverter to maintain power supply output. According to the technical scheme, continuous power supply of the inverter can be kept in the firmware upgrading period, and therefore the problems of power oscillation and power supply interruption in a traditional upgrading mode are effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and in particular to an inverter parallel operation system and its upgrading method. Background Technology

[0002] Inverters, as core devices in distributed power systems, are widely used in new energy power generation, energy storage, and grid-connected power supply scenarios. To improve the operating performance and functional stability of inverters, it is usually necessary to upgrade their control firmware during the product lifecycle. However, existing inverter firmware upgrade methods generally have the following problems: the upgrade process requires shutdown. Traditional inverters typically need to stop operation and disconnect the load when performing firmware updates to avoid interruption of control logic due to CPU pause during writing to program memory (Flash). This method inevitably causes power outages, affecting the continuity of power supply for users and the reliability of the equipment. Summary of the Invention

[0003] This invention provides an inverter parallel operation system and its upgrade method to solve the above-mentioned technical problems.

[0004] The first aspect of this invention provides an upgrade method for an inverter parallel system, the inverter parallel system including a microcontroller, a processor, and an inverter module, the microcontroller and the processor being respectively connected to the inverter module, the processor including an operating area, a first storage area, and a second storage area, the upgrade method being applied to the processor, the upgrade method including: During the operation of the inverter in the operating area, if an upgrade command is received, the operating parameters of the operating area are stored in the first storage area; Receive the upgrade firmware sent by the microcontroller and store the upgrade firmware in the second storage area; After the upgrade firmware is written, a switching instruction sent by the microcontroller is received, and the running area is switched to the second storage area according to the switching instruction; After the switching of the operating area is completed, the operating parameters are obtained from the first storage area, and the inverter is controlled according to the operating parameters based on the operating environment of the second storage area so that the inverter maintains power output.

[0005] Optionally, the inverter's operating parameters include: pulse width modulation register information, interrupt status information, current, voltage, and control loop parameters during operation.

[0006] Optionally, storing the upgraded firmware in the second storage area further includes: Continue executing the original program in the operating area to put the inverter into a power supply state.

[0007] Optionally, controlling the inverter according to the operating parameters includes: Restore the pulse width modulation register value to maintain the original waveform output after switching; Restore interrupt status information to continue task scheduling from the previous switchover; The current, voltage, and control loop parameters during operation are restored so that the inverter can continue to supply power after switching.

[0008] A second aspect of this invention provides an upgrade method for an inverter parallel system, the inverter parallel system including a microcontroller, a processor, and an inverter module, the microcontroller and the processor being respectively connected to the inverter module, the processor including an operating area, a first storage area, and a second storage area, the upgrade method being applied to the microcontroller, the upgrade method including: When the processor stores the operating parameters of the running area to the first storage area according to the upgrade instruction, it receives the upgrade firmware and sends the upgrade firmware to the processor to store it in the second storage area; Once the firmware upgrade is written, a switching command is sent to the processor to switch the operating area to the second storage area. This drives the processor to obtain the operating parameters from the first storage area and controls the inverter in the second storage area according to the operating parameters, so that the inverter maintains power output.

[0009] Optionally, receiving the firmware upgrade includes: The upgraded firmware is received via MQTT, HTTP, or ESP-NOW protocol.

[0010] Optionally, the upgraded firmware is stored in the second storage area, including... The version number and verification information of the upgraded firmware are verified. If the verification result is successful, the processor is accessed via direct memory to write the upgraded firmware into the second storage area.

[0011] Optionally, the step of causing the processor to switch the operating area to the second storage area includes: Obtain the pulse width modulation signal of the inverter module; When the pulse width modulation signal is at a trough, the level signal state of the processor's address line is adjusted by a programmable logic device to switch the running area to the second memory area.

[0012] A third aspect of the present invention provides an inverter parallel operation system, the inverter parallel operation system including a microcontroller, a processor and an inverter module, the microcontroller and the processor being respectively connected to the inverter module, the processor including an operating area, a first storage area and a second storage area; The processor stores the operating parameters of the operating area into the first storage area according to the upgrade instruction; The microcontroller receives the upgrade firmware and stores the upgrade firmware in the second storage area; After the upgrade firmware is written, the microcontroller sends a switching command to the processor, causing the processor to switch the running area to the second storage area; After the switching of the operating area is completed, the processor obtains the operating parameters from the first storage area and controls the inverter according to the operating parameters based on the operating environment of the second storage area, so that the inverter maintains power output.

[0013] Optionally, the microcontroller acquires the pulse width modulation signal of the inverter; when the pulse width modulation signal is at a trough, the microcontroller adjusts the level signal state of the address line of the processor through a programmable logic device to switch the operating area to the second memory area.

[0014] The technical effects of this invention are as follows: it enables the inverter to be upgraded without stopping during parallel operation. Compared with the prior art, it not only maintains the continuous power supply of the inverter during firmware upgrade, but also improves the safety of the upgrade process and the stability of the system through the saving and restoration of operating parameters, the fast switching completed in the PWM trough, and the firmware transmission and storage dominated by the microcontroller. This effectively avoids the power oscillation and power interruption problems that occur in traditional upgrade methods. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of an inverter parallel system provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of an upgrade method for an inverter parallel system provided in Embodiment 1 of the present invention; Figure 3 This is a flowchart of an upgrade method for an inverter parallel system provided in Embodiment 2 of the present invention; Figure 4 This is a flowchart of step S202 in an upgrade method for an inverter parallel system provided in Embodiment 2 of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0021] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0022] Example 1 This embodiment provides an upgrade method for an inverter parallel system, such as... Figure 1 As shown, the inverter parallel system includes a microcontroller 101 and a processor 102. The microcontroller 101 and processor 102 are respectively connected to the inverter module 103. The processor 102 includes an operating area, a first storage area, and a second storage area. The upgrade method is applied to the processor 102, such as... Figure 2 As shown, the upgrade methods include: Step S101. During the operation of the inverter in the operating zone, if an upgrade command is received, the operating parameters of the operating zone are stored in the first storage area; Step S102. Receive the upgrade firmware sent by the microcontroller and store the upgrade firmware in the second storage area; Step S103. After the firmware upgrade is completed, receive the switching instruction sent by the microcontroller and switch the running area to the second storage area according to the switching instruction; Step S104. After the switching is completed in the operating area, the operating parameters are obtained from the first storage area, and the inverter is controlled according to the operating parameters based on the operating environment of the second storage area so that the inverter maintains power output.

[0023] In step S101, the inverter's operating state can be completely saved before the upgrade, including pulse width modulation register values, interrupt status, and current, voltage, and control loop parameters, thereby ensuring that the operating environment can be quickly restored after switching to the new firmware and avoiding control interruption due to state loss.

[0024] In step S102, through this process, the upgrade firmware can be written to the backup storage area in the background, while the processor continues to execute the original control logic, thereby realizing the parallel operation of firmware writing and inverter power supply control, ensuring that the inverter power supply is not interrupted during the firmware download stage.

[0025] In step S103, during this process, the memory area switching can be performed at the trough of the pulse width modulation signal, and the address lines of the processor can be controlled by a programmable logic device to achieve rapid switching between the first and second memory areas. This allows firmware replacement to be completed within microseconds, reducing disturbances to power output and achieving seamless switching of the operating area.

[0026] In step S104, after the switching of the operating area is completed, the processor obtains the operating parameters from the first storage area and continues to control the inverter based on the operating environment of the second storage area, so as to ensure that the inverter maintains power output. The processor can restore the operating state before the switch in the new firmware environment and maintain the continuity of the control logic, thereby ensuring uninterrupted power supply to the inverter during the upgrade process, while ensuring the stability of voltage and current output.

[0027] The technical advantages of this implementation method are: it enables the inverter to be upgraded without stopping during parallel operation. Compared with the prior art, it not only maintains the continuous power supply of the inverter during firmware upgrade, but also improves the safety of the upgrade process and the stability of the system through the saving and restoration of operating parameters, the fast switching completed in the PWM trough, and the firmware transmission and storage led by the microcontroller. This effectively avoids the power oscillation and power interruption problems that occur in traditional upgrade methods.

[0028] As one implementation method, the inverter's operating parameters include: pulse width modulation register information, interrupt status information, current, voltage, and control loop parameters during operation.

[0029] Among them, the pulse width modulation register information is used to characterize the output state of the inverter's drive waveform before switching, the interrupt status information is used to record the task scheduling status of the processor before switching, and the current, voltage and control loop parameters are used to reflect the real-time operating conditions of the inverter before switching and the dynamic operating status inside the microcontroller.

[0030] By saving the aforementioned operating parameters to the first storage area before the upgrade, the system can be promptly restored to the new firmware's operating environment after the upgrade switch is completed, allowing the processor to seamlessly continue the control logic from before the switch. Therefore, during the upgrade process, the inverter not only maintains the continuity of power output but also avoids output power fluctuations and control loop instability caused by parameter loss, thus achieving a smooth transition in system operation and high power supply reliability.

[0031] As one implementation method, storing the upgrade firmware in the second storage area further includes: Continue executing the existing program in the operating area to keep the inverter powered.

[0032] In this process, while the firmware upgrade is being transmitted and written to the second storage area via the microcontroller, the processor continues to execute the original program in the running area, ensuring that the inverter's power control logic and power output are not disturbed.

[0033] The above method enables the parallel execution of firmware writing and inverter power supply, allowing the inverter to maintain normal operation during the firmware upgrade phase. This avoids the shutdown or power interruption problems caused by the upgrade writing operation in traditional technologies, and significantly improves the continuity and reliability of the system during the upgrade process.

[0034] As one implementation method, controlling the inverter according to operating parameters includes: Restore the pulse width modulation register value to maintain the original waveform output after switching; Restore interrupt status information to continue task scheduling from the previous switchover; Restore the current, voltage, and control loop parameters during operation so that the inverter can continue to supply power after switching.

[0035] After the processor completes the memory area switch and enters the upgraded firmware operating environment, it can quickly restore the control state before the switch, so that the inverter's output waveform remains continuous, the task scheduling is uninterrupted, and the electrical control loop remains stable.

[0036] The technical advantages of this solution are as follows: By restoring the pulse width modulation register information, interrupt status, and electrical operating parameters after the switchover is completed, this implementation method can ensure the seamless continuation of the inverter's control logic during the upgrade process, thereby achieving stability and continuity of power output. Compared with the shutdown or power interruption caused by upgrades in existing technologies, this invention not only avoids voltage and current surges but also effectively improves the reliability of the inverter in parallel operation environments and the user's power experience.

[0037] In one implementation, the triggering time of the switching window is dynamically calculated by the processor based on multiple parameters. Specifically, the processor comprehensively analyzes the current system state by real-time monitoring of the current zero-crossing signal, PWM carrier synchronization signal, temperature parameters, and bus voltage value, and calculates the optimal switching phase suitable for the current operating conditions.

[0038] During operation, when the current approaches zero-crossing, the processor dynamically adjusts the phase delay of the PWM signal based on transient fluctuations in the bus voltage and temperature changes in the power devices, enabling the power switch to turn on or off under minimum current or voltage difference conditions. This adaptive algorithm effectively reduces electromagnetic interference (EMI) and waveform distortion during switching, improving the overall power conversion efficiency and signal stability of the system.

[0039] Specifically, the current zero-crossing point represents the instantaneous state where the load current changes from forward to reverse or from reverse to forward. At this moment, the current value is close to zero. If the power device is turned on or off at this instant, switching energy loss and electromagnetic interference can be significantly reduced. The processor monitors the current waveform in real time through the current detection module to obtain the moment when the current approaches zero. Simultaneously, it combines the voltage change rate information provided by the bus voltage detection module and the junction temperature information of the power device provided by the temperature detection module to calculate the phase correction amount and adjust the output timing of the PWM signal accordingly. When the bus voltage fluctuates rapidly, the processor reduces the phase delay to avoid overlapping conduction during the voltage rise. When a rise in the power device temperature is detected, the processor appropriately increases the phase delay to compensate for the response lag caused by temperature changes in the device's turn-on and turn-off characteristics. Through this dynamic phase adjustment, the power device can be turned on or off at the moment of minimum current or minimum voltage difference, thereby effectively reducing electromagnetic interference caused by dv / dt and di / dt, reducing waveform distortion, and improving the system's adaptability and energy efficiency stability under different load types.

[0040] By employing an adaptive PWM switching algorithm, this embodiment achieves adaptive matching for different load types (including inductive and resistive loads). For inductive loads, switching can be completed near the current zero crossing to reduce voltage spikes; for resistive loads, switching can be completed at the carrier wave trough to reduce harmonic components. This effectively improves the electromagnetic compatibility and waveform quality of the system under different operating conditions, and enhances the stability and reliability of equipment operation.

[0041] Example 2 This second embodiment provides an upgrade method for an inverter parallel system, such as... Figure 1 As shown, the inverter includes a microcontroller and a processor. The processor includes an operating area, a first memory area, and a second memory area. The upgrade method is applied to the microcontroller, such as... Figure 3 As shown, the upgrade methods include: Step S201. When the processor stores the running parameters of the running area to the first storage area according to the upgrade instruction, the upgrade firmware is received and sent to the processor to be stored in the second storage area; Step S202. After the upgrade firmware is written, a switching command is sent to the processor to switch the processor to the second storage area, so as to drive the processor to obtain the operating parameters from the first storage area and to control the inverter in the second storage area according to the operating parameters, so as to keep the inverter supplying power.

[0042] In step S201, after the processor has saved the operating parameters of the runtime area to the first storage area according to the upgrade instruction, the microcontroller enters the firmware distribution process. Specifically, the microcontroller first establishes a communication connection with the cloud upgrade service to obtain the upgrade firmware and its metadata (including version number, target address area, firmware length, digest / signature information, entry address, compatibility identifier, etc.) that match the target model and version. The microcontroller performs a validity check on the firmware, preferably including: version forward verification (preventing rollback to a lower version unless authorized), length and boundary alignment verification (ensuring that the write does not exceed the boundary of the second storage area), digest / signature verification (such as CRC32 / SHA-256 and elliptic curve signature), and "bank free before write" verification (confirming that the second storage area is not occupied by the current execution). After the verification is successful, the microcontroller establishes a firmware transmission session with the processor to negotiate the write parameters (page size, block size, timeout and retransmission policy, write start offset, etc.). The transport layer preferably uses fragmented messages with sequence numbers and acknowledgments. Each fragment includes a header (magic word, sequence number, length, destination offset), a data body, and a tail check field. The microcontroller sends firmware data to the processor sequentially according to the negotiated block granularity. The processor maps the received data to the corresponding address in the second memory area. To reduce the impact on the processor's real-time control load, page programming can be performed using DMA or write buffer + asynchronous disk write. After each page is written, a readback sample is read to perform page-level verification. When page-level verification or block-level cumulative verification fails, the microcontroller triggers retransmission and rewriting until the page / block verification passes or the retry limit is reached.

[0043] Throughout the write process, the processor maintains the execution of the original program in the runtime area, and the microcontroller does not change the instruction fetch and interrupt configuration of the current runtime area; the processor's real-time control loop (such as current loop / voltage loop / PID integral) maintains its original frequency and duty cycle update cycle unchanged. After all blocks are written, the microcontroller sends a write completion / ready indication to the processor and writes the Bank header information (entry address, version number, timestamp, checksum, rollback pointer, etc.) in the second memory area. At the same time, it records upgrade session metadata in the non-volatile domain for subsequent switching and rollback tracking.

[0044] In step S202, after the microcontroller confirms that the firmware in the second memory area has been completely written and passed the overall verification, it enters the operation area switching stage. The microcontroller first calculates the safe switching window based on the running status fed back by the processor (including the current PWM carrier phase / counter value, instantaneous current / voltage, loop error, etc.), and preferably selects the trough moment of the pulse width modulation signal as the switching trigger point. In the parallel scenario, the microcontroller can first broadcast a short-term power compensation notification to other inverters in the cluster, causing adjacent nodes to temporarily increase their output according to preset rules, and then initiate a switch for the target inverter. During the switching execution, the microcontroller sends a switching instruction to the processor and performs atomic-level control of the processor's address mapping / Bank selection signal through the programmable logic device, so that the processor's instruction fetch area is mapped from the operation area to the entry address of the second memory area. To avoid transient disturbances, the processor executes according to a pre-defined startup sequence after entering the new firmware entry point: preferably, non-critical interrupts are first disabled or masked for a very short time slice (without affecting protection interrupts), the stack / vector table is relocated to the new code segment, and the instruction prefetch queue is refreshed. Then, the running parameters saved before the switchover (including PWM register group, compare and trigger registers, timers, loop controller internal states such as integral / limiting states, interrupt pending and priority states, parallel power allocation weights, synchronization phase / frequency scalars, etc.) are immediately restored in batches from the first memory area. Subsequently, the new firmware enables a shadow register / soft-start strategy to smoothly take over the power path: for example, the duty cycle / phase / current limit is gradually changed at a set slope over N PWM cycles to maintain loop error and output ripple within the threshold; at the same time, online health checks are enabled (bus voltage deviation, output current transients, circulating current monitoring, temperature rise rate, etc.). If any indicator exceeds the limit, a fast rollback is triggered, and the microcontroller switches the operating area back to the original bank in the next safety window and records the rollback reason and fault snapshot. Once the new firmware has completed takeover and the health check has passed the stability criteria (e.g., ripple / error are all below the threshold for M consecutive carrier cycles), the microcontroller persists the upgrade results (marks the second storage area as the active bank, updates the version record, clears the temporary flags of the old bank), and issues a command to the parallel cluster to release compensation / restore the power distribution, so that the system power distribution returns to normal.

[0045] This embodiment addresses the pain points of traditional upgrades requiring downtime, control interruptions, and parallel power fluctuations, significantly improving the maintainability and service continuity of the inverter system during field operation.

[0046] As one implementation, receiving firmware upgrades includes: Receive firmware upgrades via MQTT, HTTP, or ESP-NOW protocols.

[0047] The microcontroller establishes a communication connection with a cloud server and uses standardized network communication protocols to obtain upgrade firmware files. Specifically, the MQTT protocol is suitable for lightweight message transmission scenarios, enabling firmware push with low power consumption and low bandwidth; the HTTP protocol is suitable for large file transfers in conventional network environments, ensuring data transmission integrity and reliability; and the ESP-NOW protocol is suitable for local area networks or direct device connection environments, enabling point-to-point or point-to-multipoint communication without routers, thus quickly completing firmware distribution.

[0048] The technical advantage of this implementation method is that by flexibly selecting MQTT, HTTP, or ESP-NOW protocols for receiving upgrade firmware in different application scenarios, it can ensure firmware transmission security and reliability while also taking into account transmission efficiency and network adaptability. This method not only improves the flexibility and applicability of firmware upgrades but also ensures that the inverter can successfully acquire upgrade firmware under various network conditions, thereby improving the maintainability and reliability of the system.

[0049] As one implementation, the upgrade firmware is stored in a second storage area, including Verify the version number and verification information of the upgraded firmware; If the verification result passes, the processor is accessed via Direct Memory Access (DMA) to write the upgrade firmware. First, the version number and verification information of the upgrade firmware are verified to confirm that it is a legitimate file compatible with the target inverter and that no data corruption or tampering has occurred. If the verification result passes, the processor's memory interface is accessed using DMA to write the upgrade firmware to the second memory area. During this process, the processor's main core can continue to execute the original program in the runtime area, ensuring uninterrupted power control and power output of the inverter.

[0050] The technical advantages of this implementation are as follows: By verifying the version number and checksum before writing, upgrade failures or system malfunctions caused by firmware version mismatch or data corruption can be effectively avoided, thereby improving the security and reliability of firmware upgrades. Simultaneously, using direct memory access (DMI) for writing allows the firmware writing operation to be completed without consuming processor core resources, enabling parallel processing of firmware writing and inverter power supply control, thus ensuring the continuity of inverter power supply and operational stability during the firmware writing phase.

[0051] As one implementation method, such as Figure 4 As shown, step S202, which involves switching the processor from the operating area to the second memory area, includes: Step S301. Obtain the pulse width modulation signal of the inverter module; Step S302. When the pulse width modulation signal is at a trough, the level signal state of the processor's address line is adjusted by the programmable logic device to switch the running area to the second memory area.

[0052] In step S301, the inverter's pulse width modulation (PWM) signal is acquired to determine the operating state of the inverter's output waveform. In step S3202, when the PWM signal is at a trough, the level of the processor's address lines is adjusted via a programmable logic device to switch the operating area to the second storage area. By switching at the trough of the PWM signal, the transient impact of the switching action on the output voltage and current can be effectively reduced. By using a programmable logic device to control the processor's address lines, the switching of the operating area can be quickly realized at the hardware level, avoiding interruptions caused by software relocation or reset.

[0053] Through the above methods, this embodiment can complete the switching of the operating zone at the moment when the inverter power supply waveform is most stable, minimizing disturbances to the output power. Simultaneously, by using programmable logic devices to directly control the processor's address lines, microsecond-level rapid switching is achieved, enabling new firmware to take over operation instantly and ensuring the inverter maintains stable and reliable power output during upgrades.

[0054] Example 3 This embodiment three provides an inverter parallel system, wherein the inverter includes a microcontroller and a processor, and the processor includes an operating area, a first storage area and a second storage area; The processor stores the operating parameters of the runtime area into the first memory area according to the upgrade instruction; The microcontroller receives the upgrade firmware and stores it in the second storage area; After the firmware upgrade is written, the microcontroller sends a switching command to the processor, causing the processor to switch the running area to the second storage area; After the switching of the operating area is completed, the processor obtains the operating parameters from the first storage area and controls the inverter according to the operating parameters based on the operating environment of the second storage area, so as to keep the inverter supplying power.

[0055] Furthermore, the microcontroller acquires the pulse width modulation signal from the inverter; when the pulse width modulation signal is at a trough, the microcontroller adjusts the level signal state of the processor's address lines through programmable logic devices to switch the operating area to the second memory area.

[0056] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An upgrade method for an inverter parallel system, characterized in that, The inverter parallel system includes a microcontroller, a processor, and an inverter module. The microcontroller and the processor are respectively connected to the inverter module. The processor includes a running area, a first storage area, and a second storage area. The upgrade method is applied to the processor, and the upgrade method includes: During the operation of the inverter in the operating area, if an upgrade command is received, the operating parameters of the operating area are stored in the first storage area; Receive the upgrade firmware sent by the microcontroller and store the upgrade firmware in the second storage area; After the upgrade firmware is written, a switching instruction sent by the microcontroller is received, and the running area is switched to the second storage area according to the switching instruction; After the switching of the operating area is completed, the operating parameters are obtained from the first storage area, and the inverter is controlled according to the operating parameters based on the operating environment of the second storage area so that the inverter maintains power output.

2. The upgrade method as described in claim 1, characterized in that, The inverter's operating parameters include: pulse width modulation register information, interrupt status information, current, voltage, and control loop parameters during operation.

3. The upgrade method as described in claim 1, characterized in that, The step of storing the upgraded firmware to the second storage area further includes: Continue executing the original program in the operating area to put the inverter into a power supply state.

4. The upgrade method as described in claim 1, characterized in that, The step of controlling the inverter according to the operating parameters includes: Restore the pulse width modulation register value to maintain the original waveform output after switching; Restore interrupt status information to continue task scheduling from the previous switchover; The current, voltage, and control loop parameters during operation are restored so that the inverter can continue to supply power after switching.

5. An upgrade method for an inverter parallel system, characterized in that, The inverter parallel system includes a microcontroller, a processor, and an inverter module. The microcontroller and the processor are respectively connected to the inverter module. The processor includes a running area, a first storage area, and a second storage area. The upgrade method is applied to the microcontroller, and the upgrade method includes: When the processor stores the operating parameters of the running area to the first storage area according to the upgrade instruction, it receives the upgrade firmware and sends the upgrade firmware to the processor to store it in the second storage area; Once the firmware upgrade is written, a switching command is sent to the processor to switch the operating area to the second storage area. This drives the processor to obtain the operating parameters from the first storage area and controls the inverter in the second storage area according to the operating parameters, so that the inverter maintains power output.

6. The upgrade method as described in claim 5, characterized in that, The receiving of the upgraded firmware includes: The upgraded firmware is received via MQTT, HTTP, or ESP-NOW protocol.

7. The upgrade method as described in claim 6, characterized in that, Store the upgraded firmware to the second storage area, including The version number and verification information of the upgraded firmware are verified. If the verification result is successful, the processor is accessed via direct memory to write the upgraded firmware into the second storage area.

8. The upgrade method as described in claim 5, characterized in that, The step of switching the processor to the second storage area includes: Obtain the pulse width modulation signal of the inverter module; When the pulse width modulation signal is at a trough, the level signal state of the processor's address line is adjusted by a programmable logic device to switch the running area to the second memory area.

9. An inverter parallel operation system, characterized in that, The inverter parallel system includes a microcontroller, a processor, and an inverter module. The microcontroller and the processor are respectively connected to the inverter module. The processor includes an operating area, a first storage area, and a second storage area. The processor stores the operating parameters of the operating area into the first storage area according to the upgrade instruction; The microcontroller receives the upgrade firmware and stores the upgrade firmware in the second storage area; After the upgrade firmware is written, the microcontroller sends a switching command to the processor, causing the processor to switch the running area to the second storage area; After the switching of the operating area is completed, the processor obtains the operating parameters from the first storage area and controls the inverter according to the operating parameters based on the operating environment of the second storage area, so that the inverter maintains power output.

10. The inverter parallel operation system as described in claim 9, characterized in that, The microcontroller acquires the pulse width modulation signal of the inverter; when the pulse width modulation signal is at a trough, the microcontroller adjusts the level signal state of the address line of the processor through a programmable logic device to switch the operating area to the second memory area.

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