Data scheduling method, electronic device, and computer-readable storage medium

Abstract

The present disclosure provides a data scheduling method, an electronic device and a computer readable storage medium, the method comprising: receiving a plurality of CCL task packages based on a computing chip, wherein each CCL task package carries sequence marking information, and the sequence marking information is used to represent the order in which the computing chip receives the CCL task package; distributing the plurality of CCL task packages to at least two different computing cores through the computing chip; in the case that a first CCL task package in any one computing core enters an executable state, performing priority scheduling and execution processing on the first CCL task package through a computing unit in the corresponding computing core, wherein the first CCL task package is the CCL task package that enters the corresponding computing core first as represented by the sequence marking information. Through the above technical solution, dynamic scheduling of CCL tasks can be achieved, and the problem of low CCL task execution efficiency can be solved.

Description

Technical Field

[0001] This disclosure relates to the field of data scheduling technology, and in particular to a data scheduling method, electronic device, and computer-readable storage medium. Background Technology

[0002] The application of the Collective Communication Library (CCL) in general-purpose computing on graphics processing units (GPGPUs) can significantly improve computational efficiency and processing speed, meet real-time processing requirements, and fully utilize computing resources, making it of great significance in fields such as image processing and computer vision. CCL is a middleware specifically responsible for efficient data synchronization between multiple nodes / accelerator cards in distributed computing, and its application on GPGPUs is one of the key technologies for improving the performance of image processing and computer vision tasks.

[0003] However, in the existing technology, CCL tasks are processed by default using a sequential input and sequential execution method, which results in low efficiency of CCL task execution. Summary of the Invention

[0004] This disclosure provides a data scheduling method, an electronic device, and a computer-readable storage medium that can realize dynamic scheduling of CCL tasks and solve the problem of low efficiency in CCL task execution.

[0005] According to one aspect of this disclosure, a data scheduling method is provided, applied to a computing chip, the computing chip including a plurality of computing chips, each computing chip including a plurality of computing units, the data scheduling method including:

[0006] The computing chip receives multiple CCL task packets, wherein each CCL task packet carries sequence marker information, which is used to characterize the order in which the computing chip receives the CCL task packets.

[0007] The computing chip distributes multiple CCL task packages to at least two different computing chips.

[0008] When the first CCL task package in any of the computing cores enters the executable state, the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL task package, wherein the first CCL task package is the CCL task package that enters the corresponding computing core first, as indicated by the sequence mark information.

[0009] Optionally, the CCL task package includes multiple CCL sub-task packages, each of which carries label information. The label information is used to characterize the task execution priority of the CCL sub-task packages within the same CCL task package. The data scheduling method further includes:

[0010] When the first CCL subtask package in any of the computing cores enters the executable state, the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL subtask package. The first CCL subtask package is the CCL subtask package with the highest task execution priority, represented by the sequence mark information.

[0011] Optionally, when the first CCL task package in any of the computing cores enters the executable state, after the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL task package, the data scheduling method further includes:

[0012] When the first CCL task package is completed, the second CCL task package, which is in a different computing chip than the first CCL task package, enters the executable state. The second CCL task package is then processed by the computing unit in the corresponding computing chip. The second CCL task package is characterized by the sequence marking information as the CCL task package that entered the corresponding computing chip first.

[0013] Optionally, after prioritizing the execution of the first CCL subtask package by the computing unit in the corresponding computing core when the first CCL subtask package in any of the computing cores enters the executable state, the data scheduling method further includes:

[0014] When the first CCL subtask package is completed, the second CCL subtask package, which is located in a different computing core than the first CCL subtask package, enters the executable state. The second CCL subtask package is then processed by the computing unit in the corresponding computing core. The second CCL subtask package is characterized by the sequence marking information representing the CCL subtask package that first enters the corresponding computing core, and the label information representing the CCL subtask package with the highest task execution priority.

[0015] Optionally, each CCL task package corresponds to CCL task package information, which is stored in a preset storage unit. Each storage unit is pointed to by a value pointer in a linker node of a preset linked list structure. The linked list structure also includes a head pointer, and the linked list structure includes multiple linker nodes. Each linker node also includes a successor pointer, and different linker nodes are connected based on the successor pointers. The data scheduling method further includes:

[0016] Starting from the linker node pointed to by the head pointer, the CCL task package information in the storage unit pointed to by the value pointer in the linker node is detected sequentially;

[0017] When the CCL task package information indicates that the corresponding CCL task package has entered the executable state, the corresponding CCL task package is scheduled for execution.

[0018] Optionally, after scheduling and executing the corresponding CCL task package when the CCL task package information indicates that the corresponding CCL task package has entered an executable state, the data scheduling method further includes:

[0019] When the CCL task package is completed, the CCL task package information corresponding to the CCL task package is deleted from the corresponding storage unit, and the linker node pointed to by the corresponding storage unit is deleted, so that the linked list structure can be rebuilt.

[0020] Optionally, the CCL task package information includes core tag information and synchronization status information, with each computing core corresponding to one core tag information. After scheduling and executing the corresponding CCL task package when the CCL task package information indicates that the corresponding CCL task package has entered an executable state, the data scheduling method further includes:

[0021] Based on the synchronization status information, it is determined that the corresponding CCL task package has not been fully executed.

[0022] A reverse mask is generated based on the core marker information corresponding to the CCL task package.

[0023] Based on the reverse mask, unexecuted CCL task packages with the same core tagging information are marked as unschedulable until the previously executed CCL task package is completed.

[0024] Optionally, the linker node further includes a flag bit, the linked list structure further includes a tail pointer, and the data scheduling method further includes:

[0025] When the linker node pointed to by the tail pointer receives a new CCL task packet, it will store the CCL task packet in the storage unit corresponding to the corresponding linker node, and the flag bit in the corresponding linker node will be changed.

[0026] The tail pointer moves to the next linker node according to the successor pointer.

[0027] Optionally, the data scheduling method further includes:

[0028] When the CCL task package corresponding to the linker node pointed to by the head pointer is completed, the flag bit in the linker node pointed to by the head pointer is changed;

[0029] The head pointer moves to the next linker node according to the successor pointer.

[0030] According to one aspect of this disclosure, an electronic device is provided, characterized in that the electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection communication between the processor and the memory, wherein the program is executed by the processor to implement the data scheduling method as described above.

[0031] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores one or more programs, which can be executed by one or more processors to implement the data scheduling method described above.

[0032] The data scheduling method, electronic device, and computer-readable storage medium disclosed herein include: receiving multiple CCL task packets based on a computing chip, wherein each CCL task packet carries sequence marker information, which is used to characterize the order in which the computing chip receives the CCL task packets; then, allocating the multiple CCL task packets to at least two different computing chips via the computing chip; and when the first CCL task packet in any computing chip enters an executable state, the first CCL task packet can be prioritized for execution by the computing unit in the corresponding computing chip, wherein the sequence marker information indicates that the first CCL task packet entered the corresponding computing chip first. In this disclosure, the received multiple CCL task packets are allocated to at least two different computing chips, and when the first CCL task packet in any computing chip enters an executable state, the first CCL task packet can be executed first, eliminating the need for the previous method of executing CCL task packets only according to sequential input. This achieves dynamic scheduling of CCL tasks, thereby effectively solving the problem of low efficiency in CCL task execution.

[0033] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objectives and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0034] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0035] Figure 1 This is a system architecture diagram of a data scheduling method applied according to embodiments of the present disclosure;

[0036] Figure 2 This is a main flowchart of a data scheduling method according to an embodiment of the present disclosure;

[0037] Figure 3 This is a flowchart of a data scheduling method according to another embodiment of this disclosure;

[0038] Figure 4 Is it completed? Figure 2 A sub-flowchart following step S203;

[0039] Figure 5 Is it completed? Figure 3 A sub-flowchart following step S301;

[0040] Figure 6 This is a flowchart of a data scheduling method based on a linked list structure according to an embodiment of this disclosure;

[0041] Figure 7 This is a schematic diagram of a linked list structure in an empty list state according to an embodiment of this disclosure;

[0042] Figure 8 This is a schematic diagram of a linked list structure receiving a CCL task packet in an embodiment of this disclosure;

[0043] Figure 9 This is a schematic diagram illustrating the mapping relationship between a linked list structure and storage units according to an embodiment of this disclosure;

[0044] Figure 10 This is a schematic diagram of a linked list structure in a full state according to an embodiment of the present disclosure;

[0045] Figure 11 Is it completed? Figure 6 A sub-flowchart following step S602;

[0046] Figure 12 This is a schematic diagram of linked list structure reconstruction according to an embodiment of the present disclosure;

[0047] Figure 13 Is it completed? Figure 6 Another sub-flowchart following step S602;

[0048] Figure 14 This is a schematic diagram of reverse mask generation according to an embodiment of the present disclosure;

[0049] Figure 15 This is a sub-flowchart illustrating the movement of the tail pointer when executing a data scheduling method based on a linked list structure according to an embodiment of this disclosure;

[0050] Figure 16 This is a sub-flowchart illustrating the movement of the head pointer when executing a data scheduling method based on a linked list structure according to an embodiment of this disclosure;

[0051] Figure 17 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this disclosure.

[0053] Before providing a further detailed description of the embodiments of this disclosure, the terms and concepts used in these embodiments are explained, and they are subject to the following interpretations:

[0054] Collective Communication Library (CCL): A CCL is a library designed for efficient collective communication operations in distributed computing, aiming to accelerate data exchange between multiple computing centers and accelerators, which is particularly crucial in large-scale deep learning training. In modern artificial intelligence and scientific computing, models and datasets are becoming increasingly large, and single machines and GPUs cannot meet the computational and memory demands. Multiple servers must be used, each with multiple computing devices for parallel processing. In this distributed environment, these computing devices need to frequently synchronize data and summarize results. If communication efficiency is low, the bottleneck of the entire system will be in network and data exchange, causing computing devices to spend most of their time waiting and not being fully utilized. The CCL was created to optimize communication efficiency between devices. The CCL implements various collective communication primitives, including full reduction, broadcast, full collection, reduction scattering, reduction, and barriers.

[0055] General-Purpose computing on Graphics Processing Units (GPGPU): A GPGPU refers to a graphics processing unit (GPU) originally designed for graphics rendering (such as games and 3D modeling) to perform general-purpose computing tasks that were originally handled by the central processing unit (CPU). It transforms the GPU from a dedicated graphics accelerator into a powerful general-purpose parallel processor. Through its unparalleled parallel computing capabilities, it has become the core engine driving modern artificial intelligence, scientific discovery, and engineering simulations. GPGPUs can be applied to fields such as artificial intelligence and deep learning, scientific computing and simulation, data analysis and big data, and graphics and vision.

[0056] Graphics Processing Unit (GPU): A microprocessor specifically designed for processing graphics and image computations. Originally designed to accelerate computer graphics rendering, GPUs have expanded far beyond this scope with technological advancements. Initially designed to accelerate 2D and 3D graphics rendering, improving the performance of games and professional graphics software, GPUs possess thousands of cores capable of processing massive amounts of data simultaneously, making them ideal for parallel computing tasks. With technological advancements, GPUs are no longer limited to graphics processing; they are now used for a wide range of general-purpose computing tasks. GPUs play a crucial role in deep learning, machine learning, and artificial intelligence because they can rapidly process large amounts of data, accelerating the training and inference of neural networks. In scientific computing and data analysis, GPUs are used to accelerate complex numerical simulations and data analysis tasks. In cloud computing and data centers, GPUs provide high-performance computing resources to support various computationally intensive applications. In professional applications such as video editing, 3D modeling, and scientific visualization, GPUs provide real-time, high-performance rendering.

[0057] The Central Processing Unit (CPU) is the core of a computer system, responsible for computation and control. It is the final execution unit for information processing and program execution. The CPU is the brain of the computer, responsible for executing program instructions and processing data. It executes program instructions, performs data processing, and controls other hardware components of the computer. The core is the physical unit of the CPU, which can independently execute instructions. A thread is the smallest unit that an operating system can schedule; modern CPUs support multithreading. The CPU generates heat during operation, requiring a cooling system to keep it operating at a safe temperature. The CPU includes an arithmetic logic unit (ALU), a control unit, registers, and a cache. The ALU is responsible for performing all arithmetic and logical operations. The control unit fetches instructions from memory, determines the order of instructions, and controls other hardware components. Registers are small storage areas within the CPU used to store instructions and data to speed up processing. The cache is a fast memory located within the CPU used for temporary storage of frequently accessed data.

[0058] Computing chips: Computing chips typically refer to integrated circuits, which are miniature electronic devices that integrate circuitry onto tiny silicon wafers. They are widely used in various electronic devices, such as computers, mobile phones, and automobiles, to perform various functions, including computing, storage, and communication. Computing chips are packaged bare dies that can be used in actual electronic systems.

[0059] Computing Chip: A computing chip is an unpackaged, small chip diced from a silicon wafer. It contains integrated circuits that perform specific functions. A computing chip is usually composed of one or more computing chips packaged together. The functionality of a computing chip is decomposed into multiple smaller, modular, and functionally independent computing chips. These computing chips are integrated onto a packaging substrate using packaging technology to ultimately form a complete processor.

[0060] Compute Unit (CU): In a graphics processing unit (GPU) architecture, a compute unit is the basic unit for performing computational tasks. A workgroup running on a GPU is actually executing on a compute unit. A compute unit is the basic unit on a GPU used to perform parallel computing tasks; it contains a number of processing elements that can execute multiple threads in parallel. A block processing cluster can include multiple compute units.

[0061] In existing technologies, CCL is a middleware specifically responsible for efficient data synchronization between "multi-node / multi-accelerator cards" in distributed computing. The application of CCL on GPGPU is one of the key technologies to improve the performance of image processing and computer vision tasks. However, CCL tasks are processed by default using a sequential input and sequential execution method, which leads to low execution efficiency of CCL tasks.

[0062] Based on this, this disclosure proposes a data scheduling method, electronic device, and computer-readable storage medium that can avoid long information feedback paths and low synchronization efficiency.

[0063] System architecture description applied in the embodiments of this disclosure

[0064] Figure 1 This is a system architecture diagram of the data scheduling method according to an embodiment of the present disclosure. The system architecture includes at least one computing chip 100, and multiple computing cores 200 may exist within a single computing chip 100. Each computing core 200 may further include at least one computing unit 300. It is worth noting that... Figure 1 The illustration merely demonstrates that a computing chip 100 includes three computing chips 200, designated as "Computing Chip 1," "Computing Chip 2," and "Computing Chip 3." However, this does not mean that a computing chip 100 can only include three computing chips 200; the number of computing chips 200 can also be five, six, or seven, etc., and is not limited here. Furthermore, the computing chips 200 in the figure are named "Computing Chip 1," "Computing Chip 2," and "Computing Chip 3" only to facilitate a clearer explanation of the technical solutions in the embodiments of this disclosure, and do not imply that they are different components. In addition, a computing chip 200 can contain multiple computing units 300, for example... Figure 1 The diagram shows that "Computation Chip 1" includes three computing units 300, "Computation Chip 2" also includes three computing units 300, and "Computation Chip 3" includes only two computing units 300. It is worth noting that the number of computing units 300 in each computing chip 200 is not fixed. For example, "Computation Chip 1" includes "Computation Unit 1", "Computation Unit 2", and "Computation Unit 3"; "Computation Chip 2" includes "Computation Unit 4", "Computation Unit 5", and "Computation Unit 6"; and "Computation Chip 3" includes "Computation Unit 7" and "Computation Unit 8". Furthermore, the computing units 300 in the diagram are named "Computation Unit 1", "Computation Unit 2", "Computation Unit 3", "Computation Unit 4", "Computation Unit 5", "Computation Unit 6", "Computation Unit 7", and "Computation Unit 8" respectively, only for the purpose of more clearly illustrating the technical solutions of the embodiments of this disclosure, and do not represent different components. In this embodiment, the computing chip 100 can be a GPU. GPUs are often the most powerful and efficient form of computing chip when processing parallel computing tasks. The role of the GPU has evolved from a simple graphics renderer to a general-purpose parallel computing engine driving modern artificial intelligence, scientific discovery, and advanced graphics creation. Furthermore, in this embodiment, the system architecture may include multiple computing chips 100, and each computing chip 100 may include multiple computing cores 200. Figure 1 The system architecture shown here only includes one computing chip 100. However, the number of computing chips 100 in the system architecture is not limited to one. The number of computing chips 100 can also be two, three, four, etc., which are not limited here.

[0065] It is worth noting that after receiving multiple CCL task packets, the computing chip 100 can allocate the received CCL task packets to computing kernels 200. In order to achieve dynamic scheduling of CCL task packets, the received CCL task packets need to be allocated to different computing kernels 200. For example, during a task execution, the computing chip 100 receives 5 CCL task packets. During the task packet allocation process, the target computing kernel for 3 CCL task packets is "computing kernel 1", the target computing kernel for 1 CCL task packet is "computing kernel 2", and the target computing kernel for the remaining 1 CCL task packet is "computing kernel 3". Thus, the 5 received CCL task packets can be allocated to different computing kernels 200. Alternatively, during a task execution, computing chip 100 receives three CCL task packets. During the task packet allocation process, two CCL task packets target computing kernel "computing kernel 1", and the remaining CCL task packet targets computing kernel "computing kernel 3". In this case, "computing kernel 2" is not assigned to a CCL task packet, but the requirement of allocating CCL task packets to different computing kernels 200 is still met. In this embodiment, the CCL task packet is a collective communication task packet.

[0066] It is worth noting that when a computing chip 200 receives a CCL task packet, it can utilize its internal computing unit 300 to process the received CCL task packet. When a CCL task packet is assigned to different computing chips 200, theoretically, CCL task packets executed on different computing chips 200 will not affect each other, providing a basis for the dynamic scheduling of CCL task packets.

[0067] Overall Implementation of the Data Scheduling Method in the Embodiments of this Disclosure

[0068] This disclosure proposes a data scheduling method applied to a computing chip. The computing chip includes multiple computing cores, and each computing core may include multiple computing units. (Refer to...) Figure 2 Data scheduling methods include:

[0069] Step S201: The computing chip receives multiple CCL task packets, wherein each CCL task packet carries sequence marker information, which is used to characterize the order in which the computing chip receives the CCL task packets.

[0070] Step S202: Using a computing chip, multiple CCL task packages are allocated to at least two different computing chips;

[0071] Step S203: When the first CCL task package in any computing chip enters the executable state, the first CCL task package is prioritized for execution by the computing unit in the corresponding computing chip. The first CCL task package is a sequence mark information representing the CCL task package that enters the corresponding computing chip first.

[0072] Specifically, in this disclosure, the data scheduling method proposed in the embodiments of this disclosure is applied to a computing chip. The computing chip may include multiple computing cores, and each computing core may include multiple computing units. When the computing chip receives multiple CCL task packets, the received CCL task packets can be allocated to the corresponding computing cores, so that the computing units in the computing cores can perform execution processing on the received CCL task packets. Here, a CCL task packet refers to a workload data packet configured to contain a specific set of communication operations. For example, a CCL task packet may be a task packet for controlling the execution of reduction dissemination, a task packet for controlling the execution of broadcast operations, or a task packet for controlling full reduction operations, etc., and is not limited here.

[0073] In step S201, the computing chip receives multiple CCL task packets, and each CCL task packet carries sequence marker information. The sequence marker information carried by the CCL task packet is used to characterize the order in which the computing chip receives the CCL task packets. For example, during the process of receiving CCL task packets, the computing chip receives five CCL task packets sequentially, namely CCL0, CCL1, CCL2, CCL3, and CCL4. The sequence marker information carried by CCL0 can be 0, CCL1 can be 1, CCL2 can be 2, CCL3 can be 3, and CCL4 can be 4. In this embodiment, the smaller the sequence marker information, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, in the above embodiment, CCL0 is the first CCL task packet received, and CCL4 is the last CCL task packet received. Alternatively, during the process of receiving CCL task packets, the computing chip receives three CCL task packets sequentially: CCL1, CCL2, and CCL3. CCL1 carries a sequence marker of 1, CCL2 carries a sequence marker of 2, and CCL3 carries a sequence marker of 3. In this embodiment, a larger sequence marker indicates that the corresponding CCL task packet was received by the computing chip earlier. Therefore, in the above embodiment, CCL3 is the first received CCL task packet, and CCL1 is the last received CCL task packet. The sequence marker information is used to characterize the order in which the computing chip receives the CCL task packets. The sequence marker information of each CCL task packet received by the computing chip is unique during task packet execution. Based on the sequence marker information of the CCL task packets, the order in which each CCL task packet is received by the computing chip can be well distinguished, making the dynamic scheduling of subsequent tasks more reliable and effectively avoiding resource deadlocks caused by out-of-order delivery during dynamic scheduling.

[0074] In the embodiments disclosed herein, such as Figure 1As shown, the computing chip receives four CCL task packets: CCL0, CCL1, CCL2, and CCL3. The target computing kernels for CCL0 and CCL2 are designated as "Computing Kernel 1," for CCL1 as "Computing Kernel 2," and for CCL3 as "Computing Kernel 3." CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, CCL2 carries a sequence marker of 2, and CCL3 carries a sequence marker of 3. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received earliest by the computing chip and assigned to "Computing Kernel 1," while CCL3 is received latest and assigned to "Computing Kernel 3." In the traditional CCL task execution process, due to the need to follow the first-in, first-out (FIFO) principle, CCL0, CCL1, CCL2, and CCL3 must be executed sequentially. If CCL0 is not completed, CCL1, CCL2, and CCL3 cannot be executed, thus affecting task execution efficiency. The technical solution based on this disclosure eliminates the need to follow the traditional order of CCL0, CCL1, CCL2, and CCL3. When received CCL tasks are assigned to different computing chips, the corresponding CCL task package can be executed first once it becomes executable in any computing chip, significantly improving CCL task execution efficiency.

[0075] In step S202, after the computing chip receives multiple CCL task packets, it can allocate the corresponding CCL task packets to the corresponding computing chip according to the computing chip to which each CCL task packet belongs, in preparation for the subsequent execution and processing of the CCL task packets. For example, a computing chip includes four computing chips: a first computing chip, a second computing chip, a third computing chip, and a fourth computing chip. During the CCL task packet reception process, the computing chip receives four CCL task packets: CCL0, CCL1, CCL2, and CCL3. The target computing chip for CCL0 is the second computing chip, the target computing chip for CCL1 is the first computing chip, the target computing chip for CCL2 is the fourth computing chip, and the target computing chip for CCL3 is the third computing chip. Therefore, the computing chip can allocate CCL0 to the second computing chip, CCL1 to the first computing chip, CCL2 to the fourth computing chip, and CCL3 to the third computing chip.

[0076] It is worth noting that, in the embodiments of this disclosure, when multiple CCL task packets are received, the multiple CCL task packets must be allocated to at least two different computing chips in order to implement the data scheduling method of the embodiments of this application. For example, a computing chip includes three computing chips, namely a first computing chip, a second computing chip, and a third computing chip. During the execution of CCL tasks, the computing chip receives three CCL task packets, namely CCL0, CCL1, and CCL2. If the target computing chips of CCL0, CCL1, and CCL2 are all the same computing chip, the data scheduling method disclosed in the embodiments of this disclosure cannot be implemented. For example, if the target computing chips of CCL0, CCL1, and CCL2 are all the first computing chip, then the received CCL0, CCL1, and CCL2 cannot be dynamically scheduled, and the first-in-first-out principle still needs to be followed to avoid out-of-order resource deadlock. When multiple CCL task packets are assigned to at least two different computing kernels, for example, the target computing kernel for CCL0 is the first computing kernel, the target computing kernel for CCL1 is the second computing kernel, and the target computing kernel for CCL2 is the third computing kernel, the data scheduling method disclosed in this embodiment can be applied because the received CCL task packets are assigned to three different computing kernels.

[0077] It is worth noting that each CCL task packet received by the computing chip carries its own computing kernel information. This kernel information characterizes the specific computing kernel to which the CCL task packet needs to be assigned. During the allocation of the received CCL task packets, the kernel information carried by each CCL task packet is used as a reference. For example, a computing chip includes two computing kernels: a first computing kernel and a second computing kernel. The computing chip receives four CCL task packets: CCL0, CCL1, CCL2, and CCL3. CCL0 carries the kernel information for the first computing kernel, CCL1 also carries the kernel information for the first computing kernel, CCL2 carries the kernel information for the second computing kernel, and CCL3 also carries the kernel information for the first computing kernel. Therefore, in the subsequent CCL task packet allocation process, CCL0, CCL1, and CCL3 are assigned to the first computing kernel, and CCL2 is assigned to the second computing kernel. Since CCL0, CCL1, CCL2 and CCL3 are assigned to two different computing chips, the CCL tasks can be executed based on the data scheduling method disclosed in the embodiments of this disclosure.

[0078] In step S203, when the received multiple CCL task packets are assigned to at least two different computing kernels, if the first CCL task packet in any computing kernel enters the executable state, the computing unit in the computing kernel can prioritize and schedule the execution of the corresponding first CCL task packet. Furthermore, the first CCL task packet is identified by a sequence marker indicating that it entered the corresponding computing kernel first. This technical solution allows for effective dynamic scheduling and execution of CCL task packets, eliminating the need to adhere solely to the first-in, first-out (FIFO) principle, thus significantly improving the efficiency of CCL task execution.

[0079] For example, a computing chip includes three computing cores: a first computing core, a second computing core, and a third computing core. During the execution of a CCL task, three CCL task packets are received: CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received by the computing chip earliest, and CCL2 is received by the computing chip latest. Furthermore, CCL0 carries the information of the first computing core as its host computing core. The L1-carried computing kernel information is also the second computing kernel, and the CCL2-carried computing kernel information is the third computing kernel. Therefore, CCL0 is assigned to the first computing kernel, CCL1 to the second computing kernel, and CCL2 to the third computing kernel. In the subsequent execution of CCL tasks, CCL1 in the second computing kernel enters the executable state first, so the computing unit in the second computing kernel can be used to prioritize the execution of CCL1. Unlike before, it is not necessary to execute CCL1 only after CCL0 has been completed. Through the above technical solution, the efficiency of CCL task execution can be greatly accelerated.

[0080] It is worth noting that before a CCL task package can be executed, it often needs to go through a waiting state and then enter an executable state. The waiting state indicates that the corresponding CCL task package has not yet met the conditions for execution and needs to wait. The reasons for the CCL task package to wait include, but are not limited to, the following: insufficient resources, unmet dependencies, synchronization coordination, and scheduling strategies. Entering the executable state indicates that the corresponding CCL task package has met the conditions for execution, but there are other CCL task packages in the process of execution, so it still needs to wait. For example, a computing chip includes two computing cores, namely a first computing core and a second computing core. During the execution of a CCL task, three CCL task packets are received, namely CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received by the computing chip earliest, and CCL2 is received by the computing chip latest. Furthermore, CCL0 is assigned to the first computing core, while CCL1 and CCL2 are assigned to the second computing core. Therefore, CCL0 is assigned to the first computing core, and CCL1 and CCL2 are assigned to the second computing core. In subsequent... During the execution of a CCL task, CCL0 in the first computing chip is in a waiting state, while CCL1 in the second computing chip enters the executable state first. Therefore, the computing units in the second computing chip can prioritize the execution of CCL1. Even if CCL0 transitions from the waiting state to the executable state before CCL1 is completed, CCL0 still needs to wait because CCL1 has not yet been executed. Once CCL1 is completed, CCL0 can then be executed. This eliminates the need to wait for CCL0 to transition from the waiting state to the executable state before executing CCL1, as was previously done. Based on this technical solution, the efficiency of CCL task execution can be significantly improved, enabling dynamic scheduling of CCL tasks and making CCL task execution more flexible. It is worth noting that both CCL1 and CCL2 are assigned to the second computing chip, and CCL1 is received by the computing chip earlier than CCL2. CCL1 must be executed first before CCL2 can be processed. Through the above settings, resource deadlock can be effectively prevented, making CCL task scheduling more stable and reliable.

[0081] It is understandable that during the CCL task scheduling and execution process, the sequence marker information indicating the CCL task packet that first enters the corresponding computing chip can change. For example, a computing chip includes two computing chips, namely the first computing chip and the second computing chip. During CCL task execution, four CCL task packets are received: CCL0, CCL1, CCL2, and CCL3. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, CCL2 carries a sequence marker of 2, and CCL3 carries a sequence marker of 3. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received earliest by the computing chip, and CCL3 is received latest. Furthermore, the assigned computing chip information carried by CCL0 and CCL1... The information of the first computing kernel is CCL0, while the information of the computing kernels carried by CCL2 and CCL3 is the second computing kernel. Therefore, CCL0 and CCL1 are assigned to the first computing kernel, and CCL2 and CCL3 are assigned to the second computing kernel. In the subsequent execution of CCL tasks, CCL0 in the first computing kernel enters the executable state first, so CCL0 can be scheduled and executed first. After CCL0 is executed, the first CCL task package to enter the first computing kernel will change from CCL0 to CCL1. After CCL2 is executed, the first CCL task package to enter the second computing kernel will also change from CCL2 to CCL3.

[0082] In steps S201 to S203, multiple CCL task packets are received by the computing chip. Each CCL task packet carries sequence marker information, which indicates the order in which the computing chip receives the CCL task packets. Then, the computing chip allocates the multiple CCL task packets to at least two different computing chips. When the first CCL task packet in any computing chip becomes executable, it can be prioritized for execution by the computing unit in the corresponding computing chip. The sequence marker information indicates that the first CCL task packet entered the corresponding computing chip first. In this disclosure, the received multiple CCL task packets are allocated to at least two different computing chips, and when the first CCL task packet in any computing chip becomes executable, it can be executed first. This eliminates the need for the previous method of executing CCL task packets only according to the sequential input order, achieving dynamic scheduling of CCL tasks and effectively solving the problem of low execution efficiency of CCL tasks.

[0083] For example, a computing chip includes three computing cores: a first computing core, a second computing core, and a third computing core. During the execution of a CCL task, four CCL task packets are received: CCL0, CCL1, CCL2, and CCL3. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, CCL2 carries a sequence marker of 2, and CCL3 carries a sequence marker of 3. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received by the computing chip earliest, and CCL3 is received by the computing chip latest. Furthermore, CCL0 carries the information of the first computing core as its host computing core, and CCL1 carries the information of the third computing core as its host computing core. All information is from the second computing core, while the computing core information carried by CCL2 and CCL3 is from the third computing core. Therefore, CCL0 is assigned to the first computing core, CCL1 to the second computing core, and CCL2 and CCL3 to the third computing core. During the subsequent execution of CCL tasks, CCL0 in the first computing core is in a waiting state, CCL1 in the second computing core is in a waiting state, CCL2 in the third computing core enters the executable state first, and CCL3 in the third computing core is in a waiting state. Therefore, CCL2 in the third computing core can be prioritized for execution, instead of having to prioritize CCL0 as before. This allows for dynamic scheduling of CCL tasks, accelerating the efficiency of CCL task execution. Alternatively, CCL0 in the first computing chip may be in a waiting state, while CCL1 in the second computing chip may enter an executable state. CCL2 in the third computing chip may be in a waiting state, while CCL3 in the third computing chip may enter an executable state first. Although both CCL1 and CCL3 in the second and third computing chips are executable, CCL1 is received by the computing chip before CCL3, and CCL2 in the third computing chip is not yet executed. Therefore, in subsequent CCL task execution, only CCL1 in the second computing chip will be scheduled and executed first. This technical solution improves the efficiency of CCL task execution while also ensuring its stability and reliability.

[0084] In one embodiment, refer to Figure 3 A CCL task package includes multiple CCL sub-task packages, each carrying label information. This label information is used to characterize the task execution priority of the CCL sub-task packages within the same CCL task package. The data scheduling method also includes:

[0085] Step S301: When the first CCL subtask package in any computing core enters the executable state, the first CCL subtask package is prioritized for execution by the computing unit in the corresponding computing core. The first CCL subtask package is characterized by sequence mark information representing the CCL subtask package that entered the corresponding computing core first, and the label information in the first CCL subtask package represents the CCL subtask package with the highest task execution priority.

[0086] Specifically, in some embodiments of this disclosure, the CCL task package can be further segmented to obtain multiple CCL sub-task packages, and each CCL sub-task package can also carry label information, which is used to characterize the task execution priority of the CCL sub-task packages within the same CCL task package. For example, the computing chip receives a CCL0 task package and segments it into three CCL sub-task packages: CCL0-sub0, CCL0-sub1, and CCL0-sub2. The label information for CCL0-sub0 is 0, for CCL0-sub1 it is 1, and for CCL0-sub2 it is 2. Furthermore, the smaller the label information of a CCL sub-task package, the higher its task execution priority. Therefore, CCL0-sub0 has the highest task execution priority, and CCL0-sub2 has the lowest task execution priority.

[0087] In step S301, when the CCL task package received by the computing chip is a CCL sub-task package that has already been segmented, and the first CCL sub-task package in any computing chip enters the executable state, the computing unit in the computing chip can prioritize the execution of the corresponding first CCL sub-task package. Furthermore, the first CCL sub-task package is identified by its sequence marker information, representing the CCL sub-task package that entered the corresponding computing chip first, and its label information represents the CCL sub-task package with the highest execution priority. Through this technical solution, dynamic scheduling of CCL task packages can be effectively achieved, eliminating the need to adhere solely to the first-in, first-out principle as in the past, thus significantly improving the efficiency of CCL task execution. Moreover, because the CCL task package is segmented, task scheduling can be based on the state of the CCL sub-tasks, rather than the state of the entire CCL task package, thereby further improving the granularity of task execution and increasing its efficiency.

[0088] For example, a computing chip includes two computing cores, namely a first computing core and a second computing core. During the execution of a CCL task, two CCL task packets, namely CCL0 and CCL1, are received. The two CCL task packets are each divided into two CCL sub-task packets: CCL0 is divided into CCL0-sub0 and CCL0-sub1, and CCL1 is divided into CCL1-sub0 and CCL1-sub1. CCL0-sub0 and CCL0-sub1 are assigned to the first computing core, and CCL1-sub0 and CCL1-sub1 are assigned to the second computing core. In the subsequent execution of the CCL task, CCL1-sub0 in the second computing core enters the executable state first, so the computing units in the second computing core can be used to prioritize the execution of CCL1-sub0, instead of having to execute CCL0-sub0 first as in the past. Through the above technical solution, the efficiency of CCL task execution can also be accelerated. In this configuration, CCL0-sub0 is labeled with a value of 0, while CCL0-sub1 is labeled with a value of 1. The smaller the label, the higher the execution priority of the subtask package. Therefore, CCL0-sub0 belonging to the same CCL0 class must be executed before CCL0-sub1. It's important to note that if CCL0-sub0, CCL0-sub1, CCL1-sub0, and CCL1-sub1 are all assigned to the first computational core, CCL0-sub0 must still be executed first. Even if CCL1-sub0 enters the executable state before CCL0-sub0, it must wait. This configuration effectively prevents resource deadlocks caused by out-of-order scheduling during dynamic scheduling of CCL task packages, ensuring the feasibility and reliability of CCL task execution while improving its efficiency.

[0089] It is worth noting that after a CCL task packet is divided into multiple CCL sub-task packets, during task scheduling and execution, it is also necessary to first process the CCL sub-task packets within the CCL task packet that first enters the corresponding computing chip, based on the sequence marker information. Furthermore, when processing CCL sub-task packets within a CCL task packet, it is necessary to prioritize the CCL sub-task packets with higher execution priority. This improves the efficiency of CCL task execution while ensuring its reliability. For example, a computing chip includes two computing chips, namely the first computing chip and the second computing chip. During CCL task execution, three CCL task packets are received: CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received by the computing chip earliest, and CCL2 is received by the computing chip latest. Furthermore, the three CCL task packages are each divided into two CCL sub-task packages: CCL0 is divided into CCL0-sub0 and CCL0-sub1, CCL1 is divided into CCL1-sub0 and CCL1-sub1, and CCL2 is divided into CCL2-sub0 and CCL2-sub1. CCL0-sub0 and CCL0-sub1 are assigned to the first computational core, while CCL1-sub0, CCL1-sub1, CCL2-sub0, and CCL2-sub1 are assigned to the second computational core. During subsequent CCL task execution, even if CCL2-sub0 enters the executable state before CCL1-sub0, it cannot be executed before CCL1-sub0. When both belong to the same computational core, the first-in, first-out (FIFO) principle must still be followed. If CCL1-sub0 enters the executable state before CCL0-sub0, then CCL1-sub0 can be executed first, because they belong to different computational cores and are theoretically unaffected during CCL task execution. Furthermore, during the execution of a CCL task, CCL subtask packages that originally belong to the same CCL task package must first execute the CCL subtask package with higher priority. For example, for CCL0, CCL0-sub0 must be executed first; for CCL1, CCL1-sub0 must be executed first; and for CCL2, CCL2-sub0 must be executed first.

[0090] Understandably, during the CCL task scheduling and execution process, the label information in the CCL task packet, which indicates the CCL subtask packet with the highest execution priority, will change. For example, a computing chip includes two computing cores, namely the first computing core and the second computing core; during CCL task execution, three CCL task packets are received, namely CCL0, CCL1, and CCL2; among them, CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. Furthermore, the smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received by the computing chip earliest, and CCL2 is received by the computing chip latest. Furthermore, the three CCL task packages are each divided into two CCL sub-task packages: CCL0 is divided into CCL0-sub0 and CCL0-sub1, CCL1 is divided into CCL1-sub0 and CCL1-sub1, and CCL2 is divided into CCL2-sub0 and CCL2-sub1. CCL0-sub0 and CCL0-sub1 are assigned to the first computational kernel, while CCL1-sub0, CCL1-sub1, CCL2-sub0, and CCL2-sub1 are assigned to the second computational kernel. During the subsequent execution of the CCL tasks, CCL1-sub0 enters first. Since the task is in an executable state, CCL1-sub0 is executed first. After CCL1-sub0 is executed, the CCL subtask package with the highest execution priority in CCL1 will change from CCL1-sub0 to CCL1-sub1. Similarly, after CCL0-sub0 is executed, the CCL subtask package with the highest execution priority in CCL0 will change from CCL0-sub0 to CCL0-sub1. After CCL2-sub0 is executed, the CCL subtask package with the highest execution priority in CCL2 will change from CCL2-sub0 to CCL2-sub1.

[0091] In one embodiment, refer to Figure 4 After step S203 is completed, the following steps are included:

[0092] Step S401: When the first CCL task package is completed, the second CCL task package, which is in a different computing chip than the first CCL task package, enters the executable state. The second CCL task package is executed by the computing unit in the corresponding computing chip. The second CCL task package is a sequence mark information representing the CCL task package that entered the corresponding computing chip first.

[0093] In step S401, after the first CCL task package is completed, the second CCL task package, located in a different computing core than the first CCL task package, enters the executable state. The second CCL task package can then be processed by the computing unit in the corresponding computing core. The second CCL task package is also the first CCL task package to enter the corresponding computing core. After the first CCL task package is completed, the next CCL task package that has entered the executable state in another computing core is immediately executed. This setup significantly speeds up the execution efficiency of CCL tasks, enabling dynamic scheduling and execution of CCL tasks, thus making CCL task execution more flexible.

[0094] For example, a computing chip includes three computing cores: a first computing core, a second computing core, and a third computing core. During the execution of a CCL task, three CCL task packets are received: CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, CCL0 is received earliest, and CCL2 is received latest. Furthermore, CCL0 is associated with the first computing core, CCL1 with the second computing core, and CCL2 with the third computing core. CCL0 is assigned to the first computing core, CCL1 to the second computing core, and CCL2 to the third computing core. During subsequent CCL task execution, CCL1 in the second computing core enters the executable state first, allowing for priority scheduling and execution using the computing units within the second core. While CCL1 is being executed, CCL0 in the first computing core enters the executable state. Once CCL1 is completed, CCL0 in the first computing core can be executed immediately. Similarly, while CCL0 is being executed, CCL2 in the third computing core enters the executable state. Once CCL0 is completed, CCL2 in the third computing core can be executed immediately. This scheme enables flexible CCL task execution.

[0095] It is worth noting that, during the execution of a CCL task packet in one computing chip, if CCL task packets in two other computing chips also enter the executable state, the sequence marker information representing the CCL task packet that entered the computing chip first needs to be executed first. For example, a computing chip includes three computing chips: a first computing chip, a second computing chip, and a third computing chip. During the execution of a CCL task, three CCL task packets are received: CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. CCL0 is associated with the first computing chip, CCL1 with the second computing chip, and CCL2 with the third computing chip. With three computing chips, CCL0 is assigned to the first computing chip, CCL1 to the second computing chip, and CCL2 to the third computing chip. During the subsequent execution of CCL tasks, CCL1 enters the executable state first, so CCL1 in the second computing chip can be processed first. While CCL1 is being processed, CCL0 in the first computing chip and CCL2 in the third computing chip also enter the executable state. After CCL1 finishes execution, since CCL0 enters the computing chip before CCL2, CCL0 needs to be executed first. Through the above settings, out-of-order execution can be effectively prevented, ensuring the reliability of CCL task execution.

[0096] In one embodiment, refer to Figure 5 After step S301 is completed, the following steps are included:

[0097] Step S501: When the first CCL subtask package is completed, the second CCL subtask package, which is in a different computing core than the first CCL subtask package, enters the executable state. The second CCL subtask package is processed by the computing unit in the corresponding computing core. The second CCL subtask package is characterized by sequence mark information representing the CCL subtask package that entered the corresponding computing core first, and the label information represents the CCL subtask package with the highest task execution priority.

[0098] In step S501, when the first CCL subtask package is completed, the second CCL subtask package, located in a different computing core than the first CCL subtask package, enters the executable state. The second CCL subtask package can then be processed by the computing units within its corresponding computing core. The second CCL subtask package is also the first CCL subtask package to enter its corresponding computing core and has the highest execution priority. After the first CCL subtask package is completed, the next CCL subtask package that has entered the executable state in another computing core is immediately executed. This setup effectively speeds up the execution efficiency of CCL tasks. Since the CCL task package is divided into multiple CCL subtask packages, dynamic scheduling of CCL tasks can be performed based on the state of each subtask package, rather than relying on the state of the entire CCL task package. This allows for more granular task scheduling, further improving the execution scheduling efficiency of CCL tasks.

[0099] For example, a computing chip includes two computing cores, namely a first computing core and a second computing core. During the execution of a CCL task, two CCL task packets are received, namely CCL0 and CCL1. Each CCL task packet is further divided into two CCL sub-task packets: CCL0 is divided into CCL0-sub0 and CCL0-sub1, and CCL1 is divided into CCL1-sub0 and CCL1-sub1. CCL0-sub0 and CCL0-sub1 are assigned to the first computing core, and CCL1-sub0 and CCL1-sub1 are assigned to the second computing core. ub1 is assigned to the second computing core. During the subsequent execution of CCL tasks, CCL1-sub0 in the second computing core enters the executable state first, so the computing units in the second computing core can be used to prioritize the execution of CCL1-sub0. During the execution of CCL1-sub0, CCL0-sub0 in the first computing core enters the executable state. Therefore, after CCL1-sub0 is completed, CCL0-sub0 can be executed immediately. Through the above technical solution, the efficiency of CCL task execution can also be accelerated.

[0100] It is worth noting that when a CCL subtask package in one computing chip is being executed, and the CCL subtask packages in two other computing chips have both entered the executable state, the sequence marker information that represents the CCL task package that entered the computing chip first still needs to be executed first. For example, a computing chip includes three computing cores: a first computing core, a second computing core, and a third computing core. During the execution of a CCL task, three CCL task packets are received: CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. The smaller the sequence marker, the earlier the corresponding CCL task packet is received by the computing chip. CCL0 is associated with the first computing core, CCL1 with the second computing core, and CCL2 with the third computing core. Furthermore, CCL0 is segmented into CCL0-sub0 and CCL0-sub1, CCL1 is segmented into CCL1-sub0 and CCL1-sub1, and CCL2 is segmented into CCL2-sub0 and CCL2-sub0. Therefore, CCL0-sub0 and CCL0-sub1 are assigned to the first computing chip, CCL1-sub0 and CCL1-sub1 to the second computing chip, and CCL2-sub0 and CCL2-sub1 to the third computing chip. During the subsequent execution of CCL tasks, CCL1-sub0 enters the executable state first, so CCL1-sub0 in the second computing chip can be processed first. During the execution of CCL1-sub0, CCL0-sub0 in the first computing chip and CCL2-sub0 in the third computing chip also enter the executable state. After CCL1-sub0 is completed, since CCL0 enters the computing chip before CCL2, CCL0-sub0 needs to be executed first. Through the above settings, the out-of-order execution can be effectively prevented, ensuring the reliability of CCL task execution.

[0101] It is worth noting that multiple CCL subtask packets residing in the same computing chip must not only follow the first-in, first-out (FIFO) principle but also the order of subtask execution priority. For example, a computing chip includes two computing chips, designated as the first and second computing chips. During CCL task execution, three CCL task packets are received: CCL0, CCL1, and CCL2. CCL0 carries a sequence marker of 0, CCL1 carries a sequence marker of 1, and CCL2 carries a sequence marker of 2. A smaller sequence marker indicates that the corresponding CCL task packet is received by the computing chip earlier. CCL0 is associated with the first computing chip, while CCL1 and CCL2 are associated with the second computing chip. Furthermore, CCL0 is divided into CCL0-sub0 and CCL0-sub1, and CCL1 is divided into... The CCL1 is divided into CCL1-sub0 and CCL1-sub1, and CCL2 is divided into CCL2-sub0 and CCL2-sub1. Therefore, CCL0-sub0 and CCL0-sub1 are assigned to the first computing chip, and CCL1-sub0, CCL1-sub1, CCL2-sub0, and CCL2-sub1 are assigned to the second computing chip. During the subsequent execution of CCL tasks, when both CCL1-sub0 and CCL2-sub0 are in the executable state, CCL1 enters the computing chip first, so CCL1-sub0 must be executed first. Furthermore, CCL2-sub0 cannot be executed before CCL1 is fully executed. That is, in the second computing chip, CCL2-sub0 cannot be executed if CCL1-sub0 and CCL1-sub1 have not been fully executed. Furthermore, CCL sub-task packages belonging to the same CCL task package must execute the CCL sub-task package with higher priority first. For the two CCL sub-task packages CCL0-sub0 and CCL0-sub1 of the CCL0 task package, CCL0-sub0 must be executed first before CCL0-sub1 can be executed; for the two CCL sub-task packages CCL1-sub0 and CCL1-sub1 of the CCL1 task package, CCL1-sub0 must be executed first before CCL1-sub1 can be executed; for the two CCL sub-task packages CCL2-sub0 and CCL2-sub1 of the CCL2 task package, CCL2-sub0 must be executed first before CCL2-sub1 can be executed.

[0102] In one embodiment, refer to Figure 6Each CCL task package corresponds to CCL task package information, which is stored in a preset storage unit. Each storage unit is pointed to by a value pointer in a linker node of a preset linked list structure. The linked list structure also includes a head pointer, and the linked list structure includes multiple linker nodes. Each linker node also includes a successor pointer, and different linker nodes are connected based on their successor pointers. The data scheduling method also includes:

[0103] Step S601: Starting from the linker node pointed to by the head pointer, the CCL task package information in the storage unit pointed to by the value pointer in the linker node is checked in turn.

[0104] Step S602: When the CCL task package information indicates that the corresponding CCL task package has entered the executable state, the corresponding CCL task package is scheduled for execution.

[0105] Specifically, such as Figure 7 As shown, Figure 7 A linked list structure is provided, which may include a head pointer, a tail pointer, and multiple linker nodes. Each linker node may include a flag, a value pointer, and a successor pointer. Linker nodes are connected through successor pointers. Figure 7 The provided linked list structure is in an empty list state. Here, Linker is the linker node, Header is the head pointer, Tail is the tail pointer, Invalid is a flag indicating that the linker node is empty or invalid, Next is the successor pointer, and Value is the value pointer, pointing to a specific memory location. When the linked list structure is empty, both Header and Tail point to the same linker node, and the flag in that linker node is set to Invalid. Figure 8 As shown, when a CCL task enters a linker node, the flag in that linker node will change from Invalid to valid, indicating that the linker node is valid; for example... Figure 8 As shown, three CCL tasks have entered the link structure. During the process of receiving CCL tasks, the tail pointer Tail will move and always point to the first empty linker node in the link structure. Therefore, the tail pointer Tail points to the last linker node at this time.

[0106] It is worth noting that a linked list structure can include multiple linker nodes. Figure 7 The example given is just an illustration of a linked list structure with 4 linker nodes. It does not mean that a linked list structure can only include 4 linker nodes. There can also be 5, 6, or 7 linker nodes, etc., which are not limited here.

[0107] Specifically, such as Figure 9 As shown, Figure 9 A schematic diagram of the mapping relationship between the linked list structure and the storage unit is provided; Slot0, Slot1, Slot2 and Slot3 represent storage units, which correspond to the actual physical storage address. The storage unit is used to store CCL task package information corresponding to each CCL task package; Slot0, Slot1, Slot2 and Slot3 can be specified by the Value in each linker node.

[0108] In step S601, during the dynamic scheduling of CCL tasks based on the linked list structure, the entire linked list structure is traversed starting from the linker node pointed to by the head pointer. Furthermore, the CCL task package information in the storage unit pointed to by the value pointer of each linker node is checked to determine whether the corresponding CCL task has entered the executable state. Figure 8As shown, three linker nodes receive CCL tasks: the first linker node, the second linker node, and the third linker node. The first linker node, pointed to by the head pointer, begins traversing the linked list structure. It's important to note that when using the linked list structure to receive CCL tasks, for example, if three CCL tasks are received (CCL0, CCL1, and CCL2), CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, and CCL2 carries a sequence flag of 2. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, the first linker node, pointed to by the head pointer, will receive CCL0, the second linker node will receive CCL1, and the third linker node will receive CCL2. During the reception of CCL tasks based on the linked list structure, the reception is also based on the connection method of each linker node; the first received CCL task is sorted to the front of the linked list structure. In this process, CCL0 carries the information of the first computing kernel, while CCL1 and CCL2 carry the information of the second computing kernel. Therefore, CCL0 will be assigned to the first computing kernel, and CCL1 and CCL2 will be assigned to the second computing kernel. Before executing the CCL task, it is determined that CCL0, CCL1, and CCL2 do not belong to the same computing kernel. Therefore, the data scheduling method of this embodiment can be used for CCL task scheduling and execution. Starting from the head pointer of the linked list structure, during the process of detecting the CCL task package information in the storage unit pointed to by each linker node in the linked list structure, the corresponding CCL task package information can be determined. If a CL task has entered an executable state, for example, if CCL0 corresponding to the first linker node is still in a waiting state, while CCL1 corresponding to the second linker node and CCL2 corresponding to the third linker node are already in an executable state, then CCL1 corresponding to the second linker node will be executed first. During the execution of CCL1 corresponding to the second linker node, CCL0 corresponding to the first linker node will enter an executable state from a waiting state. After CCL1 corresponding to the second linker node is completed, the traversal will start again from the first linker node pointed to by the head pointer, so CCL0 corresponding to the first linker node can then be executed.

[0109] In step S602, starting from the linker node pointed to by the head pointer, the CCL task packages in the storage units pointed to by each linker node are detected and processed sequentially. If the CCL task package information in the storage unit indicates that the corresponding CCL task package has entered an executable state, then the corresponding CCL task package can be directly scheduled and executed. For example, as... Figure 10 As shown, Figure 10 Given a linked list structure in a full state, where the Header and Tail of the linked list both point to the same linker node, and the flag in the linker node is set to valid. Figure 10 The system includes four linker nodes: the first linker node, the second linker node, the third linker node, and the fourth linker node. This linked list structure receives four CCL tasks: CCL0, CCL1, CCL2, and CCL3. CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, CCL2 carries a sequence flag of 2, and CCL3 carries a sequence flag of 3. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, the first linker node, pointed to by the head pointer, will receive CCL0, and the second linker node will receive CCL1. The third linker node will receive CCL2, and the fourth linker node will receive CCL3. Starting from the head pointer of the linked list structure, during the process of checking the CCL task package information in the storage unit pointed to by each linker node in the linked list structure, it can be determined whether the corresponding CCL task has entered the executable state. For example, if CCL0 corresponding to the first linker node is still in the waiting state, while CCL1 corresponding to the second linker node is in the executable state, CCL1 corresponding to the second linker node can be executed first, without waiting for CCL0 to finish executing before executing CCL1, which can also greatly improve the execution efficiency of CCL tasks.

[0110] In steps S601 to S602, during the sorting and execution of CCL tasks based on the linked list structure, it is necessary to start from the linker node pointed to by the head pointer and traverse each linker node in the linked list structure. Simultaneously, the CCL task package information in each storage unit pointed to by each linker node is detected to determine whether the corresponding CCL task has entered the executable state. When it is detected that the CCL task package information in the storage unit pointed to by the linker node indicates that the corresponding CCL task package has entered the executable state, the corresponding CCL task package can be executed first, thereby achieving more stable and reliable CCL task scheduling and execution. For example, as shown... Figure 9 and Figure 10As shown, a linked list structure includes four linker nodes: the first linker node, the second linker node, the third linker node, and the fourth linker node. The value pointers in the first linker node point to Slot1, the second linker node to Slot3, the third linker node to Slot2, and the fourth linker node to Slot0. This linked list structure receives four CCL tasks: CCL0, CCL1, CCL2, and CCL3. CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, CCL2 carries a sequence flag of 2, and CCL3 carries a sequence flag of 3. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. The first linker node, pointed to by the head pointer, receives CCL0, the second linker node receives CCL1, the third linker node receives CCL2, and the fourth linker node receives CCL3. The node will receive CCL3; therefore, Slot1 stores CCL task package information related to CCL0, Slot3 stores CCL task package information related to CCL1, Slot2 stores CCL task package information related to CCL2, and Slot0 stores CCL task package information related to CCL3. Starting from the first linker node pointed to by the head pointer, each linker node is traversed. Therefore, the CCL task package information related to CCL0 stored in Slot1 needs to be checked first. If the CCL task package information related to CCL0 is found to be in a waiting state, the CCL task package information related to CCL1 stored in Slot3 pointed to by the second linker node will be checked. If the CCL task package information related to CCL1 is found to be in an executable state, CCL1 will be executed. This can also realize the dynamic scheduling and execution of CCL tasks without following the first-in-first-out principle.

[0111] In one embodiment, refer to Figure 11 After step S602 is executed, the data scheduling method further includes:

[0112] Step S701: When the CCL task package is completed, the CCL task package information corresponding to the CCL task package is deleted from the corresponding storage unit, and the linker node pointed to by the corresponding storage unit is deleted so that the linked list structure can be reconstructed.

[0113] In step S701, after the CCL task package is completed, the CCL task package information corresponding to the CCL task package can be deleted from the corresponding storage unit. Furthermore, the linked list structure needs to be adjusted, and the linker node corresponding to the completed CCL task package needs to be deleted to rebuild the linked list structure and prepare for subsequent CCL task execution. For example, as... Figure 9 , Figure 10 and Figure 12As shown, the linked list structure includes four linker nodes: the first linker node, the second linker node, the third linker node, and the fourth linker node. This linked list structure receives four CCL tasks: CCL0, CCL1, CCL2, and CCL3. CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, CCL2 carries a sequence flag of 2, and CCL3 carries a sequence flag of 3. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, the first linker node, pointed to by the head pointer, will receive CCL0, the second linker node, and the third linker node. The second linker node receives CCL1, the third linker node receives CCL2, and the fourth linker node receives CCL3; because the value pointer in the first linker node points to Slot1, the value pointer in the second linker node points to Slot3, the value pointer in the third linker node points to Slot2, and the value pointer in the fourth linker node points to Slot0; therefore, Slot1 stores CCL task package information related to CCL0, Slot3 stores CCL task package information related to CCL1, Slot2 stores CCL task package information related to CCL2, and Slot0 stores CCL1. The CCL task package information related to CL3 is checked by examining the CCL task package information in the storage units pointed to by each linker node in the linked list, starting from the head pointer. This process determines whether the corresponding CCL task has entered the executable state. For example, if CCL0 corresponding to the first linker node is still in a waiting state, while CCL1 corresponding to the second linker node is in an executable state, then CCL1 corresponding to the second linker node can be executed first. After CCL1 corresponding to the second linker node is executed, the CCL task package information related to CCL1 stored in Slot3 can be processed. The process involves deleting the second linker node from the original linked list structure, connecting the original first linker node directly to the original third linker node, and connecting a newly created linker node after the original fourth linker node. One end of the newly created linker node is connected to the original fourth linker node, and the other end is connected to the original first linker node. Since only the newly created linker node is empty in the newly created linked list structure, the tail pointer will move to the newly created linker node. When a new CCL task arrives, it will be assigned to the newly created linker node.

[0114] It is worth noting that when a CCL task package is divided into multiple CCL sub-task packages, the CCL task package information belonging to the same CCL task package is stored in the same storage unit. For example, the first linker node pointed to by the head pointer receives CCL0, and CCL0 is divided into three CCL sub-task packages: CCL0-sub0, CCL0-sub1, and CCL0-sub2. Since the value pointer in the first linker node points to Slot1, Slot1 stores the CCL task package information related to the three CCL sub-task packages CCL0-sub0, CCL0-sub1, and CCL0-sub2, and does not store the CCL task package information related to these three CCL sub-task packages in multiple different storage units. Furthermore, during the execution of CCL tasks, if multiple CCL sub-tasks belonging to the same CCL task package are not completely executed, the relevant linker nodes are not deleted, and the linked list structure is not rebuilt. In other words, the first linker node will not be deleted if the three CCL subtask packages CCL0-sub0, CCL0-sub1, and CCL0-sub2 are not executed completely. For example, if only CCL0-sub0 is executed and CCL0-sub1 and CCL0-sub2 are not executed, the first linker node will not be deleted.

[0115] In one embodiment, refer to Figure 13 The CCL task package information includes core tag information and synchronization status information. Each computation core corresponds to a core tag. After executing step S602, the data scheduling method further includes:

[0116] Step S801: Determine that the corresponding CCL task package has not been fully executed based on the synchronization status information;

[0117] Step S802: Generate an inverse mask based on the core marker information corresponding to the corresponding CCL task package;

[0118] Step S803: Based on the reverse mask, unexecuted CCL task packages with the same core tag information are marked as unschedulable until the previously executed CCL task packages are completed.

[0119] In step S801, the CCL task package information stored in the storage unit may include core tag information and synchronization status information; the synchronization status information is used to characterize the execution status of the CCL task package corresponding to the storage unit, wherein the synchronization status information may indicate that the corresponding CCL task package has been completely executed or that the corresponding CCL task package has not been completely executed; for example, the first linker node pointed to by the head pointer receives CCL0, and CCL0 is divided into three CCL sub-task packages: CCL0-sub0, CCL0-sub1, and CCL0-sub2; since the value pointer in the first linker node points to Slot1, Slot1 stores CCL task package information related to the three CCL sub-task packages: CCL0-sub0, CCL0-sub1, and CCL0-sub2. During the execution of CCL tasks, if only CCL0-sub0 is completed while CCL0-sub1 and CCL0-sub2 are not executed, the synchronization status information in the CCL task package information stored in Slot1 will indicate that the CCL0 task package has not been fully executed.

[0120] In step S802, since the CCL task package information stored in the storage unit also includes kernel tag information, which is used to characterize the specific computing kernel to which the CCL task is assigned; if the corresponding CCL task package is not fully executed, a reverse mask can be generated based on the corresponding kernel tag information to mark other CCL task packages in the same computing kernel as the CCL task package as unschedulable, thereby effectively preventing scheduling out-of-order situations and making the dynamic scheduling of CCL tasks more stable and reliable.For example, the linked list structure includes four linker nodes: a first linker node, a second linker node, a third linker node, and a fourth linker node. This linked list structure receives four CCL tasks: CCL0, CCL1, CCL2, and CCL3. CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, CCL2 carries a sequence flag of 2, and CCL3 carries a sequence flag of 3. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, the first linker node, pointed to by the head pointer, will receive CCL0, the second linker node, and the third linker node. The second linker node receives CCL1, the third linker node receives CCL2, and the fourth linker node receives CCL3. This is because the value pointers in the first linker node point to Slot1, the second linker node points to Slot3, the third linker node points to Slot2, and the fourth linker node points to Slot0. Therefore, Slot1 stores CCL task package information related to CCL0, Slot3 stores CCL task package information related to CCL1, Slot2 stores CCL task package information related to CCL2, and Slot0 stores CCL... 3. Relevant CCL task package information; If CCL0 and CCL1 are assigned to the first computational kernel, and CCL2 and CCL3 are assigned to the second computational kernel; starting from the head pointer of the linked list structure, during the process of checking the CCL task package information in the storage units pointed to by each linker node in the linked list structure, it can be determined whether the corresponding CCL task has entered the executable state. For example, CCL0 corresponding to the first linker node is still in the waiting state, CCL1 corresponding to the second linker node is in the executable state, CCL2 corresponding to the third linker node is in the executable state, and CCL3 corresponding to the fourth linker node is in the executable state. 3. In a waiting state; Since CCL0 and CCL1 are in the same computational kernel, but CCL0 is still in a waiting state, neither CCL0 nor CCL1 can be executed temporarily; CCL2, which is in the second computational kernel, is in an executable state and can be executed immediately; If CCL2 has not been executed, the kernel marking information in the CCL task package information stored in Slot2 will generate a reverse mask, so that other CCL tasks in the same computational kernel as CCL2 will be marked as unschedulable, that is, CCL3 will be marked as unschedulable by the reverse mask until CCL2 is executed.

[0121] In step S803, a reverse mask is generated based on the core tag information corresponding to the corresponding CCL task package. This allows CCL task packages that have not been executed to be marked as unschedulable until the corresponding CCL task package is completed. Through the above settings, CCL tasks in the same computing core will not be out of order during the execution process, making the dynamic scheduling process of CCL tasks more stable and reliable.

[0122] In steps S801 to S803, during the execution of CCL tasks, when the CCL task package information includes synchronization status information indicating that the corresponding CCL task package has not been fully executed, a reverse mask is generated based on the core marker information in the CCL task package information. Finally, based on the reverse mask, unexecuted CCL task packages with the same core marker information are marked as unschedulable until the previously executed CCL task packages are completed. Through the above settings, out-of-order execution of CCL tasks in the same computing core can be effectively prevented, resource deadlock can be avoided during dynamic scheduling of CCL tasks, and the stability and reliability of CCL task execution can be improved.

[0123] For example, the first linker node pointed to by the head pointer receives CCL0, and CCL0 is divided into CCL0-sub0 and CCL0-sub1; the second linker node receives CCL1, and CCL1 is divided into CCL1-sub0 and CCL1-sub1; the third linker node receives CCL2, and CCL2 is divided into CCL2-sub0 and CCL2-sub1; the fourth linker node receives CCL3, and CCL3 is divided into CCL3-sub0 and CCL3-sub1; and CCL0 and CCL1 are assigned to the first computing core, while CCL2 and CCL3 are assigned to the second computing core. During the process of detecting the CCL task package information in the storage units pointed to by each linker node in the linked list structure, starting from the head pointer of the linked list structure, the corresponding... The system checks whether the CCL tasks have entered the executable state. For example, CCL0-sub0 enters the waiting state, CCL0-sub1 enters the waiting state, CCL1-sub0 enters the executable state, CCL1-sub1 enters the waiting state, CCL2-sub0 enters the executable state, CCL2-sub1 enters the waiting state, CCL3-sub0 enters the executable state, and CCL3-sub1 enters the waiting state. Since CCL0-sub0 in the first computational kernel is in the waiting state and has the highest priority in the first computational kernel, all CCL task packages in the first computational kernel cannot be executed. Since CCL2-sub0 in the second computational kernel has entered the executable state and has the highest priority in the second computational kernel, CCL2-sub0 can be executed first. After CCL2-sub0 is executed, since CCL2-sub1 is not executed, the inverse mask generated by the core tag information in the CCL task package information corresponding to CCL2 will prevent CCL3-sub0 and CCL3-sub1 in the second computation core from being executed, in order to prevent out-of-order scheduling of CCL tasks.

[0124] For example, such as Figure 14As shown in the figure, a reverse mask generation process is illustrated. Logic Slot0 represents the logical storage unit corresponding to storage unit Slot0. This logical storage unit corresponds to a logical address. The kernel marker [0] is the kernel marker information in the CCL task package information stored in Slot0. Logic Slot1 represents the logical storage unit corresponding to storage unit Slot1. This logical storage unit corresponds to a logical address. The kernel marker [1] is the kernel marker information in the CCL task package information stored in Slot1. Logic Slot2 represents the logical storage unit corresponding to storage unit Slot2. This logical storage unit corresponds to a logical address. The kernel marker [2] is the kernel marker information in the CCL task package information stored in Slot2. Furthermore, Logic Slot0 can be understood as the first linker node pointed to by the head pointer in the linked list structure, Logic Slot1 can be understood as the second linker node pointed to by the head pointer in the linked list structure, and Logic Slot2 can be understood as the third linker node pointed to by the head pointer in the linked list structure. For example, starting from Logic Slot0, when the CCL task corresponding to Logic Slot0 is executed, the core marker [0] corresponding to Logic Slot0 will be set to 1, and the rest will be set to 0. After the inversion operation, the mask marker [0] corresponding to Logic Slot0 will become 0, and the rest will become 1. If the core marker [1] corresponding to Logic Slot1 is the same as the core marker [0], after the AND operation, all results will be 0. At this time, the CCL task corresponding to Logic Slot1 will be masked by the inverse mask and cannot be executed. If the core marker [1] corresponding to Logic Slot1 is different from the core marker [0], after the AND operation, one calculation result will be 1. Therefore, the mask set result [1] obtained after the merge operation will be 1. If the synchronization status information [1] corresponding to Logic Slot1 indicates that the CCL task is not completed, the scheduling marker [1] will be marked as schedulable. Similarly, other Logic Slots can also be judged in the same way to determine whether they can be scheduled for execution.

[0125] In one embodiment, refer to Figure 15 The linker node also includes a flag, the linked list structure includes a tail pointer, and the data scheduling method includes:

[0126] In step S901, when the linker node pointed to by the tail pointer receives a new CCL task packet, the CCL task packet will be stored in the storage unit corresponding to the corresponding linker node, and the flag bit in the corresponding linker node will be changed.

[0127] In step S902, the tail pointer moves to the next linker node according to the successor pointer.

[0128] In step S901, during the CCL task execution scheduling process, when the linked list structure receives a new CCL task packet, it uses the linker node pointed to by the tail pointer to receive and process the new CCL task packet. Then, the CCL task packet is stored in the memory unit corresponding to the linker node pointed to by the tail pointer, and the flag bit in the linker node pointed to by the tail pointer is changed. For example, a linked list structure includes four linker nodes: a first linker node, a second linker node, a third linker node, and a fourth linker node. This linked list structure receives three CCL tasks: CCL0, CCL1, and CCL2. CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, and CCL2 carries a sequence flag of 2. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, the first linker node receives CCL0, and the second linker node receives CCL1. The third linker node receives CCL2; and the value pointers in the first linker node point to Slot1, the second linker node points to Slot3, the third linker node points to Slot2, and the fourth linker node points to Slot0. Since the tail pointer always points to the first empty linker node in the linked list structure, it now points to the fourth linker node. When a new CCL task arrives, the fourth linker node can be used to receive and process the new CCL task, and store the received CCL task packet in Slot0. It is worth noting that when a linker node receives a CCL task packet, its internal flag bit can change from 0 to 1; therefore, in the above embodiment, the flag bit in the fourth linker node will change from 0 to 1 to indicate that the linker node is valid.

[0129] In step S902, after the linker node previously pointed to by the tail pointer receives a new CCL task packet, the tail pointer moves to the next linker node, thus preparing for the reception of subsequent CCL task packets. For example, a linked list structure includes three linker nodes: a first linker node, a second linker node, and a third linker node. This linked list structure receives one CCL task, CCL0. The first linker node receives CCL0, and at this time, the tail pointer points to the second linker node. When a new CCL task, CCL1, enters the linked list structure, the second linker node can be used to receive CCL1. After receiving the CCL1, the tail pointer moves to the next linker node after the second linker node, i.e., to the third linker node. Therefore, when a new CCL task enters subsequently, the third linker node can be used to receive it.

[0130] In steps S901 to S902, during the process of the linked list structure receiving a new CCL task packet, the linker node pointed to by the tail pointer will be used to receive and process the CCL task packet, and the received CCL task packet will be stored in the storage unit corresponding to the linker node, and the flag bit in the linker node will be converted. After the linker node pointed to by the tail pointer receives the CCL task packet, it will move to the next linker node through the successor pointer to prepare for the reception of subsequent CCL task packets. Through the above settings, the linked list structure can better realize the dynamic scheduling and processing of CCL task packets.

[0131] For example, a linked list structure includes three linker nodes: a first linker node, a second linker node, and a third linker node. This linked list structure receives one CCL task, CCL0. The value pointer in the first linker node points to Slot0, the value pointer in the second linker node points to Slot2, and the value pointer in the third linker node points to Slot1. The first linker node receives CCL0, and the CCL task packet information associated with CCL0 is stored in Slot0. At this time, the tail pointer points to the second linker node. When a new CCL task CCL1 enters the linked list structure, the second linker node can be used to receive CCL1 and store the CCL task packet information associated with CCL1 in Slot2. After receiving the task, the flag bit of the second linker node changes from 0 to 1. The tail pointer then moves to the next linker node after the second linker node, i.e., to the third linker node, to prepare for the reception of subsequent CCL tasks.

[0132] In one embodiment, refer to Figure 16 Data scheduling methods also include:

[0133] Step S1001: When the CCL task package corresponding to the linker node pointed to by the head pointer is completed, the flag bit in the linker node pointed to by the head pointer is changed.

[0134] In step S1002, the head pointer moves to the next linker node according to the successor pointer.

[0135] In step S1001, during the CCL task execution scheduling process, when the CCL task package corresponding to the linker node pointed to by the head pointer is completed, the flag bit in the linker node pointed to by the head pointer will change to indicate that the CCL task package corresponding to the linker node has been completed. For example, a linked list structure includes three linker nodes: a first linker node, a second linker node, and a third linker node. This linked list structure receives three CCL tasks: CCL0, CCL1, and CCL2. CCL0 carries a sequence flag of 0, CCL1 carries a sequence flag of 1, and CCL2 carries a sequence flag of 2. The smaller the sequence flag, the earlier the corresponding CCL task packet is received by the computing chip. Therefore, the first linker node receives CCL0, the second linker node receives CCL1, and the third linker node receives CCL2. At this time, the head pointer points to the first linker node. Starting from the head pointer, each linker node is traversed. When CCL0 enters the executable state, the CCL0 corresponding to the first linker node can be executed. After CCL0 is executed, the flag in the first linker node changes from 1 to 0, and the first linker node is deleted to reconstruct the linked list structure.

[0136] In step S1002, after the CCL task package corresponding to the linker node originally pointed to by the head pointer is executed, the head pointer of the linked list structure will move to the next linker node to prepare for the execution of subsequent CCL task packages. For example, a linked list structure includes three linker nodes: a first linker node, a second linker node, and a third linker node. This linked list structure receives two CCL tasks, CCL0 and CCL1. The first linker node receives CCL0, and the second linker node receives CCL1. Starting from the head pointer, each linker node is traversed. When CCL0 is found to be in an executable state, it can be executed immediately. After CCL0 corresponding to the first linker node is executed, the flag bit in the first linker node changes from 1 to 0, and the head pointer moves to the second linker node. Therefore, in the next execution of a CCL task, the traversal of each linker node will begin from the linker node pointed to by the head pointer.

[0137] In steps S1001 to S1002, the flag bit in the linker node pointed to by the head pointer in the linked list structure will only change if the CCL task package corresponding to the linker node pointed to by the head pointer is completed; and the linker will only move to the next linker node if the corresponding CCL task package is completely completed. If the CCL task package corresponding to the linker node pointed to by the head pointer is not completely completed, the flag bit in the linker node will not change, and the head pointer in the linked list structure will not move. For example, a linked list structure includes three linker nodes: a first linker node, a second linker node, and a third linker node. This linked list structure receives two CCL tasks: CCL0 and CCL1. CCL0 is divided into CCL0-sub0 and CCL0-sub1, and CCL1 is divided into CCL1-sub0 and CCL1-sub1. The first linker node receives CCL0-sub0 and CCL0-sub1, and the second linker node receives CCL1-sub0 and CCL1-sub1. Starting from the head pointer, each linker node is traversed. It is found that CCL0-sub0 has entered the executable state, so CCL0-sub0 can be executed immediately. However, CCL0-sub1 in the first linker node has not been executed. Therefore, the head pointer still points to the first linker node, and the flag bit in the first linker node is still 1. The head pointer will only move when CCL0-sub1 has also been executed.

[0138] It is worth noting that in the linked list structure of this embodiment, the head pointer, tail pointer, and the entire linked list structure are constantly changing during the dynamic scheduling of CCL tasks. Based on the linked list structure, the execution order of each CCL task can be adjusted well, which not only enables the CCL tasks to execute quickly, but also ensures the reliability and stability of CCL task execution. The linked list structure can well meet the requirements of dynamic scheduling of CCL tasks.

[0139] This disclosure also provides an electronic device 1700, comprising:

[0140] At least one processor, and a memory communicatively connected to the at least one processor; wherein the memory stores instructions which are executed by the at least one processor to cause the at least one processor to perform the method as described in any of the above embodiments of the present disclosure when executing the instructions.

[0141] The following is combined with Figure 17The hardware structure of the electronic device is described in detail. The electronic device includes: a processor 1710, a memory 1720, an input / output interface 1730, a communication interface 1740, and a bus 1750.

[0142] The processor 1710 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this disclosure.

[0143] The memory 1720 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1720 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1720 and is called and executed by the processor 1710 using the data scheduling method of the embodiments of this disclosure.

[0144] The input / output interface 1730 is used to implement information input and output;

[0145] The communication interface 1740 is used to enable communication and interaction between this device and other devices. Communication can be achieved via wired means (e.g., USB, Ethernet cable) or wireless means (e.g., mobile network, Wi-Fi, Bluetooth).

[0146] Bus 1750 transmits information between various components of the device (e.g., processor 1710, memory 1720, input / output interface 1730, and communication interface 1740);

[0147] The processor 1710, memory 1720, input / output interface 1730 and communication interface 1740 are connected to each other within the device via bus 1750.

[0148] This disclosure also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the data scheduling method of the above embodiments, which will not be described in detail here.

[0149] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0150] It should be understood that in this disclosure, "at least one (item)" refers to one or more, and "more than" refers to two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple. It should be understood that in the description of the embodiments of this disclosure, "more than" means two or more, "greater than", "less than", "exceeding", etc., are understood to exclude the number itself, while "above", "below", "within", etc., are understood to include the number itself.

[0151] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0152] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0153] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units. It should also be understood that the various implementation methods provided in this disclosure can be arbitrarily combined to achieve different technical effects.

[0154] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A data scheduling method, characterized in that, Applied to a computing chip, the computing chip comprising multiple computing chips, each computing chip comprising multiple computing units, the data scheduling method comprising: The computing chip receives multiple CCL task packets, wherein each CCL task packet carries sequence marker information, which is used to characterize the order in which the computing chip receives the CCL task packets. The computing chip distributes multiple CCL task packages to at least two different computing chips. When the first CCL task package in any of the computing cores enters the executable state, the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL task package, wherein the first CCL task package is the CCL task package that enters the corresponding computing core first, as indicated by the sequence mark information. Each CCL task package corresponds to CCL task package information, which is stored in a preset storage unit. Each storage unit is pointed to by a value pointer in a linker node of a preset linked list structure. The linked list structure also includes a head pointer and multiple linker nodes. Each linker node also includes a successor pointer, and different linker nodes are connected based on the successor pointers. The data scheduling method further includes: Starting from the linker node pointed to by the head pointer, the CCL task package information in the storage unit pointed to by the value pointer in the linker node is detected sequentially; When the CCL task package information indicates that the corresponding CCL task package has entered an executable state, the corresponding CCL task package is scheduled for execution. The CCL task package information includes core tag information and synchronization status information. Each computing core corresponds to one core tag information. After scheduling and executing the corresponding CCL task package when the CCL task package information indicates that the corresponding CCL task package has entered an executable state, the data scheduling method further includes: Based on the synchronization status information, it is determined that the corresponding CCL task package has not been fully executed. A reverse mask is generated based on the core marker information corresponding to the CCL task package. Based on the reverse mask, unexecuted CCL task packages with the same core tagging information are marked as unschedulable until the previously executed CCL task package is completed.

2. The data scheduling method according to claim 1, characterized in that, The CCL task package includes multiple CCL sub-task packages, each of which carries label information. The label information is used to characterize the task execution priority of the CCL sub-task packages within the same CCL task package. The data scheduling method further includes: When the first CCL subtask package in any of the computing cores enters the executable state, the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL subtask package. The first CCL subtask package is the CCL subtask package with the highest task execution priority, represented by the sequence mark information.

3. The data scheduling method according to claim 1, characterized in that, When the first CCL task package in any of the computing cores enters the executable state, after the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL task package, the data scheduling method further includes: When the first CCL task package is completed, the second CCL task package, which is in a different computing chip than the first CCL task package, enters the executable state. The second CCL task package is then processed by the computing unit in the corresponding computing chip. The second CCL task package is characterized by the sequence marking information as the CCL task package that entered the corresponding computing chip first.

4. The data scheduling method according to claim 2, characterized in that, When the first CCL subtask package in any of the computing cores enters the executable state, after the computing unit in the corresponding computing core performs priority scheduling and execution processing on the first CCL subtask package, the data scheduling method further includes: When the first CCL subtask package is completed, the second CCL subtask package, which is located in a different computing core than the first CCL subtask package, enters the executable state. The second CCL subtask package is then processed by the computing unit in the corresponding computing core. The second CCL subtask package is characterized by the sequence marking information representing the CCL subtask package that first enters the corresponding computing core, and the label information representing the CCL subtask package with the highest task execution priority.

5. The data scheduling method according to claim 1, characterized in that, After scheduling and executing the corresponding CCL task package when the CCL task package information indicates that the corresponding CCL task package has entered an executable state, the data scheduling method further includes: When the CCL task package is completed, the CCL task package information corresponding to the CCL task package is deleted from the corresponding storage unit, and the linker node pointed to by the corresponding storage unit is deleted, so that the linked list structure can be rebuilt.

6. The data scheduling method according to claim 1, characterized in that, The linker node also includes a flag bit, the linked list structure also includes a tail pointer, and the data scheduling method further includes: When the linker node pointed to by the tail pointer receives a new CCL task packet, it will store the CCL task packet in the storage unit corresponding to the corresponding linker node, and the flag bit in the corresponding linker node will be changed. The tail pointer moves to the next linker node according to the successor pointer.

7. The data scheduling method according to claim 6, characterized in that, The data scheduling method further includes: When the CCL task package corresponding to the linker node pointed to by the head pointer is completed, the flag bit in the linker node pointed to by the head pointer is changed; The head pointer moves to the next linker node according to the successor pointer.

8. An electronic device, characterized in that, The electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing communication between the processor and the memory. The program is executed by the processor to implement the data scheduling method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the data scheduling method as described in any one of claims 1 to 7.

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