Sharing cache device and method of chip

Abstract

The embodiment of the invention discloses a shared cache device and method of a chip, and the device comprises a data distribution module which is used for receiving data in a data stream sent by a data bus and sending an instruction for outputting an effective pointer to a pointer processing module, and a shared cache write operation module which is used for receiving the effective pointer output by the pointer processing module and sending the effective pointer to the pointer processing module. The data processing module is used for receiving the data sent by the data distribution module, writing the valid data into the RAM based on the bit number of the valid data in the data and the write bit width of a cache memory in the RAM, determining a cache pointer corresponding to the valid data, and sending the cache pointer to the pointer processing module; the pointer processing module is used for reading a pointer from a pointer pool set in a cache module corresponding to the RAM, and is also used for receiving a read request for reading effective data in the RAM, reading the effective data in the RAM according to a cache pointer corresponding to the read request, and inputting the cache pointer after reading the effective data as a pointer to be recycled into the pointer pool for sharing the RAM by a plurality of data streams; the utilization rate of the shared cache space is improved.

Description

Technical Field

[0001] This application relates to the field of data exchange technology, and in particular to a shared cache device and method for a chip. Background Technology

[0002] Random Access Memory (RAM) is a data cache that can be written to and read from any specified address at any time. In many applications, it is required that the address to be written to can only be used to write other data after the data written to any address (pointer) in RAM has been read and processed; otherwise, the data will be overwritten and cannot meet the application requirements.

[0003] In related technologies, when writing and reading data from RAM, RAM is typically divided into multiple RAM blocks, with a fixed cache space pre-allocated for each block. Alternatively, each RAM block can be configured using a linked list to adjust the cache space based on the specific needs of each data stream, thus caching data across multiple data streams. However, when the bandwidth rate of each data stream on the data bus changes, the allocated cache space also changes, making the above methods prone to low utilization of the shared cache space. Summary of the Invention

[0004] The purpose of this application is to provide a shared cache device and method for a chip, so as to improve the utilization rate of shared cache space.

[0005] To solve the above-mentioned technical problems, the embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a shared cache device for a chip, comprising: a data allocation module, a pointer processing module, a cache module, a shared cache write operation module, and RAM; the data allocation module is configured to receive data from a data stream transmitted via a data bus and send an instruction to the pointer processing module to output a valid pointer, thereby writing the data into the shared cache write operation module; wherein the data allocation module is a first-in-first-out (FIFO) queue, and the pointer processing module is configured to read pointers from a pointer pool set in the cache module corresponding to the RAM; the shared cache write operation module is configured to receive the valid pointer output by the pointer processing module and receive the... The data sent by the data allocation module is written into the RAM based on the number of bits of valid data and the write width of the cache memory in the RAM. The cache pointer corresponding to the valid data is determined and sent to the pointer processing module. The cache pointer includes the address where the valid data is stored. The pointer processing module is further configured to receive a read request to read the valid data in the RAM, read the valid data in the RAM according to the cache pointer corresponding to the read request, and input the cache pointer after reading the valid data as a pointer to be recycled into the pointer pool so that multiple data streams can share the RAM.

[0006] Secondly, embodiments of this application provide a method for sharing a cache. The method includes: acquiring data from a data stream transmitted via a data bus through a data allocation module, the data bus being used to poll the data streams from multiple ports; for each data stream, sending an instruction to a pointer processing module to output a valid pointer through the data allocation module, wherein the pointer processing module is used to read a new pointer from a pointer pool set in a cache module corresponding to RAM; inputting the data into a shared cache write operation module through the data allocation module, and acquiring the valid pointer output by the pointer processing module through the shared cache write operation module, and writing the valid data into RAM according to the number of bits of the valid data and the write bit width of the cache memory in RAM, and determining a cache pointer for the valid data; inputting the cache pointer into the pointer processing module, the cache pointer including: an address storing the valid data; when the pointer processing module receives a read request to read the data in RAM, reading the valid data in RAM according to the cache pointer corresponding to the read request, and inputting the cache pointer after reading the valid data as a pointer to be reclaimed into the pointer processing module to share the cache memory of RAM.

[0007] Thirdly, embodiments of this application provide an electronic device, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement a chip shared cache method as described above.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instruction is stored, and when the program or instruction is executed by a processor, it is a chip shared cache method as described above.

[0009] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement a shared cache method for a chip as described above.

[0010] The shared cache device using the chip provided in this application embodiment receives data from the data stream sent by the data bus through the data allocation module and sends an instruction to the pointer processing module to output a valid pointer so as to write the data into the shared cache write operation module. The data allocation module is a First-In-First-Out (FIFO) queue. The pointer processing module reads pointers from the pointer pool set in the cache module corresponding to the RAM. The shared cache write operation module receives the valid pointer output by the pointer processing module and receives the data sent by the data allocation module. Based on the number of bits of valid data in the data and the write width of the cache memory in the RAM, it writes the valid data into the RAM, determines the cache pointer corresponding to the valid data, and sends the cache pointer to the pointer processing module. The cache pointer includes the address where the valid data is stored. The pointer processing module receives read requests to read valid data from the RAM, reads the valid data from the RAM according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data into the pointer pool as a pointer to be recycled, so that multiple data streams can share the RAM. Compared to related technologies, the shared cache write operation module of this device writes valid data to RAM by using the number of valid data bits in the data stream, the write width of the cache memory in RAM, and the acquired valid pointer. It can write data in the data stream to the RAM cache space according to the bandwidth of the data stream itself, without allocating a fixed amount of RAM cache space for the data stream, thus saving RAM cache space and simplifying RAM cache space allocation. Furthermore, it dynamically reclaims and reuses cache pointers through a pointer pool, preventing pointer problems that could prevent data from being written to or read from RAM. Since there is no need to manually allocate cache space in RAM for each data stream in advance, automatic chip management can be achieved when the circuit is running, and the utilization rate of the shared cache space can also be improved. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a chip shared cache device according to an embodiment of this application; Figure 2 This is a schematic diagram illustrating the acquisition of a pointer group by accumulating four pointers according to an embodiment of this application; Figure 3 This is a flowchart illustrating a chip shared cache method according to an embodiment of this application; Figure 4 This is a schematic diagram of a chip shared cache method according to an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] The shared cache device for the chip provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0015] Figure 1 The diagram illustrates a shared cache device for a chip according to an embodiment of the present invention. The device includes: a data allocation module 11, a pointer processing module 12, a cache module 13, a shared cache write operation module 14, and RAM 15.

[0016] The chip includes either a Field Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC), without specific limitations. The data allocation module 11, pointer processing module 12, cache module 13, shared cache write operation module 14, and RAM 15 are functional modules integrated on the chip.

[0017] The data allocation module 11 is used to receive data from the data stream sent by the data bus and send an instruction to the pointer processing module 12 to output a valid pointer so as to write the data into the shared cache write operation module 14; wherein, the data allocation module 11 is a first-in-first-out queue (FIFO), and the pointer processing module 12 is used to read pointers from the pointer pool 131 set in the cache module 13 corresponding to RAM 15.

[0018] The data bus connects multiple ports, and the data stream output from the ports is transmitted to the data allocation module 11 via the data bus. The data allocation module 11 receives the data from the data stream sent by the data bus. When the data allocation module 11 sends data to the shared cache write operation module 14, it needs to obtain a valid pointer to record the storage address of the data. Therefore, after receiving the data stream from the data bus, the data allocation module 11 sends an instruction to the pointer processing module 12 to output a valid pointer. After sending the data to the shared cache write operation module 14, the data is written to RAM 15 according to the valid pointer and the data in the data stream.

[0019] The cache module 13 is a module in the circuit. The cache module 13 sets up a pointer pool 131, which is used to store pointers and shares the address of the cache memory in RAM 15. The pointer processing module 12 can obtain a valid pointer from the pointer pool 131.

[0020] The data allocation module 11 can also accumulate counts for each data stream to determine the transmission progress of each data stream and all data within it. When the data bus receives data streams, it polls the data streams of each port. The data bus can connect to multiple ports, and each port can output multiple data streams. The data streams of each port and the data within them are in a first-in-first-out queue, which can be represented as a port FIFO. Data from the data streams corresponding to all ports is copied onto a single data bus, ensuring that the total bandwidth of the ports does not exceed the bandwidth of the data bus.

[0021] Specifically, each data stream has a corresponding unique stream code (Identity document, ID). The data in a data stream includes: the stream ID of the data stream to which it belongs, the packet start flag, packet end flag, and the offset position of the packet end flag of the network corresponding to the port.

[0022] For example, the data bus clock is 320MHz, the data bus width is 16 bytes, and the data bus bandwidth is 40.960G, corresponding to two 10ge Ethernet service ports. It is determined whether there is data in the port. If there is data, the Ethernet data and data in the data stream in the port are read onto the data bus. For example, the number of bytes of data is 16 bytes, and the data includes: stream ID (1k streams), the start of Ethernet packet flag sop (which is the first byte of the 16 bytes), the end of Ethernet packet flag eop, and the offset position eop_offset (corresponding to invalid data after eop in the 16 bytes).

[0023] The shared cache write operation module 14 is used to receive the valid pointer output by the pointer processing module 12 and the data sent by the data allocation module 11. Based on the number of bits of the valid data in the data and the write bit width of the cache memory in RAM 15, the valid data is written into RAM 15, and the cache pointer corresponding to the valid data is determined and sent to the pointer processing module 12. The cache pointer includes the address where the valid data is stored.

[0024] RAM15 is a random access memory, primarily used in scenarios where data caching is required within the chip. Each RAM15 has the same internal structure. This application achieves the effect of sharing RAM15 by writing and reading data from RAM15 through various functional modules.

[0025] The shared cache write operation module 14 is connected to the data allocation module 11, receives the data from the data stream input by the data allocation module 11, and receives the valid pointer output by the pointer processing module 12. The shared cache write operation module 14 writes the data in the data stream to RAM 15 based on the valid pointer.

[0026] The data sent by the data allocation module 11 may contain all valid bytes or invalid bytes. For example, under normal circumstances, all 16 bytes of data sent by the data allocation module 11 are valid. However, when the data includes eop, the data after the eop_offset position in its 16 bytes are invalid. Therefore, the valid data needs to be written to RAM 15 through the shared cache write operation module 14, while the invalid data does not need to occupy the memory space in RAM 15, thus preventing invalid data from occupying too much cache memory in RAM 15.

[0027] Specifically, there is a correspondence between the write width of the cache memory and the valid pointer obtained. For example, if 2K 64-byte write addresses are shared in RAM15, and since the data bus width is 16 bytes, the corresponding write width of the cache memory is also 16 bytes. Therefore, one valid pointer contains four 16-byte write addresses. The number of bits of valid data in the data stream corresponds to the write width of the cache memory in RAM15. Valid data is written to RAM15 according to the corresponding write width of the cache memory in RAM15, while invalid data in the data stream is not written to RAM15.

[0028] The cache pointer includes a valid pointer to the valid data. That is, the valid pointer is obtained after writing the valid data into RAM 15, based on the number of bits of valid data in the data stream and the write width of the cache memory in RAM 15. When the write width of the cache memory in RAM 15 includes valid data from a data stream and also includes valid data from the next data in the data stream input by the data allocation module 11, the valid pointer corresponding to that write width is also a cache pointer. The valid pointer containing the storage location of the valid data is used as a cache pointer and temporarily stored in the pointer processing module 12. The pointer processing module 12 can also accumulate the number of cache pointers.

[0029] The pointer processing module 12 is also used to receive read requests for reading valid data in RAM 15, read valid data in RAM 15 according to the cache pointer corresponding to the read request, and input the cache pointer after reading valid data as a pointer to be recycled into the pointer pool 131 so that multiple data streams can share RAM 15.

[0030] The pointer processing module 12 can store pointers and receive read requests for reading valid data in RAM 15. For example, when other application modules outside the device need to read valid data cached in RAM 15, they can use the cache pointer in the pointer processing module 12 to determine the location of the valid data corresponding to the read request in the cache memory of RAM 15, and then read the address of the valid data corresponding to the read request pointed to by the cache pointer to read the valid data corresponding to the read request.

[0031] After valid data is read from RAM 15, if the cached pointer in pointer processing module 12 does not point to an address with valid data, it is input into pointer pool 131 as a pointer to be reclaimed. RAM 15 can then be shared by data streams with different stream IDs.

[0032] As can be seen, when the data allocation module 11 receives a large-bandwidth data stream, it will obtain enough valid pointers from the pointer pool 131 through the pointer processing module 12 and write them into RAM 15, thus occupying a large space in RAM 15. Conversely, a small-bandwidth data stream obtains fewer valid pointers, thus occupying a small amount of space in RAM 15. If a small-bandwidth data stream receives a large amount of data in a short period, and then the data stops or arrives slowly (data burst), it can still obtain enough valid pointers during this burst. In this short period, the small-bandwidth data stream will occupy a large space in RAM 15, and then the space occupied will automatically decrease or even disappear after the burst ends. For some existing processing methods, if a fixed buffer space is allocated to the data stream, since it is unknown when the data burst will occur or end, a sufficiently large space may be allocated to a small-bandwidth data stream with a data burst, resulting in a long idle time for this portion of the buffer space in RAM 15, leading to waste.

[0033] The shared cache device of the chip provided in this application embodiment receives data from the data stream sent by the data bus through the data allocation module 11 and sends an instruction to the pointer processing module 12 to output a valid pointer so as to write the data into the shared cache write operation module 14. The data allocation module 11 is a first-in-first-out (FIFO) queue. The pointer processing module 12 reads pointers from the pointer pool 131 set in the cache module 13 corresponding to RAM 15. The shared cache write operation module 14 receives the valid pointer output by the pointer processing module 12 and receives the data sent by the data allocation module 11. Based on the number of bits of valid data in the data and the write bit width of the cache memory in RAM 15, it writes the valid data into RAM 15, determines the cache pointer corresponding to the valid data, and sends the cache pointer to the pointer processing module 12. The cache pointer includes the address where the valid data is stored. The pointer processing module 12 receives a read request to read valid data from RAM 15, reads the valid data from RAM 15 according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data into the pointer pool 131 as a pointer to be recycled, so that multiple data streams can share RAM 15. Compared to related technologies, the shared cache write operation module 14 of this device writes valid data to RAM 15 by using the number of valid data bits in the data stream, the write bit width of the cache memory in RAM 15, and the obtained valid pointer. It can write data in the data stream to the cache space of RAM 15 according to the bandwidth of the data stream itself, without allocating a fixed cache space in RAM 15 for the data stream, thus saving cache space in RAM 15 and simplifying the allocation of cache space in RAM 15. Furthermore, it dynamically reclaims and reuses cache pointers through the pointer pool 131, preventing pointer problems that would prevent data from being written to or read from RAM 15 normally. Since there is no need to manually allocate cache space in RAM 15 for each data stream in advance, automatic chip management can be achieved when the circuit is running, and the utilization rate of shared cache space can also be improved.

[0034] In one embodiment, the data allocation module 11 in the device is further configured to: receive a data push instruction sent by the pointer processing module 12 when no data stream is received from the data bus, the data push instruction being used to push the shared cache write operation module 14 to output a cache pointer that has not been fully written with valid data; and after receiving the data push instruction and pushing the shared cache write operation module 14 to output a cache pointer that has not been fully written with valid data, send an instruction to the pointer processing module 12 to output a valid pointer, obtain a null pointer, and write the null pointer to the pointer processing module 12.

[0035] Specifically, in addition to sending the instruction to the pointer processing module 12 to output a valid pointer and writing the data in the data stream into the shared buffer write operation module 14, the data allocation module 11 can also receive the data push instruction sent by the pointer processing module 12 when it does not receive the data stream sent by the data bus, and write the data push instruction into the data allocation module 11.

[0036] It should be noted that when the accumulated cache pointers in the pointer processing module 12 are relatively idle, the pointer processing module 12 sends a data push instruction to the data allocation module 11. Otherwise, it means that the stream ID of the data stream is not configured or there is no data to be pushed. When the accumulated count of stream IDs is a preset number, such as stream IDs from 0 to 1023, one cycle is completed, representing a large cycle of one data push instruction.

[0037] After receiving the data push instruction, the data allocation module 11 pushes the shared cache write operation module 14 to output the cache pointer that has not been fully written with valid data. Then, it sends an instruction to the pointer processing module 12 to output a valid pointer. Since it is in a scenario where no data stream is received from the data bus, the valid pointer output by the pointer processing module 12 is a null pointer, and the null pointer can be written into the pointer processing module 12.

[0038] In this embodiment, when the data allocation module 11 does not receive the data stream sent by the data bus, it receives the data push instruction sent by the pointer processing module 12. The data push instruction is used to make the shared cache write operation module 14 output the cache pointer that has not been fully written with valid data. Then, it sends an instruction to the pointer processing module 12 to output a valid pointer, obtains a null pointer, and writes the null pointer to the pointer processing module 12. The null pointer can drive the update of the pointer in the line to promote the dynamic update of the line.

[0039] In one embodiment, the pointer processing module 12 in the device includes: a pointer reading unit 121, a null pointer unit 122, a written pointer processing unit 123, and a pointer to be recycled unit 124.

[0040] The pointer reading unit 121 is used to read pointers from the pointer pool 131 set in the cache module 13.

[0041] The pointers in pointer reading unit 121 are also in a first-in-first-out (FIFO) queue, which can be represented as a pointer FIFO. When the number of pointers in pointer reading unit 121 is less than the preset number of pointers, a new pointer is read from the pointer pool 131 set in the cache module 13, and the read pointer value in the pointer pool 131 is written to pointer reading unit 121. When new data in the data stream read by data allocation module 11 needs to be written to the shared cache (RAM 15), it will send an instruction to output a valid pointer to pointer reading unit 121. To retrieve a valid pointer, after a large cycle of data push indication is completed, during the idle time of the data bus, a pointer can also be read from pointer reading unit 121. This read pointer is a null pointer, which is recorded in the null pointer unit. The preset number of pointers can be 32.

[0042] After a preset number of null pointer fetch operations from pointer read unit 121, an update pointer indication is generated for pointer pool 131, causing the write pointer value in pointer pool 131 to be incremented by the preset number of fetch operations. In fact, fetching a null pointer is used to drive the update of pointer pool 131. Even if no data is received from the data bus input, the update of the entire pointer pool 131 will still be driven by the null pointer fetch operation. The preset number of fetch operations can be 16.

[0043] Null pointer unit 122 is used to store the null pointer output by pointer reading unit 121.

[0044] After a large cycle of data push indication is completed, during the idle time of the data bus, the null pointer unit 122 reads the pointer in the pointer reading unit 121. To retrieve the null pointer, the null pointer is written to the null pointer unit 122.

[0045] The null pointer unit 122 reads out the null pointer and writes it into the pointer to be reclaimed unit 124 when no pointer is reclaimed in the entire line, so as to keep the pointer pool 131 continuously updated.

[0046] The written pointer processing unit 123 is used to determine the position of the valid data corresponding to the single cache pointer in RAM 15 according to the single cache pointer corresponding to the read request when a read request for reading valid data in RAM 15 is received, and read the valid data cached in RAM 15.

[0047] The write pointer processing unit 123 receives read requests to read valid data from RAM 15. Each read request requests to read the corresponding valid data from RAM 15 and write the read valid data to the application module that issued the read request. The application module, such as Double Data Rate SDRAM (DDR), includes multiple write requests corresponding to multiple read requests and write data shifting. The multiple write requests form a first-in-first-out (FIFO) queue, which can be represented as a write request FIFO. Write data shifting includes shifting the valid data read by the read request to its current position (i.e., a small buffer for write data shifting), such as writing the read valid data to the small buffer of the application processing module for data shifting, and inputting the write requests from the application module that generated the read requests to read valid data from RAM into the write request FIFO of the application module in a FIFO queue. Once the multiple read requests corresponding to DDR have finished reading the valid data from RAM, no further reading of RAM is required. The application module is a functional module external to this device, and its specific functionality is not limited.

[0048] Specifically, based on the requirements of the DDR write interface (or other user interfaces), the DDR write request is determined. Based on the DDR write request, a read request signal for reading RAM is generated. Based on the read request signal, a read request is generated. Based on the read request, the target data that the DDR wants to obtain is determined. Based on the target data, the valid data cached in RAM15 is read through the cache pointer of the target data corresponding to the written pointer processing unit 123. The read valid data is used as the target data. The valid data cached in RAM15 can be read and the corresponding cache pointer can be reclaimed according to the single cache pointer corresponding to the read request.

[0049] And / or, when a read request to read valid data in RAM15 is received, the system determines the location of the valid data corresponding to the pointer group of the multiple cache pointers corresponding to the read request in RAM15, and reads the valid data cached in RAM15.

[0050] When a read request to read valid data in RAM15 is received, read requests can be accumulated to obtain multiple corresponding cache pointers to form a pointer group. Based on the pointer group, the valid data cached in RAM15 corresponding to the pointer group is read and the cache pointers in the pointer group are reclaimed.

[0051] The written pointer processing unit 123 is also used to receive cache pointers sent by the shared cache write operation module 14, and to send a data push instruction to the data allocation module 11 when the accumulated cache pointers reach a set number. This enables read requests to obtain the cache pointer corresponding to the target data, and through the data push instruction, forces the output pointer or pointer group to prevent the situation where a read request is received but the relevant cache pointer cannot be obtained to read the corresponding target data.

[0052] The shared cache write operation module 14 receives the cache pointer after writing valid data into RAM 15, and accumulates the cache pointers according to the first-in-first-out queue, which is represented as pointer accumulation FIFO.

[0053] When the accumulated cache pointers reach the set number, if the pointer accumulation FIFO is not full, that is, the set number has not reached the number of pointers in the pointer accumulation FIFO, and at the same time, the data in the current data stream has been written and no new data has arrived, a data push instruction is sent to the data allocation module 11.

[0054] For example, such as Figure 2 The diagram shown illustrates how to accumulate four pointers to form a pointer group. Figure 2 The pointer in the text refers to the cache pointer, that is, the write interface of the DDR connected to the device is 256 bytes. When a read request is initiated, the shared cache write operation module 14 outputs the cache pointer to the written pointer processing unit 123. Based on the stream ID, each stream is marked with a cache pointer number from 0 to 3 to facilitate the accumulation of cache pointers. The cache pointer number 0, 1, and 2, the DDR write address, and the eop position eop_phase are temporarily stored. The eop position eop_phase is obtained based on the specific eop information of the four pointers. When the cache pointer number is 3, the pointer group is written into the pointer accumulation FIFO in the written pointer processing unit 123 for processing, and the DDR write address is incremented by 1. The pointer group may be a complete pointer group or an incomplete pointer group. When the input cache pointer is an incomplete pointer or a null pointer, the pointer group is also written into the pointer accumulation FIFO for processing, and the DDR write address is incremented by 1. The read cache state count cnt_state is counted from 0 to 15, where cnt_state represents the current state value. The state count corresponding to one cache pointer is 4.

[0055] When cnt_state equals 0, if the pointer accumulation FIFO is not empty and the DDR write request FIFO is not full, when cache pointer 0 is valid and not a null pointer, cnt_state changes from 0 to 1, and then increments by 1 every time it is pressed until it reaches 4. When cache pointer 0 is invalid or a null pointer, cnt_state changes directly from 0 to 4. A pointer can be pressed for 4 times.

[0056] When cnt_state equals 0, if the pointer accumulation FIFO is empty or the DDR write request FIFO is full, cnt_state will remain unchanged at 0, and there is no need to generate a read request to read valid data in RAM15 based on the write request.

[0057] When cnt_state equals 4, if cache pointer 1 is valid and not null, cnt_state changes from 4 to 5, and then increments by 1 every time it is pressed until it reaches 8. If cache pointer 1 is invalid or null, cnt_state changes directly from 4 to 8.

[0058] When cnt_state equals 8, if cache pointer 2 is valid and not null, cnt_state changes from 8 to 9, and then increments by 1 for each subsequent clock cycle until it reaches 12. If cache pointer 2 is invalid or null, cnt_state changes directly from 8 to 12.

[0059] When cnt_state equals 12, if cache pointer 3 is valid and not null, cnt_state changes from 12 to 13, and is incremented by 1 every time it reaches 0. Then, a pointer group of the cache pointer's pointer accumulation FIFO is read out. If cache pointer 3 is invalid or null, cnt_state changes directly from 12 to 0, and a pointer group of the cache pointer's pointer accumulation FIFO is also read out.

[0060] The pointer value serves as the high-order bit of the shared cache read address, and the two lower bits (0~3) of cnt_state serve as the low-order bit of the shared cache read address. Valid data is read from the shared cache, which is RAM15. The number of bytes in the pointer is determined by the width of the data bus and is not specifically limited.

[0061] The pointer to be reclaimed unit 124 is used to receive the null pointer and the pointer to be reclaimed in the null pointer unit 122 and send them to the pointer pool 131 in the cache module 13.

[0062] In the pointer to be reclaimed unit 124, each pointer input to the pointer to be reclaimed unit 124 is a first-in-first-out queue, which can be represented as a pointer to be reclaimed FIFO, and a counter is used to accumulate the count of the input pointers to be reclaimed. When the null pointer unit 122 sends a null pointer, the null pointer is input to the pointer to be reclaimed unit 124 as a pointer to be reclaimed. The written pointer processing unit 123 also sends the cached pointer after reading valid data to the pointer to be reclaimed unit 124 as a pointer to be reclaimed for reclaiming.

[0063] As an example, `cnt_state` represents the counter's count for the pointer group corresponding to the read request. When accumulating pointer groups of four cached pointers, if `cnt_state` equals 0, and the pointer accumulation FIFO in the written pointer processing unit 123 is not empty, it means that a cached pointer exists in the pointer accumulation FIFO, and the DDR write request FIFO is not full. If cached pointer 0 is valid and not a null pointer, cached pointer 0 is reclaimed and written to the pointer FIFO to be reclaimed. If `cnt_state` equals 4, and cached pointer 1 is valid and not a null pointer, cached pointer 1 is reclaimed and written to the pointer FIFO to be reclaimed. If `cnt_state` equals 8, and cached pointer 2 is valid and not a null pointer, the cached pointer is reclaimed and written to the pointer FIFO to be reclaimed. Pointer 2 is recycled and written to the pointer FIFO to be recycled; when cnt_state equals 12, if cached pointer 3 is valid and not null, cached pointer 3 is recycled and written to the pointer FIFO to be recycled; if there is no cached pointer that needs to be recycled and written to the pointer FIFO to be recycled, it is checked whether there is a null pointer in the null pointer FIFO to be written to the pointer FIFO to be recycled; when a pointer needs to be written to pointer read unit 121, and the pointer FIFO to be recycled is not null, the pointer FIFO to be recycled is read. If the read pointer is outside the pointer read / write pointer in pointer pool 131, it is written to pointer read unit 121, otherwise it is recycled to pointer pool 131 (the pointer written to pointer read unit 121 is r_point in the pointer library).

[0064] In this embodiment, each functional unit in the pointer processing module 12 is described in detail. The specific process of receiving valid pointers and processing cached pointers when writing to and reading from the RAM 15 cache memory is described. The pointer processing module 12 can read pointers from the pointer pool 131 set by the cache module 13 through the pointer reading unit 121, obtain read requests for reading valid data from RAM 15 through the written pointer processing unit 123, determine the cached pointer corresponding to the read request based on the read request, and determine the address of the valid data corresponding to the cached pointer in RAM 15, thereby obtaining the valid data. Then, the written pointer processing unit 123 sends the cached pointer after reading the valid data from RAM 15 as a pointer to be reclaimed to the pointer to be reclaimed unit 124, so that the pointer to be reclaimed is sent to the pointer pool 131, realizing the dynamic updating of pointers in the pointer pool 131.

[0065] In one embodiment, the shared cache write operation module 14 in the device includes: a first write unit, a first determination unit, a second write unit, and a second determination unit.

[0066] The first write unit is used to write data to the shared cache write operation module 14 when the data in the data stream sent by the data allocation module 11 is valid data and the number of bits of the valid data is equal to the write bit width of the cache memory in RAM 15. Here, a valid pointer corresponds to the address of a first preset number of write bits.

[0067] When the first write unit in the shared cache write operation module 14 receives valid data from the data stream sent by the data allocation module 11, that is, every byte of data in the data stream is valid, then it is valid data. Since the valid data is obtained by the data allocation module 11 through the data bus, the number of bits of the valid data is equal to the write bit width of the cache memory in RAM 15. The shared cache write operation module 14 can directly write the valid data into the cache memory in RAM 15.

[0068] A valid pointer includes a first preset number of write bit width addresses, meaning that the write bit width in the shared RAM 15 is consistent with the bit width corresponding to the data bus. Each byte of a valid pointer can correspond to a preset number of write bit widths. For example, if the write bit width in the shared RAM 15 is 16 bytes and the address is 2k 64-byte addresses, then one pointer contains four 16-byte write addresses. The shared cache write operation module 14 can also accumulate and calculate each write bit width and pointer count using a counter.

[0069] The shared cache write operation module 14 can obtain a valid pointer from the pointer reading unit 121 of the pointer processing module 12 in order to write valid data.

[0070] The first determining unit is used to determine the valid pointer including the storage address of the valid data as a cache pointer after the valid data is written to the address of the first preset number of write bits, and send the cache pointer to the pointer processing module 12.

[0071] When valid data is written to an address with a first preset write width (i.e., when valid data is written to the cache memory in RAM 15), a corresponding cache pointer is obtained. This cache pointer is also a complete pointer. The first determining unit sends the cache pointer to the pointer processing module 12. Specifically, it sends it to the written pointer processing unit 123 within the pointer processing module 12.

[0072] And / or, the second write unit is used to determine the remaining number of bits of the write width based on the difference between the number of bits of the valid data and the write width when the data in the data stream sent by the data allocation module 11 includes invalid data and the number of bits of the valid data in the data is less than the write width of the cache memory in RAM 15, and write the valid data of the next data in the received data stream to the address of the remaining number of bits of the write width.

[0073] When the second write unit in the shared cache write operation module 14 receives data from the data allocation module 11 containing invalid data, and the number of bits of valid data in the data is less than the write width of the cache memory in RAM 15, it writes the valid data (excluding the invalid data) from the data stream into RAM 15. Specifically, based on the difference between the number of bits of valid data and the write width, the remaining bits of the write width are determined. Since the number of bits of valid data is less than the write width, after writing the valid data to the address corresponding to the write width according to the number of bits of valid data, the write width still includes the remaining bits. The next data from the received data stream is then written to the address of the remaining bits of the write width. The next data includes the data following the current data stream input by the data allocation module 11.

[0074] The second determining unit is used to obtain a valid pointer to the storage address containing valid data when the address of the write width after writing the remaining bits reaches a first preset number, and determine it as a cache pointer, and send the cache pointer to the pointer processing module 12.

[0075] It should be understood that because the valid pointer has remaining bits, even if the remaining bits have been padded with valid data, the valid pointer will still be sent to the pointer processing module 12 as an incomplete pointer, but also as a cached pointer.

[0076] When the address of the write width after writing the remaining bits reaches the first preset number, which is the preset number of write width addresses included in a cache pointer, the addresses corresponding to all write widths in the cache pointer are filled with valid data. Then, the valid pointer containing only the storage address of valid data is determined as the cache pointer and sent to the pointer processing module 12, specifically to the written pointer processing unit 123 in the pointer processing module 12.

[0077] In this embodiment, the first write unit, the first determination unit, the second write unit, and the second determination unit in the shared cache write operation module 14 can process the data input by the data allocation module 11 received by the shared cache write operation module 14, compare the number of bits of valid data in the data with the write bit width of the cache memory in the RAM 15 to be written, write the valid data into the RAM 15 according to the write bit width, and send the storage address pointing to the valid data written into the RAM 15 as a cache pointer to the pointer processing module 12. Since there is no need to record invalid data in the data stream, the cache memory space in the RAM 15 can be saved, and there is no need to allocate memory space in the RAM 15 for each data stream, which can also improve the efficiency of cached data.

[0078] In one embodiment, the second write unit in the shared cache write operation module 14 is specifically used to: when the invalid data included in the data of the data allocation module 11 is invalid data in the packet end flag data, determine the difference between the number of bits of valid data in the packet end flag data and the write bit width of the cache memory in RAM 15; and determine the remaining number of bits of the write bit width based on the difference, so as to fill the packet start flag data of the next data corresponding to the data stream into the address of the remaining number of bits.

[0079] Specifically, when the invalid data included in the data allocation module 11 is invalid data in the packet end flag data, the second writing unit determines the difference between the number of valid data in the packet end flag data and the write bit width of the cache memory in RAM 15, and can also fill the packet start flag data of the next data corresponding to the data stream into the address of the remaining bits.

[0080] As an example, after the shared cache write operation module 14 finishes writing the end-of-packet (eop) data, the start-of-packet (sop) data for the next packet is normally written to the cache (RAM 15) following the eop data. However, if there is invalid data in the eop data, there may be residual data. When there is residual data, the next eop data requires an extra clock cycle to process the writing of the residual data. At this time, the data allocation module 11 stops reading for one clock cycle, which is indicated by data_rden_disable. It is possible that no data from the data stream will come for a long time after an eop data. What is read from the data allocation module 11 may be a data push indicator, which pushes the eop data. This will cause the cache pointer corresponding to the previously written data to continue to be processed and reclaimed. The soop data that comes from the data stream after the data push indicator will not be written to the cache following the previous eop data. Instead, a new valid pointer will be retrieved and written to a new address.

[0081] Specifically, based on the stream ID, a count cnt16 (0~15) is generated, representing the number of bits of data write width in each data stream. 16 counts represent one write width, i.e., the number of bytes. A count cnt4 (0~3) represents the buffer pointer; one count represents one write width, and four counts represent one buffer pointer. The number of bytes of residual data is represented as byte_remainn (0~16). A new 16-byte block of valid data has no valid pointer. cnt16 remains unchanged at 0, cnt4 is incremented by 1, and byte_remainn remains unchanged at 0. A valid pointer is directly retrieved from the pointer processing module 12, and this valid pointer is used as the high-order address, with cnt4 as the low-order address, to write the 16-byte data into the shared buffer. When 16 bytes of valid data (cnt4 equals 3) are written, the pointer is output to the written pointer processing unit 123 as a complete pointer among the reclaimed buffer pointers.

[0082] When the first EOP data arrives, if the number of valid data bytes in the EOP data is equal to 16, cnt16 remains unchanged at 0, cnt4 is incremented by 1, and byte_remainn remains unchanged at 0 (if cnt4 is exactly 3, a complete pointer is output). If the number of valid data bytes in the EOP data is less than 16, cnt16 is added to the number of valid data bytes, cnt4 remains unchanged, and byte_remainn remains unchanged at 0 (the valid pointer has not been used up, so the pointer is not output). When the next SOP data arrives, cnt16 remains unchanged, cnt4 is incremented by 1 (if cnt is equal to 3 at this time, a complete pointer is output), and byte_remainn will be equal to the value of cnt16 from the previous time, representing the number of remaining data bytes.

[0083] When a subsequent EOP data arrives, if the sum of the remaining data bytes and the valid data bytes of that EOP data is less than 16, then cnt16 is added to the sum of the remaining data bytes and the valid data bytes, cnt4 remains unchanged, and the remaining data byte count is cleared to zero. This means the remaining data bytes and the valid data bytes of that EOP data are written to the buffer (address is the high bit of the valid pointer, and cnt4 is the low bit). No pointer will be output if the entire 64 bytes are not written in this cycle. If the sum of the remaining data bytes and the valid data bytes of that EOP data is exactly equal to 16, then cnt16 is set to 0, cnt4 is incremented by 1 (if cnt equals 3, a complete pointer will be output), and the remaining data byte count is cleared to zero. If the sum of the remaining data bytes and the valid data bytes of that EOP data is greater than 16, then cnt16 is set to 0, cnt4 is incremented by 1 (if cnt equals 3, a complete pointer will be output), the remaining data byte count is added to the valid data byte count of this cycle minus 16, and the bytes exceeding 16 require a pause in the cycle to generate a data_rden_disable to handle them. When data_rden_disable is valid, the excess residual portion (1~15 bytes) is processed. The number of residual bytes is added to cnt16, cnt4 remains unchanged, and the number of residual bytes is set to 0.

[0084] When the eop data is written, that is, when all the remaining bytes of data are written, and no data comes after the data stream, the data push instruction for the data stream may be read from the data allocation module 11. In this case, the data push instruction will directly output the last unused valid pointer to the written pointer processing unit 123 in the pointer processing module 12 as an incomplete pointer (indicating that the bytes after eop in the 64 bytes are invalid). Alternatively, if a valid pointer was just used up last time, the unused valid pointer will be output as a null pointer, cnt16 remains unchanged, cnt4 remains unchanged, and the number of bytes of remaining data remains 0. When the soop data of the data stream comes later, a new valid pointer will be retrieved and written to the buffer memory, cnt16 remains unchanged, cnt4 is incremented by 1, and the number of bytes of remaining data remains 0. After the valid pointer is used up (cnt4 equals 3), an incomplete pointer will be output (indicating that the bytes before soop in the 64 bytes are invalid).

[0085] In this embodiment, when invalid data is included in the received data stream, the remaining bits of the write width are determined based on the write width of RAM15 and the number of bits used as the packet end marker data in the valid data. The packet start marker data of the next data in the data stream is then inserted into the address corresponding to the remaining bits. This process removes invalid data, saves space in the RAM15 cache, and improves the utilization of the shared cache space.

[0086] In one embodiment, the shared cache write operation module 14 in the device is further configured to fill the remaining data after the address of the remaining bits with packet start flag data, and determine it as residual data; when no other data is received from the data stream of the data allocation module 11 within a preset time period, stop reading the data allocation module 11; and obtain a valid pointer from the pointer processing module 12 and write the residual data to the address pointed to by the valid pointer.

[0087] Specifically, the shared cache write operation module 14 inserts the packet start flag data of the next data in the data stream into the address of the remaining bits. Since all bytes of the packet start flag data can be valid, there will be remaining data, which is treated as residual data. Furthermore, if no other data from the data stream is received from the data allocation module 11 within a preset time, reading from the data allocation module 11 stops. Instead of obtaining a valid pointer through the data allocation module 11, a valid pointer is directly obtained from the pointer processing module 12, and the residual data is written to the address pointed to by the valid pointer. It should be understood that if the shared cache write operation module 14 already has a valid pointer obtained from the data allocation module 11, then there is no need to directly obtain a valid pointer from the pointer processing module 12.

[0088] As an example, in a packet containing end-of-packet (eop) data, not all 16 bytes may be valid. Therefore, only the first few bytes of that eop data can be written to a certain storage address in the cache. As a result, the 16 bytes of valid data received later from this data stream will have residual data, which will be written to the storage address corresponding to the next cache pointer in the cache.

[0089] In this embodiment, the remaining data after the address of the remaining bits is determined as residual data by padding the packet start flag data. When the data allocation module 11 stops reading, a valid pointer is obtained from the pointer processing module 12, and the residual data is written to the address pointed to by the valid pointer. This allows for the allocation of storage addresses for all data in the data stream, preventing uncached data and improving the rigor of data caching. Directly obtaining a valid pointer from the pointer processing module 12 also improves the efficiency of storing valid data.

[0090] In one embodiment, the cache module 13 in the device is specifically used to store the shared address of RAM 15 through the pointer pool 131 set in the cache module 13. When the number of pointers in the pointer processing module 12 is less than a second preset number, the read pointers in the pointer pool 131 are written into the pointer processing module 12. Furthermore, according to the preset difference between the read pointers and the write pointers, the pointers to be recycled in the pointer processing module 12 whose values ​​are within the preset difference are written into the cache module 13.

[0091] The pointer pool 131 set in the cache module 13 can store the shared address in RAM 15 used for shared cache memory. When the data allocation module 11 obtains a valid pointer from the pointer processing module 12, if the number of pointers in the pointer processing module 12 is less than the second preset number, the pointer processing module 12 obtains a pointer from the pointer pool 131 and writes the read pointer in the pointer pool 131 into the pointer processing module 12.

[0092] The pointer pool 131 set in the cache module 13 includes read pointers and write pointers. The read pointer is the pointer read from the pointer pool 131, and the write pointer is the pointer written to the pointer pool 131. According to the preset difference between the read pointer and the write pointer, the pointers to be recycled in the pointer processing module 12 whose values ​​are within the preset difference are written to the cache module 13.

[0093] Specifically, as an example, the pointer pool 131 set in the cache module 13 contains 2k pointers, representing 2k 64-byte addresses (8k 16-byte addresses, without specific limitation) of shared RAM 15. Initially, the write pointer in the pointer pool 131 is 2k-1, and the read pointer is 0. The difference between the read and write pointers indicates that all 2k pointers are in the pointer pool 131 and not yet used. When the number of pointers in the pointer reading unit 121 of the pointer processing module 12 is less than 32, a new pointer is read from the pointer pool 131. The pointer pool 131 writes the read pointer into the pointer FIFO corresponding to the pointer reading unit 121 and increments the value of the read pointer, indicating that a new pointer is being retrieved from the pointer pool 131, ensuring that the number of pointers in the pointer FIFO is not less than 32. When the write pointer in pointer pool 131 equals the read pointer, it means that the pointers in pointer pool 131 are empty (normally, this should not happen, and a certain margin should be left to ensure that there are enough pointers). When an update pointer instruction is received, the write pointer value will be incremented by 16 (set as needed). So even if the read pointer value in pointer pool 131 remains unchanged, the difference between the read and write pointers will increase by 16. If the value of the pointer in the pointer to be recycled is within the range of the write pointer value and the read pointer value, it will be recycled back to pointer pool 131. Otherwise, it will be directly recycled back to pointer reading unit 121 for reuse.

[0094] In this embodiment, a pointer pool 131 is set in the cache unit to store the shared address of RAM 15. Based on the difference between the read pointer and the write pointer in the pointer pool 131, a pointer to be reclaimed is obtained, ensuring dynamic updates to the pointer pool 131. This means that the pointers used in the circuit are also constantly updated. The pointers corresponding to the shared cache (RAM 15) are automatically retrieved and reclaimed in the pointer pool 131, and data can be automatically written to any address in the shared cache. This also prevents errors in the pointers used in the circuit, which could lead to data write / read failures, increasing the robustness of the circuit. For example, if the cache pointer for reading valid data malfunctions due to factors such as radiation or temperature, after reclaiming the cache pointer and obtaining the pointer to be reclaimed, the data in the data stream can be recovered and read normally.

[0095] Figure 3 This is a flowchart illustrating a chip shared cache method according to an embodiment of this application, as shown below. Figure 3 As shown, the method includes the following steps: S301, the data in the data stream transmitted by the data bus is obtained through the data allocation module 11. The data bus is used to poll the data streams of multiple ports.

[0096] S302, for each data stream, the data allocation module 11 sends an instruction to the pointer processing module 12 to output a valid pointer, wherein the pointer processing module 12 is used to read a new pointer from the pointer pool 131 set in the cache module 13 corresponding to RAM 15.

[0097] S303, the data is input to the shared cache write operation module 14 through the data allocation module 11, and the valid pointer output by the pointer processing module 12 is obtained through the shared cache write operation module 14. The valid data is written to RAM 15 according to the number of bits of valid data in the data and the write bit width of the cache memory in RAM 15, and the cache pointer of the valid data is determined.

[0098] S304, input the cache pointer into the pointer processing module 12. The cache pointer includes the address where valid data is stored.

[0099] S305, when the pointer processing module 12 receives a read request to read data in RAM 15, it reads the valid data in RAM 15 according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data as the pointer to be reclaimed into the cache module 13 to share the cache memory of RAM 15.

[0100] The specific processes from S301 to S305 have been described in detail in the above embodiments and will not be repeated here.

[0101] In summary, as Figure 4The diagram shows a schematic of a shared cache method for a chip. When the data allocation module 11 obtains data from multiple ports (e.g., port 1, port 2... port n) via the data bus, it sends an instruction to output a valid pointer to the pointer reading unit 121 of the pointer processing module 12, and sends the data to the shared cache write operation module 14. The shared cache write operation module 14 obtains the output valid pointer sent by the pointer reading unit 121, and writes the valid data into RAM 15 according to the number of bits of valid data and the write width of the cache memory in RAM 15. It can also obtain residual data, directly read the valid pointer from the pointer reading unit 121, and write the residual data into the valid pointer. Finally, the complete pointer and / or incomplete pointer including the valid data address are used as cache pointers and input to the written pointer processing unit 123 in the pointer processing module 12. The written pointer processing unit 123 can process the obtained cache pointers. The pointer is accumulated, and read requests for valid data written in RAM15 are received from other application modules such as DDR. Based on the cache pointer corresponding to the read request, the storage location of the valid data of the cache pointer in RAM15 is located, and then the valid data corresponding to the read request is read and moved to DDR. The written pointer processing unit 123 sends the cache pointer after reading the valid data as a pointer to be recycled to the pointer to be recycled unit 124. The pointer to be recycled unit 124 can accumulate pointers to be recycled, and can also obtain null pointers from the null pointer unit 122 in the pointer processing module 12 and accumulate null pointers as pointers to be recycled. When the pointers in the pointer pool 131 set in the cache module 13 have not reached the preset number, the pointers to be recycled in the pointer to be recycled unit 124 that are within the preset difference between the read pointers and write pointers in the pointer pool 131 are sent to the pointer pool 131; otherwise, they are sent to the pointer reading unit 121. When the data allocation module 11 fails to acquire data from the data bus for an extended period, and the cached pointers accumulated in the written pointer processing unit 123 are not yet full, the written pointer processing unit 123 sends a data push instruction to the data allocation module 11. This process continues until one cycle of accumulation is completed, constituting one large push cycle. If the data allocation module 11 has not acquired data after completing one large push cycle, the valid pointer obtained from the pointer reading unit 121 of the pointer processing module 12 is a null pointer. This null pointer is written to the null pointer unit 122 and then sent to the pointer to be reclaimed unit 124. It should be understood that throughout the entire shared caching method, the data in each functional module and unit is cached based on a first-in-first-out (FIFO) queue; that is, each data item is a FIFO queue.

[0102] Using the technical solution of this application embodiment, the data allocation module 11 obtains data from the data stream transmitted by the data bus. For each data stream, it sends an instruction to the pointer processing module 12 to output a valid pointer. The pointer processing module 12 can read a new pointer from the pointer pool 131 set in the cache module 13 corresponding to RAM 15. Furthermore, the data allocation module 11 inputs the data from the data stream to the shared cache write operation module 14, and obtains the valid pointer output by the pointer processing module 12 through the shared cache write operation module 14. Based on the number of bits of valid data in the data and the write bit width of the cache memory in RAM 15, the valid data is written to RAM 15. This can eliminate invalid data and improve the cache space of RAM 15. The shared cache write operation module 14 can also determine the cache pointer of valid data and input the cache pointer to the pointer processing module 12. The cache pointer includes the address where the valid data is stored. When the pointer processing module 12 receives a read request to read data from RAM 15, it reads the valid data in RAM 15 according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data as a pointer to be reclaimed into the cache module 13 to share the cache memory of RAM 15. It is evident that invalid data in the data stream can be removed, and valid data can be written into RAM15, improving the utilization rate of the cache space in RAM15. Furthermore, the pointers in the pointer pool 131 are dynamically updated to prevent errors in the cache data of the entire line due to a problem with a pointer in the line. In addition, the valid data is dynamically written into RAM15 and the valid data cached in RAM15 is read from RAM15 so that multiple data streams can share RAM15. Compared with related technologies, the shared cache space occupied by the data stream can change automatically as needed, without the need to allocate a fixed cache space for the data stream, thus improving the utilization rate of the cache space in RAM15.

[0103] Based on the same technical concept, embodiments of this application also provide an electronic device for executing the above-described chip shared cache method. Figure 5 This is a schematic diagram of the structure of an electronic device to implement various embodiments of this application. The electronic device can vary significantly due to differences in configuration or performance, and may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540. The processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call a computer program stored in the memory 530 and executable on the processor 510 to perform the following steps: The data is obtained from the data stream transmitted by the data bus through the data allocation module 11. The data bus is used to poll the data streams of multiple ports.

[0104] For each data stream, the data allocation module 11 sends an instruction to the pointer processing module 12 to output a valid pointer. The pointer processing module 12 is used to read a new pointer from the pointer pool 131 set in the cache module 13 corresponding to RAM 15.

[0105] The data is input into the shared cache write operation module 14 through the data allocation module 11, and the valid pointer output by the pointer processing module 12 is obtained through the shared cache write operation module 14. The valid data is written into RAM 15 according to the number of bits of valid data in the data and the write bit width of the cache memory in RAM 15, and the cache pointer of the valid data is determined.

[0106] The cache pointer is input into the pointer processing module 12. The cache pointer includes the address where valid data is stored.

[0107] When the pointer processing module 12 receives a read request to read data in RAM 15, it reads the valid data in RAM 15 according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data as the pointer to be reclaimed into the pointer processing module 12 to share the cache memory of RAM 15.

[0108] Using the technical solution of this application embodiment, the data allocation module 11 obtains data from the data stream transmitted by the data bus. For each data stream, it sends an instruction to the pointer processing module 12 to output a valid pointer. The pointer processing module 12 can read a new pointer from the pointer pool 131 set in the cache module 13 corresponding to RAM 15. Furthermore, the data allocation module 11 inputs the data from the data stream to the shared cache write operation module 14, and obtains the valid pointer output by the pointer processing module 12 through the shared cache write operation module 14. Based on the number of bits of valid data in the data and the write bit width of the cache memory in RAM 15, the valid data is written to RAM 15. This can eliminate invalid data and improve the cache space of RAM 15. The shared cache write operation module 14 can also determine the cache pointer of valid data and input the cache pointer to the pointer processing module 12. The cache pointer includes the address where the valid data is stored. When the pointer processing module 12 receives a read request to read data from RAM 15, it reads the valid data in RAM 15 according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data as a pointer to be reclaimed into the cache module 13 to share the cache memory of RAM 15. It is evident that invalid data in the data stream can be removed, and valid data can be written into RAM15, improving the utilization rate of the cache space in RAM15. Furthermore, the pointers in the pointer pool 131 are dynamically updated to prevent errors in the cache data of the entire line due to a problem with a pointer in the line. In addition, the valid data is dynamically written into RAM15 and the valid data cached in RAM15 is read from RAM15 so that multiple data streams can share RAM15. Compared with related technologies, the shared cache space occupied by the data stream can change automatically as needed, without the need to allocate a fixed cache space for the data stream, thus improving the utilization rate of the cache space in RAM15.

[0109] The specific execution steps can be found in the various steps of the shared cache device embodiment of the chip described above, and can achieve the same technical effect. To avoid repetition, they will not be repeated here.

[0110] It should be noted that the electronic devices in the embodiments of this application include: servers, terminals, or other devices besides terminals.

[0111] The above electronic device structure does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or arrange them differently. For example, an input unit may include a Graphics Processing Unit (GPU) and a microphone, and a display unit may use a liquid crystal display (LCD), organic light-emitting diode (OLED), or other similar display panels. User input units include at least one of a touch panel and other input devices. A touch panel is also called a touchscreen. Other input devices may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be elaborated further here.

[0112] Memory can be used to store software programs and various data. Memory can primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area can store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, memory can include volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM).

[0113] The processor may include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly handles operations related to the operating system, user interface, and applications, while the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor.

[0114] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the shared cache method embodiment of the chip described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0115] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0116] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the shared cache method embodiment of the above chip, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0117] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0118] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0119] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0120] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A shared cache device for a chip, characterized in that, The device includes: a data allocation module, a pointer processing module, a cache module, a shared cache write operation module, and a random access memory (RAM); The data allocation module is used to receive data from the data stream sent by the data bus and send an instruction to the pointer processing module to output a valid pointer so as to write the data into the shared cache write operation module; wherein, the data allocation module is a first-in-first-out (FIFO) queue, and the pointer processing module is used to read pointers from the pointer pool set in the cache module corresponding to the RAM; The shared cache write operation module is used to receive the valid pointer output by the pointer processing module and the data sent by the data allocation module. Based on the number of bits of the valid data in the data and the write bit width of the cache memory in the RAM, the module writes the valid data into the RAM, determines the cache pointer corresponding to the valid data, and sends the cache pointer to the pointer processing module. The cache pointer includes the address where the valid data is stored. The pointer processing module is further configured to receive a read request to read the valid data in the RAM, read the valid data in the RAM according to the cache pointer corresponding to the read request, and input the cache pointer after reading the valid data as a pointer to be recycled into the pointer pool so that multiple data streams can share the RAM.

2. The apparatus according to claim 1, characterized in that, The data allocation module is further configured to: when it does not receive the data stream sent by the data bus, receive a data push instruction sent by the pointer processing module, the data push instruction being used to push the shared cache write operation module to output the cache pointer that has not been fully written with the valid data; and after receiving the data push instruction and pushing the shared cache write operation module to output the cache pointer that has not been fully written with the valid data, send an instruction to the pointer processing module to output the valid pointer, so that the pointer processing module receives a null pointer.

3. The apparatus according to claim 1, characterized in that, The pointer processing module includes: a pointer reading unit, a null pointer unit, a written pointer processing unit, and a pointer to be reclaimed unit; The pointer reading unit is used to read pointers from the pointer pool set in the cache module; The null pointer unit is used to store the null pointer output by the pointer reading unit; The written pointer processing unit is configured to, when receiving a read request to read the valid data in the RAM, determine the position of the valid data corresponding to the single cache pointer in the RAM according to the single cache pointer corresponding to the read request, and read the valid data cached in the RAM; And / or, when a read request to read the valid data in the RAM is received, the system determines the position of the valid data corresponding to the pointer group in the RAM according to the pointer group of the plurality of cache pointers corresponding to the read request, and reads the valid data cached in the RAM; it is also used to receive the cache pointer sent by the shared cache write operation module; The pointer unit to be reclaimed is used to receive the null pointer and the pointer to be reclaimed from the null pointer unit, and send them to the pointer pool in the cache module.

4. The apparatus according to claim 1, characterized in that, The shared cache write operation module includes: a first write unit, a first determination unit, a second write unit, and a second determination unit; The first writing unit is used to write the data into the shared cache write operation module when the data in the data stream sent by the data allocation module is valid data and the number of bits of the valid data is equal to the write bit width of the cache memory in the RAM, wherein one valid pointer corresponds to the address of the first preset number of write bits. The first determining unit is configured to, after the valid data is written to the address of the first preset number of write bits, determine the valid pointer including the storage address of the valid data as the cache pointer, and send the cache pointer to the pointer processing module; And / or, the second writing unit is configured to, when the data in the data stream sent by the data allocation module includes invalid data and the number of bits of the valid data in the data is less than the write bit width of the cache memory in the RAM, determine the remaining bits of the write bit width based on the difference between the number of bits of the valid data and the write bit width, and write the valid data of the next data of the received data stream to the address of the remaining bits of the write bit width; The second determining unit is used to obtain the valid pointer including the storage address of the valid data when the address of the write width after writing the remaining bits reaches the first preset number, and determine it as the cache pointer, and send the cache pointer to the pointer processing module.

5. The apparatus according to claim 4, characterized in that, The second writing unit is specifically used to: when the invalid data included in the data sent by the data allocation module is invalid data in the packet end flag data, determine the difference between the number of bits of the valid data in the packet end flag data and the write bit width of the cache memory in the RAM; Based on the difference, the remaining bits of the write width are determined, and the packet start flag data of the next data corresponding to the data stream is padded into the address of the remaining bits.

6. The apparatus according to claim 5, characterized in that, The shared cache write operation module is further configured to fill the remaining data after the address of the remaining bits with the packet start flag data, and determine it as residual data; when no other data of the data stream of the data allocation module is received within a preset time period, stop reading the data allocation module; and obtain the valid pointer from the pointer processing module and write the residual data to the address pointed to by the valid pointer.

7. The apparatus according to claim 1, characterized in that, The cache module is specifically used to store the shared address of the RAM through the pointer pool set in the cache module. When the number of pointers in the pointer processing module is less than the second preset number, the read pointer in the pointer pool is written into the pointer processing module. Furthermore, based on the preset difference between the read pointer and the write pointer, the pointers to be reclaimed in the pointer processing module whose values ​​are within the preset difference are written into the cache module.

8. A method for sharing a cache in a chip, characterized in that, The method includes: The data is obtained from the data stream transmitted by the data bus through the data allocation module. The data bus is used to poll the data stream of multiple ports. For each data stream, the data allocation module sends an instruction to the pointer processing module to output a valid pointer, wherein the pointer processing module is used to read a new pointer from the pointer pool set in the cache module corresponding to RAM; The data is input into the shared cache write operation module through the data allocation module, and the valid pointer output by the pointer processing module is obtained through the shared cache write operation module. The valid data is written into the RAM according to the number of bits of valid data in the data and the write bit width of the cache memory in the RAM, and the cache pointer of the valid data is determined. The cache pointer is input into the pointer processing module, and the cache pointer includes: the address where the valid data is stored; When the pointer processing module receives a read request to read the data in the RAM, it reads the valid data in the RAM according to the cache pointer corresponding to the read request, and inputs the cache pointer after reading the valid data as a pointer to be reclaimed into the cache module to share the cache memory of the RAM.

9. An electronic device, characterized in that, include: processor; as well as A memory configured to store computer-executable instructions, which are configured to be executed by the processor, including instructions for performing a shared cache method for the chip as described in claim 8.

10. A storage medium, characterized in that, The storage medium is used to store computer-executable instructions that cause a computer to perform the shared cache method of the chip as described in claim 8.

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