Wave control chip with data error correction function

Abstract

The invention provides a wave control chip with a data error correction function, which belongs to the field of digital chip circuit design and comprises an SPI (Serial Peripheral Interface) analysis module, an RS (Reed-Solomon) decoder, a frame header cache register, a frame data cache, an MUX (Multiplexer) selector, a memory and an RS encoder. Original data is obtained after decoding of the RS decoder, frame headers of the original data are stored in the frame header cache register, if address codes of the frame headers are matched, the frame data are stored in the frame data buffer, and the MUX selector selects one type of data in the frame data buffer and outputs the data to the memory; after a sending instruction is received, wave position data are output according to an agreed sending logic, and telemetering data are encoded through an RS encoder and then output; and an ASIC integrated design is adopted, and compared with a traditional FPGA structure or a discrete device, the power consumption and the area of the circuit are remarkably optimized, and a high-integration and multifunctional integrated architecture design is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital chip circuit design, and particularly relates to a wave control chip with a data error correction function. BACKGROUND

[0002] In a radar wave control communication system, efficient transmission, processing and distribution of data are the key to ensuring stable operation of the communication system. Traditional radar wave control communication systems often face problems such as low data processing efficiency, poor anti-interference ability, poor flexibility and insufficient system reliability when processing multiple types of data packets. Especially in scenarios where continuous wave bit data, switch, telemetry data and other types of data need to be processed, how to realize efficient data analysis, error correction, distribution and backhaul functions while ensuring the anti-interference ability of the system and the real-time performance of data transmission has become a technical problem to be solved.

[0003] In the prior art, a general-purpose processor or a field-programmable gate array (FPGA) is usually used in a radar remote communication system to realize the functions of data receiving, analysis and distribution. However, the processing speed and real-time performance of the general-purpose chip are difficult to meet the high requirements of wave control communication, and although the FPGA has high flexibility, it may face problems such as resource waste, high cost, large size / weight, high power consumption and the like in specific application scenarios.

[0004] Figure 1The traditional general-purpose FPGA chip internal structure schematic diagram, the traditional general-purpose FPGA uses a programming method to realize wave control output, mainly including: input / output block (Input / Output Block, IOB) is responsible for data exchange with external devices; configurable logic block (Configurable Logic Block, CLB) is the core part of FPGA, which is composed of multiple logic units, and each logic unit can realize basic logic gate circuits (such as AND gate, OR gate, NOT gate, etc.). By combining these logic gates, complex logic functions can be realized. Block memory (Block RAM, BRAM) is used to store data and support fast read / write operations. BRAM can be configured as a normal memory or a dual-port memory to enhance data processing capability. CLB (configurable logic block) is the core part of FPGA, which is composed of multiple logic units, and each logic unit can realize basic logic gate circuits (such as AND gate, OR gate, NOT gate, etc.); BRAM (block memory) is used to store data and support fast read / write operations. BRAM can be configured as a normal memory or a dual-port memory to enhance data processing capability. Digital clock manager (Digital Clock Manager, DCM) is used to generate and manage clock signals, provide multiple clock outputs, and ensure that each part of the chip runs synchronously. Usually, the weight, volume and power consumption requirements of the satellite system to the chip are high, however, FPGA is a general-purpose logic resource, its working principle is different from that of ASIC chip, in most application scenarios, the resource utilization rate of FPGA is less than 50%, and the power consumption is large, the power consumption of general-purpose FPGA is 30W-150W, and the chip area is large, usually ≥40mm*40mm.

[0005] In addition, the existing solution has the problem of insufficient robustness of the code system burned by programming when processing indefinite length code word input, which seriously affects the performance and reliability of the remote communication system. Therefore, an efficient, flexible and reliable application specific integrated circuit (application specific integrated circuit, ASIC) solution is needed to meet the complex and diverse data processing requirements in the radar wave control communication system. SUMMARY

[0006] The technical problem to be solved by the present application is how to solve the problems of low integration, low reliability, high cost / power consumption, large volume / weight of the existing digital beam control circuit.

[0007] The application solves the above technical problems through the following technical scheme: a wave control chip with a data error correction function, comprising an SPI analysis module, an RS decoder, a frame header cache register, a frame data cache, a MUX selector, a memory, and an RS encoder, wherein the input data of the indefinite length code word is transmitted into the RS decoder through the SPI analysis module, the original data is obtained after decoding by the RS decoder, the frame header of the original data is stored in the frame header cache register, if the address code of the frame header matches, the frame data is stored in the frame data cache, the MUX selector selects a type of data in the frame data cache and outputs it to the memory, and the wave bit data is output according to the agreed sending logic after receiving the sending instruction, and the telemetry data is output after being encoded by the RS encoder.

[0008] Beneficial effects: the application proposes an indefinite length frame format architecture, which processes the frame header and frame data separately, is compatible with data structures of any frame length, effectively solves the problems such as insufficient robustness of traditional wave control circuits, adopts ASIC integrated design, and significantly optimizes the circuit power consumption and area compared with the traditional FPGA structure or discrete devices, the volume is reduced by more than 60%, the power consumption is reduced by more than 70%, and the architecture design of high integration and multifunctional integration is realized. The application is suitable for various high-integration low-cost digital beam control transceiver circuits.

[0009] Preferably, the RS decoder detects and corrects errors that may occur in the transmission process through redundant information, and the data input can correct 3 symbols every 15 symbols, and only when the parsing check is passed, the data is transmitted to the next stage, otherwise the frame is discarded.

[0010] Beneficial effects: the wave control chip design of the application has strong robustness and fault tolerance, in the data receiving process, if the input condition is not met at any time, the chip can automatically discard the frame as invalid, and the subsequent data reception will not be affected.

[0011] Preferably, the RS decoder comprises a syndrome solver module, a key equation solver module, an error pattern search module, an error correction output module and a shift register, the input data R(x) enters the syndrome solver module to obtain a syndrome, and the input data R(x) is saved in the shift register, the syndrome enters the key equation solver module, the BM iterative algorithm is used to calculate the error position polynomial sigma(x) and the error value polynomial omega(x), the root value of the error position polynomial sigma(x) is solved by using the money search, the error position number is obtained, the error position is determined, the error value is calculated according to the error position number and the error value polynomial omega(x), the error value and the error position are input into the error pattern search module to obtain an error pattern E(x), the error correction output module reads the input data R(x) in the shift register, corrects the input data R(x) according to the error pattern E(x), and outputs the code word.

[0012] The correction subscripts S1-S6 of 6 symbols are preferably:

[0013]

[0014] wherein j=m0, m0+1,..., m0+2t-1; Y i is the received symbol value, x i is the RS codebook original trail, m0 is 1, and 2t represents the error correction capability.

[0015] The error location polynomial is preferably: σ(x)=1+σ1x+σ2x 2 +σ3x 3 The process of solving the root value of the error location polynomial σ(x) by using the money search includes:

[0016] Step 1: Starting from the first position, i=n-1=14, corresponding to α 14 ;

[0017] Step 2: For each position i, calculate x=α -i , and substitute σ(x): σ(α -i )=1+σ1x+σ2(α -i ) 2 +σ3(α -i ) 3 If σ(α -i )=0, then the position i is wrong, that is, the received symbol is wrong at the i position;

[0018] Step 3: Repeat step 2 until all i=14 to i=0 are traversed.

[0019] The corrected symbol is:

[0020] The error value Y i is:

[0021] wherein x i is the error position, and σ odd represents the odd term of the error location polynomial σ(x).

[0022] The data type stored in the frame data buffer preferably includes telemetry frames, remote signaling frames, data frames, response frames, check frames, synchronization frames, heartbeat frames, control frames, and time mark frames.

[0023] Beneficial effects: the wave control chip of the application integrates common protocols of telemetry frames, remote signaling frames, data frames, response frames, check frames, synchronization frames, heartbeat frames, control frames and time mark frames in an ASIC chip, can realize efficient processing and flexible switching of multiple modes of satellite data communication through anti-radiation process, and significantly optimizes circuit size and power consumption on the basis of traditional technology.

[0024] Preferably, the RS encoder 6 4-bit registers b0~b5 and the first, second and third operation units, the 6 4-bit registers store check codes, data in feedback module feedback is inputted into the feedback module feedback together with the data in register b5 for exclusive or operation, the result b0 of exclusive or operation of data f and public factor g0 is stored in register b0, the result b1 of exclusive or operation of result b0 and public factor g1 is stored in register b1, and so on, the result b5 of exclusive or operation of result b4 and public factor g5 is stored in register b5, and the results b0~b5 are inputted into the first operation unit for operation, the first operation unit calculates intermediate value d GF0 ~d GF5 and intermediate value e GF0 ~e GF5 , the second operation unit calculates intermediate values c0~c5 according to intermediate value d GF0 ~d GF5 and intermediate value e GF0 ~e GF5 , and the third operation unit calculates output results by splicing and calculating intermediate values c0~c5 and results b0~b5.

[0025] Preferably, intermediate value d GF0 ~d GF5 is d GF0 =L×b0, d GF1 =L×b1, d GF2 =L×b2, d GF3 =L×b3, d GF4 =L×b4, d GF5 =L×b5, wherein,

[0026] Intermediate value e GF0 ~e GF5 is e GF0 =U×b0, e GF1 =U×b1, e GF2 =U×b2, e GF3 =U×b3, e GF4 =U×b4, e GF5 =U×b5, wherein,

[0027] Intermediate values c0-c5 are: c0=d GF0 +Q T e GF0 , c1=d GF1 +Q T e GF1 , c2=d GF2 +Q T e GF2 , c3=d GF3 +Q T e GF3 , c4=d GF4 +Q T e GF4 , c5=d GF5 +Q T e GF5 wherein,

[0028] Preferably, the RS decoder and the RS encoder both support transparent transmission. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 Fig. 1 is a schematic diagram of the internal structure of a conventional general-purpose FPGA chip;

[0030] Figure 2 Fig. 2 is a schematic diagram of the architecture of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0031] Figure 3 Fig. 3 is a schematic diagram of a data analysis process of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0032] Figure 4 Fig. 4 is a schematic diagram of an RS decoder of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0033] Figure 5 Fig. 5 is a calculation principle diagram of a syndrome solver module of an RS decoder of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0034] Figure 6 Fig. 6 is a principle diagram of error value calculation of an RS decoder of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0035] Figure 7 Fig. 7 is a schematic diagram of an RS encoder of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0036] Fig. 8(a) is a schematic diagram of a digital kernel in a key circuit layout of a wave control chip provided by an embodiment of the present application and having a data error correction function;

[0037] Figure 8(b) is a schematic diagram of the analog circuit in the key circuit layout of the wave controller chip with data error correction function provided in the embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0039] like Figure 2 As shown, this embodiment provides a wavecontrol chip with data error correction function, including an SPI parsing module, an RS decoder, a data processing module, and an RS encoder. The SPI parsing module adopts a four-wire SPI design and connects to peripherals through the SPI interface to realize data transmission between the wavecontrol chip and peripherals. It starts working when the chip select signal is active low and the serial clock signal arrives. It obtains input data using the rising edge of the clock and determines the length of the input data according to the frame type. The function of the data bits is defined by the internal register. The input data is transmitted to the RS decoder or the data processing module after passing through the SPI parsing module. The RS decoder in this chip supports pass-through. When the input data is encoded, it is transmitted to the RS decoder through the SPI parsing module. The RS decoder restores the encoded data to the original data. When the input data is not encoded, it is transmitted directly to the data processing module after passing through the SPI parsing module. This direct transmission of input data to the data processing module through the SPI parsing module is suitable for situations with good channel environment (no external electromagnetic interference).

[0040] Input data is transmitted to the RS decoder via the SPI parsing module. After being decoded by the RS decoder, the original data is obtained. During the decoding process, the RS decoder detects and corrects errors that may occur during transmission by using redundancy information. When it is determined that the input data contains an error that cannot be corrected, the input data is discarded to improve the reliability and accuracy of data transmission.

[0041] See Figure 4 The RS decoder includes a corrector solving module, a key equation solving module, an error pattern search module, an error correction output module, and a shift register. Input data R(x) enters both the corrector solving module and the 15-stage shift register. The input data R(x) is stored in the 15-stage shift register and split into 15 groups, entering the corrector solving module in the order r14 to r0, resulting in six-symbol correctors S1, S2, S3, S4, S5, and S6.

[0042]

[0043] wherein, j = m0, m0+1,..., m0+2t-1, j = 1 ~ 6. Y i x is the received symbol value (in finite field GF(2^m)), x i is the RS codebook primitive root, m0 is 1, and 2t represents the error correction capability (up to t errors, and the present decoder t = 3).

[0044] Referring to Figure 5 After obtaining the syndrome, the syndrome solving module sends an effective signal to start the key equation solving module. The syndromes S1, S2, S3, S4, S5, and S6 of the 6 symbols are input into the key equation solving module. After the key equation solving module is started, the state machine is run. The BM iterative algorithm is used to calculate the error position polynomial σ(x) and the error value polynomial ω(x). The root value of the error position polynomial σ(x) is solved by using the money search, the error position number is obtained, the error position is determined, the error value is calculated according to the error position number and the error value polynomial ω(x), and after the error position number, the error value, and the error position are solved, the error pattern search module and the error correction output module are started. The error value and the error position are input into the error pattern search module, the error pattern E(x) is obtained, the input data R(x) in the 15-stage shift register is read by the error correction output module, the input data R(x) is corrected according to the error pattern E(x), and the code word C(x) is output: C(x) = R(x) - E(x). The error correction process is completed, and the output code word C(x) is the original data after RS decoder decoding. If the error position number exceeds 3, the error correction capability is exceeded, and the decoded data is output as is. If the error position number is 0, that is, there is no error data, the data is also output as is. Otherwise, the corrected decoded data is output, and the check bit is not output at this time.

[0045] The money search is to obtain the root of the error position polynomial σ(x) calculated according to the error position. The code length is n = 15, the primitive element is α, and the error position polynomial is: σ(x) = 1 + σ1x + σ2x 2 + σ3x 3 (because the maximum number of errors to be corrected is t = 3, σ(x) is a 3-degree polynomial), and the money search implementation process is as follows:

[0046] Step 1, initialization: starting from the first position, usually starting from the highest bit, that is, i = n - 1 = 14, corresponding to α 14 ;

[0047] Step 2, for each position i (from i = 14 to i = 0), calculate x = α -i (that is, check the error position i), and substitute σ(x): σ(α -i) = 1 + σ1x + σ2(α -i ) 2 + σ3(α -i ) 3 If σ(α -i ) = 0, then the position i is in error, i.e. the received symbol is in error at position i.

[0048] Step 3, repeat step 2 until all i = 14 to i = 0 are traversed.

[0049] Figure 6 The error value calculation and error correction process is as follows: if according to the money search has σ(a i ) = 0 (i = 1, 2,..., n), n is the maximum value of 14, then it is found that the error position x i = a -i = a n-i , the corresponding error symbol is γ n-i , and its corresponding error value is represented by σ(x), ω(x) calculated in the previous step:

[0050]

[0051] Because σ(x) = σ0+ σ1x + σ2x 2 +... + σ t x t

[0052] Then σ'(x) = σ1+ 2σ2x + 3σ3x 2 +... + tσ t x t-1 On GF(2 m ), σ'(x) can be simplified to

[0053] σ'(x) = σ1+ 3σ3x 2 + 5σ5x 4 +...

[0054] Then xσ'(x) = σ1x + σ3x 3 + σ5x 5 +... is the sum of the odd terms of σ(x), so it is rewritten as:

[0055]

[0056] Then the corrected symbol is:

[0057]

[0058] Figure 5 In which, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r 10 ,11 12 13 14 represents 15 input symbols, including check code and encoded data, r 14 is the first symbol of information bits, r0 is check bit b0; a 1 = 4, a 2 = 2, a 3 = 1, a 4 = 12, a 5 = 6, a 6 = 3 represents an element of Galois field; s1, s2, s3, s4, s5, s6 are syndromes, which are also the final desired results of the calculation of the adjoint formula, and the syndromes are obtained when all the 15 symbols are input; after each adjoint formula is calculated, the syndrome register must be cleared.

[0059] The data processing module includes a frame header buffer register, a frame data buffer, a MUX selector and a memory. The original data decoded by the RS decoder or the input data transmitted by the SPI parsing module includes a frame header and frame data. The original data or the input data is input into the data processing module. The frame header is stored in the frame header buffer register. Whether the address code of the frame header matches is judged. If the address code of the frame header matches, the frame data is stored in the frame data buffer. If the address code of the frame header does not match, the frame data will not be stored in the frame data buffer, and the frame header of the next frame data is continuously stored in the frame header buffer register. The data type stored in the frame data buffer includes telemetry frames, remote signaling frames, data frames, response frames, check frames, synchronization frames, heartbeat frames, control frames and time mark frames. The telemetry frame is used for transmitting the state information of a satellite device, such as temperature, voltage, check, position and other telemetry parameters. The remote signaling frame is used for sending control instructions, such as the switching of the device, mode switching and other operations. The data frame is used for transmitting user data or scientific data, such as images, sensor data and the like. The response frame is used for confirming the receipt of the remote signaling frame or other frames, so as to ensure the reliability of communication. The check frame is used for the integrity check of data transmission, such as parity check or CRC check, and the confirmation of the receiving state. The synchronization frame is used for synchronizing the time reference of the communication parties, so as to ensure the correctness of data transmission. The heartbeat frame is used for maintaining the connection of the communication link and confirming the online state of the device. The control frame is used for transmitting system control information, such as adjusting the attitude of the satellite device or changing the working mode. The time mark frame is used for recording the time stamp of data, so as to ensure the time accuracy of data. In the present application, whether the address code of the frame header of the original data or the input data matches is judged. During the reception of data, at any moment, if the frame format matching condition of the input data is not met, the chip discards the frame as an invalid frame, which does not affect the reception of the next data. Even if the total length of the input data is greater than 4096 bits, the normal operation of the chip will not be affected. The wave control chip has strong robustness. ​​​

[0060] The MUX selector selects one type of data in the frame data buffer and outputs it to the memory memory, and outputs the wave bit data according to the agreed sending logic after receiving the sending instruction, encodes the telemetry data through the RS encoder and then outputs it or directly outputs it, and the RS encoder converts the original data into an encoded form with redundant information at the sending end of the chip, and the RS encoder supports transparent transmission, when the target device does not have decoding function, the telemetry data of the application is directly transmitted to the target device, when the target device has decoding function, the telemetry data of the application is transmitted to the target device after being encoded by the RS encoder, and data processing is carried out after decoding in the target device.

[0061] The wave control chip of the application further comprises a global clock CLK, a frequency division clock CLK_DIV, a reset signal RESET, a power-on reset function POR, an analog-to-data input AD, a power conversion module LDO and an input power supply POWER. Figure 3 The wave control chip of the application adopts an agreed data structure for analysis format, and the total length of data can support up to 4096 bits, and after the data is input from the standard four-wire SPI, it enters the RS decoder, if the decoded data is judged to have errors and cannot be corrected, the frame is discarded, and after the correct decoded data is obtained, data processing and sending are carried out, and the design flow of such data processing ensures the efficient analysis and transmission reliability of frame transmission, and the data can still be correctly analyzed in a certain interference environment. Traditional frame data buffer stores different frames in multiple registers, which consumes a lot of storage resources, and since the registers occupy a large number of digital back-end wiring resources, it leads to wiring difficulty.

[0062] The application stores the frame header data in the frame header buffer register by means of pipeline multiplexing of different frame data, and stores the frame data in the post-processing module, separates the data control from the data itself, the frame header 48 bits buffer, 4048 is the frame data buffer, different frames can be time multiplexed, since four frequency division clocks are designed in the chip, the output of different clocks is controlled by a state machine, therefore, it can be ensured that the frame header buffer and the frame data can work in parallel, when receiving the current frame header control information, the frame header can be defined according to different frame types, the frame header includes address code, word header and function number, the last frame data can be sent out through the post-processing module, and the adjacent two frames can be of different types, through this optimization, the effective number of bits of the register is improved from about 3000 bits in the traditional to 4096 bits. In addition, the key of the innovation of the pipeline operation is not only to save the register, but also to innovate the architecture, to integrate SPI, RS decoding and coding, frame data processing (receiving and sending) and buffer on one chip, and each realizes serial input and parallel output, and four different clock output modes are provided through the frequency divider (CLK_DIV) to be compatible with the processing capacity of the opposite interface.

[0063] Referring to Figure 7 , the RS encoder adopts (15, 9) encoding mode, and the main function is to complete RS encoding operation. The RS encoder includes six 4-bit registers b0, b1, b2, b3, b4, b5, and first, second and third operation units, the six 4-bit registers store check codes, and each register operation adopts Galois field algorithm. The Galois field GF(2 4 ) is defined by α, and the primitive polynomial of the Galois field GF(2 4 ) is p(X) = 1 + X + X 4 , and the generating polynomial is defined as G(x) = g0 + g1·X + g2·X 2 + g3·X 3 + g4·X 4 + g5·X 5 + X 6 . The RS code adopts the design idea of cyclic code, and the addition and multiplication operations involved are performed in the Galois field GF(2 4 ).

[0064] The initial values of the registers b0, b1, b2, b3, b4 and b5 are all 0, the common factors g0, g1, g2, g3, g4 and g5 are Coef values obtained by pre-operation according to the primitive polynomial, each value is a 4-bit number, the telemetry data is the data data_in to be encoded, the data data_in is taken as a basic symbol unit of 4 bits, the data data_in and the data in the register b5 are input into the feedback module feedback to perform XOR operation, and data f is obtained: f = data_in ^ b5 = {f3, f2, f1, f0}.

[0065] The result b0 of the XOR operation of the data f and the common factor g0 is stored in the register b0, the result b1 of the XOR operation of the result b0 and the common factor g1 is stored in the register b1, the result b2 of the XOR operation of the result b1 and the common factor g2 is stored in the register b2, the result b3 of the XOR operation of the result b2 and the common factor g3 is stored in the register b3, the result b4 of the XOR operation of the result b3 and the common factor g4 is stored in the register b4, and the result b5 of the XOR operation of the result b4 and the common factor g5 is stored in the register b5. The results b0, b1, b2, b3, b4 and b5 are input into the first operation unit for operation, the first operation unit is used to calculate GF0, GF1, GF2, GF3, GF4 and GF5, and the calculation manner is the same, and the calculation of GF0 is taken as an example for introduction. According to b0, the intermediate value d GF0 and the intermediate value e GF0 are calculated:

[0066]

[0067] Similarly, d GF1 = L x b1,e GF1 = U x b1;d GF2 = L x b2,e GF2 = U x b2;d GF3 = L x b3,e GF3 = U x b3;d GF4 = L x b4,e GF4 = U x b4;d GF5 = L x b5,e GF5 = U x b5.

[0068] wherein,

[0069] a m = g[m], m = 0 ~ 3, if calculating g0, the corresponding is 4 bits number of common factor g0, if calculating g1, the corresponding common factor is 4 bits number of g1.

[0070] The second operation unit calculates the intermediate value c0 according to the intermediate value d GF0 and the intermediate value e GF0

[0071]

[0072] wherein,

[0073] Similarly, the second operation unit calculates the intermediate value c1 according to the intermediate value d GF1 and the intermediate value e GF1 c1 = d GF1 + Q T e GF1 ; the second operation unit calculates the intermediate value c2 according to the intermediate value d GF2 and the intermediate value e GF2 c2 = d GF2 + Q T e GF2 ; the second operation unit calculates the intermediate value c3 according to the intermediate value d GF3 and the intermediate value e GF3 c3 = d GF3 + Q T e GF3 ; the second operation unit calculates the intermediate value c4 according to the intermediate value d GF4 and the intermediate value e GF4 c4 = d GF4 + Q T e GF4 ; the second operation unit calculates the intermediate value c5 according to the intermediate value d GF5 and the intermediate value e GF5 ​The intermediate value c5 is calculated: c5 = d GF5 +Q T e GF5 .

[0074] The third operation unit performs concatenation calculation on the intermediate values c0, c1, c2, c3, c4, and c5 and the results b0, b1, b2, b3, b4, and b5 to obtain an output result data_out: data_out = {B, original symbol data}, where B = {b0, b1, b2, b3, b4, b5}, and the original symbol data is the original data input.

[0075] The present application aims at the problems of low integration, low reliability, high cost / power consumption, large volume / weight, etc. of existing digital beam control circuits, and proposes a multi-functional integrated wave control chip circuit architecture, which integrates common protocols of telemetry frames, remote signaling frames, data frames, response frames, verification frames, synchronization frames, heartbeat frames, control frames, and time mark frames in an ASIC chip. The anti-radiation process can realize efficient processing and flexible switching of multiple modes of satellite data communication, and significantly optimizes the circuit size and power consumption based on traditional technology. The present application proposes an indefinite length frame format architecture, which separates the frame header and frame data for processing, and is compatible with data structures of any frame length, effectively solving the problem of insufficient robustness of traditional wave control circuits. The ASIC integrated design significantly optimizes the circuit power consumption and area compared to traditional FPGA structures or discrete devices, reduces the volume by more than 60%, and reduces the power consumption by more than 70%, realizing a high-integration, multi-functional integrated architecture design. The present application is suitable for various high-integration, low-cost digital beam control transceiver circuits. The chip has the following advantages:

[0076] Efficient processing of multiple types of data: The present application integrates multiple protocol analysis functions to realize efficient reception, RS encoding and decoding (supporting transparent transmission), analysis and distribution of multiple types of data, significantly improving the data processing efficiency and flexibility of the radar wave control communication system.

[0077] High integration and low power consumption: The ASIC (Application Specific Integrated Circuit) design method is adopted to integrate multiple functions in one chip, which significantly optimizes the circuit size, reduces the power consumption, and reduces the volume and weight, meeting the strict requirements of the radar wave control communication system for high integration and low power consumption.

[0078] Supporting indefinite length data input: The frame storage structure is built by using a shift register, supporting a maximum of 4096 bits, 48 bits of frame header cache, and 4808 bits of frame data cache. The data can be of any length within 4808, with strong robustness. Even if the input data length does not meet the requirements, the chip can still operate normally and will not affect the reception of the next frame of data, significantly improving the reliability and anti-interference ability of the system.

[0079] Flexible output mode: the output circuit supports multiple data transmission modes. The telemetry packaging circuit supports serial output and RS encoding, and the data does not stop in the middle, with strong flexibility and anti-interference ability.

[0080] High robustness and reliability: the chip design has strong robustness and fault tolerance. During data reception, if the input conditions are not met at any time, the chip can automatically discard the frame as invalid, without affecting the reception of subsequent data. At the same time, the output circuit design supports flexible switching of multiple modes, ensuring the stability and reliability of the system. Through the innovative chip architecture design, the present application solves the problems of low data processing efficiency, poor flexibility, and insufficient system reliability in the prior art, significantly improving the performance and application value of the radar wave control communication system.

[0081] Referring to FIGS. 8(a) and 8(b), the wave control chip with data error correction function of the present application can realize multi-mode output through GPIO, achieving extremely simple area and extremely low power consumption. Compared with the traditional FPGA scheme, the volume is reduced by more than 60%, and the power consumption is reduced by more than 70%. The area of the chip digital and analog unit circuit based on CMOS 180nm process node is only 1730umx1530um and 670umx1130um, so the packaging area can be controlled ≤10mmx10mm, and the power consumption is less than 3W.

[0082] The above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent substitutions for part of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A wave controller chip with data error correction function, characterized in that: The system includes an SPI parsing module, an RS decoder, a frame header buffer register, a frame data buffer, a MUX selector, a memory, and an RS encoder. Input data of variable-length codewords is transmitted to the RS decoder via the SPI parsing module. After decoding by the RS decoder, the raw data is obtained. The frame header of the raw data is stored in the frame header buffer register. If the address code of the frame header matches, the frame data is stored in the frame data buffer. The MUX selector selects a type of data in the frame data buffer and outputs it to the memory. After receiving the transmission command, the waveform data is output according to the agreed transmission logic. The telemetry data is encoded by the RS encoder and then output.

2. The wave controller chip with data error correction function according to claim 1, characterized in that: The RS decoder detects and corrects errors that may occur during transmission by using redundant information. It can correct 3 errors for every 15 symbols of data input. The data is only transmitted to the next level if the parsing and verification pass; otherwise, the frame is discarded.

3. The wave controller chip with data error correction function according to claim 1, characterized in that: The RS decoder includes a corrector solving module, a key equation solving module, an error pattern search module, an error correction output module, and a shift register. Input data R(x) enters the corrector solving module to obtain the corrector, and the input data R(x) is stored in the shift register. The corrector is then input into the key equation solving module, where the BM iterative algorithm is used to calculate the error location polynomial σ(x) and the error value polynomial ω(x). The root value of the error location polynomial σ(x) is solved using a Qian search algorithm to obtain the number of error locations, thus determining the error location. The error value is calculated based on the number of error locations and the error value polynomial ω(x). The error value and error location are input into the error pattern search module to obtain the error pattern E(x). The error correction output module reads the input data R(x) from the shift register, corrects the input data R(x) according to the error pattern E(x), and outputs the codeword.

4. The wave controller chip with data error correction function according to claim 3, characterized in that: Six-symbol correctors S1 to S6: Where j = m0, m0+1, ..., m0+2t-1; Y i For the received symbol value, x i For the original root of the RS codebook, m0 is 1, and 2t represents the error correction capability.

5. The wave controller chip with data error correction function according to claim 3, characterized in that: The polynomial at the error position is: σ(x)=1+σ1x+σ2x 2 +σ3x 3 The process of using Qian search to find the root value of the polynomial σ(x) at the error location includes: Step 1: Starting from the first position, i = n - 1 = 14, corresponding to α 14 ; Step 2: For each position i, calculate x = α -i Substituting into σ(x): σ(α) -i )=1+σ1x+σ2(α -i ) 2 +σ3(α -i ) 3 If σ(α) -i If ) = 0, then position i is incorrect, meaning the received symbol is incorrect at position i. Step 3: Repeat step 2 until all i=14 to i=0 have been traversed.

6. The wave controller chip with data error correction function according to claim 3, characterized in that: Corrected symbols for: Error value Y i for: Where, x i For the incorrect location, σ odd Let represent the odd-numbered terms of the error-position polynomial σ(x).

7. The wave controller chip with data error correction function according to claim 1, characterized in that: The data types stored in the frame data buffer include telemetry frames, telesignal frames, data frames, response frames, check frames, synchronization frames, heartbeat frames, control frames, and time stamp frames.

8. The wave controller chip with data error correction function according to claim 1, characterized in that: The RS encoder uses six 4-bit registers (b0-b5) and three arithmetic units: a first arithmetic unit, a second arithmetic unit, and a third arithmetic unit. The six 4-bit registers store the checksum. The data in register b5 is XORed with the data in data_in to form the feedback module. The result of XORing data f with the common factor g0 is stored in register b0. Similarly, the result of XORing b0 with the common factor g1 is stored in register b1, and so on. The result of XORing b4 with the common factor g5 is stored in register b5. The results b0-b5 are then input to the first arithmetic unit for calculation. The first arithmetic unit calculates the intermediate value d based on b0-b5. GF0 ~d GF5 and the median e GF0 ~e GF5 The second operation unit is based on the intermediate value d GF0 ~d GF5 and the median e GF0 ~e GF5 The intermediate values ​​c0 to c5 are calculated. The third operation unit concatenates the intermediate values ​​c0 to c5 with the results b0 to b5 to obtain the output result.

9. The wave controller chip with data error correction function according to claim 8, characterized in that: Intermediate value d GF0 ~d GF5 For: d GF0 =L×b0,d GF1 =L×b1,d GF2 =L×b2,d GF3 =L×b3,d GF4 =L×b4,d GF5 =L×b5, where, Intermediate value e GF0 ~e GF5 e GF0 =U×b0,e GF1 =U×b1,e GF2 =U×b2,e GF3 =U×b3,e GF4 =U×b4,e GF5 =U×b5, where, The intermediate values ​​c0 to c5 are: c0 = d GF0 +Q T e GF0 c1 = d GF1 +Q T e GF1 c2 = d GF2 +Q T e GF2 c3 = d GF3 +Q T e GF3 c4 = d GF4 +Q T e GF4 c5 = d GF5 +Q T e GF5 ,in, 10. The wave controller chip with data error correction function according to claim 1, characterized in that: Both the RS decoder and RS encoder support pass-through.

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