Convolution input structure multiplexing method and device based on signal sliding window row block cache

Abstract

The embodiment of the invention provides a convolution input structure multiplexing method and device based on signal sliding window row block cache, and relates to the technical field of embedded intelligent sensing. The method is applied to a front-end cache of a multiply-accumulate array, and comprises the following steps: determining a cache configuration parameter according to a parameter of an executed convolution operation; establishing a plurality of line caches in the front-end cache according to the cache configuration parameters; newly added data obtained through the sliding window operation is written into a row cache; and reading data from the row cache when the multiply-accumulate array executes a calculation operation. According to the implementation mode provided by the invention, the input redundant loading is remarkably reduced, the reuse rate of the overlapped part of the adjacent sliding windows is increased, and the average access frequency of the SRAM is reduced.

Description

Technical Field

[0001] This application relates to the field of embedded intelligent sensing technology, specifically to a method for reusing convolutional input structures based on signal sliding window row block buffering, a device for reusing convolutional input structures based on signal sliding window row block buffering, an electronic device, a storage medium, and a computer program product. Background Technology

[0002] Convolutional Neural Networks (CNNs) have been widely applied in embedded intelligent sensing, including tasks such as interference detection, signal state recognition, and multipath pattern classification in GNSS receivers. When deploying CNN models on SoC or MCU platforms, the acquisition and buffering of convolutional input data are crucial to the hardware architecture design. Typically, CNN accelerators use a two-dimensional sliding window approach to extract a small region of the input image or tensor, sequentially feeding it into the convolution kernel for multiplication and addition operations. To improve efficiency, mainstream convolutional hardware is equipped with an input buffer and employs sliding window technology to avoid repeatedly loading input data. Current common designs suffer from the following problems: 1. Redundant loading of row pixels: During multiple sliding window processes, there are a large number of overlapping areas between multiple windows (for example, in a 3×3 convolution, adjacent windows will share 2 / 3 of the row data), but existing designs often reload the entire block of data, resulting in wasted bandwidth; 2. Cache refresh is not intelligent enough: Most designs use whole row refresh or whole block move, failing to "update only the newly added pixel row", resulting in high SRAM access frequency and power consumption; 3. Large on-chip SRAM usage: To support high throughput, many implementations choose to load the entire input image or a large range of sliding window data at once, resulting in a large amount of redundancy occupying on-chip storage resources, which is not suitable for small SoC designs with limited area. 4. Mismatch with GNSS signal structure: GNSS signal input is often "signal residual map", "spectral map" or "1-channel multi-time sequence", which has forced structural characteristics, while current caching mechanisms are mostly geared towards image-like 2D structures, resulting in low structure reuse efficiency. Summary of the Invention

[0003] The purpose of this application is to provide a method and apparatus for reusing convolutional input structures based on signal sliding window row block caching. It replaces the traditional block input caching structure with a sliding row block caching structure, constructs an input path structure with row block sliding window, alternating bank refresh and row address rotation mechanism, realizes on-demand refresh, inter-row reuse, alternating bank and address rotation, effectively improves data reuse rate, can significantly reduce redundant access and cache resource consumption of input path, improve the overall CNN module operating efficiency and energy efficiency ratio, so as to at least solve some of the problems in the background technology.

[0004] To achieve the above objectives, this application provides a convolution input structure reuse method based on a signal sliding window row block buffer, applied to the front-end buffer of a multiply-accumulate array. The method includes: determining buffer configuration parameters based on the parameters of the convolution operation to be performed; establishing several row buffers in the front-end buffer according to the buffer configuration parameters; writing the newly added data obtained by the sliding window operation into the row buffers; and reading data from the row buffers when the multiply-accumulate array performs a calculation operation.

[0005] Preferably, the parameters of the convolution operation include the kernel size and the stride; the cache configuration parameters include: row cache width, window depth, and number of row caches; determining the cache configuration parameters based on the parameters of the executed convolution operation includes: determining the amount of data update for each window movement based on the kernel size and stride, and determining the row cache width and window depth based on the data update amount; determining the number of row caches based on the ratio of the kernel size to the data update amount, or determining the number of row caches based on a preset number.

[0006] Preferably, the plurality of row caches are divided into two groups; when the flag bit is in the first state, the newly added data obtained by the sliding window operation is written into the row cache in the first group and executed, and when the multiplication-accumulation array performs the calculation operation, the data is read from the row cache and executed in the second group; when the flag bit is in the second state, the newly added data obtained by the sliding window operation is written into the row cache in the second group and executed, and when the multiplication-accumulation array performs the calculation operation, the data is read from the row cache and executed in the first group.

[0007] Preferably, all line caches are assigned a preset sequence number, and each line cache is selected as the target line cache by the preset sequence number.

[0008] Preferably, writing the new data obtained from the sliding window operation into the row cache includes: in response to detecting the movement of the sliding window, determining a target row cache from the plurality of row caches; obtaining the new data, writing the new data into the target row cache; and updating the state of the flag bit.

[0009] Preferably, the method further includes: maintaining a sliding window row mapping table in the controller, the sliding window row mapping table being used to record the mapping relationship between logical sliding window rows and physical banks, the sliding window row mapping table being updated after the sliding window moves.

[0010] Preferably, the sliding window row mapping table is updated after the sliding window moves, including: determining whether the sliding window moves downward each time it moves; when the sliding window does not move downward, updating the column containing the newly added pixel in the sliding window row mapping table; when the sliding window moves downward, updating the index of the row cache based on the preset sequence number in the sliding window row mapping table.

[0011] Preferably, the method is applied to the input front end of the CNN perception module in a GNSS chip.

[0012] This application also provides a convolution input structure multiplexing device based on a signal sliding window row block cache. The device includes: a parameter configuration module for determining cache configuration parameters according to the parameters of the convolution operation being performed; a cache allocation module for establishing several row caches in the front-end cache according to the cache configuration parameters; a data writing module for writing new data obtained from the sliding window operation into the row caches; and a data reading module for reading data from the row caches when the multiplication-accumulation array performs a calculation operation.

[0013] This application also provides an electronic device, including: at least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the at least one processor implements the aforementioned convolutional input structure multiplexing method based on signal sliding window row block caching by executing the instructions stored in the memory.

[0014] Preferably, the electronic device is a chip.

[0015] This application also provides a machine-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform the aforementioned convolutional input structure multiplexing method based on a signal sliding window row block cache.

[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the aforementioned convolutional input structure multiplexing method based on signal sliding window row block caching.

[0017] The above technical solution has the following beneficial effects: 1. Significantly reduces redundant input loading, with a reuse rate of 70%~90% for overlapping parts of adjacent sliding windows, and an average reduction of more than 40% in the number of SRAM accesses.

[0018] 2. Input cache area is reduced by 30%~50%, supporting the on-chip deployment of smaller, low-power CNN structures.

[0019] 3. Supports real-time sliding window reading and asynchronous refresh, without waiting for the entire frame to load, suitable for GNSS periodic short frame processing needs.

[0020] 4. Improve the data throughput and parallelism of the input path to ensure that the CNN module can still complete millisecond-level inference tasks under low-frequency main control.

[0021] 5. The structure is customizable and highly adaptable, suitable for GNSS-type feature tensors such as spectrograms, residual maps, and correlation maps.

[0022] 6. Power consumption is significantly reduced. When deployed with the INT8 model, the overall input power consumption is reduced by 20% to 35%.

[0023] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings: Figure 1 This illustration schematically shows the steps of a convolutional input structure reuse method based on signal sliding window row block caching according to an embodiment of this application; Figure 2 This illustration shows a schematic diagram of an application scenario of a GNSS chip according to an embodiment of this application; Figure 3 The schematic diagram illustrates the structure of a convolutional input structure multiplexing device based on a signal sliding window row block buffer according to an embodiment of this application; Figure 4 The diagram schematically illustrates the internal structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0025] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the embodiments of this application.

[0026] The core idea of ​​convolution is to use a convolution kernel to convolve the input data, thereby extracting specific feature information. When deploying CNN models on SoC or MCU platforms, the acquisition and caching of convolution input data are crucial to the hardware architecture design. Typically, when a CNN accelerator performs convolution operations, it needs to execute sliding window operations and computation operations step by step. The sliding window operation includes: using a two-dimensional sliding window to extract a small region of the input image or tensor, and then feeding it sequentially into the convolution kernel to perform computation operations, such as multiply-accumulate operations. Figure 1 The illustration schematically depicts the steps of a convolutional input structure reuse method based on signal sliding window row block caching according to an embodiment of this application. For example... Figure 1As shown, a convolutional input structure reuse method based on signal sliding window row block caching is applied to the front-end buffer of a multiply-accumulate array. Typically, mainstream convolutional hardware is equipped with a front-end buffer, also known as an input buffer, and uses sliding window technology to avoid repeatedly loading input data, thereby improving efficiency. This method includes: S01. Determine the cache configuration parameters based on the parameters of the convolution operation being performed. One scenario of this application is running a convolution operation on a multiply-accumulate array; therefore, the convolution operation here is determined based on the model structure of the running convolutional neural network (CNN). The parameters of the convolution operation here include the kernel size and the stride.

[0027] S02. Establish several row caches in the front-end cache according to the cache configuration parameters. This step introduces row buffer, which can load input data row by row, thereby reducing the loading granularity and avoiding loading large sliding window data or even the entire image at once, thus achieving the effect of reducing the cache size.

[0028] S03. Write the newly added data obtained from the sliding window operation into the row cache. Here, "new data" refers to the data added based on the previous sliding window operation. Taking a 3×3 two-dimensional convolution kernel as an example, when its stride is 1, adjacent sliding windows will share 2 / 3 of the row data, with only one row differing. In this case, the newly added row data is written into the row cache. Each slide only updates the "new row" portion, while the remaining cached data remains valid, thus achieving row block reuse.

[0029] S04. When performing calculation operations on the multiplication-accumulation array, data is read from the row cache. Although reading the same data necessarily requires writing it first, from a macroscopic perspective, steps S04 and S03 are decoupled, and they may be performed in parallel using different processes or threads. Preferably, the sliding window update is completed within one cycle.

[0030] Through the above implementation methods, input redundancy loading is significantly reduced, the reuse rate of overlapping parts of adjacent sliding windows reaches 70%~90%, and the number of SRAM accesses is reduced by an average of more than 40%.

[0031] The effectiveness of the above implementation method is illustrated by the following usage example. The usage example (using 3×3 convolution as an example) is as follows: Input image: 32×32×1; Sliding window size: 3×3, stride 1; Only one row of pixels is updated per sliding window; After loading the first 3 rows using the Row Buffer reuse structure, only one row needs to be loaded each time thereafter, reusing the buffer of the first two rows; In actual operation, the number of row buffer accesses is reduced from the original full frame read ×32 times to only ×3 initial load + ×29 incremental row loads. It is evident that redundant loading is significantly reduced.

[0032] In some embodiments of this application, the parameters of the convolution operation include the kernel size and stride; the cache configuration parameters include the row cache width, window depth, and number of row caches; determining the cache configuration parameters based on the parameters of the executed convolution operation includes: determining the data update amount for each window movement based on the kernel size and stride, and determining the row cache width and window depth based on the data update amount; since the purpose of this application is to maximize the reuse rate of adjacent windows to improve access efficiency, the data change for each convolution becomes the determining factor for the row cache capacity configuration. Determining the data update amount for each window movement based on the kernel size and stride, and determining the row cache width and window depth based on the data update amount, specifically includes: determining the input image row width based on the kernel size, and determining the row cache width based on the input image row width. If the convolution kernel is a three-dimensional convolution, the input image has multiple channels, and the row cache width needs to take into account the window depth parameter; the row cache width is at least not less than the image width multiplied by the number of channels.

[0033] The number of row caches can be determined based on the ratio of the convolution kernel size to the data update amount, or based on a preset number. For example, with a 4×4 convolution kernel, if the convolution stride is 1, the data update amount per window is 1×4, and the ratio of the convolution kernel size to the data update amount is 4. Therefore, the number of caches can be set to 4. To account for subsequent redundancy control, the number of row caches should be set to 8. Similarly, with a 4×4 convolution kernel, if the convolution stride is 2, the data update amount per window is 2×4. Therefore, the number of caches can be set to 2, and to account for subsequent redundancy control, the number of row caches should be set to 4. In other embodiments, the number of row caches is directly determined based on a preset number, such as 6.

[0034] In some embodiments of this application, the plurality of row buffers are divided into two groups. When the flag is in the first state, the newly added data obtained from the sliding window operation is written into the row buffer in the first group for execution, and the number of row buffers is determined by a preset number. When the multiplication-accumulation array performs calculation operations, data is read from the row buffer in the second group for execution. When the flag is in the second state, the newly added data obtained from the sliding window operation is written into the row buffer in the second group for execution, and data is read from the row buffer in the first group for execution when the multiplication-accumulation array performs calculation operations. Taking a total of 6 row buffers as an example, they are divided into 2 groups (Banks). Each group includes 3 row buffers. The sliding window scans the image row by row, and the results are stored in the following cache structure: the cache structure includes 6 row buffers, and the 6 row buffers are divided into two banks. Row Buffer_0 to Row Buffer_2 are the current sliding window data row blocks, while Row Buffer_3 to Row Buffer_5 are the spare refresh areas.

[0035] In some embodiments of this application, all line caches are assigned preset sequence numbers, and each line cache is selected as the target line cache based on the preset sequence number. Taking 6 line caches as an example, their sequence numbers can be assigned from 0 to 5; the write pointer cycles between 0 and 5 using round-robin logic, starting from 0 after 5. When new line data is written, it overwrites the earliest written line block, achieving a circular refresh.

[0036] In some embodiments of this application, writing new data obtained from the sliding window operation into the row cache includes: in response to detecting the movement of the sliding window, determining a target row cache from the plurality of row caches; obtaining the new data; writing the new data into the target row cache; and updating the state of a flag bit. New data will be written after the sliding window movement operation. The target row cache is determined by obtaining the current write pointer. For example, if the current write pointer points to 4, then the row cache with sequence number 4 is used as the target row cache, and the new data is written into row cache 4. Updating the state of the flag bit includes switching between a first state and a second state. Two groups of banks alternately refresh and read. While sliding window reading and sliding window output are performed in the row cache of Bank A, the write operation is performed in the row cache of Bank B to complete the loading of a new row. After each sliding window movement, one row of new data is written into one row cache, and one Bank cell is refreshed. While one group is reading, the other group can asynchronously write new row data, improving data loading efficiency.

[0037] In some embodiments of this application, the method further includes: maintaining a sliding window row mapping table in the controller, the sliding window row mapping table being used to record the mapping relationship between logical sliding window rows and physical banks, and the sliding window row mapping table being updated after the sliding window moves. Denoted as window_map[], the sliding window row mapping table is used to record the mapping relationship between logical sliding window rows and physical banks, i.e., window_map[i] = RowBuf_k, where RowBuf_k is the physical address of the k-th row cache. The sliding window row mapping table is updated after the sliding window moves. This update includes: when the sliding window movement is not downward, updating the column containing the newly added pixel in the sliding window row mapping table; when the sliding window movement is downward, updating the index of the row cache based on the preset sequence number in the sliding window row mapping table. For example: each time the sliding window moves downward, the controller updates window_map[i] to window_map[i+1] and assigns the new bank address to window_map[last]. This implementation provides a mapping mechanism in the controller from logical sliding windows to physical banks, realizing the mapping from logical control to physical addresses.

[0038] In some embodiments of this application, the method is applied to the input front end of a CNN sensing module in a GNSS chip. This embodiment provides a typical application scenario. Figure 2 The illustration shows a schematic diagram of an application scenario of a GNSS chip according to an embodiment of this application. For example... Figure 2 As shown, in a typical GNSS chip, this method is applied to the input front end of the CNN sensing module. This invention can process the spectrogram / pseudocode residual map transmitted from the GNSS preprocessing module, which is then read by the MAC array. The overall deployment structure is as follows: the input buffer module collaborates with the main controller via AXI or a local bus, and the CNN controller configures parameters such as the sliding window size, stride, and number of buffer banks. In this application scenario, a decoding / multiplexing module is set between the input path and the MAC array; it can adapt to convolutional kernels of any size (such as 3×3, 1×1), supports dynamic sliding window size and stride, and also supports row and column skipping configurations, suitable for sparse or pruned input structures.

[0039] Based on the same inventive concept, this application also provides a convolutional input structure multiplexing device based on signal sliding window row block buffering. Figure 3 The diagram illustrates the structure of a convolutional input structure multiplexing device based on a signal sliding window row block buffer according to an embodiment of this application. Figure 3As shown, the device includes: a parameter configuration module for determining cache configuration parameters based on the parameters of the convolution operation being performed; a cache allocation module for establishing several row caches in the front-end cache based on the cache configuration parameters; a data writing module for writing new data obtained from the sliding window operation into the row caches; and a data reading module for reading data from the row caches when the multiplication-accumulation array performs a calculation operation.

[0040] In some optional implementations, the parameters of the convolution operation include the kernel size and the stride; the cache configuration parameters include the row cache width, the sliding window depth, and the number of row caches; determining the cache configuration parameters based on the parameters of the executed convolution operation includes: determining the amount of data update for each sliding window movement based on the kernel size and the stride, and determining the row cache width and the sliding window depth based on the data update amount; determining the number of row caches based on the ratio of the kernel size to the data update amount, or determining the number of row caches based on a preset number.

[0041] In some optional implementations, the plurality of row caches are divided into two groups; when the flag is in the first state, the newly added data obtained by the sliding window operation is written into the row cache in the first group and executed, and when the multiplication-accumulation array performs the calculation operation, data is read from the row cache and executed in the second group; when the flag is in the second state, the newly added data obtained by the sliding window operation is written into the row cache in the second group and executed, and when the multiplication-accumulation array performs the calculation operation, data is read from the row cache and executed in the first group.

[0042] In some alternative implementations, all line caches are assigned a preset sequence number, and each line cache is selected as the target line cache by the preset sequence number.

[0043] In some alternative implementations, writing the new data obtained from the sliding window operation into the row cache includes: in response to detecting the movement of the sliding window, determining a target row cache from the plurality of row caches; obtaining the new data, writing the new data into the target row cache; and updating the state of a flag bit.

[0044] In some alternative embodiments, the apparatus further includes: maintaining a sliding window row mapping table in the controller, the sliding window row mapping table being used to record the mapping relationship between logical sliding window rows and physical banks, the sliding window row mapping table being updated after the sliding window moves.

[0045] In some optional implementations, the sliding window row mapping table is updated after the sliding window moves, including: determining whether the sliding window moves downwards each time it moves; if the sliding window does not move downwards, updating the column containing the newly added pixel in the sliding window row mapping table; and if the sliding window moves downwards, updating the index of the row cache based on the preset sequence number in the sliding window row mapping table.

[0046] In some alternative implementations, the device is applied to the input front end of a CNN sensing module in a GNSS chip.

[0047] The specific limitations of each functional module in the aforementioned convolutional input structure multiplexing device based on signal sliding window row block caching can be found in the limitations of the convolutional input structure multiplexing method based on signal sliding window row block caching described above, and will not be repeated here. Each module in the above system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module. This also achieves the beneficial effects of significantly reducing input redundancy loading, improving the multiplexing rate of overlapping parts of adjacent sliding windows, and reducing the average number of SRAM accesses.

[0048] In some embodiments of this application, an electronic device is also provided, comprising: at least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which executes the aforementioned convolutional input structure multiplexing method based on signal sliding window row block caching. Its internal structure diagram can be shown as follows. Figure 4 As shown. Figure 4 The diagram schematically illustrates the internal structure of an electronic device according to an embodiment of this application. The electronic device includes a processor A01, a network interface A02, a memory (not shown), and a database (not shown) connected via a system bus. The processor A01 provides computational and control capabilities. The memory includes internal memory A03 and a non-volatile storage medium A04. The non-volatile storage medium A04 stores an operating system B01, a computer program B02, and a database (not shown). The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 stored in the non-volatile storage medium A04. The network interface A02 is used for communication with external terminals via a network connection. When the computer program B02 is executed by the processor A01, it implements a convolutional input structure multiplexing method based on a signal sliding window row block buffer.

[0049] Those skilled in the art will understand that Figure 4The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0050] In some implementations, the aforementioned electronic device is a chip, and the following chip implementation suggestion is given here based on a 28nm process.

[0051]

[0052] Optionally, the chip is a GNSS chip. The aforementioned methods or apparatus can be applied to intelligent sensing performed by a GNSS chip. The table below shows the implementation methods and beneficial effects for typical application tasks in GNSS intelligent sensing.

[0053]

[0054] In one embodiment provided in this application, a machine-readable storage medium is provided, on which instructions are stored, which, when executed by a processor, cause the processor to be configured to perform the aforementioned convolutional input structure multiplexing method based on signal sliding window row block caching.

[0055] In one embodiment provided in this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the aforementioned convolutional input structure multiplexing method based on signal sliding window row block caching.

[0056] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0057] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0058] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0059] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0060] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0061] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0062] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0063] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0064] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for reusing convolutional input structures based on signal sliding window row block buffering, characterized in that, A front-end cache applied to a multiply-accumulate array, the method comprising: The cache configuration parameters are determined based on the parameters of the convolution operation being performed. Based on the cache configuration parameters, several rows of cache are created in the front-end cache; Write the new data obtained from the sliding window operation to the row cache; Data is read from the row buffer when the multiply-accumulate array performs a calculation operation.

2. The method according to claim 1, characterized in that, The parameters of the convolution operation include the kernel size and the stride; the cache configuration parameters include the row cache width, the sliding window depth, and the number of row caches. The cache configuration parameters are determined based on the parameters of the convolution operation being performed, including: The amount of data update for each sliding window movement is determined based on the kernel size and stride, and the row cache width and sliding window depth are determined based on the data update amount. The number of row caches is determined based on the ratio of the convolution kernel size to the data update amount, or based on a preset number.

3. The method according to claim 1, characterized in that, The cached rows are divided into two groups; When the flag is in the first state, the new data obtained from the sliding window operation is written into the row cache in the first group for execution. When the multiplication-accumulation array performs the calculation operation, the data is read from the row cache and executed in the second group. When the flag is in the second state, the new data obtained from the sliding window operation is written into the row cache in the second group for execution, and when the multiplication-accumulation array performs the calculation operation, the data is read from the row cache and executed in the first group.

4. The method according to claim 3, characterized in that, All line caches are assigned a preset sequence number, and each line cache is selected as the target line cache by the preset sequence number.

5. The method according to claim 4, characterized in that, Write the new data obtained from the sliding window operation to the row cache, including: In response to detecting movement of the sliding window, a target row cache is determined from the plurality of row caches; Obtain the newly added data and write the newly added data into the target row cache; Update the status of the flag.

6. The method according to claim 1, characterized in that, The method further includes maintaining a sliding window row mapping table in the controller, the sliding window row mapping table being used to record the mapping relationship between logical sliding window rows and physical banks, and the sliding window row mapping table being updated after the sliding window moves.

7. The method according to claim 6, characterized in that, The sliding window row mapping table is updated after the sliding window is moved, including: Each time the sliding window moves, determine whether the movement is downward. When the sliding window is not moving downwards, update the column containing the newly added pixel in the sliding window row mapping table; When the sliding window moves downwards, the index of the row cache based on the preset sequence number is updated in the sliding window row mapping table.

8. The method according to any one of claims 1 to 7, characterized in that, The method is applied to the input front end of the CNN perception module in a GNSS chip.

9. A convolutional input structure multiplexing device based on signal sliding window row block buffering, characterized in that, The device includes: The parameter configuration module is used to determine the cache configuration parameters based on the parameters of the convolution operation being performed. The cache allocation module is used to create several rows of cache in the front-end cache according to the cache configuration parameters; The data writing module is used to write the new data obtained from the sliding window operation to the row cache; The data reading module reads data from the row cache when performing calculation operations on the multiply-accumulate array.

10. An electronic device, characterized in that, include: At least one processor; A memory connected to the at least one processor; The memory stores instructions executable by the at least one processor, which implements the convolutional input structure multiplexing method based on signal sliding window row block caching as described in any one of claims 1 to 8 by executing the instructions stored in the memory.

11. The electronic device according to claim 10, characterized in that, The electronic device is a chip.

12. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instruction is executed by the processor, it implements the convolutional input structure reuse method based on signal sliding window row block caching as described in any one of claims 1 to 8.

13. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the convolutional input structure reuse method based on signal sliding window row block caching as described in any one of claims 1 to 8.

Images