Memristor array optimization method

Abstract

The invention discloses a memristor array optimization method. The method comprises the following steps: obtaining a Boolean function to be calculated and a memristor array to be optimized; processing the Boolean function to be calculated by using a genetic algorithm to obtain an optimal binary decision diagram; and according to the optimal binary decision diagram, the memristor array is optimized, and an optimal memristor array is obtained. The method is low in calculation energy consumption and low in calculation cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memristor, more particularly, to a method for optimizing a memristor array. BACKGROUND

[0002] Memory computing in analog form can perform matrix-vector multiplication and other logical operations at a faster speed and lower energy consumption in a dense crossbar array, and has an advantage in the face of data-driven technologies such as deep neural networks and basic artificial intelligence models. As a new type of non-volatile device, the memristor provides a new computing paradigm through the ingenious use of the resistance state and switching characteristics of the memristor.

[0003] At present, the relatively classic digital memory computing paradigms include IMPLY, MAGIC, MAJORITY, FLOW and PATH. These memory computing paradigms have the following commonalities more or less: these paradigms include two broad stages. First, there is a one-time compilation stage, and second, there is an execution stage for each function input. The read and write operations performed in each stage are different for different logical paradigms. The first four paradigms use write operations in the execution stage. Write operations are several orders of magnitude more expensive than read operations. In addition, write operations are harmful to the durability of the life of the memristor. In contrast, the PATH-based computing paradigm evaluates Boolean logic using read operations in the execution stage, reducing the high-energy write operations and thus prolonging the life of the system. However, the PATH-based computing paradigm faces the problem of large mapping area when mapping Boolean logic computation to a crossbar array, resulting in a large final computing cost.

[0004] The prior art discloses a method for operating a memristor array, a memristor device, a processing unit and an instruction processing method thereof. The method for operating the memristor array includes: operating weight data for array computation in a first part of the memristor array; and operating code data for execution by a processing unit in a second part of the memristor array different from the first part. The method focuses on the utilization of storage space and does not comprehensively consider factors such as the life of the memristor and the array area. SUMMARY

[0005] The present application provides a method for optimizing a memristor array, which has a small computing energy consumption and a small computing cost.

[0006] The primary object of the present application is to solve the above technical problems, and the technical solution of the present application is as follows: A method for optimizing a memristor array, comprising: S1: obtaining a Boolean function to be calculated and a memristor array to be optimized; S2: processing the to-be-calculated Boolean function by using a genetic algorithm to obtain an optimal binary decision graph; S3: optimizing the memristor array according to the optimal binary decision graph to obtain an optimal memristor array.

[0007] Further, in step S2, the to-be-calculated Boolean function is processed by using a genetic algorithm to obtain an optimal binary decision graph: S201: randomly generating a plurality of sequences as a first population; S202: determining whether a first condition is reached; if the first condition is reached, step S204 is executed; otherwise, step S203 is executed; S203: performing crossover and mutation on the first population to obtain a second population; and step S205 is executed; S204: calculating the fitness of each sequence in the first population, selecting a sequence with the minimum fitness as a first sequence; randomly generating a plurality of sequences as a new first population; adding the first sequence to the first population; and executing step S202; S205: taking the second population as a new first population; determining whether a second condition is reached; if the second condition is reached, step S206 is executed; otherwise, step S202 is executed; S206: calculating the fitness of each sequence in the first population, and selecting a sequence with the minimum fitness as an optimal sequence; S207: obtaining an optimal binary decision graph according to the optimal sequence and the to-be-calculated Boolean function.

[0008] Further, the fitness of each sequence in the first population is calculated, including: S20101: selecting one sequence in the first population as a second sequence; S20102: obtaining a binary decision graph corresponding to the second sequence according to the second sequence and the to-be-calculated Boolean function; S20103: obtaining the fitness corresponding to the second sequence according to the binary decision graph corresponding to the second sequence; S20104: selecting another sequence in the first population as a new second sequence; repeating steps S20101-S20103 until all sequences in the first population are selected; and obtaining the fitness corresponding to each sequence in the first population.

[0009] Further, the formula of the fitness calculation is as follows: Fitness = sharedSize × totalSharedEdges × (1 + log(1 + totalnPaths)) sharedSize represents the number of nodes of the second sequence corresponding to the binary decision diagram, totalSharedEdges represents the number of non-zero connection edges of the second sequence corresponding to the binary decision diagram, and totalnPaths represents the number of paths from the root node to the constant 1 node of the binary decision diagram corresponding to the second sequence.

[0010] A Boolean function calculation method, comprising: S01: obtaining a Boolean function to be calculated and a memristor array to be optimized; S02: processing the binary decision diagram to be calculated and the memristor array to be optimized by using the memristor array optimization method to obtain an optimal memristor array; S03: applying a voltage to the input end of the memristor array and detecting a current at the output end to obtain the value of the Boolean function to be calculated.

[0011] A memristor array optimization method for multiple Boolean functions, comprising: S11: obtaining multiple Boolean functions to be calculated and a memristor array to be optimized; S12: integrating the multiple Boolean functions to be calculated to form an extended Boolean function; S13: processing the extended Boolean function by using a genetic algorithm to obtain an optimal shared binary decision diagram; S14: optimizing the memristor array according to the optimal shared binary decision diagram to obtain an optimal memristor array.

[0012] A memristor array optimization system, comprising: a first parameter acquisition module configured to obtain a Boolean function to be calculated and a memristor array to be optimized; a first genetic algorithm module configured to process the Boolean function to be calculated by using a genetic algorithm to obtain an optimal binary decision diagram; a first array optimization module configured to optimize the memristor array according to the optimal binary decision diagram to obtain an optimal memristor array.

[0013] A Boolean function calculation system, comprising: a second parameter acquisition module configured to obtain a Boolean function to be calculated and a memristor array to be optimized; a second memristor optimization module configured to process a binary decision diagram to be calculated and the memristor array to be optimized by using a memristor array optimization method to obtain an optimal memristor array; a second result generation module configured to apply a voltage to the input end of the memristor array and detect a current at the output end to obtain the value of the Boolean function to be calculated.

[0014] A memristor array optimization system for multiple Boolean functions, comprising: A third parameter acquisition module: acquire multiple Boolean functions to be calculated, and a memristor array to be optimized; A third Boolean function integration module: integrate the multiple Boolean functions to be calculated to form an extended Boolean function; A third genetic algorithm module: process the extended Boolean function using a genetic algorithm to obtain an optimal shared binary decision diagram; A third array optimization module: optimize the memristor array according to the optimal shared binary decision diagram to obtain an optimal memristor array.

[0015] A computer readable storage medium, the computer readable storage medium comprising a memristor array optimization method program, the memristor array optimization method program being executed by a processor to implement the steps of the memristor array optimization method.

[0016] Compared with the prior art, the beneficial effects of the present application are: The present application optimizes the memristor array by genetic algorithm to obtain the optimal memristor array; the memristor array can reduce the use amount of memristor, and reduce the calculation energy consumption and calculation cost when calculating Boolean functions.

[0017] At the same time, for multiple Boolean functions, by comprehensively considering the calculation of multiple Boolean functions, the use amount of the generated memristor array is smaller, and the calculation energy consumption and calculation cost are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A flowchart of a memristor array optimization method provided for embodiment 1.

[0019] Figure 2 A flowchart of a genetic algorithm provided for embodiment 1.

[0020] Figure 3 A flowchart of a genetic algorithm provided for embodiment 1.

[0021] Figure 4 A flowchart of fitness calculation provided for embodiment 1.

[0022] Figure 5 A flowchart of a Boolean function calculation method provided for embodiment 1.

[0023] Figure 6 A flowchart of a memristor array optimization method for multiple Boolean functions provided for embodiment 1.

[0024] Figure 7 A schematic diagram of Boolean function integration provided for embodiment 1.

[0025] Figure 8 A schematic diagram of a memristor array optimization system provided for embodiment 1.

[0026] Figure 9 A schematic diagram of a memristor array optimization system provided for embodiment 1.

[0027] Figure 10 A schematic diagram of the relationship between a memristor array and hardware provided for embodiment 1.

[0028] Figure 11 A schematic diagram of the transformation of a binary decision diagram provided for embodiment 1.

[0029] Figure 12 A schematic diagram of the flow of a binary decision diagram mapping provided for embodiment 1. DETAILED DESCRIPTION

[0030] The accompanying drawings are only intended to illustrate, and cannot be understood as a limitation to the patent; In order to better illustrate the embodiments, some components in the drawings may be omitted, enlarged or reduced, and do not represent the actual size of the product; It can be understood by those skilled in the art that some well-known structures and their descriptions in the drawings may be omitted.

[0031] The technical solutions of the present application will be further described below in combination with the drawings and embodiments.

[0032] Embodiment 1 As shown in Figure 1 , a memristor array optimization method comprises: S1: obtaining a Boolean function to be calculated and a memristor array to be optimized; S2: processing the Boolean function to be calculated by using a genetic algorithm to obtain an optimal binary decision diagram; S3: optimizing the memristor array according to the optimal binary decision diagram to obtain an optimal memristor array.

[0033] The present application is directed to a path-based memristor architecture. Compared with the traditional computing method, the architecture only performs a write operation on the memristor in the compilation stage, that is, only applies a voltage to the memristor in the write stage to change the resistance value. In the execution of the Boolean function calculation stage, only a read operation is performed, and the resistance value of the memristor is not changed. Compared with the traditional computing framework, the architecture has better durability, and only performs a read operation in the calculation stage, so the energy consumption is lower.

[0034] Further, as Figure 2 , Figure 3As shown, in step S2, the Boolean function to be calculated is processed using a genetic algorithm to obtain the optimal binary decision graph: S201: Randomly generate multiple sequences as the first group; S202: Determine whether the first condition has been met; if the first condition has been met, proceed to step S204; otherwise, proceed to step S203. S203: Perform crossover mutation on the first population to obtain the second population; proceed to step S205; S204: Calculate the fitness of each sequence in the first group, select the sequence with the smallest fitness as the first sequence; randomly generate multiple sequences as the new first group; add the first sequence to the first group; execute step S202; S205: Treat the second population as the new first population; determine whether the second condition is met; if the second condition is met, proceed to step S206; otherwise, proceed to step S202. S206: Calculate the fitness of each sequence in the first group and select the sequence with the smallest fitness as the optimal sequence; S207: Based on the optimal sequence and the Boolean function to be calculated, the optimal binary decision graph is obtained.

[0035] In one specific embodiment, in step S201, the Fisher-Yates random shuffle algorithm is used to generate multiple sequences.

[0036] In one specific embodiment, the first condition is to determine that the number of executions without improvement is greater than a preset value.

[0037] Furthermore, such as Figure 4 As shown, the fitness of each sequence in the first population is calculated, including: S20101: Select a sequence from the first group as the second sequence; S20102: Based on the second sequence and the Boolean function to be calculated, obtain the binary decision graph corresponding to the second sequence; S20103: Obtain the fitness of the second sequence based on the binary decision graph corresponding to the second sequence; S20104: Select another sequence from the first group as the new second sequence; repeat steps S20101~S20103 until all sequences in the first group have been selected; obtain the fitness of each sequence in the first group.

[0038] Furthermore, the formula for calculating the fitness is as follows: Fitness=sharedSize×totalSharedEdges×(1+log(1+totalnPaths)) sharedSize represents the number of nodes of the second sequence corresponding to the binary decision diagram, totalSharedEdges represents the number of non-zero connection edges of the binary decision diagram corresponding to the second sequence, and totalnPaths represents the number of paths from the root node to the constant 1 node of the binary decision diagram corresponding to the second sequence.

[0039] It should be noted that the non-zero connection edge refers to all edges in a binary decision diagram except the edge connected to the constant 0 node; all non-zero paths in a binary decision diagram are totalnPaths, and the non-zero path refers to a path in a binary decision diagram from the root node to the constant 1 node. In the mapping process, the number of non-zero connection edges and the number of all nodes in the binary decision diagram or the shared binary decision diagram determine the number of columns and rows of the memristor cross array, so the fitness function is optimized for the number of non-zero connection edges. For the same binary decision diagram, different variable orders generate different binary decision diagram structures, which provides the possibility of optimization. The introduction of non-zero path is the result of reducing the number of non-zero connection edges from another aspect, but the value of this index is too large to prevent affecting the judgment of fitness, and the logarithm is taken for weakening processing.

[0040] As shown in Figure 5 , a Boolean function calculation method comprises the following steps: S01: obtaining a Boolean function to be calculated and a memristor array to be optimized; S02: processing the binary decision diagram to be calculated and the memristor array to be optimized by using the memristor array optimization method to obtain an optimal memristor array; S03: applying a voltage to the input end of the memristor array and detecting the current at the output end to obtain the value of the Boolean function to be calculated.

[0041] As shown in Figure 6 , a memristor array optimization method for multiple Boolean functions comprises the following steps: S11: obtaining multiple Boolean functions to be calculated and a memristor array to be optimized; S12: integrating the multiple Boolean functions to be calculated to form an extended Boolean function; S13: processing the extended Boolean function by using a genetic algorithm to obtain an optimal shared binary decision diagram; S14: optimizing the memristor array according to the optimal shared binary decision diagram to obtain an optimal memristor array.

[0042] As shown in Figure 7 , two Boolean functions or two binary decision diagrams can be integrated into a shared binary decision diagram (extended Boolean function). The Boolean function and the binary decision diagram can be converted into each other.

[0043] As Figure 8 , Figure 9 , Figure 10 illustrated, a memristor array optimization system comprises: A first parameter acquisition module: obtaining a Boolean function to be calculated, and a memristor array to be optimized; A first genetic algorithm module: using a genetic algorithm to process the Boolean function to be calculated, to obtain an optimal binary decision graph; A first array optimization module: according to the optimal binary decision graph, optimizing the memristor array to obtain an optimal memristor array.

[0044] A Boolean function calculation system comprises: A second parameter acquisition module: obtaining a Boolean function to be calculated, and a memristor array to be optimized; A second memristor optimization module: using a memristor array optimization method to process the binary decision graph to be calculated and the memristor array to be optimized, to obtain an optimal memristor array; A second result generation module: applying a voltage to the input end of the memristor array, detecting the current at the output end, and obtaining the value of the Boolean function to be calculated.

[0045] A memristor array optimization system for multiple Boolean functions comprises: A third parameter acquisition module: obtaining multiple Boolean functions to be calculated, and a memristor array to be optimized; A third Boolean function integration module: integrating the multiple Boolean functions to be calculated to form an extended Boolean function; A third genetic algorithm module: using a genetic algorithm to process the extended Boolean function, to obtain an optimal shared binary decision graph; A third array optimization module: according to the optimal shared binary decision graph, optimizing the memristor array to obtain an optimal memristor array.

[0046] A computer readable storage medium comprises a memristor array optimization method program, which is executed by a processor to implement the steps of the memristor array optimization method.

[0047] As Figure 11 illustrated, a Boolean function can be converted into an unsimplified binary decision graph in a certain order, and the unsimplified binary decision graph can be converted into a binary decision graph after conversion.

[0048] As Figure 12 illustrated, in step S3, the preprocessed binary decision graph is mapped into a bipartite graph, and the specific steps include: (1) All the nodes with serial numbers form a set as U1 of the bipartite graph; (2) All the edges with variable values form a set as U2; (3) The mapping from U1 to U2 is constructed according to the relationship between the edges and nodes in the original directed graph, and the mapping forms an edge set F; The bipartite graph is compressed to optimize the area of the final mapping, and the compression steps are as follows: according to the equivalence of the Boolean variables, the nodes in the U2 set are merged, and if multiple edges F have the same source node U1 and the U2 nodes pointed by the multiple edges F are the same, the U2 nodes are merged. The bipartite graph after the compression operation is taken as the final bipartite graph.

[0049] In step S03, each node in U1 is allocated as a word line of the cross array, and each node in U2 is allocated as a bit line. For the edge set F, at the intersection of the word line and the bit line, that is, at the connection of U1 and U2, the memristor is programmed to a low resistance state. The non-connection intersection point remains in a high resistance state. The variables in the Boolean function are bound to the corresponding bit line, and current is passed through the corresponding bit line according to the variables of the Boolean function. If the value of the variable in the Boolean function is 1, current is passed through the bit line, otherwise no current is passed through the bit line. Voltage is applied to the word line corresponding to the input node, and current is detected on the word line corresponding to the output node. The detected current result represents the value of the Boolean function.

[0050] The same or similar reference signs correspond to the same or similar components; The terms used to describe the positional relationship in the drawings are only used for illustrative description, and should not be understood as a limitation on the patent; Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the implementation modes of the present application. For those skilled in the art, on the basis of the above description, other different forms of changes or variations can also be made. Here, it is not necessary and impossible to exhaust all the implementation modes. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A method of optimizing a memristor array, comprising: The method comprises the following steps: S1: obtaining a Boolean function to be calculated and a memristor array to be optimized; S2: processing the Boolean function to be calculated by using a genetic algorithm to obtain an optimal binary decision graph; S3: optimizing the memristor array according to the optimal binary decision graph to obtain an optimal memristor array.

2. The method of claim 1, wherein, In step S2, the Boolean function to be calculated is processed by using a genetic algorithm to obtain an optimal binary decision graph: S201: randomly generating a plurality of sequences as a first population; S202: determining whether a first condition is reached; if the first condition is reached, step S204 is performed; otherwise, step S203 is performed; S203: performing crossover and mutation on the first population to obtain a second population; and step S205 is performed; S204: calculating the fitness of each sequence in the first population, selecting a sequence with the minimum fitness as a first sequence, randomly generating a plurality of sequences as a new first population, adding the first sequence to the first population, and performing step S202; S205: taking the second population as a new first population; and determining whether a second condition is reached; if the second condition is reached, step S206 is performed; otherwise, step S202 is performed; S206: calculating the fitness of each sequence in the first population, and selecting a sequence with the minimum fitness as an optimal sequence; S207: obtaining an optimal binary decision graph according to the optimal sequence and the Boolean function to be calculated.

3. The method of claim 2, wherein, The fitness of each sequence in the first population is calculated, comprising: S20101: selecting one sequence in the first population as a second sequence; S20102: obtaining a binary decision graph corresponding to the second sequence according to the second sequence and the Boolean function to be calculated; S20103: obtaining the fitness corresponding to the second sequence according to the binary decision graph corresponding to the second sequence; S20104: selecting another sequence in the first population as a new second sequence; repeating steps S20101-S20103 until all sequences in the first population are selected; and obtaining the fitness corresponding to each sequence in the first population.

4. The method of claim 3, wherein, The formula for calculating the fitness is as follows: Fitness=sharedSize×totalSharedEdges×(1+log(1+totalnPaths)) sharedSize represents the number of nodes of the binary decision graph corresponding to the second sequence, totalSharedEdges represents the number of non-zero connection edges of the binary decision graph corresponding to the second sequence, and totalnPaths represents the number of paths from the root node to the constant 1 node of the binary decision graph corresponding to the second sequence.

5. A method of Boolean function computation, characterized by, The method comprises the following steps: S01: obtaining a Boolean function to be calculated and a memristor array to be optimized; S02: processing the binary decision graph to be calculated and the memristor array to be optimized by using the memristor array optimization method according to any one of claims 1-4 to obtain an optimal memristor array; S03: applying a voltage to an input end of the memristor array, detecting a current at an output end, and obtaining a value of the Boolean function to be calculated.

6. A method for optimizing memristor arrays for multiple Boolean functions, characterized in that, The method comprises the following steps: S11: obtaining a plurality of Boolean functions to be calculated and a memristor array to be optimized; S12: integrate the plurality of Boolean functions to be calculated to form an extended Boolean function; S13: processing the extended Boolean function by using a genetic algorithm to obtain an optimal shared binary decision diagram; S14: according to the optimal shared binary decision diagram, optimizing the memristor array to obtain an optimal memristor array.

7. A memristor array optimization system, applied to the memristor array optimization method of any one of claims 1-4, characterized in that, Comprise: The first parameter acquisition module: obtain the Boolean function to be calculated, the memristor array to be optimized; The first genetic algorithm module: processing the Boolean function to be calculated by using a genetic algorithm to obtain an optimal binary decision diagram; The first array optimization module: according to the optimal binary decision diagram, optimizing the memristor array to obtain an optimal memristor array.

8. A Boolean function computing system applied to the computing method of claim 5, wherein, Comprise: The second parameter acquisition module: obtain the Boolean function to be calculated, the memristor array to be optimized; The second memristor optimization module: processing the binary decision diagram to be calculated and the memristor array to be optimized by using a memristor array optimization method to obtain an optimal memristor array; The second result generation module: applying a voltage to the input end of the memristor array, detecting the current at the output end, and obtaining the value of the Boolean function to be calculated.

9. A memristor array optimization system for a plurality of Boolean functions, applied to the optimization method of claim 6, characterized in that, Comprise: The third parameter acquisition module: obtain a plurality of Boolean functions to be calculated, and a memristor array to be optimized; The third Boolean function integration module: integrating the plurality of Boolean functions to be calculated to form an extended Boolean function; The third genetic algorithm module: processing the extended Boolean function by using a genetic algorithm to obtain an optimal shared binary decision diagram; The third array optimization module: according to the optimal shared binary decision diagram, optimizing the memristor array to obtain an optimal memristor array.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises a memristor array optimization method program, and when the processor executes the memristor array optimization method program, the steps of the memristor array optimization method in any one of claims 1 to 4 are realized.

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