Preparation method of ESD (Electro-Static Discharge) device and ESD device

Abstract

The invention provides a preparation method of an ESD (Electro-Static Discharge) device and the ESD device. The preparation method of the ESD device comprises the following steps that a substrate is provided, the substrate comprises a substrate body, a high-voltage P well region and a deep N well region which are formed on the substrate body, and a first oxide layer covering the surfaces of the high-voltage P well region and the deep N well region, and the high-voltage P well region and the deep N well region are arranged in the first direction parallel to the substrate body; forming a first trench isolation structure on the substrate, wherein the first trench isolation structure isolates the high-voltage P well region from the deep N well region; a grid grounding NMOS structure is formed on the high-voltage P well region, a Schottky barrier diode structure and a voltage stabilizing diode structure are formed on the deep N well region, the Schottky barrier diode structure and the voltage stabilizing diode structure are arranged in a staggered mode in the second direction parallel to the substrate, and the second direction is perpendicular to the first direction. According to the ESD device, stepped protection can be formed, ESD impact is in smooth transition, current distribution is uniform, and the reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a preparation method of an ESD device and the ESD device. BACKGROUND

[0002] With the continuous progress of semiconductor manufacturing process, the chip and electronic product failure problem caused by electrostatic discharge (ESD) is increasingly prominent, which has become an important challenge for engineers. At present, the ESD protection device used in the 40HV platform is mainly constructed based on the principle of gated grounded N-MOS (GGNMOS), and its working mechanism is as follows: when the electrostatic discharge current flows from the anode, the potential of the high-voltage P-well (HVPW) is lifted through the reverse breakdown effect between the low-voltage N-well (LVNW) and the high-voltage P-well (HVPW) of the anode, so as to trigger the parasitic bipolar junction transistor (BJT) structure (consisting of the anode N + Drain-LVNW / Cathode P + -LVPW-HVPW / Cathode N + -LVNW) to conduct, so as to discharge the ESD current. The trigger voltage of the structure is usually above 4V, which is suitable for ESD protection under the middle and high voltage process. However, in more advanced processes, such a higher trigger voltage is difficult to meet the protection needs of sensitive circuits, and on the contrary, the internal sensitive device may be damaged due to response lag. SUMMARY

[0003] The present application provides a preparation method of an ESD device and the ESD device, so as to reduce the trigger voltage of the ESD device.

[0004] The present application provides a preparation method of an ESD device, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a high-voltage P-well and a deep N-well formed on the substrate, and a first oxide layer covering the surface of the high-voltage P-well and the deep N-well, and the high-voltage P-well and the deep N-well are arranged along a first direction parallel to the substrate; forming a first trench isolation structure on the substrate, wherein the first trench isolation structure separates the high-voltage P-well and the deep N-well; A gate-ground NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a zener diode structure are formed on the deep N-well region, the Schottky barrier diode structure and the zener diode structure being staggered along a second direction parallel to the substrate, the second direction being perpendicular to the first direction.

[0005] In an embodiment of the present application, the number of the first trench isolation structures is plural, the plural first trench isolation structures are arranged at intervals along the first direction, and the high-voltage P-well region is sequentially isolated into a P-ion implantation region, an N-ion implantation region, a gate formation region, an N-ion implantation region, and the deep N-well region is sequentially isolated into a first region and an N-ion implantation region on the high-voltage P-well region along a direction from the high-voltage P-well region to the deep N-well region. While the plural first trench isolation structures are formed on the substrate, the method for manufacturing the ESD device further comprises forming plural second trench isolation structures on the substrate, the plural second trench isolation structures are located in the middle of the first region and arranged at intervals along the second direction, an N-ion implantation region is formed in the gap between the second trench isolation structures, and a P-ion implantation region extending along the second direction is formed in the first region on both sides of the second trench isolation structures along the first direction.

[0006] In an embodiment of the present application, a gate-ground NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a zener diode structure are formed on the deep N-well region, the Schottky barrier diode structure and the zener diode structure being staggered along a second direction parallel to the substrate, comprising the following steps: A first P-ion implantation is performed on the P-ion implantation region to form a low-voltage P-well region, and a first N-ion implantation is performed on the N-ion implantation region to form a low-voltage N-well region; A gate structure is formed on the surface of the gate formation region; A second P-ion implantation is performed on the P-ion implantation region to form a P+-doped region, and a second N-ion implantation is performed on the N-ion implantation region outside the first region to form an N+-doped region.

[0007] In an embodiment of the present application, while the plural first trench isolation structures are formed on the substrate, the method for manufacturing the ESD device further comprises forming plural second trench isolation structures on the substrate, comprising the following steps: A patterned third photoresist layer is formed on the surface of the first oxide layer, the third photoresist layer exposing the first trench region and the second trench region; The first oxide layer and the substrate are etched in sequence to form plural first trenches and plural second trenches on the substrate; Depositing an insulating medium in the first and second trenches to cover the surface of the first oxide layer; Performing a planarization process on the insulating medium to make the insulating medium level with the first oxide layer, forming the first and second trench isolation structures.

[0008] In an embodiment of the present application, the ion concentration of the high-voltage P well region is 5E11~1E13 / cm 3 , the ion concentration of the deep N well region is 5E11~1E13 / cm 3 .

[0009] In an embodiment of the present application, the ion concentration of the low-voltage P well region is 1E12~5E14 / cm 3 , the ion concentration of the low-voltage N well region is 1E12~5E14 / cm 3 , the ion concentration of the P+ doped region is 5E13~1E16 / cm 3 , the ion concentration of the N+ doped region is 5E13~1E16 / cm 3 .

[0010] In an embodiment of the present application, a gate structure is formed on the surface of the gate formation region, comprising the following steps: Removing the first oxide layer to form a nitride layer on the surface of the substrate; Using a patterned photoresist as a mask to etch the nitride layer, and the nitride layer exposes the gate formation region; Forming a gate oxide layer on the surface of the gate formation region; Forming a gate material layer on the surface of the gate oxide layer.

[0011] In an embodiment of the present application, after forming the P+ doped region and the N+ doped region, the preparation method of the ESD device further comprises forming a self-aligned silicide layer on the surface of the P ion implantation region, the N ion implantation region and the gate structure, comprising the following steps: Depositing a self-aligned silicide barrier layer on the surface of the substrate, and the self-aligned silicide barrier layer exposes the surface of the P ion implantation region, the N ion implantation region and the gate structure; Depositing a first contact material layer on the surface of the P ion implantation region, the N ion implantation region and the gate structure; Sequentially performing a first annealing process and a second annealing process.

[0012] In an embodiment of the present application, the preparation method of the substrate comprises the following steps: Providing the substrate; depositing a first oxide layer on the substrate; performing P ion implantation on the substrate to form a high-voltage P well region by taking the patterned first photoresist layer as a mask layer; performing N ion implantation on the substrate to form a deep N well region by taking the patterned second photoresist layer as a mask layer.

[0013] The application further provides an ESD device, which comprises a substrate, a gate-grounded NMOS structure, a Schottky barrier diode structure and a zener diode structure; the substrate comprises a substrate and a high-voltage P well region and a deep N well region formed on the substrate, the high-voltage P well region and the deep N well region are isolated by a trench isolation structure and are arranged along a first direction parallel to the substrate; the gate-grounded NMOS structure is formed on the high-voltage P well region; the Schottky barrier diode structure is arranged on the deep N well region; the zener diode structure is arranged on the deep N well region and is staggered with the Schottky barrier diode structure along a second direction parallel to the substrate, the second direction is perpendicular to the first direction.

[0014] The application provides an ESD device preparation method, the high-voltage P well region and the deep N well region are isolated by the first trench isolation structure and are arranged along the first direction parallel to the substrate, the gate-grounded NMOS structure is formed on the high-voltage P well region, the Schottky barrier diode structure and the zener diode structure are formed on the deep N well region, the Schottky barrier diode structure and the zener diode structure are staggered along the second direction parallel to the substrate, and the second direction is perpendicular to the first direction. The unexpected effect of the application is that when a low-energy pulse comes, the Schottky barrier diode structure can clamp the ESD voltage quickly due to the extremely low forward voltage drop and picosecond-level response speed. When a high-energy pulse comes, the multiple Schottky barrier diode structures in parallel can absorb the initial ESD peak, and then the zener diode structure and the gate-grounded NMOS structure open to become the main discharge path, maintaining the large-current discharge capability. When the gate-grounded NMOS structure is in parallel with the multiple Schottky barrier diode structures and the zener diode structure, a multi-stage voltage clamping can be formed to provide step-by-step protection for the key potentials at medium and low voltages. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles behind the application. It is readily apparent to one skilled in the art that the following description in the drawings merely illustrates some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0016] In the drawings: Figure 1This is a flowchart illustrating the fabrication process of an ESD device according to an embodiment of the present invention. Figure 2 This is a schematic diagram of forming a first oxide layer on a substrate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the formation of a high-pressure P-well region provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of forming a deep N-well region according to an embodiment of the present invention; Figure 5 This is a schematic diagram of removing the second photoresist layer according to one embodiment of the present invention; Figure 6 This is a schematic diagram of the formation of a third photoresist layer provided in one embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the formation of a first trench and a second trench according to one embodiment of the present invention; Figure 8 This is a schematic diagram of the formation of a first trench isolation structure and a second trench isolation structure provided in one embodiment of the present invention; Figure 9 This is a top view schematic diagram of the formation of the first trench isolation structure and the second trench isolation structure provided in one embodiment of the present invention; Figure 10 This is a schematic diagram of the first P-ion implantation in a P-ion implantation region provided in one embodiment of the present invention; Figure 11 This is a schematic diagram of the first N-ion implantation in an N-ion implantation region provided in one embodiment of the present invention; Figure 12 This is a schematic diagram of the formation of a nitride layer provided in one embodiment of the present invention; Figure 13 This is a schematic diagram of an etched nitride layer provided in one embodiment of the present invention; Figure 14 This is a schematic diagram of the formation of a gate oxide layer provided in one embodiment of the present invention; Figure 15 This is a schematic diagram of forming a polycrystalline silicon layer according to an embodiment of the present invention; Figure 16 This is a schematic diagram of the formation of a gate material layer provided in one embodiment of the present invention; Figure 17 This is a schematic diagram of a second P-ion implantation in a P-ion implantation region provided in one embodiment of the present invention; Figure 18 This is a schematic diagram of a second N-ion implantation in an N-ion implantation region provided in one embodiment of the present invention; Figure 19 for Figure 18 Corresponding top view diagram; Figure 20 Fig. 1 is a schematic diagram of a cross section along the direction B-B; Figure 19 Fig. 2 is a schematic diagram of a cross section along the direction B-B; Figure 21 Fig. 3 is a schematic diagram of forming a second oxide layer in an embodiment of the present application; Figure 22 Fig. 4 is a schematic diagram of forming a self-aligned silicide block layer in an embodiment of the present application; Figure 23 Fig. 5 is a schematic diagram of forming a first contact material layer in an embodiment of the present application; Figure 24 Fig. 6 is a schematic diagram of forming an initial self-aligned silicide layer in an embodiment of the present application; Figure 25 Fig. 7 is a schematic diagram of forming a self-aligned silicide layer in an embodiment of the present application; Figure 26 Fig. 8 is another schematic diagram of forming a self-aligned silicide layer in an embodiment of the present application; Figure 27 Fig. 9 is a schematic diagram of electrode connection of an ESD device in an embodiment of the present application; Figure 28 Fig. 10 is another schematic diagram of electrode connection of an ESD device in an embodiment of the present application; Figure 29 Fig. 11 is a current-voltage relationship diagram of an ESD device in an embodiment of the present application and a prior art ESD device.

[0017] Reference signs are as follows: 10, substrate; 100, substrate; 110, high-voltage P well region; 120, deep N well region; 130, first trench isolation structure; 140, second trench isolation structure; 150, P ion implantation region; 151, low-voltage P well region; 152, P+ doped region; 160, N ion implantation region; 161, low-voltage N well region; 162, N+ doped region; 170, gate formation region; 171, gate structure; 1711, gate oxide layer; 1712, gate material layer; 180, first region; 200, first oxide layer; 300, second photoresist layer; 310, third photoresist layer; 320, fourth photoresist layer; 330, fifth photoresist layer; 340, fifth photoresist layer; 400, nitride layer; 500, polysilicon layer; 600, second oxide layer; 610, self-aligned silicide block layer; 700, first contact material layer; 710, initial self-aligned silicide layer; 720, self-aligned silicide layer; 20, gate-grounded NMOS structure; 30, Schottky barrier diode structure; 40, zener diode structure. DETAILED DESCRIPTION

[0018] Following, the embodiments of the present application will be described in details by specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of this specification. The present application can also be implemented or applied by other different embodiments, and each detail in this specification can be modified or changed based on different views and applications without departing from the spirit of the present application, and the following examples and features in the examples can be combined with each other without conflict.

[0019] It should be noted that the diagrams provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and the components shown in the drawings are not drawn according to the number, shape and size of the components in actual implementation, and the shape, number and ratio of each component in actual implementation can be arbitrarily changed, and the layout pattern of the components can also be more complex.

[0020] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present application, however, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details, and in other embodiments, the known structures and devices are shown in the form of block diagrams rather than in the form of details to avoid making the embodiments of the present application difficult to understand.

[0021] Please refer to Figures 1 to 20 , the present application provides a preparation method of an ESD device, comprising the following steps: S1, providing a substrate 10 as shown in Figure 5 , the substrate 10 comprises a substrate 100 and a high-voltage P-well region 110 and a deep N-well region 120 formed on the substrate 100, and a first oxide layer 200 covering the surface of the high-voltage P-well region 110 and the deep N-well region 120, the high-voltage P-well region 110 and the deep N-well region 120 are arranged along a first direction (i.e. the X direction in Figure 5 ) parallel to the substrate 100.

[0022] S2, as shown in Figures 6 to 9 , a first trench isolation structure 130 is formed on the substrate 10, the first trench isolation structure 130 separates the high-voltage P-well region 110 and the deep N-well region 120.

[0023] S3, as shown in Figures 10 to 20 , a gate-grounded NMOS structure 20 is formed on the high-voltage P-well region 110, a Schottky barrier diode structure 30 and a voltage regulator diode structure 40 are formed on the deep N-well region 120, the Schottky barrier diode structure 30 and the voltage regulator diode structure 40 are staggered arranged along a second direction (i.e. the Y direction in Figure 9 ) parallel to the substrate 100, the second direction is perpendicular to the first direction.

[0024] The substrate 10 can be a semi-finished product purchased from a third party or prepared by the manufacturer. In one embodiment, the substrate 10 is prepared by the manufacturer on the basis of a substrate 100. Please refer to Figures 2 to 5 As shown in FIG. 1, the substrate 10 is prepared as follows: Please refer to Figure 2 As shown in FIG. 1, the substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc. The present application does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate 100 or an N-doped semiconductor substrate 100. The type of impurity doping can be flexibly set according to the semiconductor structure to be formed. In the present embodiment, the substrate 100 is, for example, a P-doped semiconductor substrate.

[0025] Please refer to Figure 2 As shown in FIG. 1, in one embodiment of the present application, a first oxide layer 200 is formed on the surface of the substrate 100. The first oxide layer 200 can serve as a protective layer for the substrate 100 and protect the substrate 100 covered thereby in subsequent processes, so as to avoid unnecessary damage to the substrate 100. The material of the first oxide layer 200 can be silicon dioxide or the like, and the first oxide layer 200 can be formed by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, or an in-situ steam generation (ISSG) method, for example. In the present embodiment, the first oxide layer 200 is formed by a dry oxygen oxidation method, for example. Illustratively, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with the oxygen at high temperature to form a dense first oxide layer 200. The preparation process of the substrate 10 can further include cleaning the substrate 100 before forming the first oxide layer 200 thereon, so as to remove impurities present on the surface of the substrate 100 and avoid the influence of the impurities on subsequent processes, thereby ensuring the performance of the device. Illustratively, the substrate 100 can be cleaned using a cleaning solution to achieve cleaning of the substrate 100, or the substrate 100 can be purged using a gas such as nitrogen to achieve cleaning of the substrate 100.

[0026] Please refer to Figures 3 to 5As shown, in one embodiment of the present invention, after forming a first oxide layer 200, a patterned first photoresist layer 300 is formed on the surface of the first oxide layer 200. Using the first photoresist layer 300 as a mask layer, P-type ion implantation is performed on the substrate 100 to form a high-voltage P-well region 110. The P-type ions are, for example, boron (B) or gallium (Ga). After removing the first photoresist layer 300, a patterned second photoresist layer 310 is formed on the surface of the first oxide layer 200. Using the second photoresist layer 310 as a mask layer, N-type ion implantation is performed on the substrate 100 to form a deep N-well region 120. The N-type ions are, for example, phosphorus (P) or arsenic (As). After forming the deep N-well region 120, the second photoresist layer 310 is removed. The high-voltage P-well region 110 and the deep N-well region 120 are arranged along a first direction parallel to the substrate 100. The type of photoresist material for the first photoresist layer 300 and the second photoresist layer 310 is not limited here; it can be a common positive photoresist material or a negative photoresist material. For example, the first photoresist layer 300 and the second photoresist layer 310 can be removed by wet cleaning or ashing. Exemplarily, the ion concentration in the high-voltage P-well region 110 can be 5E11~1E13 / cm³. 3 For example, 5E11 / cm 3 1E12 / cm 3 1E13 / cm 3 5E11~1E13 / cm 3 Any value in the range. The ion concentration in the deep N-well region 120 can be 5E11~1E13 / cm³. 3 For example, 5E11 / cm 3 1E12 / cm 3 1E13 / cm 3 5E11~1E13 / cm 3 Any value in the range.

[0027] In step S2 of this invention, the number of first trench isolation structures 130 is multiple. While forming multiple first trench isolation structures 130 on the substrate 10, the ESD device fabrication method also includes forming multiple second trench isolation structures 140 on the substrate 10. Please refer to... Figures 6 to 9 As shown, forming a plurality of first trench isolation structures 130 and a plurality of second trench isolation structures 140 on the substrate 10 includes the following steps: Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, a patterned third photoresist layer 320 is formed on the surface of the first oxide layer 200, and the third photoresist layer 320 exposes the first trench region and the second trench region. Figure 6etching the first oxide layer 200 and the substrate 100 in sequence with the third photoresist layer 320 as a mask layer to form a plurality of first grooves and a plurality of second grooves. The number, position, depth, width and other parameters of the first grooves and the second grooves are set according to actual needs, which are not limited herein. In this embodiment, the first grooves and the second grooves extend from the first oxide layer 200 into the substrate 100, and the shapes of the first grooves and the second grooves are rectangular. The first grooves and the second grooves can be formed by dry etching to remove the first oxide layer 200 and part of the substrate 100 in sequence. The etching gas includes one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination of them and oxygen (O2). After the first grooves and the second grooves are formed, the third photoresist layer 320 is removed, for example, by wet cleaning or ashing treatment.

[0028] Please refer to Figure 8 and Figure 9 In an embodiment of the present application, after the first grooves and the second grooves are formed, an insulating medium is deposited in the plurality of first grooves and the plurality of second grooves until the insulating medium covers the surface of the first oxide layer 200. The present application does not limit the deposition method of the insulating medium. For example, the insulating medium can be deposited by high-density plasma chemical vapor deposition (HDP CVD) or high aspect ratio process chemical vapor deposition (HARP CVD). ​The insulating medium is deposited using methods such as CVD (chemical vapor deposition). The insulating medium is, for example, a highly abrasive insulating material such as silicon oxide or fluorosilicone glass. After deposition, a high-temperature tempering process is performed to increase the density and stress characteristics of the insulating medium. After deposition, the insulating medium is planarized, for example, by chemical mechanical polishing, to obtain multiple first trench isolation structures 130 and multiple second trench isolation structures 140. The first trench isolation structures 130 and the second trench isolation structures 140 are at least partially exposed on the substrate 100. This invention does not limit the planarization of the insulating medium to a specific location; it can be placed at any location according to the semiconductor device design requirements. For example, the insulating medium in the first and second trenches can be planarized to be flush with the first oxide layer 200. In this embodiment, a plurality of first trench isolation structures 130 are spaced apart along a first direction to isolate the high-voltage P-well region 110 and the deep N-well region 120. Along the direction from the high-voltage P-well region 110 to the deep N-well region 120, a P-ion implantation region 150, an N-ion implantation region 160, a gate formation region 170, and an N-ion implantation region 160 are sequentially isolated on the high-voltage P-well region 110. A first region 180 and an N-ion implantation region 160 are sequentially isolated on the deep N-well region 120. A plurality of second trench isolation structures 140 are located in the middle of the first region 180 and are spaced apart along a second direction parallel to the substrate 100 and perpendicular to the first direction. An N-ion implantation region 160 is formed within the gaps between the second trench isolation structures 140. A P-ion implantation region 150 extending along the second direction is formed within the first region 180 on both sides of the second trench isolation structure 140 along the first direction.

[0029] Please see Figure 10 As shown, in one embodiment of the present invention, after forming the first trench isolation structure 130 and the second trench isolation structure 140, a patterned fourth photoresist layer 330 is formed on the surface of the first oxide layer 200, and the fourth photoresist layer 330 exposes the first oxide layer 200 above the P-ion implantation region 150. Figure 10 In the area not covered by the fourth photoresist layer 330, a first P-ion implantation is performed on the P-ion implantation region 150 to form a low-pressure P-well region 151. P-type ions are, for example, boron (B) or gallium (Ga). After forming the low-pressure P-well region 151, the fourth photoresist layer 330 is removed, for example, by wet cleaning or ashing. The ion concentration of the low-pressure P-well region 151 can be 1E12~5E14 / cm³. 3 For example, 1E12 / cm 3 5E13 / cm 3 5E14 / cm 3 1E12~5E14 / cm 3 Any value in the range.

[0030] Please see Figure 11As shown, in one embodiment of the present invention, after removing the fourth photoresist layer 330, a patterned fifth photoresist layer 340 is formed on the surface of the first oxide layer 200, and the fifth photoresist layer 340 exposes the first oxide layer 200 above the N ion implantation region 160. Figure 11 In the area not covered by the fifth photoresist layer 340, a first N-ion implantation is performed on the N-ion implantation region 160 to form a low-pressure N-well region 161. N-type ions are, for example, phosphorus (P) or arsenic (As). After forming the low-pressure N-well region 161, the fifth photoresist layer 340 is removed, for example, by wet cleaning or ashing. The ion concentration of the low-pressure N-well region 161 can be 1E12~5E14 / cm³. 3 For example, 1E12 / cm 3 5E13 / cm 3 5E14 / cm 3 1E12~5E14 / cm 3 Any value in the range. This application does not restrict the formation order of the low-pressure P-well region 151 and the low-pressure N-well region 161. In some embodiments, the low-pressure N-well region 161 may be formed first and then the low-pressure P-well region 151 may be formed.

[0031] Please see Figure 12 As shown, in one embodiment of the present invention, after removing the fifth photoresist layer 340, the first oxide layer 200 is removed, and a nitride layer 400 is formed on the surface of the substrate 100. The material of the nitride layer 400 can be silicon nitride or oxynitride. In this embodiment, the nitride layer 400 is, for example, a silicon nitride (SiN) layer. The nitride layer 400 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. Exemplarily, when preparing the nitride layer 400 using a low-pressure chemical vapor deposition process, silicon nitride can be formed by reacting ammonia and dichlorosilane. Exemplarily, after removing the first oxide layer 200 and before forming the nitride layer 400, etching of the insulating medium may be performed to adjust the height of the first trench isolation structure 130 and the second trench isolation structure 140, such that the first trench isolation structure 130 and the second trench isolation structure 140 are flush with the substrate 100.

[0032] Please see Figures 13 to 16As shown in the figure, in an embodiment of the present application, after the nitride layer 400 is formed, the nitride layer 400 is etched using the patterned photoresist layer as a mask layer, and the gate formation region 170 is exposed. Then, the gate structure 171 is formed on the gate formation region 170. For example, first, the gate oxide layer 1711 is formed on the surface of the substrate 100. Then, the gate material layer 1712 is formed on the surface of the gate oxide layer 1711. The material of the gate material layer 1712 is, for example, polysilicon. Specifically, the gate formation region 170 is oxidized to form the gate oxide layer 1711 on the surface of the gate formation region 170. For example, the substrate 100 is placed in a furnace tube, and oxygen is introduced into the furnace tube. The surface of the substrate 100 exposed by the gate formation region 170 reacts with the oxygen at a high temperature to form the gate oxide layer 1711. After the gate oxide layer 1711 is formed, the nitride layer 400 is removed, and the polysilicon layer 500 is deposited on the surface of the substrate 100. The polysilicon layer 500 is etched using the patterned photoresist layer as a mask layer to form the gate material layer 1712 on the surface of the gate oxide layer 1711. The present application does not limit the method for removing the nitride layer 400. For example, the nitride layer 400 can be removed by a dry etching method, a wet etching method, or a combination of the dry etching method and the wet etching method. For example, the polysilicon layer 500 can be etched by a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process.

[0033] As shown in the figure, Figure 17 and Figure 18 As shown in the figure, in an embodiment of the present application, after the gate material layer 1712 is formed, the P ion implantation region 150 is implanted with P ions for a second time to form the P+ doped region 152, and the N ion implantation region 160 is implanted with N ions for a second time to form the N+ doped region 162, using the patterned photoresist layer as a mask layer. The P ions are, for example, boron (B) or gallium (Ga), and the N ions are, for example, phosphorus (P) or arsenic (As). For example, the ion concentration of the P+ doped region 152 can be any value in the range of 5E13 / cm3~1E16 / cm3, such as 5E13 / cm3, 1E15 / cm3, 1E16 / cm3, or the like. 3 3 3 3 3 3 3 3 3 3

[0034] As shown in the figure, Figure 19 ​​​​​​​​​​As shown, after forming the P+ doped region 152 and the N+ doped region 162, the gate-ground NMOS structure 20 is formed on the high-voltage P-well region 110, the Schottky barrier diode structure 30 and the zener diode structure 40 are formed on the deep N-well region 120, and the Schottky barrier diode structure 30 and the zener diode structure 40 are staggered along a second direction parallel to the substrate 100, and the second direction is perpendicular to the first direction. Figure 18 A cross-sectional view of the Schottky barrier diode structure 30 formed after the second N ion implantation to the N ion implantation region 160 is shown in FIG. 3B. Figure 19 A cross-sectional view along the A-A direction is shown in FIG. 4A. Figure 20 A cross-sectional view along the B-B direction is shown in FIG. 4B. Figure 19 A cross-sectional view along the B-B direction is shown in FIG. 4B.

[0035] In an embodiment of the present application, to ensure the connection between the prepared ESD device and the external circuit, the preparation of the ESD device further includes forming a self-aligned silicide layer 720 on the surface of the P ion implantation region 150, the N ion implantation region 160 and the gate structure 171. Please refer to FIG. 5A. Figures 21 to 25 As shown, the formation of the self-aligned silicide layer 720 includes the following steps: Please refer to FIG. 5A. Figures 21 to 23 As shown, in an embodiment of the present application, the self-aligned silicide layer 720 is formed by the following steps: Figure 18 Taking the cross-section of the Schottky barrier diode structure 30 as an example, after forming the P+ doped region 152 and the N+ doped region 162, a second oxide layer 600 is deposited on the surface of the substrate 10, and the second oxide layer 600 is etched with a patterned photoresist layer as a mask layer to form a self-aligned silicide barrier layer 610 on the surface of the substrate 10, and the self-aligned silicide barrier layer 610 exposes the surface of the P ion implantation region 150, the N ion implantation region 160 and the gate structure 171. A first contact material layer 700 is deposited on the surface of the substrate 10. The first contact material layer 700 can be formed by any process, such as physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process or atomic layer epitaxy process, etc. In this embodiment, the first contact material layer 700 is formed on the substrate 10 by physical vapor deposition, and the first contact material layer 700 is, for example, a NiPt layer. For example, the thickness of the NiPt layer is 100-150 Å, such as 100 Å, 120 Å or 150 Å, etc.

[0036] Please refer to FIG. 5A. Figure 24In some embodiments, after the first contact material layer 700 is deposited, a first annealing process is performed. The first annealing process can be performed at a temperature ranging from 200 °C to 400 °C, for example, for a time period ranging from 20 s to 40 s. For example, the first annealing process can be performed at a temperature of 200 °C, 300 °C, or 400 °C, or any temperature within the range from 200 °C to 400 °C, and for a time period of 20 s, 30 s, or 40 s, or any time period within the range from 20 s to 40 s. The first annealing process can cause the NiPt layer to react with the P ion implantation region 150, the N ion implantation region 160, and the surface Si of the gate structure 171 to form an initial self-aligned silicide layer 710 having a high resistance. The initial self-aligned silicide layer 710 can be a Ni2PtSi layer. In some embodiments, before the first annealing process is performed, the preparation of the self-aligned silicide layer 720 further includes depositing a second contact material layer (not shown in the figures) on the surface of the first contact material layer 700. The second contact material layer can be formed by any suitable deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer epitaxy process. The second contact material layer can be a TiN layer having a thickness ranging from 50 A to 100 A, such as 50 A, 80 A, or 100 A, or any thickness within the range from 50 A to 100 A. During the first annealing process, the second contact material layer TiN can reduce the mobility of Ni in the NiPt layer, so that the initial self-aligned silicide layer 710 is formed within a certain region without drilling randomly. In addition, Ti in the TiN layer has a stronger oxygen absorption capacity than Ni, and can absorb the O naturally oxidized on the surface of the P ion implantation region 150, the N ion implantation region 160, and the gate structure 171. In some embodiments, during the first annealing process, a mixture of nitrogen and helium can be introduced. The nitrogen is added to remove oxygen, because oxygen can affect the reaction. The helium is added to ensure that the entire wafer is uniformly heated, because the temperature of the first annealing process is relatively low. After the initial self-aligned silicide layer 710 is formed, the second contact material layer, the unconverted first contact material layer 700, and the self-aligned silicide barrier layer 610 are removed. The present disclosure does not limit the method of removing the second contact material layer, the unconverted first contact material layer 700, and the self-aligned silicide barrier layer 610. For example, the second contact material layer, the unconverted first contact material layer 700, and the self-aligned silicide barrier layer 610 can be removed by dry etching or wet etching. In some embodiments, before the first contact material layer 700 is deposited on the substrate 10, a SiCoNi pre-cleaning process is performed on the surface of the substrate 10. The SiCoNi pre-cleaning process can selectively remove SiO2 on the surface of the substrate 10 to form a clean, atomically flat surface. For example, after the SiCoNi pre-cleaning process is performed on the substrate 10, the thickness of the surface of the substrate 10 is reduced by 60 A.

[0037] See Figure 25As shown, in an embodiment of the present application, after removing the second contact material layer, the unconverted first contact material layer 700 and the self-aligned silicide barrier layer 610, a second annealing process is performed to form a self-aligned silicide layer 720, which is a NiPtSi2 layer. The second annealing process is, for example, a rapid annealing process, and the temperature of the second annealing process can be 600-900 °C, for example, any value in the range of 600-900 °C, such as 600 °C, 700 °C, 800 °C or 900 °C. During the second annealing process, nitrogen gas can be introduced in a high-temperature environment to convert the high-resistance Ni2PtSi into low-resistance NiPtSi2, so as to reduce the contact resistance of the subsequent circuit and improve the electrical performance of the subsequently prepared semiconductor device. In an embodiment of the present application, the second annealing process is performed in a nitrogen environment at a temperature of 800 °C. Figure 19 A schematic diagram of a cross-sectional top surface of the structure 40 including the self-aligned silicide layer 720 is shown in Figure 26 As shown, in the preparation process of the ESD device in the present application, a standard CMOS process is used, and no additional mask is needed, thereby saving costs.

[0038] As shown in Figure 27 and Figure 28 , along the first direction of the substrate 10, the P+ doped region 152 of the gate-grounded NMOS structure 20 is connected as the base, the N+ doped region 162 is connected as the emitter, and the N+ doped region 162 is connected as the collector, and the electrodes are connected in the manner of Figure 27 and Figure 28 , and the breakdown voltage of the ESD device is tested. As a comparison, an ESD device with only a gate-grounded NMOS structure is tested, and the results are shown in Figure 29As shown, the trigger voltage of existing ESD devices is 4V, while the trigger voltage Vt1 of the ESD device in this application is reduced to 1V. The trigger voltage of the ESD device in this application is four times lower than that of existing ESD devices, significantly improving device sensitivity. Furthermore, when a low-energy pulse arrives, the ESD device of this application can quickly clamp the ESD voltage due to the extremely low forward voltage drop and picosecond-level response speed of the Schottky barrier diode structure 30. When a high-energy pulse arrives, multiple Schottky barrier diode structures 30 connected in parallel can absorb the initial ESD spike. Subsequently, the Zener diode structure 40 and the gate-grounded NMOS structure 20 turn on, becoming the main discharge path and maintaining high current discharge capability. In other words, the ESD device of this application forms a stepped protection system with the Schottky barrier diode structure 30, Zener diode structure 40, and gate-grounded NMOS structure 20 in that order, smoothly transitioning through ESD impacts, resulting in uniform current distribution, reduced thermal stress, and improved device reliability. Therefore, when the gate-grounded NMOS structure 20 is connected in parallel with multiple Schottky barrier diode structures 30 and Zener diode structures 40, it can form a multi-level voltage clamp, providing stepped protection at each critical potential in the medium and low voltage range, so that the secondary breakdown current It2 remains at a high level. In advanced process sensitive circuits or high-speed interface circuits, multi-level protection in the medium and low voltage range is realized.

[0039] The present invention also provides, for example Figure 19 The ESD device shown includes a substrate 10, a gate-grounded NMOS structure 20, a Schottky barrier diode structure 30, and a Zener diode structure 40. The substrate 10 includes a base 100 and a high-voltage P-well region 110 and a deep N-well region 120 formed on the substrate 100. The high-voltage P-well region 110 and the deep N-well region 120 are isolated by a trench isolation structure and are arranged along a first direction parallel to the substrate 100. The gate-grounded NMOS structure 20 is formed on the high-voltage P-well region 110. The Schottky barrier diode structure 30 is disposed in the deep N-well region 120. The Zener diode structure 40 is disposed on the deep N-well region 120 and is staggered with the Schottky barrier diode structure 30 along a second direction parallel to the substrate 100. The second direction is perpendicular to the first direction. The ESD device of this application features a Schottky barrier diode structure 30 and a Zener diode structure 40 interleaved on the same deep N-well region 120, which reduces the device layout and saves 20-30% of area compared to a structure with a series-connected Schottky barrier diode structure 30 and a Zener diode structure 40. Furthermore, the number of Schottky barrier diode structures 30 and Zener diode structures 40 can be adjusted according to actual needs, allowing for different combinations of numbers to be used for different technology nodes and voltages.

[0040] In summary, the application provides a preparation method of an ESD device, a high-voltage P-well region and a deep N-well region are isolated by a first trench isolation structure and arranged along a first direction parallel to a substrate, a gate-grounded NMOS structure is formed on the high-voltage P-well region, a Schottky barrier diode structure and a voltage regulator diode structure are formed on the deep N-well region, the Schottky barrier diode structure and the voltage regulator diode structure are staggered along a second direction parallel to the substrate, and the second direction is perpendicular to the first direction. The unexpected effect of the application is that the gate-grounded NMOS structure can form a multi-stage voltage clamping when connected in parallel with the multiple Schottky barrier diode structures and voltage regulator diode structures, provide stepped protection for each key potential at a low voltage, smoothly transition ESD impact, make the current distribution uniform, reduce thermal stress, and improve the reliability of the device.

[0041] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not intended to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A method for fabricating an ESD device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a substrate and a high-voltage P-well region and a deep N-well region formed on the substrate, and a first oxide layer covering the surfaces of the high-voltage P-well region and the deep N-well region, the high-voltage P-well region and the deep N-well region being arranged along a first direction parallel to the substrate; A first trench isolation structure is formed on the substrate, the first trench isolation structure isolating the high-voltage P-well region and the deep N-well region; A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, and the second direction is perpendicular to the first direction.

2. The preparation method according to claim 1, characterized in that, The number of the first trench isolation structures is multiple, and the multiple first trench isolation structures are spaced apart along the first direction. Along the direction from the high-voltage P-well region to the deep N-well region, the high-voltage P-well region is sequentially isolated into a P-ion implantation region, an N-ion implantation region, a gate formation region, and an N-ion implantation region. The deep N-well region is sequentially isolated to form a first region and an N-ion implantation region. While forming a plurality of first trench isolation structures on the substrate, the method for fabricating the ESD device further includes forming a plurality of second trench isolation structures on the substrate. The plurality of second trench isolation structures are located in the middle of the first region and are spaced apart along the second direction. N-ion implantation regions are formed in the gaps between the second trench isolation structures, and P-ion implantation regions extending along the second direction are formed in the first region on both sides of the second trench isolation structures along the first direction.

3. The preparation method according to claim 2, characterized in that, A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, comprising the following steps: The P-ion implantation region is subjected to a first P-ion implantation to form a low-pressure P-well region, and the N-ion implantation region is subjected to a first N-ion implantation to form a low-pressure N-well region. A gate structure is formed on the surface of the gate forming region; A second P-ion implantation is performed on the P-ion implantation region to form a P+ doped region, and a second N-ion implantation is performed on the N-ion implantation region outside the first region to form an N+ doped region.

4. The preparation method according to claim 2, characterized in that, While forming multiple first trench isolation structures on the substrate, the method for fabricating the ESD device also includes forming multiple second trench isolation structures on the substrate, comprising the following steps: A patterned third photoresist layer is formed on the surface of the first oxide layer, and the third photoresist layer exposes the first trench region and the second trench region; The first oxide layer and the substrate are etched sequentially to form a plurality of first trenches and a plurality of second trenches on the substrate; An insulating medium is deposited in a plurality of first trenches and a plurality of second trenches until the insulating medium covers the surface of the first oxide layer; The insulating medium is planarized until it is flush with the first oxide layer, forming a plurality of first trench isolation structures and a plurality of second trench isolation structures.

5. The preparation method according to claim 1, characterized in that, The ion concentration in the high-pressure P-trap region is 5E11~1E13 / cm³ 3 The ion concentration in the deep N-well region is 5E11~1E13 / cm³. 3 .

6. The preparation method according to claim 3, characterized in that, The ion concentration in the low-pressure P-trap region is 1E12~5E14 / cm³. 3 The ion concentration in the low-pressure N-trap region is 1E12~5E14 / cm³. 3 The ion concentration of the P+ doped region is 5E13~1E16 / cm³. 3 The ion concentration of the N+ doped region is 5E13~1E16 / cm³. 3 .

7. The preparation method according to claim 3, characterized in that, Forming a gate structure on the surface of the gate forming region includes the following steps: Remove the first oxide layer and form a nitride layer on the surface of the substrate; The nitride layer is etched using a patterned photoresist as a mask layer, and the nitride layer exposes the gate formation region; A gate oxide layer is formed on the surface of the gate forming region; A gate material layer is formed on the surface of the gate oxide layer.

8. The preparation method according to claim 3, characterized in that, After forming the P+ doped region and the N+ doped region, the fabrication method of the ESD device further includes forming a self-aligned silicide layer on the surface of the P-ion implantation region, the N-ion implantation region, and the gate structure, including the following steps: A self-aligned silicide barrier layer is deposited on the surface of the substrate, the self-aligned silicide barrier layer exposing the surfaces of the P-ion implantation region, the N-ion implantation region and the gate structure; A first contact material layer is deposited on the surfaces of the P-ion implantation region, the N-ion implantation region, and the gate structure; The first annealing process and the second annealing process are performed sequentially.

9. The preparation method according to claim 1, characterized in that, The method for preparing the substrate includes the following steps: Provide the substrate; The first oxide layer is deposited on the substrate; A high-voltage P-well region is formed by implanting P-ions into the substrate using a patterned first photoresist layer as a mask layer. A patterned second photoresist layer is used as a mask layer to perform N-ion implantation on the substrate to form a deep N-well region.

10. An ESD device, characterized in that, include: The substrate includes a substrate and a high-voltage P-well region and a deep N-well region formed on the substrate, the high-voltage P-well region and the deep N-well region being isolated by a trench isolation structure and arranged along a first direction parallel to the substrate; A gate-grounded NMOS structure is formed on the high-voltage P-well region; A Schottky barrier diode structure is disposed on the deep N-well region; A Zener diode structure is disposed on the deep N-well region and is staggered with the Schottky barrier diode structure along a second direction parallel to the substrate, the second direction being perpendicular to the first direction.

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