Providing multi-request arbitration authorization policies for time-sensitive arbitration decisions in processor-based devices

Abstract

Providing a multi-request arbitration authorization policy for time-sensitive arbitration decisions in a processor-based device is disclosed. In this aspect, a processor-based device provides an arbitration circuit configured to select a request tracker entry of a plurality of request tracker entries of a request tracker circuit to apply a multi-request arbitration authorization policy. The arbitration circuitry determines a count N of a plurality of requests associated with the request tracker entry, and determines a count R of available resource elements of a plurality of resource elements of an arbitrated resource. The arbitration circuitry determines whether the count R of available resource elements is equal to or greater than N, and if so, issues a single arbitration authorization to the request tracker circuitry for a plurality of requests associated with the request tracker entry.

Description

Technical Field

[0001] The technology disclosed herein relates to the management of arbitrated resources in processor-based devices, and more specifically to providing time-sensitive arbitration decisions. Background Technology

[0002] Modern processor-based devices provide different types of shared resources that can be accessed by multiple clients (e.g., multiple devices or components of a processor-based device, and / or multiple processes being executed by a processor-based device). Such shared resources may include, but are not limited to, access to memory, access to a communication bus, and access to queues or caches provided by the processor-based device. To resolve conflicts between multiple clients seeking access to shared resources, processor-based devices can provide an arbitration circuit associated with the shared resource (i.e., the "arbitrated resource"), and this arbitration circuit is configured to arbitrate requests for access to the arbitrated resource from multiple clients.

[0003] A conventional arbitration mechanism utilizes a request tracker circuit that provides multiple request tracker entries, each associated with one or more requests from a client, for example, to be placed in an output request queue. The arbitration circuit in such a mechanism applies a single-request arbitration grant strategy, under which each request tracker entry has equal priority to arbitrate the resource to be arbitrated (in this example, the output request queue), and each arbitration grant is issued only for one (1) request. Therefore, a request tracker entry associated with a number of N linked requests (e.g., requests related to a single transaction or operation) will require a total of N arbitration grants to place all the linked requests of that request tracker entry into the resource to be arbitrated. Assuming a total number T of request tracker entries with requests ready for arbitration, one possible scenario is that one (1) of the N linked requests of a request tracker entry receives an arbitration grant within a given processor cycle, while the remaining N-1 linked requests of the request tracker entry may require up to N... It takes T processor cycles for all requests to receive arbitration authorization. If the requests are time-sensitive and require tight coupling for optimal performance, this traditional arbitration mechanism will negatively impact processor performance, resulting in longer lifecycles for each request tracker entry and generally slower request processing.

[0004] The aforementioned challenges when processing linked requests can be mitigated by using a "stop arbitrator" mechanism. This mechanism attempts to detect linked commands and "stop" the pointer at the current request tracker entry instead of moving on to the next. While this mechanism allows the same request tracker entry to win arbitration authorization in successive arbitrations, this approach leads to a more complex design of the arbitration circuit and requires different arbitration authorization strategies for linked and non-linked requests. Furthermore, while the stop arbitrator approach may result in linked requests of a request tracker entry winning arbitration authorization consecutively, there is no guarantee that these requests will be processed close to each other in time. Summary of the Invention

[0005] Exemplary embodiments disclosed herein include providing a multi-request arbitration granting strategy for time-sensitive arbitration decisions in a processor-based device. In this regard, in one exemplary embodiment, a processor-based device includes a arbitrated resource comprising a plurality of resource elements. In some embodiments, the arbitrated resource may include an output request queue, and the plurality of resource elements may include a plurality of output request queue entries of the output request queue. The processor-based device also includes request tracker circuitry comprising a plurality of request tracker entries. Each request tracker entry may be associated with one or more requests, such as a request or command seeking access to the arbitrated resource. To arbitrate these requests, the processor-based device provides arbitration circuitry. In exemplary operation, the arbitration circuitry selects a request tracker entry to apply the multi-request arbitration granting strategy. The arbitration circuitry determines a count N of requests associated with the request tracker entry and further determines a count R of resource elements of the arbitrated resource available for arbitration. The arbitration circuitry then determines whether the count R of available resource elements is equal to or greater than N, and if so, the arbitration circuitry issues a single arbitration grant to the request tracker circuitry for the plurality of requests associated with the first request tracker entry.

[0006] In some embodiments, the arbitration circuit may provide a mechanism to reduce the likelihood of starvation for request tracker entries. In such embodiments, the arbitration circuit maintains multiple lost arbitration counts corresponding to multiple request tracker entries. Each lost arbitration count tracks the number of consecutive arbitrations lost for each corresponding request tracker entry. If the arbitration circuit determines that the count R of available resource elements is equal to or greater than N, the arbitration circuit resets the lost arbitration count associated with the request tracker entry to a value of zero (0). However, if the arbitration circuit determines that the count R of available resource elements is not equal to or greater than N, the arbitration circuit increments the lost arbitration count associated with the request tracker entry among the multiple lost arbitration counts. The arbitration circuit then determines whether at least one of the multiple lost arbitration counts exceeds a starvation threshold. If so, the arbitration circuit applies a single-request arbitration granting strategy to the next request tracker entry among the multiple request tracker entries. If no lost arbitration count among the multiple lost arbitration counts exceeds the starvation threshold, the arbitration circuit applies a multi-request arbitration granting strategy to the next request tracker entry among the multiple request tracker entries.

[0007] Some embodiments may specify that the arbitration circuit determines the count R of available resource elements by determining the count of credits received from the resource being arbitrated. According to some embodiments, the arbitration circuit may determine the count R of available resource elements by querying the resource being arbitrated for the count R of available resource elements.

[0008] In another exemplary embodiment, a processor-based device is disclosed. The processor-based device includes an arbitration resource comprising a plurality of resource elements, and further includes request tracker circuitry comprising a plurality of request tracker entries, each request tracker entry associated with a transaction comprising one or more requests for corresponding one or more resource elements. The processor-based device also includes arbitration circuitry configured to select a first request tracker entry from the plurality of request tracker entries of the request tracker circuitry to apply a multi-request arbitration grant strategy. The arbitration circuitry is further configured to determine a count N of the plurality of requests associated with the first request tracker entry. The arbitration circuitry is also configured to determine a count R of available resource elements among the plurality of resource elements of the arbitration resource. The arbitration circuitry is further configured to determine whether the count R of available resource elements is equal to or greater than N. The arbitration circuitry is further configured to, in response to determining that the count R of available resource elements is equal to or greater than N, issue a single arbitration grant to the request tracker circuitry for the plurality of requests associated with the first request tracker entry.

[0009] In another exemplary embodiment, a method for providing a multi-request arbitration granting strategy is disclosed. The method includes an arbitration circuit of a processor-based device selecting a first request tracker entry from a plurality of request tracker entries of a request tracker circuit to apply the multi-request arbitration granting strategy. The method further includes determining a count N of a plurality of requests associated with the first request tracker entry. The method further includes determining a count R of available resource elements among a plurality of resource elements of the arbitrated resource. The method further includes determining that the count R of available resource elements is equal to or greater than N. The method further includes: in response to determining that the count R of available resource elements is equal to or greater than N, issuing a single arbitration grant to the request tracker circuit for the plurality of requests associated with the first request tracker entry.

[0010] In another exemplary embodiment, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores computer-executable instructions thereon that, when executed, cause a processor of a processor-based system to select a first request tracker entry from a plurality of request tracker entries of a request tracker circuit to apply a multi-request arbitration grant strategy. The computer-executable instructions also cause the processor to determine a count N of a plurality of requests associated with the first request tracker entry. The computer-executable instructions further cause the processor to determine a count R of available resource elements among a plurality of resource elements of the arbitrated resource. The computer-executable instructions further cause the processor to determine whether the count R of available resource elements is equal to or greater than N. The computer-executable instructions further cause the processor, in response to determining that the count R of available resource elements is equal to or greater than N, to issue a single arbitration grant to the request tracker circuit for the plurality of requests associated with the first request tracker entry.

[0011] Those skilled in the art will appreciate the scope of this disclosure and implement additional embodiments thereof after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0013] Figure 1 This is a block diagram illustrating an exemplary processor-based device including arbitration circuitry configured to provide a multi-request arbitration authorization strategy;

[0014] Figures 2A to 2C Provided are illustrations according to some embodiments Figure 1 A flowchart illustrating exemplary operations of a processor-based device for providing a multi-request arbitration authorization strategy;

[0015] Figure 3This refers to exemplary processor-based devices (such as...) configured to provide a multi-request arbitration authorization strategy according to some embodiments. Figure 1 A block diagram of a processor-based device. Detailed Implementation

[0016] Exemplary embodiments disclosed herein include providing a multi-request arbitration granting strategy for time-sensitive arbitration decisions in a processor-based device. In this regard, in one exemplary embodiment, a processor-based device includes a arbitrated resource comprising a plurality of resource elements. In some embodiments, the arbitrated resource may include an output request queue, and the plurality of resource elements may include a plurality of output request queue entries of the output request queue. The processor-based device also includes request tracker circuitry comprising a plurality of request tracker entries. Each request tracker entry may be associated with one or more requests, such as a request or command seeking access to the arbitrated resource. For arbitrating a request, the processor-based device provides arbitration circuitry. In exemplary operation, the arbitration circuitry selects a request tracker entry to apply the multi-request arbitration granting strategy. The arbitration circuitry determines a count N of requests associated with the request tracker entry and further determines a count R of arbitrated resource elements available for arbitration. The arbitration circuitry then determines whether the count R of available resource elements is equal to or greater than N, and if so, the arbitration circuitry issues a single arbitration grant to the request tracker circuitry for the plurality of requests associated with the first request tracker entry.

[0017] In some embodiments, the arbitration circuit may provide a mechanism to reduce the likelihood of starvation for request tracker entries. In such embodiments, the arbitration circuit maintains multiple lost arbitration counts corresponding to multiple request tracker entries. Each lost arbitration count tracks the number of consecutive arbitrations lost for each corresponding request tracker entry. If the arbitration circuit determines that the count R of available resource elements is equal to or greater than N, the arbitration circuit resets the lost arbitration count associated with the request tracker entry to a value of zero (0). However, if the arbitration circuit determines that the count R of available resource elements is not equal to or greater than N, the arbitration circuit increments the lost arbitration count associated with the request tracker entry among the multiple lost arbitration counts. The arbitration circuit then determines whether at least one of the multiple lost arbitration counts exceeds a starvation threshold. If so, the arbitration circuit applies a single-request arbitration granting strategy to the next request tracker entry among the multiple request tracker entries. If no lost arbitration count among the multiple lost arbitration counts exceeds the starvation threshold, the arbitration circuit applies a multi-request arbitration granting strategy to the next request tracker entry among the multiple request tracker entries.

[0018] Some embodiments may specify that the arbitration circuit determines the count R of available resource elements by determining the count of credits received from the resource being arbitrated. According to some embodiments, the arbitration circuit may determine the count R of available resource elements by querying the resource being arbitrated for the count R of available resource elements.

[0019] in this regard, Figure 1 An exemplary processor-based device 100 is illustrated, which provides a processor 102 for providing a multi-request arbitration authorization strategy. In some aspects, the processor 102 may include a central processing unit (CPU) having one or more processor cores, and in some exemplary aspects, the processor 102 may be one of a plurality of similarly configured processors (not shown) of the processor-based device 100. The processor 102 is communicatively coupled to an interconnect bus 104, which in some embodiments may include other components (e.g., bus controller circuitry and / or arbitration circuitry, as a non-limiting example), which are not shown for clarity. Figure 1 As shown in the diagram. Processor 102 is also communicatively coupled to memory controller 106 via interconnect bus 104, which controls access to system memory 108 and manages the data flow to and from system memory 108. System memory 108 provides addressable memory for data storage of processor-based device 100, and therefore, as a non-limiting example, may include synchronous dynamic random access memory (SDRAM).

[0020] Figure 1 The processor 102 provides arbitrated resources 110 comprising multiple resource elements 112(0)-112(Q). As used herein, the term "arbitrated resource" refers to any resource that can be shared among multiple clients (e.g., multiple devices or elements of the processor-based device 100, and / or multiple processes (not shown) executed by the processor-based device 100). As used herein, the term "resource element" refers to a discrete subset of the arbitrated resources 110 that can be assigned to a single client or accessed by or on behalf of a single client. Figure 1 In the example, the arbitrated resource 110 includes output request queue 114, while multiple resource elements 112(0)-112(Q) include multiple output request queue entries of output request queue 114. Figure 1 The title is “Output Request Queue Entry”) 116 (0) - 116 (Q).

[0021] In order to manage the resources 110 that were arbitrated (i.e., for...) Figure 1For access to the output request queue 114 in the example, processor 102 provides request tracker circuit 118 and arbitration circuit 120. Request tracker circuit 118 provides multiple request tracker entries 122(0)-122(T), each of which can be used to track one or more requests. As used herein, a “request” includes an access request or command issued by a client (not shown). Some request tracker entries (such as request tracker entry 122(T)) may be associated with a single request 124, while other request tracker entries (such as request tracker entry 122(0)) may be associated with multiple requests 126(0)-126(N). Requests 126(0)-126(N) (which may also be referred to herein as “linked requests 126(0)-126(N)”) may be associated with a single transaction or operation, such that it is expected that the dispatched requests 126(0)-126(N) are as close as possible in time.

[0022] Figure 1 Arbitration circuit 120 is configured to select request tracker entries from request tracker entries 122(0)-122(T) and apply an arbitration authorization strategy to control access to the arbitrated resource 110 for each request tracker entry(s) associated with each request tracker entry(s) in request tracker entries 122(0)-122(T). Arbitration circuit 120 may select request tracker entries from request tracker entries 122(0)-122(T) using any conventional arbitration criteria.

[0023] Figure 1 The processor-based device 100 and its constituent elements may include any known digital logic elements, semiconductor circuits, processing cores and / or memory structures, as well as other elements, or combinations thereof. The embodiments described herein are not limited to any particular element arrangement, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor sockets or packages. It should be understood that some embodiments of the processor-based device 100 may include more than Figure 1 The processor 102 may include more or fewer components as shown. For example, it may also include one or more functional units, an instruction cache, a unified cache, a memory controller, an interconnect bus and / or additional memory devices, cache and / or controller circuitry, which, for clarity, are shown in [the diagram]. Figure 1 The text is omitted. It should also be understood that although the requesting tracker circuit 118, arbitration circuit 120, and the arbitrated resource 110 are in... Figure 1 While shown as a separate element, in some embodiments, one or more elements may be implemented as an integrated element of another component of the processor-based device 100.

[0024] As described above, the conventional arbitration mechanism involves the arbitration circuit 120 applying a single-request arbitration grant strategy. Under this strategy, each request tracker entry 122(0)-122(T) has equal priority to arbitrate the arbitrated resource 110, and each arbitration grant is issued for one (1) request (such as requests 126(0)-126(N) and 124). Therefore, a request tracker entry 122(0) associated with a number of N requests 126(0)-126(N) will require a total of N arbitration grants to complete all requests 126(0)-126(N). One possible scenario is that one (1) of the requests 126(0)-126(N) of the request tracker entry 122(0) receives an arbitration grant within a given processor cycle, while the remaining requests of the requests 126(0)-126(N) of the request tracker entry 122(0) may require up to N It takes T processor cycles to receive all the arbitration grants. In cases where requests 126(0)-126(N) are time-sensitive and require tight coupling for optimal performance, such a traditional arbitration mechanism will negatively impact processor performance and result in a longer lifecycle for each request tracker entry in request tracker entries 122(0)-122(T), and processing of requests 126(0)-126(N) and 124 will typically be slower.

[0025] in this regard, Figure 1Arbitration circuit 120 is configured to provide a multi-request arbitration authorization strategy under which multiple requests in requests 126(0)-126(N) and 124 can be covered by a single arbitration authorization. In exemplary operation, arbitration circuit 120 selects a request tracker entry (such as request tracker entry 122(0)) to apply the multi-request arbitration authorization strategy. Arbitration circuit 120 determines a count N of requests 126(0)-126(N) associated with request tracker entry 122(0), and further determines a count R of resource elements available (i.e., for fulfilling, processing, or storing requests such as requests 126(0)-126(N)) in resource elements 112(0)-112(Q) of the arbitrated resource 110. In some embodiments, a credit mechanism may be used to manage access to the arbitrated resource 110, whereby the arbitrated resource 110 authorizes credit(s) corresponding to available resource elements(s) in resource elements 112(0)-112(Q) to request tracker entries 122(0)-122(T). In such embodiments, the arbitration circuit 120 may determine the count R of available resource elements in resource elements 112(0)-112(Q) by determining the count (not shown) of credits received from the arbitrated resource 110. Some embodiments may specify that the arbitration circuit 120 may determine the count R of available resource elements in resource elements 112(0)-112(Q) by querying the count R of available resource elements in the arbitrated resource 110.

[0026] Then, arbitration circuit 120 determines whether the count R of available resource elements is equal to or greater than N. If so, arbitration circuit 120 issues a single arbitration grant 128 to request tracker circuit 118 for multiple requests 126(0)-126(N) associated with the first request tracker entry 122(0). By issuing a single arbitration grant 128 for multiple requests 126(0)-126(N), arbitration circuit 120 can optimize the performance of multiple requests 126(0)-126(N) compared to waiting for N separate arbitration grants (which may occur at intervals of several processor cycles). Therefore, in Figure 1 In the example, if N=2 and the arbitration circuit 120 determines that both output request queue entries 116(0) and 116(1) are available, then the arbitration grant 128 causes requests 126(0)-126(N) to be inserted into output request queue entries 116(0) and 116(1) within the same processor cycle or within processor cycles that are close in time, thereby achieving optimized performance.

[0027] To ensure that only a single request tracker entry is associated with a single request (e.g., Figure 1Request tracker entries 122(T) will not be starved due to the prioritization of request tracker entries associated with multiple requests by the arbitration circuit 120. In some embodiments, the arbitration circuit 120 may also provide a resource starvation prevention mechanism. Figure 1 As seen in the diagram, the arbitration circuit 120 may include multiple lost arbitration counts corresponding to request tracker entries 122(0)-122(T). Figure 1 The table below is titled “Lost Arbitration Count”. Each of the lost arbitration counts 130(0)-130(T) represents the number of consecutive arbitrations lost for each corresponding request tracker entry 122(0)-122(T). When an arbitration for a request tracker entry (such as request tracker entry 122(0)) is successful (i.e., the count R of available resource elements is not greater than N), the arbitration circuit 120 can reset the lost arbitration count 130(0) associated with request tracker entry 122(0) in the multiple lost arbitration counts 130(0)-130(T) to a value of zero (0). However, if the arbitration circuit 120 determines that the count R of available resource elements is not equal to or greater than N, the arbitration circuit 120 can increment the lost arbitration count 130(0) associated with the first request tracker entry 122(0).

[0028] Then, arbitration circuit 120 can determine whether at least one of the multiple lost arbitration counts 130(0)-130(T) exceeds the starvation threshold 132. If so, arbitration circuit 120 selects the next request tracker entry among the multiple request tracker entries 122(0)-122(T), such as request tracker entry 122(T), to apply a single-request arbitration grant strategy (i.e., each arbitration grant is applied to a strategy for one (1) request). If arbitration circuit 120 determines that no lost arbitration count among the multiple lost arbitration counts 130(0)-130(T) exceeds the starvation threshold 132, arbitration circuit 120 selects the next request tracker entry 122(T) among the multiple request tracker entries 122(0)-122(T) to apply a multi-request arbitration grant strategy. It should be understood that “next request tracker entry” refers to the request tracker entry subsequently selected and processed by arbitration circuit 120, and not necessarily the “next” request tracker entry in an ordinal sense.

[0029] To illustrate according to some embodiments Figure 1 The processor-based device 100 is used to provide exemplary operation of a multi-request arbitration authorization strategy. Figures 2A to 2C A flowchart illustrating exemplary operation 200 is provided. For clarity, in the description... Figures 2A to 2C When quoted Figure 1 The components in. It should be understood that, Figures 2A to 2CSome of the exemplary operations 200 shown may be performed in a different order than that shown herein, or may be omitted. Exemplary operation 200 begins at... Figure 2A In the context of processor-based devices, the arbitration circuit (e.g., Figure 1 The arbitration circuit 120 of the processor-based device 100 selects the first request tracker entry (such as...) from a plurality of request tracker entries of the request tracker circuit. Figure 1 The request tracker circuit 118 uses multiple request tracker entries 122(0)-122(T) to apply a multi-request arbitration authorization strategy (block 202). The arbitration circuit 120 determines multiple requests (e.g., requests in the first request tracker entry 122(0)) to apply a multi-request arbitration authorization strategy. Figure 1 The request 126(0)-126(N)) counts N (block 204). The arbitration circuit 120 also determines multiple resource elements of the arbitrated resource (e.g., Figure 1 The count R of available resource elements in resource elements 112(0)-112(Q)) of the arbitrated resource 110 is determined (block 206). In some embodiments, the operation of block 206 for determining the count R of available resource elements may include the arbitration circuit 120 determining a count of credits received from the arbitrated resource 110 (block 208). Some embodiments may specify that the operation of block 206 for determining the count R of available resource elements includes: the arbitration circuit 120 querying the count R of available resource elements in the arbitrated resource 110 (block 210). Then, exemplary operation 200 continues to be performed. Figure 2B Block 212.

[0030] Now for reference Figure 2B Arbitration circuit 120 determines whether the count R of available resource elements is equal to or greater than N (block 212). If so, arbitration circuit 120 issues a single arbitration authorization to request tracker circuit 118 for multiple requests 126(0)-126(N) associated with the first request tracker entry 122(0) (e.g., Figure 1 Arbitration authorization 128 (block 214). In some embodiments, arbitration circuit 120 may also include lost arbitration counts associated with the first request tracker entry 122 (0) from a plurality of lost arbitration counts (e.g., Figure 1 The lost arbitration count 130(0) in the multiple lost arbitration counts 130(0)-130(T) is reset to the value zero(0) (block 216). Then, exemplary operation 200 continues to execute. Figure 2CBlock 218. However, if the arbitration circuit 120 determines at decision block 212 that the count R of available resource elements is not equal to or greater than N, in some embodiments, the arbitration circuit 120 may increment a plurality of lost arbitration counts 130(0)-130(T) associated with the first request tracker entry 122(0) (block 220). Then, exemplary operation 200 continues to execute. Figure 2C Block 218.

[0031] Now go to Figure 2C According to some aspects, arbitration circuit 120 can determine whether at least one of the multiple lost arbitration counts 130(0)-130(T) exceeds a starvation threshold (such as...). Figure 1 The hunger threshold 132 (block 218). If so, the arbitration circuit 120 selects the next request tracker entry from the plurality of request tracker entries 122(0)-122(T) (e.g., Figure 1 The request tracker entry 122(T) is used to apply the single-request arbitration authorization strategy (block 222). If the arbitration circuit 120 determines at decision block 218 that no lost arbitration count among the multiple lost arbitration counts 130(0)-130(T) exceeds the starvation threshold 132, then the arbitration circuit 120 selects the next request tracker entry 122(T) among the multiple request tracker entries 122(0)-122(T) to apply the multi-request arbitration authorization strategy (block 224).

[0032] Figure 3 It is an exemplary processor-based device 300 (such as...) Figure 1 This is a block diagram of a processor-based device 300 that provides a multi-request arbitration authorization strategy for time-sensitive arbitration decisions. The processor-based device 300 may be one or more circuits included in an electronic board (such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device), and may represent, for example, a server or a user's computer. In this example, the processor-based device 300 includes a processor 302. The processor 302 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc., and may correspond to... Figure 1Processor 102. Processor 302 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 302 includes an instruction cache 304 for temporary, fast access to instructions and instruction processing circuitry 310. Instructions fetched or prefetched from memory (such as from system memory 308 via system bus 306) are stored in instruction cache 304. Instruction processing circuitry 310 is configured to process the instructions fetched into instruction cache 304 and process these instructions for execution.

[0033] Processor 302 and system memory 308 are coupled to system bus 306 and can interconnect peripheral devices included in processor-based device 300. It is well known that processor 302 communicates with these other devices by exchanging address, control, and data information via system bus 306. For example, processor 302 can transmit bus transaction requests to memory controller 312 in system memory 308 (as an example of a peripheral device). Although Figure 3 Not shown, but multiple system buses 306 may be provided, each forming a different architecture. In this example, memory controller 312 is configured to provide memory access requests to memory array 314 in system memory 308. Memory array 314 consists of an array of storage bit cells for storing data. As a non-limiting example, system memory 308 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM), etc.), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0034] Other devices can be connected to system bus 306. For example... Figure 3As shown, as an example, these devices may include system memory 308, one or more input devices 316, one or more output devices 318, modem 324, and one or more display controllers 320. The input devices 316 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 318 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 324 may be any device configured to allow data exchange with network 326. Network 326 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. Modem 324 may be configured to support any type of desired communication protocol. Processor 302 may also be configured to access the display controllers 320 via system bus 306 to control information sent to one or more displays 322. The displays 322 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0035] Figure 3 The processor-based device 300 may include a set of instructions 328, which can be executed by the processor 302 for any desired application. The instructions 328 may be stored in system memory 308, the processor 302, and / or instruction cache 304, such as in a non-transitory computer-readable medium 330. The instructions 328 may also reside wholly or at least partially in system memory 308 and / or the processor 302 during their execution. The instructions 328 may also be transmitted or received via a network 326 through a modem 324, such that the network 326 includes the computer-readable medium 330.

[0036] Although in the exemplary embodiments, computer-readable medium 330 is shown as a single medium, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions 328. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform one or more methods of the embodiments disclosed herein. Therefore, "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0037] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be constituted by hardware components or may be embodied as machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform the steps. Alternatively, these steps may also be performed by a combination of hardware and software processes.

[0038] The embodiments disclosed herein can be provided as a computer program product or software process, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform the processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0039] Unless otherwise expressly stated and as is apparent from the preceding discussion, it should be understood that throughout the description, the use of terms such as “processing,” “computing,” “determining,” and “displaying” refers to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities in the registers and memory of the computer system into other data similarly represented as physical quantities in the memory or registers or other such information storage, transmission, or display devices of the computer system.

[0040] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with the programs taught herein, or building more specialized devices to perform the required method steps may prove convenient. The necessary architectures for various such systems will be apparent from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that the teachings of the embodiments described herein can be implemented using various programming languages.

[0041] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, components of the systems described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of various illustrative components, blocks, modules, circuits, and steps has been described above in a general manner. The implementation of these functionalities depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of the embodiments herein.

[0042] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, a combination of one or more microprocessors with a DSP core, or any other such configuration).

[0043] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0044] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussion. The described operations can be performed in a variety of different sequences other than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips (as may be referenced in the above description) can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0045] Unless otherwise expressly stated, no method described herein is intended to be construed as requiring its steps to be performed in a particular order. Therefore, no particular order is intended to be inferred if the method claims do not actually describe the order in which the steps should be followed, or if the claims or description do not expressly state that the steps should be limited to a particular order.

[0046] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments incorporated into the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be understood to include all contents within the scope of the appended claims and their equivalents.

Claims

1. A processor-based device (100), comprising: The arbitrated resource (110) includes multiple resource elements (112(0)-112(Q)). The request tracker circuit (118) includes a plurality of request tracker entries (122(0)-122(T)), each request tracker entry being associated with a transaction that includes one or more requests (126(0)-126(N)) for one or more corresponding resource elements (112(0)-112(Q)). as well as Arbitration circuit (120), said arbitration circuit (120) being configured to: The first request tracker entry (122(0)) of the plurality of request tracker entries (122(0)-122(T)) of the request tracker circuit (118) is selected to apply the multi-request arbitration authorization strategy; Determine the count N of multiple requests (126(0)-126(N)) associated with the first request tracker entry (122(0)); Determine the count R of available resource elements among the plurality of resource elements (112(0)-112(Q)) of the arbitrated resource (110); Determine whether the count R of the available resource elements is equal to or greater than N; and In response to determining that the count R of the available resource elements is equal to or greater than N, a single arbitration grant (128) is issued to the request tracker circuit (118) for the plurality of requests (126(0)-126(N)) associated with the first request tracker entry (122(0)).

2. The processor-based device of claim 1, wherein the arbitration circuit is further configured to select the next request tracker entry from the plurality of request tracker entries to apply the multi-request arbitration authorization strategy in response to determining that the count R of available resource elements is not equal to or greater than N.

3. The processor-based device according to any one of claims 1 to 2, wherein the arbitration circuit is further configured to: In response to determining that the count R of the available resource element is equal to or greater than N, the lost arbitration count associated with the first request tracker entry among a plurality of lost arbitration counts is reset to the value zero (0). In response to the determination that the count R of the available resource elements is not equal to or greater than N, the lost arbitration count associated with the first request tracker entry is incremented; Determine whether at least one of the multiple lost arbitration counts exceeds the starvation threshold; In response to determining that at least one of the plurality of lost arbitration counts exceeds the starvation threshold, the next request tracker entry among the plurality of request tracker entries is selected to apply the single request arbitration authorization strategy; as well as In response to determining that no lost arbitration count among the plurality of lost arbitration counts exceeds the starvation threshold, the next request tracker entry among the plurality of request tracker entries is selected to apply the multi-request arbitration authorization strategy.

4. The processor-based device according to any one of claims 1 to 3, wherein: The resources being arbitrated include the output request queue; and The plurality of resource elements include a plurality of output request queue entries of the output request queue.

5. The processor-based device according to any one of claims 1 to 4, wherein the arbitration circuit is configured to determine a count R of available resource elements by being configured to determine a count of credits received from the arbitrated resource.

6. The processor-based device according to any one of claims 1 to 4, wherein the arbitration circuit is configured to determine the count R of available resource elements by querying the arbitrated resource for a count R of available resource elements.

7. A method for providing a multi-claim arbitration authorization strategy, comprising: The arbitration circuit (120) of the processor-based device (100) selects the first request tracker entry (122(0)) from a plurality of request tracker entries (122(0)-122(T)) of the request tracker circuit (118) to apply a multi-request arbitration authorization strategy; Determine the count N of multiple requests (126(0)-126(N)) associated with the first request tracker entry (122(0)); Determine the count R of available resource elements among the multiple resource elements (112(0)-112(Q)) of the arbitrated resource (110); Determine that the count R of the available resource elements is equal to or greater than N; and In response to determining that the count R of the available resource elements is equal to or greater than N, a single arbitration grant (128) is issued to the request tracker circuit (118) for the plurality of requests (126(0)-126(N)) associated with the first request tracker entry (122(0)).

8. The method of claim 7, further comprising, in response to determining that the count R of the available resource element is equal to or greater than N, resetting the lost arbitration count associated with the first request tracker entry among a plurality of lost arbitration counts to a value of zero (0).

9. The method according to any one of claims 7 to 8, further comprising: The second request tracker entry from the plurality of request tracker entries of the request tracker circuit is selected to apply the multi-request arbitration authorization strategy; Determine the count X of multiple requests associated with the second request tracker entry; Determine the count Z of available resource elements among the plurality of resource elements of the arbitrated resource; The count Z of available resource elements is determined to be neither equal to nor greater than X; as well as In response to determining that the count Z of available resource elements is not equal to or greater than X, the next request tracker entry among the plurality of request tracker entries is selected to apply the multi-request arbitration authorization strategy.

10. The method of claim 9, further comprising: In response to the determination that the count Z of the available resource elements is not equal to or greater than X, the lost arbitration count associated with the second request tracker entry is incremented.

11. The method according to any one of claims 7 to 10, further comprising: Determine that none of the multiple lost arbitration counts exceed the starvation threshold; as well as In response to determining that no lost arbitration count among the plurality of lost arbitration counts exceeds the starvation threshold, the next request tracker entry among the plurality of request tracker entries is selected to apply the multi-request arbitration authorization strategy.

12. The method according to any one of claims 7 to 10, further comprising: Determine that at least one of multiple lost arbitration counts exceeds the starvation threshold; as well as In response to determining that at least one of the plurality of lost arbitration counts exceeds the starvation threshold, the next request tracker entry among the plurality of request tracker entries is selected to apply the single request arbitration authorization strategy.

13. The method according to any one of claims 7 to 12, wherein: The resources being arbitrated include the output request queue; and The plurality of resource elements include a plurality of output request queue entries of the output request queue.

14. The method according to any one of claims 7 to 13, wherein determining the count R of the available resource elements includes determining the count of credits received from the arbitrated resource.

15. The method of any one of claims 7 to 13, wherein determining the count R of available resource elements comprises querying the arbitrated resource against the count R of available resource elements.

16. A computer-readable medium (328) having stored thereon computer-executable instructions (330) that, when executed, cause the processor (102) of a processor-based device (100): Select the first request tracker entry (122(0)) from the multiple request tracker entries (122(0)-122(T)) of the request tracker circuit (118) to apply the multi-request arbitration authorization strategy; Determine the count N of multiple requests (126(0)-126(N)) associated with the first request tracker entry (122(0)); Determine the count R of available resource elements among the multiple resource elements (112(0)-112(Q)) of the arbitrated resource (110); Determine whether the count R of the available resource elements is equal to or greater than N; and In response to determining that the count R of the available resource elements is equal to or greater than N, a single arbitration grant (128) is issued to the request tracker circuit (118) for the plurality of requests (126(0)-126(N)) associated with the first request tracker entry (122(0)).

17. The computer-readable medium of claim 16, wherein the computer-executable instructions further cause the processor to: in response to determining that the count R of available resource elements is not equal to or greater than N, select the next request tracker entry among the plurality of request tracker entries to apply the multi-request arbitration authorization strategy.

18. The computer-readable medium according to any one of claims 16 to 17, wherein the computer-executable instructions further cause the processor to: In response to determining that the count R of the available resource element is greater than or equal to N, the lost arbitration count associated with the first request tracker entry in the plurality of lost arbitration counts is reset to the value zero (0). In response to the determination that the count R of the available resource elements is not equal to or greater than N, the lost arbitration count associated with the second request tracker entry is incremented; Determine whether at least one of the multiple lost arbitration counts exceeds the starvation threshold; In response to determining that at least one of the plurality of lost arbitration counts exceeds the starvation threshold, the next request tracker entry among the plurality of request tracker entries is selected to apply the single request arbitration authorization strategy; as well as In response to determining that no lost arbitration count among the plurality of lost arbitration counts exceeds the starvation threshold, the next request tracker entry among the plurality of request tracker entries is selected to apply the multi-request arbitration authorization strategy.

19. The computer-readable medium according to any one of claims 16 to 18, wherein: The resources being arbitrated include the output request queue; and The plurality of resource elements include a plurality of output request queue entries of the output request queue.

20. The computer-readable medium according to any one of claims 16 to 19, wherein the computer-executable instructions further cause the processor to determine a count R of available resource elements by causing the processor to determine a count of credits received from the arbitrated resource.

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