Standard unit function test circuit

Abstract

The invention discloses a standard cell function test circuit, and the circuit comprises an input signal generation unit which is used for generating n-bit input test signals; and a plurality of modules to be tested, each module to be tested comprises a plurality of standard units, each standard unit comprises 1-n input ports and one output port, one input port of the standard unit correspondingly inputs one input test signal in the n input test signals, and the other input port of the standard unit corresponds to one output test signal in the n input test signals. The total number of input ports of standard units included in each to-be-tested module does not exceed n, and the total number of output ports of each to-be-tested module is at least greater than or equal to 1; and the multiplexer is coupled to the output ports of the plurality of to-be-tested modules and is used for selecting one to-be-tested module from the plurality of to-be-tested modules according to a selection control signal and outputting a corresponding test result. The standard unit function test circuit can effectively solve the problems that an existing test method is low in efficiency and serious in time waste.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a standard unit function test circuit. Background Technology

[0002] In chip design, the standard cell library is the foundational library for integrated circuit design. To ensure the reliability of the standard cell library, various functional verifications are required for each standard cell in the library to ensure that the actual silicon wafer test results match the simulation data. The standard cell library contains a variety of basic logic units, and different units have different input ports.

[0003] Existing standard unit testing methods typically employ a unified test architecture, using selectors to sequentially select the standard units to be tested and then iterating through the corresponding input combinations to verify the functionality of the standard units. However, existing testing methods suffer from the following issues regarding testing efficiency: for relatively simple standard units, existing methods may result in redundant testing time, wasting time; however, simple standard units are frequently used in standard unit libraries, making this problem particularly prominent in practical testing and impacting overall testing efficiency. Summary of the Invention

[0004] The purpose of this application is to provide a standard unit function test circuit to solve the problems of low testing efficiency and serious time waste in the prior art.

[0005] To achieve the above objectives, this application adopts the following technical solution.

[0006] This application provides a standard unit function test circuit, which includes: an input signal generation unit for generating an n-bit input test signal; multiple modules under test (DUTs), each DUT including several standard units, each standard unit including 1 to n input ports and 1 output port, wherein one input port of a standard unit corresponds to one bit of the n-bit input test signal, the total number of input ports of the standard units included in each DUT does not exceed n, and the total number of output ports of each DUT is at least greater than or equal to 1; and a multiplexer coupled to the output ports of the multiple DUTs for selecting one DUT from the multiple DUTs according to a selection control signal and outputting the corresponding test result.

[0007] In some possible implementations, the total number of input ports of the module under test is equal to the number of bits of the input test signal.

[0008] In some possible implementations, n equals 6, and the number of standard units in each module under test ranges from 1 to 6.

[0009] In some possible implementations, the module under test may be configured in one of the following ways: one 6-input standard unit; one 1-input standard unit and one 5-input standard unit; one 2-input standard unit and one 4-input standard unit; two 1-input standard units and one 4-input standard unit; two 3-input standard units; one 1-input standard unit, one 2-input standard unit and one 3-input standard unit; three 1-input standard units and one 3-input standard unit; three 2-input standard units; two 1-input standard units and two 2-input standard units; four 1-input standard units and one 2-input standard unit; or six 1-input standard units.

[0010] In some possible implementations, the selection control signal is an m-bit binary signal, where m is determined based on the number of modules under test.

[0011] In some possible implementations, the selection control signal is a 9-bit binary signal, and the number of modules under test is less than or equal to 512.

[0012] In some possible implementations, the number of standard units within each module under test ranges from 1 to 6.

[0013] In some possible implementations, the number of output ports of each module under test is equal to the number of standard units within the module under test.

[0014] In some possible implementations, the input test signal generated by the input signal generation unit traverses from all 0 states to all 1 states.

[0015] In some possible implementations, the multiplexer employs a multi-stage cascaded structure.

[0016] In some possible implementations, each of the standard units includes one of the following: 1. an input standard unit, including an inverter and a buffer; 2. an input standard unit, including an AND gate, an OR gate, and an XOR gate; 3. an input standard unit, including a three-input AND gate and a three-input OR gate; 4. an input standard unit, including an NAND gate, a AND-OR-NOT gate, an OR-AND gate, and an AND-OR gate; 5. an input standard unit, including an NAND gate, a AND-OR-NOT gate, an OR-AND gate, and an AND-OR gate; 6. an input standard unit, including an NAND gate, a AND-OR-NOT gate, an OR-AND gate, and an AND-OR gate.

[0017] The standard unit function test circuit described in this application combines standard units with different input numbers into a test module with a total of 6 inputs. Multiple standard units within the module can be tested simultaneously using 6-bit input signals, thus making full use of the test time and avoiding the time wasted by testing each standard unit individually in existing technologies. Taking a library containing 463 standard units as an example, existing testing methods require 64 time units per unit, totaling 29,632 time units. However, using the standard unit function test circuit of this application, the 463 units are combined into 296 modules, requiring only 18,944 time units for the total test, reducing the test time by 36% and thus improving test efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the architecture of the standard unit function test circuit in the embodiments of this application.

[0020] Figure 2 for Figure 1 The diagram shows the architecture of the module under test.

[0021] Figure 3A and Figure 3B This is a schematic diagram of a standard unit.

[0022] Figure 4A and Figure 4B The diagrams show the unit time required for the circuit using this application and the existing method, respectively. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Standard cell libraries are the foundational IP (intellectual property module) libraries for integrated circuit design. To ensure the reliability of these libraries, various functional verifications of each standard cell are required. Current standard cell testing methods typically employ a unified test architecture, using selectors to sequentially select the standard cells under test and employing multi-bit input test signals to perform complete functional verification on each cell. However, this approach suffers from low testing efficiency in practical applications.

[0025] Specifically, existing methods employ the same test procedure for all standard units. For example, for a standard unit with 6 input ports (e.g., OA33), it is necessary to traverse all 64 combinations of input signals from 000000 to 111111 in order to fully cover its input logic combinations. However, for a standard unit with only 1 input port (e.g., inverter inv), theoretically only two cases are needed: input[0] is 0 and input[1] is 1, meaning only 2 time units are required to complete the functional verification. However, existing methods still require executing the complete 64-time-unit test procedure, resulting in a redundancy of 62 time units.

[0026] The researchers of this application found that the problem stems from the fact that existing technologies employ a "one-size-fits-all" testing approach, failing to consider the differences in input ports among different standard cells. Since standard cells with fewer input ports in the standard cell library are typically used more frequently and in larger quantities, existing testing methods result in a significant waste of testing time and low testing efficiency in practical applications.

[0027] Based on this, this application provides a novel test circuit architecture that combines standard units with different numbers of input ports to form a module under test (DUT) with a total of n input ports. The circuit includes an input signal generation unit, multiple DUTs, and a multiplexer. The input signal generation unit generates an n-bit input test signal. Each DUT includes several standard units, each with 1 to n input ports and 1 output port. One input port of a standard unit corresponds to one bit of the n-bit input test signal. The total number of input ports for each DUT is configured to be n as much as possible to ensure full utilization of the n-bit input test signal. The multiplexer is coupled to each DUT, selects the DUT according to a selection control signal, and outputs the corresponding test result. In this way, each combination of n-bit input test signals can simultaneously verify the functionality of multiple standard units within the DUT, thereby avoiding the time wastage of existing testing methods and improving testing efficiency.

[0028] The standard unit function test circuit of this application will be further described below with reference to the accompanying drawings.

[0029] See Figure 1 As shown, one embodiment of this application provides a standard unit function test circuit, which may include: an input signal generation unit 10, a plurality of modules under test 20, and a multiplexer 30.

[0030] Specifically, the input signal generation unit 10 can be used to generate an n-bit input test signal. In this embodiment, the input signal generation unit 10 is used to generate a 6-bit input test signal in[0-5]. During the entire test process, the input signal generation unit 10 sequentially traverses the input test signal from 000000 (i.e., all 0 states) to 111111 (i.e., all 1 states) according to a predetermined test order, generating a total of 64 different input combinations. This ensures complete functional verification of each selected module under test 20, thereby guaranteeing the comprehensiveness of the test and demonstrating the functionality of the standard unit 21 under various input conditions. Of course, in other embodiments, the input signal generation unit 10 can also be used to generate, for example, a 4-bit input test signal in[0-3], generating a total of 16 different input combinations, or to generate, for example, an 8-bit input test signal in[0-7], generating a total of 256 different input combinations. The value of n can be determined according to the actual situation. It should be noted that the value of n is also limited by the number of pins on the chip. For example, in a chip with a total of 22 pins, in addition to input test signals, power supply and output pins also need to be configured.

[0031] like Figure 2 As shown, in this embodiment, there are multiple modules under test (DUTs) 20, and each DUT 20 includes several standard units 21. One input port P of each standard unit 21 of the DUT 20 corresponds to one bit of an n-bit input test signal. The total number of input ports of the DUT 20 is equal to the number of bits of the input test signal. Each standard unit 21 includes 1 to n input ports and 1 output port. The total number of input ports A of the standard units included in each DUT 20 does not exceed n. It is worth noting that, in order to maximize testing efficiency, this application preferentially groups multiple standard units into DUTs with a total number of n input ports. Ideally, all standard units can exactly form several DUTs with a total number of n input ports. When the remaining standard units cannot form DUTs with a total number of n input ports, DUTs with a total number of input ports less than n can be formed to ensure that all standard units are tested. The total number of output ports B of each DUT 20 is at least greater than or equal to 1.

[0032] In this embodiment, n=6 is used as an example for explanation. The number of standard units 21 in each module under test 20 ranges from 1 to 6.

[0033] If a module under test 20 includes three standard units 21, namely an inverter inv (1 input port), a three-input AND gate and3 (3 input ports), and a two-input XOR gate and2 (2 input ports), in the module under test 20, one input port P of the standard unit of the inverter inv corresponds to 1 bit of the 6-bit input test signal in[0], the three input ports P of the standard unit of the three-input AND gate and3 correspond to 3 bits of the 6-bit input test signal in[1], in[2], and in[3], respectively, and the two input ports P of the standard unit of the two-input XOR gate and2 correspond to 2 bits of the 6-bit input test signal in[4] and in[5]. In this way, the total number of input ports A of the three standard units 21 in the module under test 20 is equal to 6 (i.e., 1+3+2=6), which corresponds to 6 bits of input test signal, thereby realizing the full utilization of 6 bits of input test signal.

[0034] In one embodiment, if a module under test 20 includes two standard units 21, namely two three-input AND gates AND3 (each three-input AND gate has 3 input ports), in the module under test 20, the three input ports P of the first three-input AND gate AND3 correspond to 3 bits of the 6-bit input test signal in[0], in[1], and in[2], and the three input ports P of the second three-input AND gate AND3 correspond to 3 bits of the 6-bit input test signal in[3], in[4], and in[5]. In this way, the total number of input ports A of the two standard units 21 in the module under test 20 is equal to 6 (i.e., 3+3=6), which corresponds to 6 bits of input test signal, thereby realizing the full utilization of 6 bits of input test signal.

[0035] In one embodiment, a module under test 20 includes four standard units 21, namely three inverters inv (each inverter has one input port) and a three-input AND gate and3 (three input ports). In this module under test 20, one input port P of the first inverter inv corresponds to one bit of the 6-bit input test signal in[0], one input port P of the second inverter inv corresponds to one bit of the 6-bit input test signal in[1], one input port P of the third inverter inv corresponds to one bit of the 6-bit input test signal in[2], and the three input ports P of the three-input AND gate and3 correspond to three bits of the 6-bit input test signal in[3], in[4], and in[5]. Thus, the total number of input ports A of the four standard units 21 in the module under test 20 is equal to 6 (i.e., 1+1+1+3=6), which corresponds to 6-bit input test signals, thereby enabling full utilization of the 6-bit input test signals.

[0036] In one embodiment, if a module under test 20 includes four standard units 21, namely two inverters inv (each inverter has one input port) and two two-input AND gates and2 (each two-input AND gate has two input ports). In this module under test 20, one input port P of the first inverter inv corresponds to one bit of the 6-bit input test signal in[0], one input port P of the second inverter inv corresponds to one bit of the 6-bit input test signal in[1], the two input ports P of the first two-input AND gate and2 correspond to two bits of the 6-bit input test signal in[2] and in[3], and the two input ports P of the second two-input AND gate and2 correspond to two bits of the 6-bit input test signal in[4] and in[5]. In this way, the total number of input ports A of the four standard units 21 in the module under test 20 is equal to 6 (i.e., 1+1+2+2=6), which corresponds to 6 bits of input test signal, thereby realizing the full utilization of 6 bits of input test signal.

[0037] As can be seen from the above embodiments, the composition of the module under test 20 is diverse and flexible. Specifically, the composition of each module under test 20 may include one of the following: one 6-input standard unit; one 1-input standard unit and one 5-input standard unit; one 2-input standard unit and one 4-input standard unit; two 1-input standard units and one 4-input standard unit; two 3-input standard units; one 1-input standard unit, one 2-input standard unit and one 3-input standard unit; three 1-input standard units and one 3-input standard unit; three 2-input standard units; two 1-input standard units and two 2-input standard units; four 1-input standard units and one 2-input standard unit; six 1-input standard units.

[0038] The types of standard units 21 in the above combinations are diverse, and may specifically include one of the following: 1. Input standard unit, including but not limited to inverters and buffers; 2. Input standard unit, including but not limited to AND gates, OR gates, and XOR gates; 3. Input standard unit, including but not limited to three-input AND gates and three-input OR gates; 4. Input standard unit, including but not limited to NAND gates (OAI22), AND-OR-NOT gates (AOI22), OR-AND gates (OA22), and AND-OR gates (AO22); 5. Input standard unit, including but not limited to NAND gates (OAI32), AND-OR-NOT gates (AOI32), OR-AND gates (OA32), and AND-OR gates (AO32); 6. Input standard unit, including but not limited to NAND gates (OAI222), AND-OR-NOT gates (AOI222), OR-AND gates (OA33), and AND-OR gates (AO33).

[0039] Among them, the inverter in the 1-input standard unit has the fewest input ports (corresponding to in[0]), such as Figure 3A ;6. Among the standard input units, the OR-NAND gate (OAI222) has the most input ports (corresponding to in[0], in[1], in[2], in[3], in[4], in[5]), such as Figure 3B .

[0040] These different types of standard units 21 can be combined in different ways according to actual needs to form a test module 20 with a total number of input ports A of 6, thereby realizing efficient testing of the standard unit library.

[0041] It should be noted that the above embodiment is illustrated using n=6 as an example. In other embodiments, the total number of input ports n of the module under test can be adjusted according to actual application requirements and the number of bits of the input test signal. For example, when the input test signal is 4 bits, the total number of input ports A of the standard units included in the module under test 20 is 4. In this case, a 4-input standard unit, a combination of two 2-input standard units, or a combination of a 1-input standard unit and a 3-input standard unit can be used. By using different types of standard units 21 from the standard unit library, input test requirements of different bit lengths can be met to achieve efficient testing.

[0042] It should also be noted that when n=6, the number of standard units 21 in each module under test 20 ranges from 1 to 6. In practical applications, to make full use of resources, most modules under test 20 will contain as many as 6 standard units 21 to maximize the use of the 6-bit input test signal. Considering that the number of standard units 21 in the standard unit library may be uneven, a few modules under test 20 may contain 1 to 5 standard units. For example, in a unit library containing 463 standard units, after combination, there may be 290 modules under test 20 containing 6 standard units, and 6 modules under test 20 containing 1 to 5 standard units 21, for a total of 296 modules under test 20. The above combination method can ensure that all standard units 21 can be effectively tested and maximizes testing efficiency.

[0043] In this embodiment, the multiplexer 30 is coupled to the output port B of the plurality of modules under test 20, and is used to select one module under test 20 from the plurality of modules under test 20 for testing according to the selection control signal, and output the corresponding test result of the module under test 20 through the output terminal (Final_out) of the multiplexer 30, wherein the test result is a fixed n-bit data (a fixed 6-bit data in this embodiment).

[0044] In one embodiment, the number of output ports B in each module under test 20 is equal to the number of standard units 21 contained within the module under test 20. In other words, if a module under test 20 includes 3 standard units 21, then the module under test 20 has 3 output ports; if a module under test 20 includes 6 standard units 21, then the module under test 20 has 6 output ports. This ensures that the test of each standard unit 21 within the module under test 20 can be output independently.

[0045] In this embodiment, the selection control signal can be represented using binary encoding. The number of bits (m bits) of the selection control signal is determined based on the total number of modules under test 20. According to the principle of binary encoding, if it is necessary to select one module under test 20 from multiple modules under test 20, for example, to select one module under test 20 from X modules under test 20, then a selection control signal of log2X bits is required.

[0046] Taking this embodiment as an example, when the total number of modules under test 20 is 296, then log2296 = 9 bits of selection control signal are required, i.e., sel[0-8]. Different combinations of the 9 bits of selection control signal can generate 512 different selection methods. That is, when the selection control signal is a 9-bit binary signal, the number of modules under test can be less than or equal to 512. Of these 512 selection methods, the first 296 combinations (i.e., from 0 to 295) are used to select the corresponding module under test 20, while the last 216 combinations (i.e., from 296 to 511) are invalid combinations. If these invalid combinations occur in practical applications, the output of the multiplexer 30 can be set to a constant value (e.g., all 0s or all 1s).

[0047] In this embodiment, the multiplexer 30 can adopt a multi-stage cascaded structure to facilitate the selection of 296 modules under test 20. Specifically, this multi-stage structure adopts an 8-stage cascade method, successively reducing the 296 inputs to 148, 74, 37, 19, 10, 5, and 3, ultimately resulting in a single output. Each stage uses a relatively simple selector, thereby achieving the selection function from multiple inputs to a single output. Compared to a single large selector, the above-described multi-stage cascaded structure has better signal propagation characteristics and occupies a smaller area.

[0048] Since different modules under test (DUTs) 20 may contain different numbers of standard units 21, the number of output ports of the DUTs 20 may also vary from 1 to 6. Therefore, in one embodiment, the test result output by the multiplexer 30 is fixed at 6 bits to ensure a uniform output format. When the number of output ports of the selected DUTs 20 is less than 6, unused bits are set to low. For example, when a DUT 20 containing 3 standard units 21 is selected, the first 3 bits of the output 6-bit data are valid test results, and the last 3 bits are padded with zeros. By adopting the above method, the data flow can be simplified and the consistency of the test system can be ensured.

[0049] See Figure 4A and Figure 4B As shown, for a library containing 463 standard units, if existing testing methods (such as...) are used... Figure 4BAs shown, each standard unit needs to be functionally tested one by one. That is, the first standard unit is tested in time period T1, the second standard unit is tested in time period T2, and so on, until time period T... 463 The 463rd standard unit was tested. Each time cycle requires 64 time units to traverse all input combinations, therefore a total of 29632 time units (i.e., 463 * 64) are needed. However, the standard unit functional test circuit of this application (such as...) Figure 4A As shown), for 463 standard units, 296 modules under test (20) can be formed (see the description above for details). The first module under test is tested in time period T1, and the second module under test is tested in time period T20. 296 The last module under test also requires 64 time units per time cycle to traverse all input combinations, for a total of 18,944 time units (i.e., 296*64). Compared with existing technologies, this reduces the testing and simulation time by 36%, thereby improving the testing effect.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0051] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A standard unit function test circuit, characterized in that, include: The input signal generation unit is used to generate an n-bit input test signal; Multiple modules under test, each module under test includes several standard units, each standard unit includes 1 to n input ports and 1 output port, one input port of the standard unit corresponds to one bit of the n input test signals, the total number of input ports of the standard units included in each module under test does not exceed n, and the total number of output ports of each module under test is at least greater than or equal to 1; A multiplexer, coupled to the output ports of multiple modules under test, is used to select one module under test from the multiple modules under test according to a selection control signal and output the corresponding test result.

2. The standard unit function test circuit as described in claim 1, characterized in that, The total number of input ports of the module under test is equal to the number of bits of the input test signal.

3. The standard unit function test circuit as described in claim 2, characterized in that, The value of n is 6; The number of standard units in each of the modules under test ranges from 1 to 6.

4. The standard unit function test circuit as described in claim 3, characterized in that, The composition of each of the modules under test includes one of the following: A standard 6-input cell; One 1-input standard unit and one 5-input standard unit; One 2-input standard unit and one 4-input standard unit; Two 1-input standard cells and one 4-input standard cell; Two 3-input standard cells; One 1-input standard unit, one 2-input standard unit, and one 3-input standard unit; Three 1-input standard cells and one 3-input standard cell; Three 2-input standard cells; Two 1-input standard cells and two 2-input standard cells; Four 1-input standard cells and one 2-input standard cell; Six 1-input standard cells.

5. The standard unit function test circuit as described in claim 1, characterized in that, The selection control signal is an m-bit binary signal, where m is determined based on the number of modules under test.

6. The standard unit function test circuit as described in claim 5, characterized in that, The selection control signal is a 9-bit binary signal, and the number of modules under test is less than or equal to 512.

7. The standard unit function test circuit as described in claim 1, characterized in that, The number of output ports of each module under test is equal to the number of standard units within the module under test.

8. The standard unit function test circuit as described in claim 1, characterized in that, The input test signal generated by the input signal generation unit traverses from all 0 states to all 1 states.

9. The standard unit function test circuit as described in claim 1, characterized in that, The multiplexer adopts a multi-stage cascaded structure.

10. The standard unit function test circuit as described in claim 1, characterized in that, Each of the aforementioned standard units includes one of the following:

1. Input standard unit, including inverter and buffer; 2. Input standard units, including AND gates, OR gates, and XOR gates; 3-input standard unit, including three-input AND gate and three-input OR gate; 4. Input standard units, including NAND gates, AND-OR-NOT gates, OR-AND gates, and AND-OR gates; 5. Input standard units, including NAND gate, AND-OR-NOT gate, OR-AND gate, and AND-OR gate; 6. Input standard units, including NAND gate, AND-OR-NOT gate, OR-AND gate, and AND-OR gate.

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