Ultrasonic fingerprint sensor, ultrasonic fingerprint sensor module and electronic device

Abstract

The application discloses an ultrasonic fingerprint sensor, an ultrasonic fingerprint sensor module and an electronic device, and belongs to the technical field of ultrasonic fingerprint sensors.The ultrasonic fingerprint sensor comprises a chip layer, a piezoelectric layer, a conductive layer and an insulating layer.The chip layer comprises a substrate layer, a circuit layer, a metal wiring layer and a passivation layer.The metal wiring layer comprises an inner layer metal wiring layer and a top layer metal wiring layer.The chip layer is provided with chip pins on the periphery, and the chip pins comprise driving pins for driving electrical signals.A redistribution layer is arranged above the passivation layer.The passivation layer is provided with a first windowed area to expose the metal of the top layer metal wiring layer to form a driving electrode.The redistribution layer is provided with driving traces that can be electrically connected to the driving pins and the driving electrode.The thickness of the driving traces is configurable.The material of the driving traces is different from the material of the top layer metal wiring layer.In the application, the driving traces are arranged in the redistribution layer above the passivation layer, the thickness of the driving traces can be flexibly adjusted, and electromagnetic interference can be effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of sensor technology, and in particular to an ultrasonic fingerprint sensor, an ultrasonic fingerprint sensor module, and an electronic device. Background Technology

[0002] Ultrasonic fingerprint sensors enable fingerprint recognition and unlocking because when a finger touches the screen cover, the screen touch unit detects this information, sends it back to the phone system, and then performs a series of sensing, measurement, recognition, and unlocking actions.

[0003] In existing technologies, such as Figure 29 , Figure 30 , Figure 31 As shown, in the ultrasonic fingerprint sensor, a drive pin 110 responsible for driving electrical signals is set at the edge of the chip. A drive electrode 109 and a lower electrode 108, which are not connected to each other, are set on the same layer of the chip's top metal interconnect layer. The drive pin 110 and the drive electrode 109 are electrically connected through a drive trace 111. The drive pin 110, drive electrode 109, and drive trace 111 are set on the same layer, and the drive trace 111 and the metal of the top metal interconnect layer are of the same material and thickness, such as aluminum, aluminum-copper alloy, or aluminum-silicon-copper alloy.

[0004] The existing technology has the following drawbacks:

[0005] (1) The drive signal transmitted by the drive trace 111 has high requirements for transmission quality. The drive trace made of aluminum, aluminum-copper alloy, or aluminum-silicon-copper alloy has a large impedance and inevitably has transmission loss. Furthermore, since the design of the lower electrode thickness affects the acoustic performance of the sensor, and the lower electrode thickness is equal to the thickness of the top metal layer, it is usually not adjustable. Therefore, the thickness of the drive trace 111 cannot be adjusted at will. Its trace thickness is constrained, so it is impossible to reduce the impedance by thickening it.

[0006] (2) The driving signal transmitted by the driving trace 111 may have electrical characteristics such as high voltage and high frequency, which may easily cause electromagnetic interference to other signal traces of the top metal interconnect layer 102 of the CMOS chip, the inner metal traces of the CMOS chip, CMOS devices, etc., affecting the operation of the sensor.

[0007] Therefore, based on years of experience and practice in related industries, the inventor proposes an ultrasonic fingerprint sensor, an ultrasonic fingerprint sensor module, and an electronic device to overcome the shortcomings of the prior art. Summary of the Invention

[0008] The purpose of this invention is to provide an ultrasonic fingerprint sensor, an ultrasonic fingerprint sensor module, and an electronic device, overcoming the problems of limited drive trace thickness and electromagnetic interference of drive traces to other components in the prior art. In this invention, the drive trace is located on the redistribution layer above the passivation layer, the drive trace thickness can be flexibly adjusted, and electromagnetic interference can be effectively avoided.

[0009] The objective of this invention can also be achieved as follows: An ultrasonic fingerprint sensor includes a chip layer, a piezoelectric layer, a conductive layer, and an insulating layer. The chip layer includes a substrate layer, a circuit layer, a metal interconnect layer, and a passivation layer. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer. Chip pins are disposed around the periphery of the chip layer, and the chip pins include drive pins for driving electrical signals. A redistribution layer is disposed above the passivation layer. The passivation layer has a first window area exposing the metal of the top metal interconnect layer to form a drive electrode. Drive traces capable of electrically connecting the drive pins and the drive electrode are disposed within the redistribution layer. The thickness of the drive traces is configurable. The material of the drive traces is different from the material of the top metal interconnect layer.

[0010] In a preferred embodiment of the present invention, the drive trace is made of copper, silver, gold, titanium, nickel, tungsten, or a titanium-tungsten alloy.

[0011] In a preferred embodiment of the present invention, the passivation layer has a second window area to expose the metal of the top metal interconnect layer to form the lower electrode, and the passivation layer has a third window area to expose the metal of the top metal interconnect layer to form the chip pin.

[0012] In a preferred embodiment of the present invention, the metal of the top metal interconnect layer exposed in the first window area of ​​the passivation layer is isolated from the metal of the top metal interconnect layer exposed in the second window area of ​​the passivation layer.

[0013] In a preferred embodiment of the present invention, the chip pin further includes an external chip connection pin, and the length of at least one side of the window at the driving pin is greater than or equal to the length of the corresponding side of the window at the external chip connection pin.

[0014] In a preferred embodiment of the present invention, the driving electrode and the conductive layer are at least partially overlapped, and at the overlap location, the conductive layer covers the driving electrode.

[0015] In a preferred embodiment of the present invention, the driving electrode and the piezoelectric layer are partially overlapped, and at the overlap position, the piezoelectric layer covers the driving electrode.

[0016] In a preferred embodiment of the present invention, the drive trace and the drive electrode are at least partially overlapped, and at the overlapped position, the drive trace covers the drive electrode.

[0017] In a preferred embodiment of the present invention, the drive trace and the conductive layer are partially overlapped, and at the overlap position, the conductive layer covers the drive trace.

[0018] In a preferred embodiment of the present invention, the drive trace and the piezoelectric layer are partially overlapped, and at the overlap position, the piezoelectric layer covers the drive trace.

[0019] In a preferred embodiment of the present invention, conductive bumps are provided on each of the chip pins, and the top of the conductive bumps is higher than the top of the passivation layer and located within the redistribution layer; the cross-section of the conductive bumps is smaller than the cross-section of the corresponding chip pins.

[0020] The objective of this invention can also be achieved as follows: an ultrasonic fingerprint sensor includes a chip layer, a piezoelectric layer, a conductive layer, and an insulating layer. The chip layer includes a substrate layer, a circuit layer, a metal interconnect layer, and a passivation layer. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer. A redistribution layer is disposed above the passivation layer. The redistribution layer is provided with a driving electrode, driving traces, and driving pins. The driving traces are electrically connected to the driving pins and the driving electrode. The thickness of the driving traces is configurable. The material of the driving traces is different from the material of the top metal interconnect layer.

[0021] In a preferred embodiment of the present invention, the redistribution layer is provided with at least one driving module. Each driving module includes the driving electrode, the driving trace, and the driving pin. The metal in the area of ​​each driving module for bonding with the circuit board pin constitutes the driving pin. The metal in the area of ​​each driving module in contact with the conductive layer or the piezoelectric layer constitutes the driving electrode. The metal in the area of ​​each driving module electrically connecting the driving electrode and the driving pin constitutes the driving trace.

[0022] The objective of this invention can also be achieved as follows: an ultrasonic fingerprint sensor includes a chip layer, a piezoelectric layer, a conductive layer, and an insulating layer. The chip layer includes a substrate layer, a circuit layer, a metal interconnect layer, and a passivation layer. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer. Chip pins are disposed around the periphery of the chip layer, and the chip pins include drive pins for driving electrical signals. A redistribution layer is disposed above the passivation layer. A drive electrode is disposed in the redistribution layer. Drive traces capable of electrically connecting the drive pins and the drive electrode are disposed within the redistribution layer. The thickness of the drive traces is configurable. The material of the drive traces is different from the material of the top metal interconnect layer.

[0023] The object of the present invention can also be achieved by providing an ultrasonic fingerprint sensor module, including the aforementioned ultrasonic fingerprint sensor, wherein the ultrasonic fingerprint sensor is electrically connected to a circuit board.

[0024] In a preferred embodiment of the present invention, circuit board pins are provided on the circuit board; the ultrasonic fingerprint sensor and the circuit board pins are bonded together by anisotropic conductive adhesive.

[0025] The object of the present invention can also be achieved by providing an electronic device, including a screen, including the aforementioned ultrasonic fingerprint sensor module, wherein the ultrasonic fingerprint sensor module is fixedly connected to the screen.

[0026] In a preferred embodiment of the present invention, an adhesive layer is disposed on the side of the substrate layer away from the piezoelectric layer, and the chip layer is fixedly connected to the screen through the adhesive layer.

[0027] As described above, the ultrasonic fingerprint sensor, ultrasonic fingerprint sensor module, and electronic device of the present invention have the following beneficial effects:

[0028] In this invention, the driving signals transmitted by the driving traces may have electrical characteristics such as high voltage and high frequency. The driving traces are located above the passivation layer and are far away from the chip circuit. They are less likely to cause electromagnetic interference to other signal traces on the top metal interconnect layer of the CMOS chip, the inner metal traces of the CMOS chip, CMOS devices, etc., thus avoiding affecting the operation of the sensor.

[0029] The drive signals transmitted by the drive traces have high requirements for transmission quality. Using redistribution layer technology to fabricate drive traces allows the use of metals with good electrical properties, reducing electrical losses; and the trace thickness can be adjusted to be thicker, which is beneficial for further optimization of electrical performance.

[0030] Rerouting layer technology is a mature technology with simple processes and low costs. Attached Figure Description

[0031] The following figures are intended only to illustrate and explain the present invention and do not limit the scope of the invention. Wherein:

[0032] Figure 1 This is a cross-sectional view of Embodiment 1 of the ultrasonic fingerprint sensor of the present invention.

[0033] Figure 2 for Figure 1 Enlarged view of section I in the middle.

[0034] Figure 3 This is a top view of the passivation layer and redistribution layer of an embodiment 1 of the ultrasonic fingerprint sensor of the present invention.

[0035] Figure 4 This is a top view of the passivation layer, redistribution layer, piezoelectric layer, and conductive layer of Embodiment 1 of the ultrasonic fingerprint sensor of the present invention.

[0036] Figure 5 This is a cross-sectional view of Embodiment 2 of the ultrasonic fingerprint sensor of the present invention.

[0037] Figure 6 for Figure 5 Enlarged view of section II in the middle.

[0038] Figure 7 This is a top view of the passivation layer and redistribution layer of an embodiment 2 of the ultrasonic fingerprint sensor of the present invention.

[0039] Figure 8 This is a top view of the passivation layer, redistribution layer, piezoelectric layer, and conductive layer of Embodiment 2 of the ultrasonic fingerprint sensor of the present invention.

[0040] Figure 9 This is a cross-sectional view of Embodiment 3 of the ultrasonic fingerprint sensor of the present invention.

[0041] Figure 10 for Figure 9 Enlarged view of section III.

[0042] Figure 11 This is a top view of the passivation layer and redistribution layer of Embodiment 3 of the ultrasonic fingerprint sensor of the present invention.

[0043] Figure 12 This is a top view of the passivation layer, redistribution layer, piezoelectric layer, and conductive layer of Embodiment 3 of the ultrasonic fingerprint sensor of the present invention.

[0044] Figure 13 This is a cross-sectional view of Embodiment 4 of the ultrasonic fingerprint sensor of the present invention.

[0045] Figure 14 for Figure 13 Enlarged view of section VII.

[0046] Figure 15This is a top view of the passivation layer and redistribution layer of Embodiment 4 of the ultrasonic fingerprint sensor of the present invention.

[0047] Figure 16 This is a top view of the passivation layer, redistribution layer, piezoelectric layer, and conductive layer of Embodiment 4 of the ultrasonic fingerprint sensor of the present invention.

[0048] Figure 17 This is a schematic diagram of an ultrasonic fingerprint sensor module including the ultrasonic fingerprint sensor of Embodiment 1 of the present invention.

[0049] Figure 18 for Figure 17 Enlarged view of section IV in the middle.

[0050] Figure 19 This is a schematic diagram of the ultrasonic fingerprint sensor module of the present invention, including the ultrasonic fingerprint sensor of Embodiment 2.

[0051] Figure 20 for Figure 19 Enlarged view of section V.

[0052] Figure 21 This is a schematic diagram of an ultrasonic fingerprint sensor module including the ultrasonic fingerprint sensor of Embodiment 3 of the present invention.

[0053] Figure 22 for Figure 21 Enlarged view of section VI.

[0054] Figure 23 This is a schematic diagram of the ultrasonic fingerprint sensor module of the present invention, including the ultrasonic fingerprint sensor of Embodiment 4.

[0055] Figure 24 for Figure 23 Enlarged view of section VIII.

[0056] Figure 25 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 1 of the present invention.

[0057] Figure 26 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 2 of the present invention.

[0058] Figure 27 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 3 of the present invention.

[0059] Figure 28 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 4 of the present invention.

[0060] Figure 29 This is a cross-sectional view of a conventional ultrasonic fingerprint sensor.

[0061] Figure 30This is a top view of the passivation layer of a conventional ultrasonic fingerprint sensor.

[0062] Figure 31 This is a top view of the passivation layer, piezoelectric layer, and conductive layer of a conventional ultrasonic fingerprint sensor.

[0063] In the picture:

[0064] 101. Substrate layer; 102. Top metal interconnect layer; 103. Passivation layer; 104. Piezoelectric layer; 105. Conductive layer; 106. Insulating layer; 107. Chip external connection pin; 108. Bottom electrode; 109. Driving electrode; 110. Driving pin; 111. Driving trace; 112. Circuit board; 113. Circuit board pin; 114. Anisotropic conductive adhesive; 115. Adhesive layer; 116. Screen; 117. Conductive bump; 118. Fingerprint sensor. Detailed Implementation

[0065] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0066] The specific embodiments of the present invention described herein are for illustrative purposes only and should not be construed as limiting the invention in any way. Under the teachings of this invention, those skilled in the art can conceive of any possible modifications based on the invention, all of which should be considered within the scope of the invention. It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there may be an intervening element. The terms "mounted," "connected," and "linked" should be interpreted broadly; for example, they can refer to mechanical or electrical connections, or internal communication between two elements, and can be direct or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible embodiments.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0068] like Figures 1 to 12As shown, the present invention provides an ultrasonic fingerprint sensor, including a chip layer, a piezoelectric layer 104, a conductive layer 105 and an insulating layer 106. The chip layer includes a substrate layer 101, a circuit layer, a metal interconnect layer and a passivation layer 103. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer 102. Chip pins are disposed around the chip layer, and the chip pins include drive pins 110 for driving electrical signals.

[0069] The piezoelectric layer 104 is made of a piezoelectric material, such as polyvinylidene fluoride (PVDF); the conductive layer 105 is made of a conductive material, such as silver paste; the conductive layer 105 can serve as the upper electrode of the ultrasonic sensor; the insulating layer 106 is made of an insulating material, such as resin; the insulating layer 106 can protect the conductive layer 105.

[0070] The substrate layer 101 may include a silicon substrate, a glass substrate, or an SOI substrate, etc. The circuit layer may include a CMOS circuit or a TFT circuit, etc. The metal interconnect layer includes an inner metal interconnect layer (which may include multiple layers) and a top metal interconnect layer 102, and the dielectric layer is disposed between the inner metal interconnect layer and the top metal interconnect layer 102.

[0071] In this embodiment, the chip layer is a silicon-based CMOS chip, its substrate layer 101 is a silicon substrate, and the circuit layer is a CMOS circuit layer (CMOS device located on the surface of the silicon substrate). The passivation layer 103 of the chip layer can be used to protect the top metal interconnect layer 102, and the top metal can be exposed through the opening of the passivation layer 103 to form pins that can be used for subsequent electrical connection with the outside, as well as driving electrodes 109 and lower electrodes 108. The passivation layer opening area on the chip layer used for electrical signal lead-out is called the chip pin, which is divided into driving pin 110 and chip external connection pin 107 (other pins). The driving pin 110 is mainly responsible for driving electrical signals, while the chip external connection pin 107 (other pins) may be responsible for communication signals, power supply, ground, etc. These pins are typically located at the edge (periphery) of the chip layer; in the sensing area of ​​the chip layer, the passivation layer window array area used to contact the piezoelectric layer 104 is called the lower electrode 108; the driving electrode 109 is in direct contact with the conductive layer 105 and is electrically connected; in order for the driving electrode 109 to receive external driving voltage signals, the driving pin 110 located at the edge of the chip is electrically connected to the driving electrode 109, and this connection line is called the driving trace 111, which is generally implemented through the top metal interconnect in the prior art; apart from being connected to the driving pin 110 via the driving trace 111, the driving electrode 109 is not electrically connected to the lower electrode 108 or other chip pins (chip external connection pins 107) that are not driving pins via the top metal interconnect layer 102; driving electrodes that are not shorted to each other in the top metal interconnect layer are defined as an independent driving electrode, and the number of driving electrodes 109 can be only one or more.

[0072] Unlike existing technologies, in this invention, a redistribution layer is disposed above the passivation layer 103; the passivation layer 103 has a first window area exposing the top metal to form the driving electrode 109 (e.g., Figure 1 , Figure 2 , Figure 5 , Figure 6 (as shown), or, the redistribution layer is configured with drive electrodes 109 (as shown). Figure 9 , Figure 10 (as shown), or, the redistribution layer sets the drive electrode 109 and drive pin 110 (as shown). Figure 13 , Figure 14 As shown). Figure 1 , Figure 2 , Figure 5 , Figure 6 , Figure 9 , Figure 10 , Figure 13 , Figure 14 As shown, a drive trace 111 is provided in the redistribution layer to electrically connect the drive pin 110 and the drive electrode 109. The thickness of the drive trace 111 is configurable. The material of the drive trace 111 is different from that of the top metal interconnect layer 102 (the drive trace 111 and the top metal interconnect layer 102 are made of different materials).

[0073] Common metal materials used in the top metal interconnect layer 102 include aluminum, aluminum-copper alloy, and aluminum-silicon-copper alloy. Using these materials for driver traces results in high impedance and unavoidable transmission loss. In this application, the driver trace 111 is constructed from a different material than the top metal interconnect layer 102, thereby optimizing transmission performance.

[0074] In this invention, the drive trace 111 is located on the redistribution layer, and its thickness can be flexibly configured, for example, 1.5μm to 10μm. The thickness of the drive trace 111 can be configured to be a thicker dimension (the thickness of the drive trace 111 is ≥1.5μm).

[0075] The drive trace 111 is not covered by the passivation layer 103, and has electrical contact with both the drive electrode 109 and the drive pin 110, thus meeting the requirement for electrical connection between the drive pin 110 and the drive electrode 109.

[0076] In this invention, the driving signal transmitted by the driving trace 111 may have electrical characteristics such as high voltage and high frequency. The driving trace 111 is located above the passivation layer 103 and is far away from the chip circuit. It is not easy to cause electromagnetic interference to other signal traces of the top metal interconnect layer 102 of the CMOS chip, the inner metal traces of the CMOS chip, CMOS devices, etc., so as to avoid affecting the operation of the sensor.

[0077] The drive signal transmitted by the drive trace 111 has high requirements for transmission quality. The drive trace 111 is made using redistribution layer technology, which allows the use of metals with good electrical properties to reduce electrical losses. In addition, the trace thickness can be adjusted to be thicker (≥1.5μm), which is beneficial for further optimization of electrical performance.

[0078] Rerouting layer technology is a mature technology with simple processes and low costs.

[0079] Furthermore, the drive trace 111 is located in the redistribution layer and is made of a different material from the top metal interconnect layer 102. The drive trace 111 can be made of metals such as copper, silver, gold, titanium, nickel, tungsten, or titanium-tungsten alloy. Alternatively, a multi-layered metal redistribution layer with a hierarchical structure can be used, such as a redistribution layer of titanium, copper, nickel, and gold deposited sequentially from the inside out.

[0080] In the chip manufacturing process, a top metal interconnect layer 102 is first formed on the first dielectric layer of the substrate (the dielectric layer between the inner metal interconnect layer and the top metal interconnect layer 102, including openings). Then, a second dielectric layer is formed on the first dielectric layer, with some openings in the second dielectric layer exposing the top metal. Finally, a redistribution layer is formed on the second dielectric layer, filling the aforementioned openings to form conductive pads. These conductive pads are connected to the top metal. It can be understood that the top metal is a key node for the redistribution layer to connect to the internal circuitry of the substrate. The redistribution layer is connected to the top metal through conductive pads, thereby achieving electrical connection with the metal layers in the substrate.

[0081] The top metal layer serves as a transition between the circuitry within the substrate and the redistribution layer, acting as a means to transmit electrical signals from the substrate to the redistribution layer. The redistribution layer, in turn, is responsible for rearranging the signal transmission path, guiding the signal from the top metal layer to a more suitable location. Therefore, the redistribution layer can include single or multiple redistribution layers, with dielectric layers placed between adjacent redistribution layers.

[0082] Compared with metal interconnection, rewiring is simpler and less expensive.

[0083] The drive traces can be set in one or more layers of the redistribution layer using the redistribution process.

[0084] Furthermore, such as Figure 3 , Figure 4 , Figure 7 , Figure 8 , Figure 11 , Figure 12 As shown, the passivation layer 103 has a second window area to expose the metal of the top metal interconnect layer 102 to form the lower electrode 108, and the passivation layer 103 has a third window area to expose the metal of the top metal interconnect layer 102 to form the chip pin.

[0085] The metal of the top metal interconnect layer (driving electrode 109, electrically connected to conductive layer 105) exposed in the first window area of ​​passivation layer 103 is isolated from the metal of the top metal interconnect layer (lower electrode 108) exposed in the second window area of ​​passivation layer 103, that is, the driving electrode 109 and the lower electrode 108 are not connected to each other.

[0086] Furthermore, such as Figure 1 , Figure 2 , Figure 9 , Figure 10 As shown, conductive bumps 117 can be provided inside the chip pins (i.e., conductive bumps 117 are provided on each chip pin). The top of the conductive bump 117 is higher than the top of the passivation layer 103 and is located in the redistribution layer. The cross-section of the conductive bump 117 is smaller than the cross-section of the corresponding chip pin.

[0087] The top of the conductive bump 117 is higher than the top of the passivation layer 103, which helps to improve the bonding effect between the chip pins and the circuit board pins 113 of the ultrasonic fingerprint sensor module. This allows the conductive particles in the anisotropic conductive adhesive 114 of the ultrasonic fingerprint sensor module to preferentially contact the top of the conductive bump 117 rather than the top of the passivation layer 103 during the bonding process under a smaller bonding pressure. To ensure that the top of the conductive bump 117 is higher than the top of the passivation layer 103, the thickness of the conductive bump 117 needs to be specifically designed, for example, the thickness of the conductive bump 117 is greater than the thickness of the passivation layer 103.

[0088] The circuit board pin 113 (bonding pin on the substrate side) and the conductive bump 117 are bonded together by anisotropic conductive adhesive 114, which indirectly realizes the transmission of external electrical signals and electrical signals of chip pins.

[0089] A conductive bump 117 can be fabricated on the driver pin 110 and other pins using redistribution layer technology. The top of the conductive bump 117 is higher than the top of the passivation layer 103, which helps to improve the bonding effect between the chip pin, the driver pin and the circuit board pin.

[0090] In addition, when the conductive bumps 117 are not provided on the chip pins, the circuit board pins 113 of the ultrasonic fingerprint sensor module can also be directly bonded to the chip pins through the anisotropic conductive adhesive 114. Whether to provide conductive bumps 117 can be decided by comprehensive consideration.

[0091] Furthermore, such as Figure 3 , Figure 4 , Figure 7 , Figure 8 , Figure 11 , Figure 12As shown, the chip pins include a drive pin 110 and an external connection pin 107 (other pins). The length of at least one side of the window at the drive pin 110 is greater than or equal to the length of the corresponding side of the window at the external connection pin 107.

[0092] The drive pin 110 needs to be bonded to the outside world and also needs to be connected to the drive trace 111 on the chip surface; while the external connection pin 107 (other pins besides the drive pin) only needs to be bonded to the outside world; combined with the fact that the drive pin 110 will have a larger voltage, the drive pin 110 is usually not smaller than the external connection pin 107.

[0093] Furthermore, the driving electrode 109 and the conductive layer 105 are at least partially overlapped. At the overlap location, the conductive layer 105 covers the driving electrode 109 (i.e., at the overlap location, the conductive layer 105 is located above the driving electrode 109). The conductive layer 105 and the driving electrode 109 have an overlapping portion. The conductive layer 105 covers one edge of the driving electrode 109, which may extend beyond or not extend beyond the opposite edge. That is, the conductive layer 105 may fully cover the driving electrode 109 or only partially cover it. Figure 4 As can be seen, the edge of the conductive layer 105 coincides with, but does not exceed, the edge of the driving electrode 109 on the other side. Figure 8 As can be seen, the conductive layer 105 extends beyond the edge of the driving electrode 109 on the other side.

[0094] Furthermore, the driving electrode 109 and the piezoelectric layer 104 are partially overlapped, with the piezoelectric layer 104 covering the driving electrode 109 at the overlap location. Figure 4 , Figure 8 , Figure 12 As can be seen, the piezoelectric layer 104 covers one edge of the driving electrode 109, but does not extend beyond the opposite edge.

[0095] Furthermore, by Figure 2 , Figure 6 , Figure 10 As can be seen, the drive trace 111 and the drive electrode 109 are at least partially overlapped. At the overlap position, the drive trace 111 covers the drive electrode 109 to achieve electrical connection between the two.

[0096] Furthermore, by Figure 2 , Figure 6 , Figure 10 As can be seen, the drive trace 111 and the conductive layer 105 can be partially overlapped, and at the overlap position, the conductive layer 105 covers the drive trace 111.

[0097] The drive trace 111 and the conductive layer 105 can also be non-overlapping.

[0098] Furthermore, the drive trace 111 and the piezoelectric layer 104 can be partially overlapped, with the piezoelectric layer 104 covering the drive trace 111 at the overlap location.

[0099] like Figure 2 , Figure 6 , Figure 10 As shown, the drive trace 111 and the piezoelectric layer 104 can also be non-overlapping.

[0100] Furthermore, such as Figure 1 , Figure 2 As shown, the conductive layer 105 and the piezoelectric layer 104 are partially overlapped, and at the overlap position, the conductive layer 105 covers the piezoelectric layer 104.

[0101] Example 1:

[0102] like Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, in this embodiment, the driving trace 111 is located on the redistribution layer above the passivation layer 103, and the driving electrode 109 is located in the passivation layer opening area of ​​the top metal interconnect layer 102. That is, the passivation layer 103 is provided with a first window area to expose the top metal to form the driving electrode 109; the driving pin 110 is located in the passivation layer opening area of ​​the top metal interconnect layer 102. That is, the passivation layer 103 is provided with a third window area to expose the top metal to form the chip pin, which includes the driving pin 110; the driving trace 111 makes the driving pin 110 and the driving electrode 109 electrically connected.

[0103] like Figure 1 , Figure 2 As shown, there are conductive bumps 117 located in the redistribution layer within the chip pins. The top of the conductive bumps 117 is higher than the top of the passivation layer 103, which helps to improve the bonding effect between the chip pins and the circuit board pins. This allows the conductive particles in the anisotropic conductive adhesive 114 to preferentially contact the top of the conductive bumps 117 rather than the top of the passivation layer 103 during the bonding process under a smaller bonding pressure. To ensure that the top of the conductive bumps 117 is higher than the top of the passivation layer 103, the thickness of the conductive bumps 117 is specifically designed, such as the thickness of the conductive bumps 117 being greater than the thickness of the passivation layer 103.

[0104] like Figure 3 , Figure 4 As shown, the length of at least one side of the window at the drive pin 110 must be greater than or equal to the length of the corresponding side of the window at the external connection pin 107 (other pins).

[0105] Conductive bumps 117 are fabricated on all chip pins. The pattern of the conductive bump 117 is smaller than the corresponding pin, that is, the pattern of the conductive bump 117 is inside the pin area. The circuit board pins 113 (bonding pins on the substrate side) and the conductive bumps are bonded to each other through anisotropic conductive adhesive 114, thereby indirectly realizing the transmission of external electrical signals and electrical signals between the chip pins.

[0106] from Figure 2 , Figure 4 From above, the conductive layer 105 and the driving electrode 109 have an overlapping portion. The conductive layer 105 covers one edge of the driving electrode 109, which may extend beyond the opposite edge, or may not extend beyond it. Figure 4 This is the case where the edge of the conductive layer 105 coincides with the edge of the other side of the driving electrode 109, but does not exceed it.

[0107] from Figure 2 , Figure 4 From above, the piezoelectric layer 104 and the driving electrode 109 have an overlapping portion. The piezoelectric layer 104 covers one edge of the driving electrode 109, but does not extend beyond the opposite edge.

[0108] from Figure 2 , Figure 4 Looking at the top view, the drive trace 111 of the redistribution layer and the drive electrode 109 have an overlapping portion; the drive trace 111 of the redistribution layer and the conductive layer 105 may or may not have an overlapping portion. Figure 2 , Figure 4 In cases where there is an overlap, the conductive layer 105 covers the drive trace 111 within this overlap area. The drive trace 111 of the redistribution layer and the piezoelectric layer 104 may or may not overlap. Figure 2 , Figure 4 In the case of no overlapping portion, when there is an overlapping portion, the piezoelectric layer 104 covers the drive trace 111 within the overlapping portion.

[0109] from Figure 2 Looking at the top, the conductive layer 105 and the piezoelectric layer 104 have an overlapping portion, and within this overlapping portion, the conductive layer 105 covers the piezoelectric layer 104.

[0110] Example 2:

[0111] like Figure 5 , Figure 6 , Figure 7 , Figure 8 As shown, the difference between this embodiment and Embodiment 1 is that:

[0112] There are no conductive bumps 117 inside the chip pins. The circuit board pins can also be directly bonded to the chip pins through anisotropic conductive adhesive 114 to realize the transmission of external electrical signals and electrical signals between the chip pins.

[0113] In this embodiment, the overlap pattern of the conductive layer 105 and the driving electrode 109 is different from that in Embodiment 1. Figure 8 This refers to the case where the conductive layer 105 extends beyond the edge of the driving electrode 109 on the other side.

[0114] Example 3:

[0115] like Figure 9 , Figure 10 , Figure 11 , Figure 12 As shown, the difference between this embodiment and Embodiment 1 is that the driving electrode 109 is disposed on the redistribution layer above the passivation layer 103. By disposing of the driving electrode 109 on the redistribution layer, isolation between the driving electrode 109 and the lower electrode is achieved, allowing for more flexible design of the lower electrode region in the top metal interconnect layer 102 and reducing the design complexity of the top metal interconnect layer 102.

[0116] The driving electrode is no longer determined by the passivation layer opening area, but is natively part of a metal pattern in the redistribution layer. Therefore, the conductive bumps, driving traces, and driving electrodes that are shorted to each other in the redistribution layer can also be regarded as a driving module. The number of driving modules is ≥1. The metal on the driving module that is bonded to the substrate side pin and falls within the opening area of ​​the driving pin is called a conductive bump because it has a thickness higher than the passivation layer within the opening. The part of the metal on the driving module that is in contact with the conductive layer or piezoelectric layer is called the driving electrode. The metal pattern area of ​​a driving module other than the conductive bumps and driving electrodes is called the driving trace.

[0117] In this embodiment, the overlap between the driving electrode 109 and the driving trace 111 differs from that in Embodiment 1. In this embodiment, the driving electrode 109 and the driving trace 111 are on the same redistribution layer, with no overlapping coverage.

[0118] from Figure 10 , Figure 12 Looking at the top, the conductive layer 105 and the driving electrode 109 have overlapping portions.

[0119] like Figure 10 , Figure 12 As shown, the driving electrode 109 and the piezoelectric layer 104 are at least partially overlapped, and at the overlap position, the piezoelectric layer 104 covers the driving electrode 109.

[0120] from Figure 10Looking at the top, the conductive layer 105 and the piezoelectric layer 104 have an overlapping portion, and within this overlapping portion, the conductive layer 105 covers the piezoelectric layer 104.

[0121] Example 4:

[0122] like Figure 13 , Figure 14 , Figure 15 , Figure 16 As shown, in this invention, a redistribution layer is disposed above the passivation layer 103; the redistribution layer is provided with a driving electrode 109, a driving trace 111 and a driving pin 110, and the driving trace 111 is electrically connected to the driving pin 110 and the driving electrode 109; the thickness of the driving trace 111 is configurable; the material of the driving trace 111 is different from the material of the top metal interconnect layer 102 (the driving trace 111 and the top metal interconnect layer 102 are made of different materials).

[0123] Common metal materials used in the top metal interconnect layer 102 include aluminum, aluminum-copper alloy, and aluminum-silicon-copper alloy. Using these materials for driver traces results in high impedance and unavoidable transmission loss. In this application, the driver trace 111 is constructed from a different material than the top metal interconnect layer 102, thereby optimizing transmission performance.

[0124] In this invention, the drive trace 111 is located in the redistribution layer, and its thickness can be flexibly configured, for example, 1.5μm to 10μm.

[0125] The drive trace 111 is not covered by the passivation layer 103, and has electrical contact with both the drive electrode 109 and the drive pin 110, thus meeting the requirement for electrical connection between the drive pin 110 and the drive electrode 109.

[0126] In this invention, the driving signal transmitted by the driving trace 111 may have electrical characteristics such as high voltage and high frequency. The driving trace 111 is located above the passivation layer 103 and is far away from the chip circuit. It is not easy to cause electromagnetic interference to other signal traces of the top metal interconnect layer 102 of the CMOS chip, the inner metal traces of the CMOS chip, CMOS devices, etc., so as to avoid affecting the operation of the sensor.

[0127] The drive signal transmitted by the drive trace 111 has high requirements for transmission quality. The drive trace 111 is made using redistribution layer technology, which allows the use of metals with good electrical properties to reduce electrical losses. In addition, the trace thickness can be adjusted to be thicker (≥1.5μm), which is beneficial for further optimization of electrical performance.

[0128] Rerouting layer technology is a mature technology with simple processes and low costs.

[0129] Furthermore, the drive trace 111 is located in the redistribution layer and is made of a different material from the top metal interconnect layer 102. The drive trace 111 can be made of metal materials such as copper, silver, gold, titanium, nickel, tungsten or titanium-tungsten alloy.

[0130] Alternatively, a multilayer metal redistribution layer with a hierarchical structure can be created, such as a redistribution layer of titanium, copper, nickel, and gold deposited sequentially from the inside out.

[0131] In the chip manufacturing process, a top metal interconnect layer 102 is first formed on the first dielectric layer of the substrate (the dielectric layer between the inner metal interconnect layer and the top metal interconnect layer 102, including openings). Then, a second dielectric layer is formed on the first dielectric layer, with some openings in the second dielectric layer exposing the top metal. Finally, a redistribution layer is formed on the second dielectric layer, filling the aforementioned openings to form conductive pads. These conductive pads are connected to the top metal. It can be understood that the top metal is a key node for the redistribution layer to connect to the internal circuitry of the substrate. The redistribution layer is connected to the top metal through conductive pads, thereby achieving electrical connection with the metal layers in the substrate.

[0132] The top metal layer serves as a transition between the circuitry within the substrate and the redistribution layer, acting as a means to transmit electrical signals from the substrate to the redistribution layer. The redistribution layer, in turn, is responsible for rearranging the signal transmission path, guiding the signal from the top metal layer to a more suitable location. Therefore, the redistribution layer can include single or multiple redistribution layers, with dielectric layers placed between adjacent redistribution layers.

[0133] Compared with metal interconnection, rewiring is simpler and less expensive.

[0134] The drive traces can be set in one or more layers of the redistribution layer using the redistribution process.

[0135] Furthermore, the passivation layer 103 is provided with a second window area to expose the metal of the top metal interconnect layer 102 to form the lower electrode 108.

[0136] Furthermore, such as Figure 15 , Figure 16 As shown, the passivation layer 103 has a second window area exposed to form the chip external connection pin 107 of the top layer metal. The length of at least one side of the drive pin 110 is greater than or equal to the length of the window on the corresponding side of the chip external connection pin 107.

[0137] The drive pin 110 needs to be bonded to the outside world and also needs to be connected to the drive trace 111 on the chip surface; while the external connection pin 107 (other pins besides the drive pin) only needs to be bonded to the outside world; combined with the fact that the drive pin 110 will have a larger voltage, the drive pin 110 is usually not smaller than the external connection pin 107.

[0138] Furthermore, conductive bumps 117 can be provided inside the chip pins (i.e., conductive bumps are provided on each chip external connection pin 107). The top of the conductive bump is higher than the top of the passivation layer 103 and is located in the redistribution layer; the cross-section of the conductive bump is smaller than the cross-section of the corresponding chip external connection pin 107.

[0139] The top of the conductive bump is higher than the top of the passivation layer 103, which helps to improve the bonding effect between the external connection pin 107 of the chip and the circuit board pin 113 of the ultrasonic fingerprint sensor module. This allows the conductive particles in the anisotropic conductive adhesive 114 of the ultrasonic fingerprint sensor module to preferentially contact the top of the conductive bump rather than the top of the passivation layer 103 during the bonding process under a smaller bonding pressure. To ensure that the top of the conductive bump is higher than the top of the passivation layer 103, the thickness of the conductive bump needs to be specifically designed, for example, the thickness of the conductive bump is greater than the thickness of the passivation layer 103.

[0140] The circuit board pin 113 (bonding pin on the substrate side) and the conductive bump 117 are bonded together by anisotropic conductive adhesive 114, which indirectly realizes the transmission of external electrical signals and electrical signals of chip pins.

[0141] A conductive bump can be fabricated on the driver pin 110 and the chip external connection pin 107 using redistribution layer technology. The top of the conductive bump is higher than the top of the passivation layer 103, which helps to improve the bonding effect between the chip external connection pin 107, the driver pin 110 and the circuit board pin 113.

[0142] In addition, when the conductive bumps 117 are not provided on the chip pins, the circuit board pins 113 of the ultrasonic fingerprint sensor module can also be directly bonded to the chip pins through the anisotropic conductive adhesive 114. Whether to provide conductive bumps 117 can be decided by comprehensive consideration.

[0143] Furthermore, such as Figure 13 , Figure 14 , Figure 15 , Figure 16As shown, the redistribution layer has at least one driving module. Each driving module includes a driving electrode 109, a driving trace 111, and a driving pin 110. By placing the driving electrode 109 and driving pin 110 in the redistribution layer, isolation is achieved between the driving electrode 109 and the lower electrode, and between the driving pin 110 and non-driving pins (external connection pin 107). Designing and fabricating the driving trace 111, driving electrode 109, and driving pin 110 all in the redistribution layer facilitates global routing layout. Furthermore, the driving pin 110 and the conductive bump 117 are both located in the redistribution layer. The wiring layer is designed and fabricated to facilitate material and process compatibility at the bonding interface and to improve the bonding effect between the chip external connection pin 107, the drive pin 110 and the circuit board pin 113. The metal in the area where each drive module is bonded to the circuit board pin 113 of the ultrasonic fingerprint sensor module constitutes the drive pin 110. The metal in the area where each drive module contacts the conductive layer 105 or the piezoelectric layer 104 constitutes the drive electrode 109. The metal in the area where each drive module is electrically connected to the drive electrode 109 and the drive pin 110 constitutes the drive trace 111.

[0144] Specifically, since the driving electrode 109 and driving pin 110 are no longer defined by the opening area of ​​the passivation layer 103, but are natively part of a metal pattern in the redistribution layer, the driving pin 110, driving trace 111, and driving electrode 109 that are shorted to each other in the redistribution layer can also be regarded as a driving module. The number of driving modules is ≥1. The metal on the driving module that is bonded to the circuit board pin 113 (substrate-side bonding pin) is called the driving pin 110. The part of the metal on the driving module that is in contact with the conductive layer 105 or the piezoelectric layer 104 is called the driving electrode 109. The metal pattern area of ​​a driving module other than the conductive bump and the driving electrode 109 is called the driving trace.

[0145] Furthermore, such as Figure 13 , Figure 14 , Figure 15 , Figure 16 As shown, the driving electrode 109 and the conductive layer 105 are at least partially overlapped. At the overlap position, the conductive layer 105 covers the driving electrode 109 (i.e., at the overlap position, the conductive layer 105 is located above the driving electrode 109).

[0146] Furthermore, such as Figure 13 , Figure 14 , Figure 15 , Figure 16 As shown, the driving electrode 109 and the piezoelectric layer 104 are partially overlapped, and at the overlap position, the piezoelectric layer 104 covers the driving electrode 109.

[0147] Furthermore, such as Figure 13 , Figure 14, Figure 15 , Figure 16 As shown, the conductive layer 105 and the piezoelectric layer 104 are partially overlapped, and at the overlap position, the conductive layer 105 covers the piezoelectric layer 104.

[0148] Example 5:

[0149] In a typical implementation of the prior art, the driving trace is implemented using a top metal wiring layer covered by a passivation layer, transmitting a square wave signal with a voltage of 10-200V to ground and a frequency of 8-15MHz. The following model uses 200V and 14MHz. The driving trace has a metal line width of 100μm, a length of 480μm, is made of aluminum, and has a thickness of 0.9μm. However, using the technology of this invention, the driving trace 111 is implemented using a redistribution layer located above the passivation layer 103, with the line width and length remaining unchanged, made of silver, and a thickness of 2μm. A comparison of theoretical calculations and experimental data is as follows:

[0150] 1. Transmission Loss Analysis

[0151] (1) DC resistance comparison is shown in Table 1:

[0152] Table 1

[0153]

[0154] (2) High-frequency AC loss (14MHz)

[0155] Current estimation (50Ω load):

[0156] Aluminum: I_Al = 200V / (50Ω+1.504Ω) ≈ 3.88A;

[0157] Silver: I_Ag = 200V / (50Ω+0.3816Ω) ≈ 3.97A;

[0158] Power loss:

[0159] Aluminum: P_Al = (3.88A)² × 1.504Ω ≈ 22.65W;

[0160] Silver: P_Ag = (3.97A)² × 0.3816Ω ≈ 6.01W;

[0161] Losses were reduced by 73.5% (energy saving of 16.64W).

[0162] 2. Electromagnetic Interference (EMI) Analysis

[0163] (1) Comparison of radiation mechanisms is shown in Table 2:

[0164] Table 2

[0165]

[0166] (2) Signal integrity comparisons are shown in Table 3:

[0167] Table 3

[0168]

[0169] 3. Comparison of overall performance is shown in Table 4:

[0170] Table 4

[0171]

[0172] like Figures 17 to 24 As shown, the present invention also provides an ultrasonic fingerprint sensor module, including the aforementioned ultrasonic fingerprint sensor and ultrasonic fingerprint sensor electrical connection circuit board 112.

[0173] Figure 17 This is a schematic diagram of an ultrasonic fingerprint sensor module including the ultrasonic fingerprint sensor of Embodiment 1 of the present invention. Figure 19 This is a schematic diagram of the ultrasonic fingerprint sensor module of the present invention, including the ultrasonic fingerprint sensor of Embodiment 2. Figure 21 This is a schematic diagram of an ultrasonic fingerprint sensor module including the ultrasonic fingerprint sensor of Embodiment 3 of the present invention. Figure 23 This is a schematic diagram of the ultrasonic fingerprint sensor module of the present invention, including the ultrasonic fingerprint sensor of Embodiment 4.

[0174] Furthermore, such as Figures 17 to 24 As shown, circuit board pins 113 are provided on circuit board 112; the ultrasonic fingerprint sensor and circuit board pins 113 are bonded to each other through anisotropic conductive adhesive 114.

[0175] The circuit board 112 is composed of a substrate, a circuit layer, an insulating layer, etc. The substrate can be a flexible material, such as a flexible printed circuit board (FPC). The terminal circuits of the FPC are not covered by the insulating layer but exposed, and can be used for electrical connection with the outside. The circuit board pins 113 are used for electrical connection with the outside. The anisotropic conductive adhesive 114 is located between the circuit board pins 113 and the chip pins. Using the bonding process, the circuit board pins 113, the chip pins, and the drive pins can be fixed to each other and electrically connected, so that the chip layer can exchange electrical signals and energy with the outside.

[0176] like Figures 25 to 28 As shown, the present invention also provides an electronic device, including a screen 116, including the aforementioned ultrasonic fingerprint sensor module, wherein the ultrasonic fingerprint sensor module is fixedly connected to the screen 116. Figure 25 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 1 of the present invention; Figure 26This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 2 of the present invention; Figure 27 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 3 of the present invention. Figure 28 This is a schematic diagram of an electronic device including the ultrasonic fingerprint sensor of Embodiment 3 of the present invention.

[0177] Furthermore, such as Figures 25 to 28 As shown, an adhesive layer 115 is disposed on the side of the substrate layer 101 away from the piezoelectric layer 104, and the chip layer is fixedly connected to the screen 116 through the adhesive layer 115.

[0178] Specifically, the adhesive layer 115 fixes the silicon substrate side of the ultrasonic sensor to the substrate side of the screen; the screen 116, for example, is a screen composed of a cover plate, transparent adhesive, polarizer, display panel, organic substrate, etc.

[0179] The basic working principle of the electronic device of the present invention, including the aforementioned ultrasonic fingerprint sensor module, is as follows:

[0180] During the emission phase: The pixel electrode (in the prior art, the pixel electrode is the core component of each pixel in the display, consisting of a transparent electrode and a metal electrode, which controls the pixel state, such as brightness and color saturation, through charge changes) is grounded or biased. The drive pin 110 receives the drive voltage through the flexible circuit board (FPC), which is transmitted to the drive electrode 109 through the drive trace 111, and then to the upper electrode. Thus, a voltage difference is generated between the upper electrode and the lower electrode at both ends of the piezoelectric layer 104. Due to the inverse piezoelectric effect, the piezoelectric material vibrates mechanically and emits ultrasonic waves.

[0181] Propagation stage: The ultrasonic waves propagate layer by layer towards the finger. When they reach the finger surface, the ridges and valleys of the fingerprint 118 will produce different reflections of the ultrasonic waves. The valleys will produce stronger ultrasonic wave reflections due to the air gap between them and the screen 116 (screen cover). The reflected waves return layer by layer along the original path and reach the piezoelectric material.

[0182] Receiving stage: Due to the positive piezoelectric effect, the ultrasound causes the piezoelectric layer 104 to vibrate mechanically, generating charges, which are collected by each pixel electrode; the pixel electrodes at the locations of the ridges and valleys of the fingerprint 118 will collect different amounts of charge; after a series of processing circuits, the analog signal can be converted into a digital signal, and the fingerprint image can be reconstructed, thus completing the measurement of the finger fingerprint.

[0183] As described above, the ultrasonic fingerprint sensor, ultrasonic fingerprint sensor module, and electronic device of the present invention have the following beneficial effects:

[0184] In this invention, the driving signals transmitted by the driving traces may have electrical characteristics such as high voltage and high frequency. The driving traces are located above the passivation layer and are far away from the chip circuit. They are less likely to cause electromagnetic interference to other signal traces on the top metal interconnect layer of the CMOS chip, the inner metal traces of the CMOS chip, CMOS devices, etc., thus avoiding affecting the operation of the sensor.

[0185] The drive signals transmitted by the drive traces have high requirements for transmission quality. Using redistribution layer technology to fabricate drive traces allows the use of metals with good electrical properties, reducing electrical losses; and the trace thickness can be adjusted to be thicker, which is beneficial for further optimization of electrical performance.

[0186] Rerouting layer technology is a mature technology with simple processes and low costs.

[0187] The above description is merely an illustrative embodiment of the present invention and is not intended to limit the scope of the invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention should fall within the scope of protection of the present invention.

Claims

1. An ultrasonic fingerprint sensor, characterized in that, The system comprises a chip layer, a piezoelectric layer, a conductive layer, and an insulating layer. The chip layer includes a substrate layer, a circuit layer, a metal interconnect layer, and a passivation layer. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer. Chip pins are disposed around the periphery of the chip layer, including drive pins for driving electrical signals. A redistribution layer is disposed above the passivation layer. The passivation layer has a first window area exposing the metal of the top metal interconnect layer to form a drive electrode. Drive traces capable of electrically connecting the drive pins and the drive electrodes are disposed within the redistribution layer. The thickness of the drive traces is configurable. The material of the drive traces is different from the material of the top metal interconnect layer.

2. The ultrasonic fingerprint sensor as described in claim 1, characterized in that, The drive traces are made of copper, silver, gold, titanium, nickel, tungsten, or titanium-tungsten alloy.

3. The ultrasonic fingerprint sensor as described in claim 1, characterized in that, The passivation layer has a second window area to expose the metal of the top metal interconnect layer to form the lower electrode, and the passivation layer has a third window area to expose the metal of the top metal interconnect layer to form the chip pin.

4. The ultrasonic fingerprint sensor as described in claim 3, characterized in that, The metal of the top metal interconnect layer exposed in the first window area of ​​the passivation layer is isolated from the metal of the top metal interconnect layer exposed in the second window area of ​​the passivation layer.

5. The ultrasonic fingerprint sensor as described in claim 3, characterized in that, The chip pins also include external chip connection pins, and the length of at least one side of the window at the driving pin is greater than or equal to the length of the corresponding side of the window at the external chip connection pin.

6. The ultrasonic fingerprint sensor as described in claim 1, characterized in that, The driving electrode and the conductive layer are disposed in at least partial overlap, and at the overlap location, the conductive layer covers the driving electrode.

7. The ultrasonic fingerprint sensor as described in claim 6, characterized in that, The driving electrode and the piezoelectric layer are partially overlapped, and at the overlap position, the piezoelectric layer covers the driving electrode.

8. The ultrasonic fingerprint sensor as described in claim 1, characterized in that, The drive trace and the drive electrode are at least partially overlapped, and at the overlap location, the drive trace covers the drive electrode.

9. The ultrasonic fingerprint sensor as described in claim 8, characterized in that, The drive trace and the conductive layer are partially overlapped, and at the overlap location, the conductive layer covers the drive trace.

10. The ultrasonic fingerprint sensor as described in claim 8, characterized in that, The drive trace and the piezoelectric layer are partially overlapped, and at the overlap position, the piezoelectric layer covers the drive trace.

11. The ultrasonic fingerprint sensor as described in claim 1, characterized in that, Each of the chip pins is provided with a conductive bump, the top of which is higher than the top of the passivation layer and located within the redistribution layer; the cross-section of the conductive bump is smaller than the cross-section of the corresponding chip pin.

12. An ultrasonic fingerprint sensor, characterized in that, The system includes a chip layer, a piezoelectric layer, a conductive layer, and an insulating layer. The chip layer includes a substrate layer, a circuit layer, a metal interconnect layer, and a passivation layer. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer. A redistribution layer is disposed above the passivation layer. The redistribution layer is provided with driving electrodes, driving traces, and driving pins. The driving traces are electrically connected to the driving pins and the driving electrodes. The thickness of the driving traces is configurable. The material of the driving traces is different from the material of the top metal interconnect layer.

13. The ultrasonic fingerprint sensor as described in claim 12, characterized in that, The redistribution layer is provided with at least one driving module. Each driving module includes a driving electrode, a driving trace, and a driving pin. The metal in the area of ​​each driving module used to bond with the circuit board pin constitutes the driving pin. The metal in the area of ​​each driving module in contact with the conductive layer or the piezoelectric layer constitutes the driving electrode. The metal in the area of ​​each driving module that is electrically connected to the driving electrode and the driving pin constitutes the driving trace.

14. An ultrasonic fingerprint sensor, characterized in that, The system comprises a chip layer, a piezoelectric layer, a conductive layer, and an insulating layer. The chip layer includes a substrate layer, a circuit layer, a metal interconnect layer, and a passivation layer. The metal interconnect layer includes an inner metal interconnect layer and a top metal interconnect layer. Chip pins are disposed around the periphery of the chip layer, including drive pins for driving electrical signals. A redistribution layer is disposed above the passivation layer. A drive electrode is disposed on the redistribution layer. Drive traces capable of electrically connecting the drive pins and the drive electrode are disposed within the redistribution layer. The thickness of the drive traces is configurable. The material of the drive traces is different from the material of the top metal interconnect layer.

15. An ultrasonic fingerprint sensor module, characterized in that, Includes an ultrasonic fingerprint sensor as described in any one of claims 1 to 14, wherein the ultrasonic fingerprint sensor is electrically connected to a circuit board.

16. The ultrasonic fingerprint sensor module as described in claim 15, characterized in that, The circuit board is provided with circuit board pins; the ultrasonic fingerprint sensor and the circuit board pins are bonded together by anisotropic conductive adhesive.

17. An electronic device, comprising a screen, characterized in that, Includes the ultrasonic fingerprint sensor module as described in claim 15, wherein the ultrasonic fingerprint sensor module is fixedly connected to the screen.

18. The electronic device as claimed in claim 17, characterized in that, An adhesive layer is disposed on the side of the substrate layer away from the piezoelectric layer, and the chip layer is fixedly connected to the screen through the adhesive layer.

Images