A high-speed, low-power successive approximation analog-to-digital converter, system, and method

Abstract

This application discloses a high-speed, low-power successive approximation analog-to-digital converter (ADC), system, and method, relating to the field of analog integrated circuit design technology. The ADC includes an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit. The auxiliary ADC includes a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module. The main ADC includes a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module. An M-bit non-binary digital code is obtained through quantization by the auxiliary ADC, and an N-M-bit non-binary digital code is obtained through quantization by the main ADC. The digital error correction circuit then converts the M-bit and N-M-bit non-binary digital codes into binary digital codes and outputs them. This application can improve conversion speed and accuracy while maintaining low power consumption.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design technology, and in particular to a high-speed, low-power successive approximation analog-to-digital converter, system, and method. Background Technology

[0002] Successive approximation analog-to-digital converters (SARADCs), as an analog-to-digital conversion solution that combines moderate accuracy, speed, and low power consumption, have been widely used in many fields due to their advantages such as simple structure and low power consumption. With the continuous innovation of information processing technology, the requirements of systems for data processing speed, accuracy, and energy efficiency are constantly increasing, making the development of high-speed, low-power analog-to-digital converters a current research hotspot.

[0003] Traditional SARADC architectures based on binary capacitor arrays suffer from significant drawbacks: the maximum capacitance of its capacitor-to-analog converter (CDAC) array increases exponentially with conversion accuracy N, posing a fundamental challenge to achieving high-speed, low-power designs in high-precision scenarios. Specifically, the high-precision requirements lead to a dramatic increase in capacitance, causing severe capacitor mismatch issues, while also prolonging the settling time of the capacitor array, ultimately resulting in increased system power consumption, larger area, limited effective bits, and reduced conversion rate. For high-speed, high-precision SARADCs, the massive unit capacitor array not only causes a surge in charging and discharging current and increased switching power consumption but also significantly increases chip area and manufacturing costs. Therefore, optimizing the DAC capacitor array to reduce quantization time is crucial to overcoming performance bottlenecks.

[0004] Traditional binary segmented DACs reduce the total number of capacitors to some extent by introducing bridging capacitors. However, this structure has inherent drawbacks: the fractional ratio between the bridging capacitor and the unit capacitor makes layout implementation difficult and it is extremely sensitive to parasitic capacitance. In practical designs, the unit capacitor is often used instead of the bridging capacitor. While this improves matching, it alters the binary characteristics of the capacitor weights (denominator reduced by 1), thus introducing a fixed gain error. Furthermore, the reduction in the size of the unit capacitor exacerbates the impact of parasitic capacitance, further limiting ADC performance. To ensure accuracy, segmented structures often require increasing the value of the unit capacitor, which contradicts the design goals of low power consumption and small area.

[0005] Besides capacitor matching and parasitic effects, the highest-order capacitance in traditional architectures is extremely large, and its settling time directly determines the overall speed of the analog-to-digital converter (ADC). There is an inherent trade-off between accuracy and speed in SAR ADCs, resulting in high-precision designs often being accompanied by low-speed characteristics. While non-binary DACs can reduce settling time through redundancy, the highest-order capacitances remain large. Accurate settling requires very large switching circuits, and the high-speed quantization process also introduces non-ideal factors such as charge injection and clock feedthrough.

[0006] In summary, how to provide a high-speed, low-power successive approximation analog-to-digital converter that can effectively improve its conversion speed and accuracy while maintaining the low-power characteristics of the converter, thereby achieving the dual goals of chip area reduction and economic benefits, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this application is to provide a high-speed, low-power successive approximation analog-to-digital converter, system, and method, which features low power consumption, high conversion speed, and high accuracy, and can improve conversion speed and accuracy while maintaining low power consumption characteristics.

[0008] To achieve the above objectives, this application provides the following solution.

[0009] In a first aspect, this application provides a high-speed, low-power successive approximation analog-to-digital converter, which includes: an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit, where M and N are positive integers, and M < N.

[0010] The auxiliary ADC includes: a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module.

[0011] The main ADC includes: a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module.

[0012] The input terminal of the first non-binary DAC capacitor array is connected to the first gate voltage bootstrap circuit, the output terminal of the first non-binary DAC capacitor array is connected to the input terminal of the first comparator, the output terminal of the first comparator is connected to the input terminal of the first successive approximation logic module, and the output terminal of the first successive approximation logic module is connected to the digital error correction circuit.

[0013] The input terminal of the second non-binary DAC capacitor array is connected to the second gate voltage bootstrap circuit, the output terminal of the second non-binary DAC capacitor array is connected to the input terminal of the second comparator, the output terminal of the second comparator is connected to the input terminal of the second successive approximation logic module, and the output terminal of the second successive approximation logic module is connected to the digital error correction circuit; the first successive approximation logic module and the second successive approximation logic module are communicatively connected.

[0014] The first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are used to simultaneously receive externally input analog signals and simultaneously transmit the analog signals to their respective first non-binary DAC capacitor array and second non-binary DAC capacitor array.

[0015] The first non-binary DAC capacitor array is used to sample the analog signal, determine the first upper plate voltage pair, and send it to the first comparator; the second non-binary DAC capacitor array is used to sample the analog signal, determine the second upper plate voltage pair, and send it to the second comparator.

[0016] The first comparator is used to compare the first upper plate voltage pair, obtain a first comparison result, and send it to the first successive approximation logic module; the second comparator is used to compare the second upper plate voltage pair, obtain a second comparison result, and send it to the second successive approximation logic module.

[0017] The first successive approximation logic module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code, and send the M-bit non-binary digital code to the second successive approximation logic module and the digital error correction circuit respectively.

[0018] The second successive approximation logic module is used to perform successive approximation quantization based on the M-bit non-binary digital code and the second comparison result to obtain an NM-bit non-binary digital code, and send the NM-bit non-binary digital code to the digital error correction circuit.

[0019] The digital error correction circuit is used to convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital code and output them.

[0020] Optionally, both the first non-binary DAC capacitor array and the second non-binary DAC capacitor array adopt a non-binary capacitor arrangement structure.

[0021] Optionally, the capacitor weighting ratio of the first non-binary DAC capacitor array is 9:7:6:10.

[0022] Optionally, the capacitor weight ratio of the second non-binary DAC capacitor array is 72:56:48:24:20:16:8:5:3:2:1:4:2:1.

[0023] Optionally, the second non-binary DAC capacitor array uses a two-level reference level.

[0024] Optionally, both the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit adopt a differential structure. The input terminals of the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are respectively connected to differential analog signals Vin and Vip, and their switching states are controlled by the clock signal Clks.

[0025] Optionally, the high-speed, low-power successive approximation analog-to-digital converter further includes a timing generator and a frequency divider.

[0026] The output of the timing generator is connected to the first comparator, the first successive approximation logic module and the frequency divider, respectively. The timing generator is used to provide a driving clock signal.

[0027] The input of the frequency divider is connected to the timing generator and the first successive approximation logic module, and the output of the frequency divider is connected to the second comparator and the second successive approximation logic module. The frequency divider is used to allocate twice the quantization time of the auxiliary ADC to the main ADC.

[0028] Secondly, this application provides a method for operating a high-speed, low-power successive approximation analog-to-digital converter as described in the first aspect, the method comprising the following steps.

[0029] A1: Sampling phase.

[0030] Based on the auxiliary ADC and the main ADC, the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit simultaneously receive the same external input analog signal, and the first non-binary DAC capacitor array and the second non-binary DAC capacitor array respectively sample the analog signal and store the sampled charge to obtain the first upper plate voltage pair and the second upper plate voltage pair respectively.

[0031] A2: Quantification stage.

[0032] The first M-bit capacitors of the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are sequentially quantized. After each quantization, the voltage of the first upper plate is compared with the voltage of the first plate using the first comparator to obtain the first comparison result. Then, the first successive approximation logic module performs successive approximation quantization based on the first comparison result to obtain the M-bit non-binary digital code.

[0033] Based on the first M bits of code value, the remaining NM bits of the capacitors in the second non-binary DAC capacitor array are sequentially quantized. After each quantization, the voltage of the second upper plate is compared with the second comparator to obtain a second comparison result. Then, the second successive approximation logic module performs successive approximation quantization based on the M bits of non-binary digital code and the second comparison result to obtain the NM bits of non-binary digital code.

[0034] A3: Digital error correction stage.

[0035] Using a digital error correction circuit, the M-bit non-binary digital code and the NM-bit non-binary digital code are converted into binary digital codes, and the binary digital codes are output.

[0036] Thirdly, this application provides a high-speed, low-power successive approximation analog-to-digital converter method based on the high-speed, low-power successive approximation analog-to-digital converter described in the first aspect, the high-speed, low-power successive approximation analog-to-digital converter method comprising the following steps.

[0037] Acquire analog signals from external input.

[0038] The analog signals are sampled separately to determine the first upper plate voltage pair and the second upper plate voltage pair.

[0039] The voltage pairs of the first upper plate are compared to obtain a first comparison result; at the same time, the voltage pairs of the second upper plate are compared to obtain a second comparison result.

[0040] Based on the first comparison result, successive approximation quantization is performed to obtain an M-bit non-binary digital code.

[0041] Based on the M-bit non-binary digital code, successive approximation quantization is performed according to the second comparison result to obtain an NM-bit non-binary digital code.

[0042] Convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital codes.

[0043] Fourthly, this application provides a high-speed, low-power successive approximation analog-to-digital conversion system, wherein the high-speed, low-power successive approximation analog-to-digital conversion system applies the high-speed, low-power successive approximation analog-to-digital conversion method as described in the first aspect, and the high-speed, low-power successive approximation analog-to-digital conversion system includes the following functional modules.

[0044] The analog signal acquisition module is used to acquire externally input analog signals.

[0045] The sampling module is used to sample the analog signals respectively to determine the first upper plate voltage pair and the second upper plate voltage pair.

[0046] The comparison module is used to compare the voltage pairs of the first upper plate to obtain a first comparison result; and at the same time, to compare the voltage pairs of the second upper plate to obtain a second comparison result.

[0047] The first quantization module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code.

[0048] The second quantization module is used to perform successive approximation quantization based on the M-bit non-binary digital code and according to the second comparison result to obtain an NM-bit non-binary digital code.

[0049] A conversion module is used to convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital code.

[0050] According to the specific embodiments provided in this application, this application has the following technical effects.

[0051] This application provides a high-speed, low-power successive approximation analog-to-digital converter (ADC), system, and method. The ADC includes an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit. The auxiliary ADC includes a first gate-voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module. The main ADC includes a second gate-voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module. The auxiliary ADC is primarily used for quantizing and outputting an M-bit non-binary digital code; while the main ADC is primarily used for quantizing and outputting an NM-bit non-binary digital code. Through the coordinated operation of the auxiliary ADC (first gate-voltage bootstrap circuit, first non-binary DAC capacitor array, first comparator, and first successive approximation logic module), the main ADC (second gate-voltage bootstrap circuit, second non-binary DAC capacitor array, second comparator, and second successive approximation logic module), and the digital error correction circuit, analog signal sampling, successive approximation quantization, and digital error correction can be achieved, ultimately outputting a total of N bits of binary digital code. Because this analog-to-digital converter uses a main ADC and an auxiliary ADC, and both the main ADC and the auxiliary ADC use non-binary DAC capacitor arrays, this non-binary DAC capacitor array does not require a large number of capacitors, thereby reducing power consumption. Combined with the successive approximation quantization function of the first successive approximation logic module and the second successive approximation logic module, as well as the digital error correction function of the digital error correction circuit, it can improve conversion speed and accuracy while maintaining low power consumption characteristics. This is conducive to achieving the dual goals of chip area reduction and economic efficiency improvement, and solves the problem that traditional SAR ADCs cannot achieve both high accuracy and reduce the number of DAC capacitors and power consumption. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the circuit structure of a high-speed, low-power successive approximation analog-to-digital converter provided in an embodiment of this application.

[0054] Figure 2This is a timing diagram of a high-speed, low-power successive approximation analog-to-digital converter provided in an embodiment of this application.

[0055] Figure 3 This is a flowchart illustrating the operation of a high-speed, low-power successive approximation analog-to-digital converter provided in an embodiment of this application.

[0056] Figure 4 This is a flowchart illustrating a high-speed, low-power successive approximation analog-to-digital conversion method provided in an embodiment of this application.

[0057] Figure 5 This is a schematic diagram of the structure of a high-speed, low-power successive approximation analog-to-digital converter system provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0059] This application aims to provide a high-speed, low-power successive approximation analog-to-digital converter (ADC). It employs a high-precision, low-power ADC architecture to address the problem that traditional SARADCs cannot simultaneously achieve high precision while reducing the number of capacitors and power consumption in the DAC. On one hand, in this architecture, the main ADC has high precision but a large high-order capacitor, resulting in a long setup time during high-order switching. Direct quantization of the high M bits by the auxiliary ADC eliminates the need for switching and quantization of the high-order capacitors in the main DAC, directly assigning the code value from the auxiliary ADC to the corresponding weighted bits of the main ADC. On the other hand, the low-precision coarse SARADC requires a smaller capacitor area and a shorter setup time. Allocating a shorter quantization cycle to this ADC allows for faster conversion speeds, effectively improving the overall operating speed and thus increasing the sampling rate. Furthermore, the second non-binary DAC capacitor array utilizes a two-level reference level structure, enabling the use of a two-level reference level instead of a two-level reference level. N The unit capacitance is reduced to 2. N-2 The number of capacitors used is on the order of +6 units, which significantly reduces the number of capacitors used and thus significantly reduces power consumption.

[0060] In summary, this application achieves high-precision N-bit quantization while improving sampling speed and significantly reducing power consumption through synchronous quantization of the auxiliary ADC and the main ADC. In terms of speed, the low-precision coarse SAR ADC requires less capacitance and shorter setup time, resulting in faster conversion speeds. Furthermore, the high-order bits of the main ADC do not require setup; the code value from the auxiliary ADC is directly loaded, effectively improving the overall ADC operating speed and thus increasing the sampling rate. Regarding power consumption, since the auxiliary ADC quantizes before the main ADC, it not only reduces the number of comparisons in the main ADC but also reduces the power waste of the high-precision comparator in the main ADC. In addition, the non-binary DAC array further reduces setup time and improves quantization speed through redundancy. These advantages not only improve ADC speed but also reduce overall power consumption, making the ADC architecture perform better than other SAR ADCs.

[0061] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] like Figure 1 As shown, this embodiment proposes a high-speed, low-power successive approximation analog-to-digital converter, which includes: an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit (DEC), where M and N are positive integers, and M < N.

[0063] The auxiliary ADC includes: a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic (SAR Logic) module.

[0064] The main ADC includes: a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module.

[0065] The input terminal of the first non-binary DAC capacitor array is connected to the first gate voltage bootstrap circuit, the output terminal of the first non-binary DAC capacitor array is connected to the input terminal of the first comparator, the output terminal of the first comparator is connected to the input terminal of the first successive approximation logic module, and the output terminal of the first successive approximation logic module is connected to the digital error correction circuit.

[0066] The input terminal of the second non-binary DAC capacitor array is connected to the second gate voltage bootstrap circuit, the output terminal of the second non-binary DAC capacitor array is connected to the input terminal of the second comparator, the output terminal of the second comparator is connected to the input terminal of the second successive approximation logic module, and the output terminal of the second successive approximation logic module is connected to the digital error correction circuit; the first successive approximation logic module and the second successive approximation logic module are communicatively connected.

[0067] The first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are used to simultaneously receive externally input analog signals and simultaneously transmit the analog signals to their respective first non-binary DAC capacitor array and second non-binary DAC capacitor array.

[0068] The first non-binary DAC capacitor array is used to sample the analog signal, determine the first upper plate voltage pair, and send it to the first comparator; the second non-binary DAC capacitor array is used to sample the analog signal, determine the second upper plate voltage pair, and send it to the second comparator.

[0069] The first comparator is used to compare the first upper plate voltage pair, obtain a first comparison result, and send it to the first successive approximation logic module; the second comparator is used to compare the second upper plate voltage pair, obtain a second comparison result, and send it to the second successive approximation logic module.

[0070] The first successive approximation logic module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code, and send the M-bit non-binary digital code to the second successive approximation logic module and the digital error correction circuit respectively.

[0071] The second successive approximation logic module is used to perform successive approximation quantization based on the M-bit non-binary digital code and the second comparison result to obtain an NM-bit non-binary digital code, and send the NM-bit non-binary digital code to the digital error correction circuit.

[0072] The digital error correction circuit is used to convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital code and output them.

[0073] In this embodiment, both the first non-binary DAC capacitor array and the second non-binary DAC capacitor array adopt a non-binary capacitor arrangement structure.

[0074] In this embodiment, the capacitor weight ratio of the first non-binary DAC capacitor array is 9:7:6:10.

[0075] In this embodiment, the capacitor weight ratio of the second non-binary DAC capacitor array is 72:56:48:24:20:16:8:5:3:2:1:4:2:1.

[0076] In this embodiment, the second non-binary DAC capacitor array adopts a two-level reference level, which includes Vref, Vref / 8 and Gnd, and can reduce the total number of capacitors in the second non-binary DAC capacitor array.

[0077] In this embodiment, both the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit adopt a differential structure. The input terminals of the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are respectively connected to differential analog signals Vin and Vip, and their switching states are controlled by the clock signal Clks.

[0078] In this embodiment, the high-speed, low-power successive approximation analog-to-digital converter further includes a timing generator and a frequency divider.

[0079] The output of the timing generator is connected to the first comparator, the first successive approximation logic module and the frequency divider, respectively. The timing generator is used to provide a driving clock signal.

[0080] The input of the frequency divider is connected to the timing generator and the first successive approximation logic module, and the output of the frequency divider is connected to the second comparator and the second successive approximation logic module. The frequency divider is used to allocate twice the quantization time of the main ADC to the auxiliary ADC to ensure that the voltage of the second non-binary DAC capacitor array is fully established.

[0081] In this embodiment, the M-bit auxiliary ADC and the N-bit main ADC are connected through their respective comparators (i.e., the first comparator and the second comparator) and successive approximation logic modules (i.e., the first successive approximation logic module and the second successive approximation logic module). The externally input analog signals Vin and Vip are simultaneously connected to the non-binary DAC capacitor arrays (i.e., the first non-binary DAC capacitor array and the second non-binary DAC capacitor array) of the main ADC and the auxiliary ADC through gate voltage bootstrap circuits (i.e., the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit). The N-bit non-binary digital code converted by the two successive approximation logic modules (i.e., the first successive approximation logic module and the second successive approximation logic module) is converted into binary digital code and output through a digital error correction circuit.

[0082] In this embodiment, the main ADC is a high-precision ADC, also known as a fine ADC, while the auxiliary ADC is a low-precision ADC, also known as a coarse ADC. Compared to the coarse ADC, the fine ADC allocates twice the quantization time through a frequency divider, allowing for more sufficient DAC quantization time and thus ensuring accurate ADC conversion. Therefore, the conversion accuracy of the fine ADC is slightly higher than that of the coarse ADC.

[0083] In this embodiment, the main ADC includes a set of gate voltage bootstrap circuits, a set of non-binary DAC capacitor arrays, a comparator, and a successive approximation logic module. The auxiliary ADC and the main ADC's non-binary DAC capacitor arrays sample the input analog signal through the gate voltage bootstrap circuits, and then input the voltages of the two upper plates of the non-binary DAC capacitor arrays to the comparator. The comparison result of the comparator yields a digital code value, which is output by the code value output module to the highest-order bit switches of the auxiliary ADC and the main ADC, respectively. The switch control module controls the switching of the lower plate switches of the two non-binary DAC capacitor arrays, and then establishes a new DAC upper plate voltage based on the charge redistribution principle. The non-binary DAC capacitor array is then fed into the comparator for the next comparison, thus realizing the successive approximation function of the SARADC. The M bits of the auxiliary ADC are loaded into the corresponding bits of the main ADC after each quantization.

[0084] In this embodiment, the main ADC consists of a non-binary DAC capacitor array, a comparator, and a successive approximation logic module. The DAC switching circuit of the main ADC controls the switching by receiving the M-bit code value quantized by the auxiliary ADC, thereby re-establishing the voltage on the upper plate of the non-binary DAC capacitor array. Finally, the remaining NM bits are quantized using the re-established voltage on the upper plate of the non-binary DAC capacitor array to obtain an N-bit non-binary output code value. This non-binary DAC capacitor array adopts a non-binary capacitor arrangement structure and can use a two-stage reference level to reduce the number of capacitors used in the main DAC.

[0085] The working method of the high-speed, low-power successive approximation analog-to-digital converter proposed in this embodiment is as follows.

[0086] (1) During the sampling phase, the auxiliary ADC and the main ADC sample the same input signal through their respective gate voltage bootstrap circuits.

[0087] (2) After sampling, the quantization stage begins. First, the most significant bit of the capacitors in the first and second non-binary DAC capacitor arrays is quantized. After quantization, the first comparator of the auxiliary ADC begins comparing the input voltage and outputs the first digital code value after comparison.

[0088] Based on the result of the first comparison and the drive signal from the timing generator, the second-highest bit capacitors of the first and second non-binary DAC capacitor arrays are quantized. After quantization, the first comparator of the auxiliary ADC begins comparing the magnitude of the input voltage and outputs the second bit of the digital code value after the comparison.

[0089] Based on the result of the second comparison and the drive signal from the timing generator, the third capacitor of the first and second non-binary DAC capacitor arrays is quantized. After quantization, the first comparator of the auxiliary ADC begins comparing the magnitude of the input voltage and outputs the third digital code value after the comparison.

[0090] Based on the result of the third comparison and the drive signal from the timing generator, the fourth capacitor of the first and second non-binary DAC capacitor arrays is quantized. After quantization, the first comparator of the auxiliary ADC begins comparing the magnitude of the input voltage and outputs the fourth digital code value after the comparison.

[0091] Based on the result of the fourth comparison and the drive signal from the timing generator, the fifth capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the fifth digital code value after the comparison.

[0092] Based on the result of the 5th comparison and the drive signal from the timing generator, the 6th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 6th digital code value after the comparison.

[0093] Based on the result of the 6th comparison and the drive signal from the timing generator, the 7th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 7th digital code value after the comparison.

[0094] Based on the result of the 7th comparison and the drive signal from the timing generator, the 8th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 8th digital code value after the comparison.

[0095] Based on the result of the 8th comparison and the drive signal from the timing generator, the 9th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 9th digital code value after the comparison.

[0096] Based on the result of the 9th comparison and the drive signal from the timing generator, the 10th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 10th digital code value after the comparison.

[0097] Based on the result of the 10th comparison and the drive signal from the timing generator, the 11th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 11th digital code value after the comparison.

[0098] Based on the result of the 11th comparison and the drive signal from the timing generator, the 12th bit of the capacitor in the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 12th bit digital code value after the comparison.

[0099] Based on the result of the 12th comparison and the drive signal from the timing generator, the 13th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 13th digital code value after the comparison.

[0100] Based on the result of the 13th comparison and the drive signal from the timing generator, the 14th capacitor of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the magnitude of the input voltage and outputs the 14th bit digital code value after the comparison.

[0101] (3) After quantization, the digital error correction circuit performs binary encoding on the N-bit non-binary digital output code and finally outputs the binary code value.

[0102] To make the technical solution of this application clearer, the following examples will be used to illustrate in detail the specific structure and working method of the high-speed, low-power successive approximation analog-to-digital converter in this application.

[0103] like Figure 1 As shown, the high-speed, low-power successive approximation analog-to-digital converter proposed in this application mainly includes a main ADC and an auxiliary ADC, specifically including a first gate voltage bootstrap circuit, a second gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a second non-binary DAC capacitor array, a first comparator, a second comparator, a first successive approximation register (i.e., the first successive approximation logic module) and a second successive approximation register (i.e., the second successive approximation logic module), a timing generator, a frequency divider, and a digital error correction circuit.

[0104] The auxiliary ADC contains two differential first gate voltage bootstrap circuits. The first gate voltage bootstrap circuit and the common-mode voltage Vcm switch are controlled by a clock cycle Clks. The inputs of the first gate voltage bootstrap circuits are connected to the differential input signals Vin and Vip, respectively. The outputs of the first gate voltage bootstrap circuits are connected to four sampling switches of the first non-binary DAC capacitor array. The four differential sampling switches are connected to the lower plates of four differential capacitors with a weighting ratio of 9:7:6:10. The upper plates of the four differential capacitors are connected to the differential input + / - ports of the first comparator and the output of the common-mode voltage Vcm switch. The differential output of the first comparator is connected to the circuit of the corresponding first successive approximation logic module. Based on the first comparison result of the first comparator in the auxiliary ADC, the output of the first successive approximation logic module is adjusted. Finally, the high 4 bits of the differential control switches of the first and second non-binary DAC capacitor arrays are controlled to perform the charging and discharging operation of the DAC capacitors.

[0105] The main ADC contains two sets of differential second gate voltage bootstrap circuits. The second gate voltage bootstrap circuits and the common-mode voltage Vcm switch are controlled by the clock Clks. The inputs of the second gate voltage bootstrap circuits are connected to the differential input signals Vin and Vip, respectively. The outputs of the second gate voltage bootstrap circuits are connected to the 14 sampling switches of the second non-binary DAC capacitor array. These 14 differential sampling switches are connected to the lower plates of 14 differential capacitors with a weighting ratio of 72:56:48:24:20:16:8:5:3:2:1:4:2:1. The upper plates of these 14 differential capacitors are connected to the differential input + / - ports of the second comparator and the output of the common-mode voltage Vcm switch. The differential output of the second comparator is connected to the circuit of the corresponding second successive approximation logic module. Based on the second comparison result of the second comparator in the main ADC, the output of the second successive approximation logic module is adjusted, ultimately controlling the differential control switches of the second non-binary DAC capacitor array (excluding the high 4 bits) to perform the charging and discharging operations of the DAC capacitors.

[0106] The input terminals of the timing generator are as follows: Figure 2 The control signal Clks with a duty cycle of 20% is shown. The output of the timing generator is connected to the first comparator, the first successive approximation logic module of the auxiliary ADC, and the frequency divider.

[0107] The input of the frequency divider is connected to the first successive approximation logic module of the auxiliary ADC and the output signal Clkc of the timing generator, and the output is connected to the fine comparator and successive approximation logic of the main ADC.

[0108] The input terminals of the digital error correction circuit are connected to the first successive approximation logic module of the auxiliary ADC and the second successive approximation logic module of the main ADC, respectively.

[0109] Figure 2 This is the timing diagram for a high-speed, low-power successive approximation analog-to-digital converter (ADC). The timing includes the main operating clock Clks, and the control clocks Clkcr, Clkc, Clkfr, and Clkf for the successive approximation logic and comparators of the auxiliary ADC and main ADC. Clkfr and Clkf clocks are obtained by frequency division of Clkc. Each quantization cycle of the main ADC is divided to obtain twice the quantization time of the auxiliary ADC, thus achieving high quantization accuracy for the main ADC. The operation of this ADC is divided into... Figure 2 The Clks timing sequence is shown to have two stages: sampling and quantization.

[0110] During the sampling phase, Figure 2 When Clks is high, the switches connecting the common-mode voltage Vcm to the auxiliary ADC and the main ADC, along with the sampling switches composed of their respective gate voltage bootstrap circuits, close under the high-level drive of the main clock Clks. The lower plates of the first and second non-binary DAC capacitor arrays begin sampling. At this time, the upper plates are first connected to the common-mode voltage Vcm. The lower plates of the two sets of non-binary DAC capacitor arrays in the differential circuit are connected to the input signals Vin and Vip, respectively. During the reset phase, the switches for the common-mode voltage Vcm and the sampling switches open sequentially under the low-level drive of the main clock Clks, completing the sampling of the input signal.

[0111] After sampling, the quantization phase begins. First, the logic circuit, driven by the first pulse of the timing generator's drive signal Clkcr, starts quantizing the highest-order capacitors 9C and 72C of the first and second non-binary DAC capacitor arrays. After quantization, the first comparator of the auxiliary ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. And then, within Clkcr... C The first bit code value B is output after the first comparison cycle in the timing sequence. <13> .

[0112] Based on the result of the first comparison and driven by the second pulse of the timing generator drive signal Clkcr, quantization is performed on the second-highest capacitors 7C and 56C of the first and second non-binary DAC capacitor arrays. After quantization, the first comparator of the auxiliary ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The second bit of the digital code value B is output after the second comparison cycle on the Clkc timing sequence. <12> .

[0113] Based on the result of the second comparison and driven by the third pulse of the timing generator drive signal Clkcr, quantization is performed on the third-bit capacitors 6C and 48C of the first and second non-binary DAC capacitor arrays. After quantization, the first comparator of the auxiliary ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The third digital code value B is output after the third comparison cycle on the Clkc timing sequence. <11> .

[0114] Based on the result of the third comparison and driven by the fourth pulse of the timing generator drive signal Clkcr, quantization is performed on the fourth-bit capacitors 10C and 24C of the first and second non-binary DAC capacitor arrays. After quantization, the first comparator of the auxiliary ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The fourth digital code value B is output after the fourth comparison cycle on the Clkc timing sequence. <10> .

[0115] Based on the result of the fourth comparison and driven by the fifth pulse of the timing generator drive signal Clkfr, the fifth capacitor 20C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The fifth digital code value B is output after the fifth comparison cycle on the Clkf timing sequence. <9> .

[0116] Based on the result of the 5th comparison and driven by the 6th pulse of the timing generator drive signal Clkfr, the 6th capacitor 16C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The 6th digital code value B is output after the 6th comparison cycle on the Clkf timing sequence. <8> .

[0117] Based on the result of the 6th comparison and driven by the 7th pulse of the timing generator drive signal Clkfr, the 7th capacitor 8C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The 7th digital code value B is output after the 7th comparison cycle on the Clkf timing sequence. <7> .

[0118] Based on the result of the 7th comparison and driven by the 8th pulse of the timing generator drive signal Clkfr, the 8th capacitor 5C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The 8th digital code value B is output after the 8th comparison cycle on the Clkf timing sequence. <6> .

[0119] Based on the result of the 8th comparison and driven by the 9th pulse of the timing generator drive signal Clkfr, the 9th capacitor 3C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The 9th digital code value B is output after the 9th comparison cycle on the Clkf timing sequence. <5> .

[0120] Based on the result of the 9th comparison and driven by the 10th pulse of the timing generator drive signal Clkfr, the 10th capacitor 2C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. It then outputs the 10th bit digital code value B after the 10th comparison cycle on the Clkf timing sequence. <4> .

[0121] Based on the result of the 10th comparison and driven by the 11th pulse of the timing generator drive signal Clkfr, the 11th-bit capacitor 1C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. It then outputs the 11th-bit digital code value B after the 11th comparison cycle on the Clkf timing sequence. <3> .

[0122] Based on the result of the 11th comparison and driven by the 12th pulse of the timing generator drive signal Clkfr, the 12th-bit capacitor 4C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. It then outputs the 12th-bit digital code value B after the 12th comparison cycle on the Clkf timing sequence. <2> .

[0123] Based on the result of the 12th comparison and driven by the 13th pulse of the timing generator drive signal Clkfr, the 13th capacitor 2C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. The 13th digital code value B is output after the 13th comparison cycle on the Clkf timing sequence. <1> .

[0124] Based on the result of the 13th comparison and driven by the 14th pulse of the timing generator drive signal Clkfr, the 14th-bit capacitor 1C of the second non-binary DAC capacitor array is quantized. After quantization, the second comparator of the main ADC begins comparing the voltages at the positive (+) and negative (-) input terminals. It then outputs the 14th-bit digital code value B after the 14th comparison cycle on the Clkf timing sequence. <0> .

[0125] The input terminals of the digital error correction circuit are connected to the first successive approximation logic module of the auxiliary ADC and the second successive approximation logic module of the main ADC, respectively, to convert the 4-bit digital output code B<13:10> of the auxiliary ADC and the 10-bit digital output code B<9:0> of the main ADC into 12-bit binary output codes.

[0126] In this embodiment, both the first and second non-binary DAC capacitor arrays employ a binary redundant recombination structure. This introduces redundancy during quantization, reducing overall quantization time and increasing quantization speed. The binary redundant recombination structure can also improve quantization accuracy by calibrating errors during quantization through redundancy. The low-precision auxiliary ADC requires a smaller capacitor area and shorter setup time, achieving faster conversion speeds. Furthermore, the high 4 bits of the main ADC do not require rapid setup; the code value from the auxiliary ADC is directly loaded, effectively improving the overall ADC operating speed and thus increasing the sampling rate. The high-precision main ADC determines the final overall ADC accuracy and requires a longer setup time. Compared to the auxiliary ADC, the main ADC allocates twice the quantization time through a frequency divider, allowing for more sufficient DAC quantization time and ensuring accurate ADC conversion. Regarding linearity, the introduction of a second-level reference level in the lowest 3 bits of the main ADC allows for a significant reduction in the total capacitor count while increasing the unit capacitor size, thus mitigating nonlinearity issues caused by capacitor mismatch. By employing binary redundant recombination, two ADCs (main ADC and auxiliary ADC), and a non-binary DAC capacitor array with two levels of reference levels, the conversion rate and accuracy of the analog-to-digital converter can be significantly improved, while reducing circuit power consumption and area.

[0127] In one exemplary embodiment, such as Figure 3 As shown, a method for operating the high-speed, low-power successive approximation analog-to-digital converter is provided, which includes the following steps.

[0128] A1: Sampling Stage. Based on the auxiliary ADC and the main ADC, the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit simultaneously receive the same external input analog signal, and the first non-binary DAC capacitor array and the second non-binary DAC capacitor array respectively sample the analog signal and store the sampled charge to obtain the first upper plate voltage pair and the second upper plate voltage pair respectively.

[0129] A2: Quantization Stage. The first M bits of the capacitors in the first and second non-binary DAC capacitor arrays are sequentially quantized. After each quantization, a first comparator is used to compare the voltage pairs of the first upper plate to obtain a first comparison result. A first successive approximation logic module then performs successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code. Based on the first M-bit code value, the remaining NM bits of the capacitors in the second non-binary DAC capacitor array are sequentially quantized. After each quantization, a second comparator is used to compare the voltage pairs of the second upper plate to obtain a second comparison result. A second successive approximation logic module then performs successive approximation quantization based on the M-bit non-binary digital code and the second comparison result to obtain an NM-bit non-binary digital code.

[0130] A3: Digital Error Correction Stage. Using a digital error correction circuit, the M-bit non-binary digital code and the NM-bit non-binary digital code are converted into binary digital code, and the binary digital code is output.

[0131] In one exemplary embodiment, such as Figure 4 As shown, a high-speed, low-power successive approximation analog-to-digital converter (ADC) method based on the aforementioned high-speed, low-power successive approximation ADC is provided. The high-speed, low-power successive approximation ADC method includes the following steps.

[0132] B1: Acquire the analog signal input from the outside.

[0133] B2: Sample the analog signals respectively to determine the first upper plate voltage pair and the second upper plate voltage pair.

[0134] B3: Compare the voltage pairs of the first upper plate to obtain a first comparison result; at the same time, compare the voltage pairs of the second upper plate to obtain a second comparison result.

[0135] B4: Perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code.

[0136] B5: Based on the M-bit non-binary digital code, perform successive approximation quantization according to the second comparison result to obtain an NM-bit non-binary digital code.

[0137] B6: Convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital code.

[0138] In one exemplary embodiment, such as Figure 5As shown, a high-speed, low-power successive approximation analog-to-digital conversion system is provided. The high-speed, low-power successive approximation analog-to-digital conversion system applies the high-speed, low-power successive approximation analog-to-digital conversion method described above. The high-speed, low-power successive approximation analog-to-digital conversion system includes the following functional modules.

[0139] The analog signal acquisition module is used to acquire externally input analog signals.

[0140] The sampling module is used to sample the analog signals respectively to determine the first upper plate voltage pair and the second upper plate voltage pair.

[0141] The comparison module is used to compare the voltage pairs of the first upper plate to obtain a first comparison result; and at the same time, to compare the voltage pairs of the second upper plate to obtain a second comparison result.

[0142] The first quantization module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code.

[0143] The second quantization module is used to perform successive approximation quantization based on the M-bit non-binary digital code and according to the second comparison result to obtain an NM-bit non-binary digital code.

[0144] A conversion module is used to convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital code.

[0145] This application provides a high-speed, low-power successive approximation analog-to-digital converter (ADC), system, and method. The ADC includes an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit. The auxiliary ADC includes a first gate-voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module. The main ADC includes a second gate-voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module. The auxiliary ADC is primarily used for quantizing and outputting an M-bit non-binary digital code; while the main ADC is primarily used for quantizing and outputting an NM-bit non-binary digital code. Through the coordinated operation of the auxiliary ADC (first gate-voltage bootstrap circuit, first non-binary DAC capacitor array, first comparator, and first successive approximation logic module), the main ADC (second gate-voltage bootstrap circuit, second non-binary DAC capacitor array, second comparator, and second successive approximation logic module), and the digital error correction circuit, analog signal sampling, successive approximation quantization, and digital error correction can be achieved, ultimately outputting a total of N bits of binary digital code. Because this analog-to-digital converter uses a main ADC and an auxiliary ADC, and both the main ADC and the auxiliary ADC use non-binary DAC capacitor arrays, this non-binary DAC capacitor array does not require a large number of capacitors, thereby reducing power consumption. Combined with the successive approximation quantization function of the first successive approximation logic module and the second successive approximation logic module, as well as the digital error correction function of the digital error correction circuit, it can improve conversion speed and accuracy while maintaining low power consumption characteristics. This is conducive to achieving the dual goals of chip area reduction and economic efficiency improvement, and solves the problem that traditional SAR ADCs cannot achieve both high accuracy and reduce the number of DAC capacitors and power consumption.

[0146] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A high-speed, low-power successive approximation analog-to-digital converter, characterized in that, The high-speed, low-power successive approximation analog-to-digital converter includes: an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit, where M and N are positive integers, and M < N; The auxiliary ADC includes: a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module; the capacitor weight ratio of the first non-binary DAC capacitor array is 9:7:6:10; The main ADC includes: a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module; the capacitor weight ratio of the second non-binary DAC capacitor array is 72:56:48:24:20:16:8:5:3:2:1:4:2:1; the second non-binary DAC capacitor array adopts a two-level reference level. The input terminal of the first non-binary DAC capacitor array is connected to the first gate voltage bootstrap circuit, the output terminal of the first non-binary DAC capacitor array is connected to the input terminal of the first comparator, the output terminal of the first comparator is connected to the input terminal of the first successive approximation logic module, and the output terminal of the first successive approximation logic module is connected to the digital error correction circuit. The input terminal of the second non-binary DAC capacitor array is connected to the second gate voltage bootstrap circuit, the output terminal of the second non-binary DAC capacitor array is connected to the input terminal of the second comparator, the output terminal of the second comparator is connected to the input terminal of the second successive approximation logic module, and the output terminal of the second successive approximation logic module is connected to the digital error correction circuit; the first successive approximation logic module and the second successive approximation logic module are communicatively connected. Both the first gate-voltage bootstrap circuit and the second gate-voltage bootstrap circuit adopt a differential structure. The input terminals of the first gate-voltage bootstrap circuit and the second gate-voltage bootstrap circuit are respectively connected to differential analog signals Vin and Vip, and their switching states are controlled by clock signal Clks. The first gate-voltage bootstrap circuit and the second gate-voltage bootstrap circuit are used to simultaneously receive externally input analog signals and simultaneously transmit the analog signals to their respective first non-binary DAC capacitor array and second non-binary DAC capacitor array. The first non-binary DAC capacitor array is used to sample the analog signal, determine the first upper plate voltage pair, and send it to the first comparator; the second non-binary DAC capacitor array is used to sample the analog signal, determine the second upper plate voltage pair, and send it to the second comparator. The first comparator is used to compare the first upper plate voltage pairs, obtain a first comparison result, and send it to the first successive approximation logic module; the second comparator is used to compare the second upper plate voltage pairs, obtain a second comparison result, and send it to the second successive approximation logic module. The first successive approximation logic module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code, and send the M-bit non-binary digital code to the second successive approximation logic module and the digital error correction circuit respectively. The second successive approximation logic module is used to perform successive approximation quantization based on the M-bit non-binary digital code and the second comparison result to obtain an NM-bit non-binary digital code, and send the NM-bit non-binary digital code to the digital error correction circuit. The digital error correction circuit is used to convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital codes and output them. The high-speed, low-power successive approximation analog-to-digital converter also includes: a timing generator and a frequency divider; The output of the timing generator is connected to the first comparator, the first successive approximation logic module and the frequency divider, respectively. The timing generator is used to provide a driving clock signal. The input of the frequency divider is connected to the timing generator and the first successive approximation logic module, and the output of the frequency divider is connected to the second comparator and the second successive approximation logic module. The frequency divider is used to allocate twice the quantization time of the auxiliary ADC to the main ADC.

2. The high-speed, low-power successive approximation analog-to-digital converter according to claim 1, characterized in that, Both the first non-binary DAC capacitor array and the second non-binary DAC capacitor array adopt a non-binary capacitor arrangement structure.

3. A method for operating a high-speed, low-power successive approximation analog-to-digital converter as described in claim 1 or 2, characterized in that, The operating method of the high-speed, low-power successive approximation analog-to-digital converter includes: A1: Sampling Phase Based on the auxiliary ADC and the main ADC, the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit simultaneously receive the same external input analog signal, and the first non-binary DAC capacitor array and the second non-binary DAC capacitor array respectively sample the analog signal and store the sample charge to obtain the first upper plate voltage pair and the second upper plate voltage pair respectively. A2: Quantification Phase The first M-bit capacitors of the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are sequentially quantized. After each quantization, the voltage of the first upper plate is compared with the voltage of the first plate using the first comparator to obtain the first comparison result. The first successive approximation logic module is then used to perform successive approximation quantization based on the first comparison result to obtain the M-bit non-binary digital code. Based on the M-bit non-binary digital code, the remaining NM-bit capacitors of the second non-binary DAC capacitor array are sequentially quantized. After each quantization, the voltage of the second upper plate is compared using a second comparator to obtain a second comparison result. The second successive approximation logic module is then used to perform successive approximation quantization based on the M-bit non-binary digital code and the second comparison result to obtain the NM-bit non-binary digital code. A3: Digital Error Correction Stage: Using a digital error correction circuit, the M-bit non-binary digital code and the NM-bit non-binary digital code are converted into binary digital codes, and the binary digital codes are output.

4. A high-speed, low-power successive approximation analog-to-digital conversion method based on the high-speed, low-power successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that, The high-speed, low-power successive approximation analog-to-digital conversion method includes: Acquire externally input analog signals; The analog signals are sampled respectively to determine the first upper plate voltage pair and the second upper plate voltage pair; The voltage pairs of the first upper plate are compared to obtain a first comparison result; at the same time, the voltage pairs of the second upper plate are compared to obtain a second comparison result. Based on the first comparison result, successive approximation quantization is performed to obtain an M-bit non-binary digital code. Based on the M-bit non-binary digital code, successive approximation quantization is performed according to the second comparison result to obtain an NM-bit non-binary digital code. Convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital codes.

5. A high-speed, low-power successive approximation analog-to-digital converter system, characterized in that, The high-speed, low-power successive approximation analog-to-digital conversion system uses the high-speed, low-power successive approximation analog-to-digital conversion method as described in claim 4, and the high-speed, low-power successive approximation analog-to-digital conversion system includes: Analog signal acquisition module, used to acquire externally input analog signals; The sampling module is used to sample the analog signals respectively to determine the first upper plate voltage pair and the second upper plate voltage pair; The comparison module is used to compare the voltage pairs of the first upper plate to obtain a first comparison result; and simultaneously compare the voltage pairs of the second upper plate to obtain a second comparison result. The first quantization module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code. The second quantization module is used to perform successive approximation quantization based on the M-bit non-binary digital code and according to the second comparison result to obtain an NM-bit non-binary digital code. A conversion module is used to convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary digital code.

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