Ethernet data transmitting and receiving circuit, circuit board and data transmitting and receiving equipment

Abstract

The invention provides an Ethernet data receiving and transmitting circuit, a circuit board and data receiving and transmitting equipment, relates to the technical field of electronic circuits, and solves the problem that a data acquisition scheme provided by a related technology is difficult to meet a multi-protocol coexistence requirement in an industrial scene. According to the scheme, the data receiving and transmitting circuit can adapt to different Ethernet modes on the basis of switching of the transmission channels on the channel switching module, so that the zero-delay acquisition requirement of real-time Ethernet such as EtherCAT is met, and the full-duplex communication requirement of data acquisition in the gigabit Ethernet can be met; therefore, the Ethernet data receiving and transmitting circuit can provide a more reliable data acquisition scheme and meet the requirement of coexistence of multiple protocols.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to an Ethernet data transceiver circuit, circuit board and data transceiver device. Background Technology

[0002] With the development of industrial automation and intelligent manufacturing, industrial Ethernet occupies a core position in equipment communication and control. It needs to transmit control commands and status data in real time and accurately, and has strict requirements for the real-time performance and accuracy of data acquisition and analysis. At the same time, there is a need for multiple protocols (such as EtherCAT and Gigabit Ethernet) to coexist in industrial scenarios, and it is necessary to adapt to Ethernet data processing with different speeds and protocols.

[0003] In related technologies, traditional data acquisition solutions require data to be forwarded through PHY chips, FPGAs, or processor logic. The accumulated latency from analog-to-digital conversion and logic forwarding is significant. However, in timing-sensitive scenarios such as EtherCAT, this latency can lead to data timing errors, affecting the accuracy of collaborative device control and failing to meet the low-latency data capture requirements of industrial real-time control. Moreover, the analyzers provided by related technologies are only designed for data analysis using the 100Mbps Ethernet protocol, and their fixed mode makes it difficult to efficiently process Ethernet data in industrial scenarios where multiple protocols coexist. Summary of the Invention

[0004] This application provides an Ethernet data transceiver circuit, circuit board, and data transceiver device, which solves the problem that the data acquisition solutions provided by related technologies are difficult to meet the requirements of multi-protocol coexistence in industrial scenarios. The Ethernet data transceiver circuit provided by this solution can realize Ethernet data processing by switching different channels, thereby meeting the requirements of multi-protocol coexistence.

[0005] In one aspect, this application provides an Ethernet data transceiver circuit, which includes a channel switching module, a data transceiver module, a SoC chip, and at least one pair of transceiver interfaces.

[0006] A pair of transceiver interfaces are used to connect the first device and the second device for data transmission between the first device and the second device; the channel switching module corresponds one-to-one with the transceiver interface. The channel switching module includes four input terminals and two output terminals. The two output terminals of the channel switching module are respectively connected to the two first terminals on the corresponding transceiver interface for sending data. In the channel switching module, a pair of input terminals corresponds to one output terminal and is used to switch different input terminals and form a first data transmission channel or a second data transmission channel when a control signal is received. The data transceiver module and the channel switching module are in one-to-one correspondence. The data transceiver module includes two data transmitting ends and two data receiving ends. The two data transmitting ends of the data transceiver module are respectively connected to the two input ends of the corresponding first data transmitting channel in the channel switching module. The two data receiving ends of the data transceiver module are connected to the two second terminals on the transceiver interface corresponding to the channel switching module for receiving data. The two data receiving ends of the data transceiver module are also connected to the two input ends of the corresponding second data transmitting channel in another channel switching module. The channel switching module to which the data transmitting end of the data transceiver module is connected and the other channel switching module to which the data receiving end of the data transceiver module is connected are both used to connect to the same pair of transceiver interfaces. The logic control port of the SoC chip is connected to the control terminal of the channel switching module, and the data transceiver terminal of the SoC chip is connected to the data interface terminal of the data transceiver module to send data to or receive data from the data transceiver module.

[0007] Secondly, this application also provides a circuit board that includes the Ethernet data transceiver circuit provided in the first aspect above.

[0008] Thirdly, this application also provides a data transceiver device, which includes the circuit board provided in the second aspect above.

[0009] The data transceiver circuit of this application can adapt to different Ethernet modes by switching the transmission channel on the channel switching module, thereby ensuring the "zero latency" acquisition requirements of real-time Ethernet such as EtherCAT, and also meeting the full-duplex communication requirements of data acquisition in Gigabit Ethernet. This enables the Ethernet data transceiver circuit of this application to provide a more reliable data acquisition solution and meet the requirements of multi-protocol coexistence. Attached Figure Description

[0010] Figure 1 This is a logic block diagram of an Ethernet data transceiver circuit provided in an embodiment of this application.

[0011] Figure 2 The circuit structure diagram of the differential numerator unit provided in one embodiment of this application is shown.

[0012] Figure 3 The circuit structure diagram of a channel switching module provided in an embodiment of this application is shown.

[0013] Figure 4 This is a schematic diagram of the structure of an Ethernet data transceiver circuit provided in an embodiment of this application. Detailed Implementation

[0014] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of the present application and are not intended to limit the scope of the present application. Furthermore, it should be noted that, for ease of description, the accompanying drawings only show the parts relevant to the embodiments of the present application, and not all structures. Those skilled in the art, after reading this specification, should be able to deduce that any combination of technical features can constitute an optional implementation method, provided that the technical features do not contradict each other.

[0015] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. In the description of this application, "multiple" means two or more, and "several" means one or more.

[0016] With the development of industrial automation and intelligent manufacturing, industrial Ethernet plays a core role in equipment communication and control. It requires real-time and precise transmission of control commands and status data, placing stringent demands on the real-time performance and accuracy of data acquisition and analysis. Furthermore, industrial scenarios often require the coexistence of multiple protocols, necessitating adaptation to Ethernet data processing at different speeds and protocols. For example, protocols such as EtherCAT and Gigabit Ethernet employ different data processing methods, with EtherCAT serving as an Ethernet-based fieldbus system.

[0017] In related technologies, traditional data acquisition solutions require data to be forwarded through PHY chips, FPGAs, or processor logic. The accumulated latency from analog-to-digital conversion and logic forwarding is significant. However, in timing-sensitive scenarios such as EtherCAT, this latency can lead to data timing errors, affecting the accuracy of collaborative device control and failing to meet the low-latency data capture requirements of industrial real-time control. Moreover, the analyzers provided by related technologies are only designed for data analysis using the 100Mbps Ethernet protocol, and their fixed mode makes it difficult to efficiently process Ethernet data in industrial scenarios where multiple protocols coexist.

[0018] In response, this application provides an Ethernet data transceiver circuit that can be used to connect two devices that need to transmit data, and can also be connected to a host computer or other devices, so that while transmitting data between devices, the host computer can also complete data acquisition, thereby achieving a better data processing solution. Figure 1A logic block diagram of an Ethernet data transceiver circuit provided in an embodiment of this application is shown below. Figure 1 As shown, in one embodiment, the Ethernet data transceiver circuit includes a channel switching module 120, a data transceiver module 130, a SoC (System on Chip) chip, and at least one pair of transceiver interfaces 110.

[0019] The same pair of transceiver interfaces 110 are used to connect the first device and the second device for data transmission. Specifically, one interface in the same pair of transceiver interfaces 110 is used to connect the first device, and the other interface is used to connect the second device. The channel switching module 120 corresponds one-to-one with the transceiver interfaces 110. At least two channel switching modules 120 exist to connect to different transceiver interfaces 110 in the same pair. Specifically, each transceiver interface 110 has two first terminals for transmitting data and two second terminals for receiving data. The channel switching module 120 includes four input terminals and two output terminals. The two output terminals of the channel switching module 120 are respectively connected to the two first terminals on the corresponding transceiver interface 110 used for transmitting data. The four input terminals of the channel switching module 120 can be divided into two pairs, with each pair of input terminals corresponding to one output terminal. Therefore, the channel switching module 120 can be controlled by a control signal to switch different input terminals to form a first data transmission channel or a second data transmission channel.

[0020] Understandably, upon receiving a control signal, both pairs of input terminals of the channel switching module 120 are switched, ensuring that before and after each switch, one input terminal in each pair of input terminals in the channel switching module 120 is connected to the corresponding output terminal. This creates different data transmission channels before and after the switch, with two channels for each type. For example, the channel switching module 120 includes four input terminals: port I1, port I2, port I3, and port I4, and two output terminals: port O1 and port O2. Port I1 and port I2 are a pair corresponding to port O1, and port I3 and port I4 are a pair corresponding to port I2. When the channel switching module 120 switches to a connection between port I1 and port O1, and port I3 and port O2, a first data transmission channel is formed in the channel switching module 120. When the channel switching module 120 switches to a connection between port I2 and port O1, and port I4 and port O2, ports O1 and O2 are respectively connected to the first interface I of the transceiver interface 110. RD1 The two first terminals on the channel switching module 120 form a second data transmission channel.

[0021] Each data transceiver module 130 corresponds one-to-one with a channel switching module 120. Similarly, the number of data transceiver modules 130 is the same as the number of transceiver interfaces 110. Each data transceiver module 130 includes two data transmitting ends and two data receiving ends. The two data transmitting ends of the data transceiver module 130 are respectively connected to the two input ends of the corresponding first data transmitting channel in the channel switching module 120. The two data receiving ends of the data transceiver module 130 are connected to the two second terminals on the transceiver interface 110 corresponding to the channel switching module 120 for receiving data. The two data receiving ends of the data transceiver module 130 are also connected to the two input ends of the corresponding second data transmitting channel in another channel switching module 120. Furthermore, both the channel switching module 120 to which the data transmitting ends of the data transceiver module 130 are connected and the other channel switching module 120 to which the data receiving ends of the data transceiver module 130 are connected to the same pair of transceiver interfaces 110. For example, the data transceiver module 130 includes two data transmitting ends, port TD1 and port TD2, and two data receiving ends, port RD1 and port RD2. Port TD1 is connected to port I1 of the channel switching module 120, port TD2 is connected to port I3 of the channel switching module 120, and port RD1 is connected to the first interface I. RD1 One of the second terminals, port RD2, is connected to the first interface I. RD1 The other second terminal; ports RD1 and RD2 on another data transceiver module 130 are respectively connected to the first interface I. RD1 The two first terminals on it.

[0022] Furthermore, the logic control port of the SoC chip 140 is connected to the control terminal of the channel switching module 120, and the data transceiver terminal of the SoC chip 140 is connected to the data interface terminal of the data transceiver module 130 for sending data to or receiving data from the data transceiver module 130. That is, bidirectional data transmission can be performed between the SoC chip 140 and the data transceiver module 130. The SoC chip 140 is also connected to the channel switching module 120 to send control signals to the channel switching module 120, thereby realizing the switching control of the data transmission channel.

[0023] It is understood that the channel switching module 120 connects to the data transmitting end of one data transceiver module 130 and the data receiving end of another data transceiver module 130 via its input terminals. The data receiving end of the data transceiver module 130 is also connected to the second terminal of the corresponding transceiver interface 110. Based on this, the channel switching module 120 can be controlled to switch data channels with different transmission directions. For example, by controlling the channel switching module 120, data sent by the first device can pass through the transceiver interface 110 and then through the channel switching module 120 to flow into another transceiver interface 110, thereby being transmitted to the second device; or data sent by the second device can pass through the transceiver interface 110 and then through the channel switching module 120 to flow into another transceiver interface 110, thereby being transmitted to the first device. Furthermore, after switching via the channel switching module 120, the data transceiver module 130 can also adapt to the full-duplex signal transmission requirements of Gigabit Ethernet to achieve Gigabit Ethernet data transmission. In other words, by controlling the channel switching module 120, different data transmission methods can be implemented and the transmission requirements of different protocols can be adapted.

[0024] Optionally, in one embodiment, the SoC chip is also connected to a storage unit and stores data in the storage unit. The storage unit includes at least one of a SD-type memory card, a DDR3-type internal memory, and an EMMC-type embedded flash memory. That is, the SoC chip can store data in the storage unit or read data from the storage unit and send it to other devices. For example, the SoC chip connects to a SD (Secure Digital) type memory card, a DDR3 (Double-Data-Rate Three) type internal memory, and an EMMC-type embedded flash memory, and then stores the received data in the corresponding storage device. The EMMC-type embedded flash memory is used to store system firmware, the DDR3-type internal memory is used for Ethernet data caching, and the SD-type memory card is used to save the parsed Ethernet signal for convenient offline analysis by the user.

[0025] As can be seen from the above scheme, the data transceiver circuit of this scheme can adapt to different Ethernet modes by switching the transmission channel on the channel switching module, thereby ensuring the "zero latency" acquisition requirements of real-time Ethernet such as EtherCAT, and also meeting the full-duplex communication requirements of data acquisition in Gigabit Ethernet. This enables the Ethernet data transceiver circuit of this scheme to provide a more reliable data acquisition solution and meet the requirements of multi-protocol coexistence.

[0026] In one embodiment, the data transceiver module includes a dual differential drive unit, a PHY chip, and an isolation transformer. Specifically, the dual differential drive unit provides a full-duplex transmission channel. The dual differential drive unit includes two first transceiver terminals and two second transceiver terminals, with each first transceiver terminal corresponding to one of the second transceiver terminals. The isolation transformer includes four signal input terminals and four output terminals, with each output terminal corresponding to a corresponding signal input terminal to enable signal transmission.

[0027] To address this, the two first transceiver terminals of the dual differential drive unit serve as the two data receiving terminals of the data transceiver module, while the two second transceiver terminals of the dual differential drive unit are connected to the two signal input terminals of the isolation transformer. The other two signal input terminals of the isolation transformer serve as the two data transmitting terminals of the data transceiver module. The four output terminals of the isolation transformer are connected to the first signal transceiver terminals of the PHY chip, and the second signal transceiver terminals of the PHY chip are connected to the data transceiver terminals of the SoC chip. It is conceivable that the first and second signal transceiver terminals of the PHY chip are each equipped with multiple interface terminals for connecting the isolation transformer and the SoC chip. Optionally, the PHY chip and the SoC chip are connected via the RGMII interface. The RGMII interface, as a 4-bit data interface, has high transmission efficiency, enabling fast data transmission between the PHY chip and the SoC chip. It is understood that the dual differential drive unit provides a full-duplex transmission channel, meaning the data transceiver module can receive data from or send data to the transceiver interface through the dual differential drive unit, thereby realizing the data transceiver function. Therefore, by providing a full-duplex transmission channel through the dual differential drive unit and enabling mode switching through the channel switching module, the Ethernet data transceiver circuit can adapt to the data acquisition requirements of Gigabit Ethernet, thereby helping to provide a reliable data acquisition channel.

[0028] In some embodiments, the dual differential driver unit includes two differential numerator units, each with its input connected to the output of the other differential numerator unit. Essentially, the input to the output of each differential numerator unit constitutes a transmission channel. This is achieved by connecting the other differential numerator units in reverse parallel, i.e., the input of one differential numerator unit is connected to the output of the other, and vice versa. This dual differential driver unit provides a bidirectional transmission channel for transmitting full-duplex signals over Gigabit Ethernet. By providing a full-duplex transmission channel to adapt to data transmission requirements, the dual differential driver unit in this solution allows for switching between different channels to meet the needs of multi-protocol coexistence. The solution is simple in structure and more efficient.

[0029] Optionally, Figure 2The circuit diagram of the differential numerator unit provided in one embodiment of this application is shown in the figure. The differential numerator unit includes a differential driver Q1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The positive output terminal of the differential driver Q1 is connected to the first resistor R1, the negative output terminal of the differential driver Q1 is connected to the second resistor R2, the inverting input terminal of the differential driver Q1 is connected to the first capacitor C1, and the non-inverting input terminal of the differential driver Q1 is connected to the second capacitor C2. The positive power supply voltage terminal of the differential driver Q1 is connected to the first terminal of the third capacitor C3, which is connected to a positive voltage. The fourth capacitor C4 is connected in parallel with the third capacitor C3, and the second terminal of the third capacitor C3 is grounded. The negative power supply voltage terminal of the differential driver Q1 is connected to the first terminal of the fifth capacitor C5, which is connected to a negative voltage. The sixth capacitor C6 is connected in parallel with the fifth capacitor C5, and the second terminal of the fifth capacitor C5 is grounded. Understandably, the positive and negative voltages connected to the differential driver Q1 can be provided by an isolated power supply, and using a negative power supply can achieve better low-distortion performance. The signal is connected through the first capacitor C1 and the second capacitor C2 on the inverting input and non-inverting input of the differential driver Q1. The first capacitor C1 and the second capacitor C2 can also isolate the DC voltage on the Ethernet cable, and the first resistor R1 and the second resistor R2 serve as matching resistors, forming impedance matching in the transmission line to improve signal integrity.

[0030] Optionally, the differential driver is a high-speed differential driver, which can provide twice the signal gain. Understandably, a resistor connected to the output of a high-speed differential driver on the transmission line will attenuate the output signal by half. However, with a high-speed differential driver providing twice the signal gain, even if the output signal is attenuated by half, the end-to-end net gain in the system remains at 1, that is, consistent with the original signal amplitude, helping to ensure complete signal transmission.

[0031] Figure 3 The circuit diagram of a channel switching module provided in one embodiment of this application is shown in the figure. In one embodiment, the channel switching module includes an NPN transistor Q2, a third resistor R3, a fourth resistor R4, a seventh capacitor C7, an eighth capacitor C8, a diode D1, and a dual-switch relay. Specifically, the base of the NPN transistor Q2 is connected to the first terminal of the third resistor R3, the second terminal of the third resistor R3 serves as the control terminal of the channel switching module, the first terminal of the fourth resistor R4 is connected to the second terminal of the third resistor R3, the second terminal of the fourth resistor R4 is connected to the emitter terminal of the NPN transistor Q2, and the emitter terminal of the NPN transistor Q2 is grounded.

[0032] The collector of NPN transistor Q2 is connected to the negative terminal of coil K1C of the dual-switch relay, and the positive terminal of coil K1C is connected to the operating voltage. The dual-switch relay is used to control the switching of the first switch K1A and the second switch K1B through coil K1C. The first switch K1A and the second switch K1B are used to provide the first data transmission channel and the second data transmission channel, respectively. The negative terminal of coil K1C of the dual-switch relay is also connected to the grounded seventh capacitor C7, and the positive terminal of coil K1C of the dual-switch relay is also connected to the grounded eighth capacitor C8. The anode of diode D1 is connected to the negative terminal of coil K1C of the dual-switch relay, and the cathode of diode D1 is connected to the positive terminal of coil K1C of the dual-switch relay.

[0033] Understandably, upon receiving a high-level control signal from the SoC chip, the base of NPN transistor Q2 receives this signal through the third resistor R3, causing NPN transistor Q2 to conduct. This allows the coil K1C of the dual-switch relay, which is connected to the operating voltage, to form a conduction circuit through NPN transistor Q2, thus energizing coil K1C. Under the action of the energized coil K1C, the first switch K1A and the second switch K1B switch to switch the first data transmission channel to the second data channel or vice versa. As shown in the figure, when coil K1C is not energized, the first input terminal of the first switch K1A is connected to the transceiver interface, and the second input terminal of the first switch K1A is connected to the isolation transformer in the data transceiver module. The first input terminal of the second switch K1B is connected to the transceiver interface, and the second input terminal of the second switch K1B is connected to the isolation transformer in the data transceiver module. At this time, the first input terminal of the first switch K1A is connected to the output terminal, and the first input terminal of the second switch K1B is connected to the output terminal. Based on this, when coil K1C is energized, both the first switch K1A and the second switch K1B switch are switched, meaning the second input terminal of the first switch K1A is connected to its output terminal, and the second input terminal of the second switch K1B is connected to its output terminal. Therefore, this scheme utilizes the conduction control of the switching transistors to achieve the switching of different data channels in the channel switching module, effectively realizing data transmission control and thus improving the reliability of the circuit in Ethernet data transmission.

[0034] Figure 4The figure shows a schematic diagram of an Ethernet data transceiver circuit according to an embodiment of this application. The Ethernet data transceiver circuit has at least one pair of transceiver interfaces. Optionally, the transceiver interfaces use RJ45 interfaces. These interfaces include interface NET0 and interface NET1. Each transceiver interface includes two first terminals for transmitting data (e.g., terminals TD_0+ and TD_0-) and two second terminals for receiving data (e.g., terminals RD_0+ and RD_0-). At least two channel switching modules are also provided, each corresponding to one of the transceiver interfaces. The two output terminals of the channel switching module are connected to the two first terminals of the transceiver interface (e.g., terminals TD_0+ and TD_0- on interface NET0), while the two input terminals of the channel switching module are connected to the second terminals of the other transceiver interface (e.g., terminals RD_0+ and RD_0- on interface NET1). The other two input terminals of the channel switching module are connected to the two signal input terminals of the isolation transformer in the data transceiver module, which correspond to the two first terminals of the transceiver interface.

[0035] Furthermore, the two second terminals on the transceiver interface are connected to the input of one differential driver in the dual differential drive unit of the data transceiver module. The output of this differential driver is connected to the other two signal input terminals of the isolation transformer. The dual differential drive unit also has another differential driver, which is connected in reverse parallel with the other differential driver. That is, the input of this differential driver is connected to the output of the other differential driver, and the output of the differential driver is also connected to the input of the other differential driver. The output of the isolation transformer is connected to the first signal transceiver terminal of the PHY chip, while the second signal transceiver terminal of the PHY chip is connected to the data transceiver terminal of the SoC chip. The SoC chip is also connected to a corresponding SD type memory card, a corresponding DDR3 type internal memory, and a corresponding eMMC type embedded flash memory.

[0036] Understandably, with the first device for sending data connected to interface NET0 and the second device for receiving data connected to interface NET1, the SoC chip can output corresponding control signals through its logic control ports to enable the channel switching module to switch between different input terminals to form either the first or second data transmission channel. As shown in the diagram, when the input terminal in the channel switching module is switched to the two input terminals connected to the second terminal on another transceiver interface, the data sent from the first device enters through interface NET0 and flows out through interface NET1. After entering through interface NET0, the data is split into two. One path is forwarded to interface NET1 via the transmission channel formed by the channel switching module. This path is a direct hardware connection and does not introduce delay into the signal, maintaining the original communication link's attributes. This achieves direct forwarding through the interface, effectively eliminating delay and thus effectively meeting the real-time requirements of EtherCAT. The other path is connected to the isolation transformer after gaining through a differential driver. Due to the high impedance input of the differential driver, impedance changes caused by the long branch from the signal to the transformer are avoided. Furthermore, the differential signal is boosted to enhance driving capability, reducing the probability of communication errors and device failures.

[0037] However, when the input terminal in the control channel switching module is switched to the two input terminals of the two signal access terminals in the isolation transformer, full-duplex communication is required in the gigabit Ethernet acquisition mode. To address this, another differential driver is connected in reverse parallel to the differential driver, thereby forming two transmission channels in different directions. This allows for bidirectional transmission after the signal is accessed through the second terminal on interface NET0 or interface NET1, thus achieving full-duplex communication and avoiding signal superposition during bidirectional transmission.

[0038] This application also provides a circuit board including the Ethernet data transceiver circuit provided in the above embodiments. The circuit board connects to other devices to access data transmitted by other devices, thereby ensuring "zero-latency" acquisition of real-time Ethernet such as EtherCAT, avoiding signal interference, and being compatible with different Ethernet scenarios. This solution can precisely address the pain points of industrial Ethernet data acquisition by optimizing the data path, adopting high-impedance differential drive, and introducing a mode switching mechanism, supporting efficient and stable operation of industrial automation. Through mode switching of the relay in the channel switching module, the Ethernet data transceiver circuit of this solution is also suitable for data acquisition and analysis of Gigabit Ethernet.

[0039] This application also provides a data transceiver device, which includes the circuit board provided in the above embodiments. The data transceiver device can connect to devices that need to transmit data, and can also switch between different modes through its circuit structure to ensure "zero latency" acquisition of real-time Ethernet such as EtherCAT and compatibility with different Ethernet scenarios, thereby efficiently realizing data transmission and acquisition.

[0040] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0041] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. An Ethernet data transceiver circuit, characterized in that, include: At least one pair of transceiver interfaces, the pair of transceiver interfaces being used to connect a first device and a second device, so that the first device and the second device can transmit data; A channel switching module is provided, which corresponds one-to-one with the transceiver interface. The channel switching module includes four input terminals and two output terminals. The two output terminals of the channel switching module are respectively connected to two first terminals on the corresponding transceiver interface for sending data. In the channel switching module, a pair of input terminals corresponds to one output terminal and is used to switch different input terminals and form a first data transmission channel or a second data transmission channel when a control signal is received. A data transceiver module, which corresponds one-to-one with the channel switching module, includes two data transmitting ends and two data receiving ends. The two data transmitting ends of the data transceiver module are respectively connected to the two input ends of the channel switching module corresponding to the first data transmitting channel. The two data receiving ends of the data transceiver module are connected to the two second terminals on the transceiver interface corresponding to the channel switching module for receiving data. The two data receiving ends of the data transceiver module are also connected to the two input ends of another channel switching module corresponding to the second data transmitting channel. The channel switching module to which the data transmitting ends of the data transceiver module are connected and the other channel switching module to which the data receiving ends of the data transceiver module are connected are both used to connect to the same pair of transceiver interfaces. The SoC chip has its logic control port connected to the control terminal of the channel switching module, and its data transceiver terminal connected to the data interface terminal of the data transceiver module for sending data to or receiving data from the data transceiver module.

2. The Ethernet data transceiver circuit according to claim 1, characterized in that, The data transceiver module includes a dual differential drive unit, a PHY chip, and an isolation transformer; The two first transceiver terminals of the dual differential drive unit serve as the two data receiving terminals of the data transceiver module, and the two second transceiver terminals of the dual differential drive unit are respectively connected to the two signal input terminals in the isolation transformer. The dual differential drive unit is used to provide a full-duplex transmission channel. The other two signal input terminals of the isolation transformer serve as the two data transmission terminals of the data transceiver module, and the four output terminals of the isolation transformer are respectively connected to the first signal transceiver terminal of the PHY chip. The second signal transceiver terminal of the PHY chip is connected to the data transceiver terminal of the SoC chip.

3. The Ethernet data transceiver circuit according to claim 2, characterized in that, The dual differential drive unit includes two differential numerator units, and the input terminal of each differential numerator unit is connected to the output terminal of the other differential numerator unit.

4. The Ethernet data transceiver circuit according to claim 3, characterized in that, The differential numerator unit includes a differential driver, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor; The positive output terminal of the differential driver is connected to the first resistor, the negative output terminal of the differential driver is connected to the second resistor, the inverting input terminal of the differential driver is connected to the first capacitor, and the non-inverting input terminal of the differential driver is connected to the second capacitor. The positive power supply voltage terminal of the differential driver is connected to the first terminal of the third capacitor, the first terminal of the third capacitor is connected to a positive voltage, the fourth capacitor is connected in parallel with the third capacitor, and the second terminal of the third capacitor is grounded; the negative power supply voltage terminal of the differential driver is connected to the first terminal of the fifth capacitor, the first terminal of the fifth capacitor is connected to a negative voltage, the sixth capacitor is connected in parallel with the fifth capacitor, and the second terminal of the fifth capacitor is grounded.

5. The Ethernet data transceiver circuit according to claim 4, characterized in that, The differential driver is a high-speed differential driver, and the high-speed differential driver is used to provide twice the signal gain.

6. The Ethernet data transceiver circuit according to any one of claims 2-5, characterized in that, The PHY chip and the SoC chip are connected via the RGMII interface.

7. The Ethernet data transceiver circuit according to claim 1 or 2, characterized in that, The channel switching module includes an NPN transistor, a third resistor, a fourth resistor, a seventh capacitor, an eighth capacitor, a diode, and a dual-switch relay. The base of the NPN transistor is connected to the first end of the third resistor, the second end of the third resistor serves as the control terminal of the channel switching module, the first end of the fourth resistor is connected to the second end of the third resistor, the second end of the fourth resistor is connected to the emitter of the NPN transistor, and the emitter of the NPN transistor is grounded. The collector of the NPN transistor is connected to the negative terminal of the coil of the dual-switch relay, and the positive terminal of the coil of the dual-switch relay is connected to the working voltage. The dual-switch relay is used to control the switching of the first switch and the second switch through the coil. The first switch and the second switch are respectively used to provide the first data transmission channel and the second data transmission channel. The negative terminal of the coil of the dual-switch relay is also connected to the grounded seventh capacitor, and the positive terminal of the coil of the dual-switch relay is also connected to the grounded eighth capacitor. The anode of the diode is connected to the negative terminal of the coil of the dual-switch relay, and the cathode of the diode is connected to the positive terminal of the coil of the dual-switch relay.

8. The Ethernet data transceiver circuit according to claim 1, characterized in that, The SoC chip is also connected to a storage unit and stores data in the storage unit, which includes at least one of a memory card of type SD, internal memory of type DDR3, and embedded flash memory of type EMMC.

9. A circuit board, characterized in that, Includes the Ethernet data transceiver circuit as described in any one of claims 1-8.

10. A data transceiver device, characterized in that, Includes the circuit board as described in claim 9.

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