SiC MOSFET chip terminal structure based on groove technology

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) chip terminal structure based on a groove process. The SiC MOSFET chip terminal structure comprises a terminal region n-type drift region and a plurality of basic units, wherein the plurality of basic units are sequentially arranged on the terminal region n-type drift region along the length direction of the terminal region n-type drift region. The problem that a traditional SiC MOSFET terminal is large in area is solved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and particularly relates to a SiC MOSFET chip termination structure based on trench technology. Background Technology

[0002] Third-generation semiconductor material SiC (silicon carbide) has advantages over traditional silicon materials in terms of high voltage resistance, high thermal conductivity, and high mechanical strength, making it a hot research topic in the field of power semiconductors. SiC MOSFETs (metal-oxide-semiconductor field-effect transistors) are also a strong alternative to traditional silicon-based power devices in the 600V-1700V voltage range and are currently used in electric vehicles, photovoltaic power generation, and other fields.

[0003] The device structure of SiC MOSFETs is basically the same as that of silicon-based MOSFETs. Both require termination structures to improve the breakdown voltage at the chip edges. However, in terms of manufacturing processes, SiC MOSFETs face challenges. Firstly, ion implantation is more difficult, making it hard to form deep p-wells like in Si MOSFETs. Secondly, SiC itself has high hardness and stable chemical properties, making it difficult to form high-quality deep trenches. Therefore, SiC MOSFET terminations cannot utilize the wide and deep p-well equipotential ring-field confinement ring structure found in Si IGBTs, nor can they use deep trenches as terminations like in SiTMOS. Currently, the mainstream termination structure for SiC MOSFETs consists of dozens of very narrow field confinement rings, resulting in a significant portion of the chip area occupied by the terminations. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a SiC MOSFET chip termination structure based on trench technology, which solves the problem of large termination area of ​​traditional SiC MOSFETs.

[0005] The objective of this invention is achieved through the following technical solution: a SiC MOSFET chip termination structure based on trench technology, comprising: an n-type drift region of the termination region and multiple basic units; wherein, the multiple basic units are sequentially disposed on the n-type drift region of the termination region along the length direction of the n-type drift region of the termination region.

[0006] In the aforementioned SiC MOSFET chip termination structure based on trench technology, the basic unit includes a surface p-well, a p-type buried layer, a trench periphery p-well, a trench oxide layer, and a trench polysilicon layer. Specifically, an ion implantation process forms a surface p-well on the upper surface of the n-type drift region of the termination area. A trench is formed in the center of the surface p-well through a trench etching process. An ion implantation process forms a p-type buried layer at the bottom of the trench, and ion implantation on the sides of the trench forms a trench periphery p-well. The trench is filled with oxide to form a trench oxide layer, and the etched portion at the center of the trench oxide layer is filled with polysilicon to form a trench polysilicon layer.

[0007] In the aforementioned SiC MOSFET chip termination structure based on trench technology, the trench depth is not less than 1μm.

[0008] In the aforementioned SiC MOSFET chip terminal structure based on trench technology, multiple basic units are arranged sequentially with equal or unequal spacing.

[0009] In the aforementioned SiC MOSFET chip termination structure based on trench technology, when multiple basic units are arranged sequentially with equal spacing, the higher the doping concentration of the n-type drift region in the termination area, the smaller the spacing.

[0010] In the aforementioned SiC MOSFET chip terminal structure based on trench technology, when multiple basic units are arranged sequentially with unequal spacing, the spacing increases as the distance from the active region increases.

[0011] In the aforementioned SiC MOSFET chip terminal structure based on trench technology, a basic unit is composed of multiple basic cells, which are arranged sequentially with unequal spacing. The spacing increases with distance from the active region. The spacing between two adjacent basic cells in each basic unit is equal.

[0012] A method for fabricating a basic unit of a SiC MOSFET chip terminal structure based on trench technology includes: forming a surface p-well by ion implantation on the surface of an n-type drift region in the terminal region; forming a trench in the middle of the surface p-well by trench etching; forming a p-type buried layer by ion implantation at the bottom of the trench; forming a trench perimeter p-well by ion implantation on the side of the trench; filling the trench with oxide to form a trench oxide layer; and filling the center of the trench oxide layer with polysilicon by etching to form a trench polysilicon layer.

[0013] In the above-mentioned method for preparing basic units, the depth of the trench is not less than 1 μm.

[0014] In the above-mentioned basic unit preparation method, p-type impurities are ion implanted at the bottom of the trench to form a p-type buried layer.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] This invention addresses the limitation of traditional SiC MOSFET termination processes in forming deep and wide p-wells, which are not possible in Si processes, by combining trench technology. As a result, a single deep p-well can replace multiple shallow p-wells, thereby reducing the overall termination structure area. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1 This is a cross-sectional view of the basic unit of the SiC MOSFET terminal based on trench technology provided in an embodiment of the present invention;

[0019] Figure 2 This is a cross-sectional view of a terminal structure composed of multiple basic units arranged at equal intervals according to an embodiment of the present invention;

[0020] Figure 3 This is a cross-sectional view of the terminal structure composed of multiple basic units arranged with gradually varying spacing, as provided in the embodiments of the present invention.

[0021] Figure 4 This is a cross-sectional view of the terminal structure composed of two basic units arranged with gradually varying spacing, as provided in the embodiments of the present invention;

[0022] Figure 5 This is a schematic diagram of the depletion region interface of the chip during voltage withstand provided in an embodiment of the present invention;

[0023] Figure 6 This is a lateral distribution diagram of the electric field at the bottom of the basic unit of the terminal area when the chip withstands voltage, provided in an embodiment of the present invention. Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] The main reason why traditional SiC MOSFETs have a large terminal area is that the ion implantation process of SiC cannot form a deep and wide p-well, and the breakdown voltage can only be improved by increasing the number of field limiting rings.

[0026] This embodiment provides a SiC MOSFET chip termination structure based on trench technology. The structure includes: a termination region n-type drift region 1 and multiple basic units; wherein, the multiple basic units are sequentially arranged on the termination region n-type drift region 1 along the length direction of the termination region n-type drift region 1.

[0027] Figure 1 This is a cross-sectional view of the basic unit of a SiC MOSFET terminal based on trench technology provided in an embodiment of the present invention. Figure 1 As shown, the basic unit includes a surface p-well 2, a p-type buried layer 3, a trench periphery p-well 4, a trench oxide layer 5, and a trench polysilicon layer 6; wherein, the surface p-well 2 is formed by ion implantation on the upper surface of the terminal n-type drift region 1; a trench is formed in the middle of the surface p-well 2 by trench etching process, the bottom of the trench is ion implanted to form a p-type buried layer 3, the side of the trench is ion implanted to form a trench periphery p-well 4, the trench is filled with oxide to form a trench oxide layer 5, and the central etched part of the trench oxide layer 5 is filled with polysilicon to form a trench polysilicon layer 6.

[0028] The depth of the trench is not less than 1 μm.

[0029] Multiple basic units are arranged sequentially with equal or unequal spacing. When multiple basic units are arranged sequentially with equal spacing, the higher the doping concentration of the n-type drift region at the termination point, the smaller the spacing. When multiple basic units are arranged sequentially with unequal spacing, the farther away from the active region, the larger the spacing.

[0030] A basic unit is composed of multiple basic units, which are arranged sequentially at unequal intervals; the further away from the active region, the larger the interval; the interval between two adjacent basic units in each basic unit is equal.

[0031] This embodiment utilizes the trench process of SiC MOSFETs. In the termination region, a trench at least 1 μm deep is etched. P-type impurities are ion-implanted at the bottom of the trench to form a p-type buried layer with a lateral width at least twice the trench width. P-type well regions are ion-implanted around the trench to form surrounding p-type wells. The overall width of the p-type well regions and the trench is approximately the same as the p-type buried layer. Surface p-wells are formed on both sides of the top of the trench using ion implantation or thermal diffusion. The overall width of the structure formed by the surface p-wells and the trench is at least the width of the p-type buried layer. The p-type buried layer and the surface p-wells are connected by the p-type well regions surrounding the trench, forming a wider and deeper deep p-well. This deep p-well and the trench together serve as the basic unit of the termination structure. Several basic units are arranged sequentially at equal or unequal intervals to form the termination structure. This interval varies depending on the doping concentration of the drift region; the higher the doping concentration, the smaller the interval. When using unequal intervals, the farther away from the active region, the larger the interval. When using unequal spacing, multiple basic units can be arranged in a basic unit with unequal spacing. The spacing inside the basic unit is equal, and the spacing inside different basic units can be equal or increase as the distance from the active region increases.

[0032] Example 1: Multiple sets of surface p-wells 2 are formed by ion implantation at equal intervals on the upper surface of the n-type drift region 1 in the terminal region. A trench is formed in the middle of the surface p-wells 2 using a trench etching process. A p-type buried layer 3 is formed by ion implantation at the bottom of the trench. P-wells 4 are formed around the trench by ion implantation on the sides of the trench. An oxide layer 5 is formed by filling the trench with oxide. A polysilicon layer 6 is formed by etching a portion in the center of the oxide layer 5. Figure 2 , Figure 5 and Figure 6 As shown.

[0033] Example 2: Multiple sets of surface p-wells 2 are formed by ion implantation with a gradually varying spacing on the upper surface of the n-type drift region 1 in the terminal region. A trench is formed in the middle of 2 by trench etching. A p-type buried layer 3 is formed by ion implantation at the bottom of the trench. P-wells 4 are formed around the trench by ion implantation on the sides of the trench. An oxide layer 5 is formed by filling the trench with oxide. A polysilicon layer 6 is formed by etching a portion in the center of the oxide layer. Figure 3 As shown.

[0034] Example 3: On the upper surface of the n-type drift region 1 in the terminal region, a trench is formed in the middle of 2 using a trench etching process with a gradually varying spacing between two implantation sites. A p-type buried layer 3 is formed by ion implantation at the bottom of the trench, and a p-well 4 is formed around the trench by ion implantation on the sides of the trench. An oxide layer 5 is formed by filling the trench with oxide. A polysilicon layer 6 is formed by etching a portion at the center of the oxide layer and filling it with polysilicon. Figure 4 As shown.

[0035] This embodiment also provides a method for fabricating a basic unit of a SiC MOSFET chip terminal structure based on trench technology. The method includes: forming a surface p-well 2 by surface ion implantation on the n-type drift region 1 of the terminal region; forming a trench in the middle of the surface p-well 2 by trench etching; forming a p-type buried layer 3 by ion implantation at the bottom of the trench; forming a trench perimeter p-well 4 by ion implantation on the side of the trench; filling the trench with oxide to form a trench oxide layer 5; and filling the center of the trench oxide layer 5 with polysilicon to form a trench polysilicon layer 6.

[0036] This embodiment addresses the limitation of traditional SiC MOSFET termination processes in forming deep and wide p-wells, which are not possible in Si processes, by combining trench technology. This allows a single deep p-well to replace multiple shallow p-wells, thereby reducing the overall termination structure area.

[0037] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A SiC MOSFET chip termination structure based on trench technology, characterized in that... include: Terminal region n-type drift region (1) and multiple basic units; among which, Multiple basic units are sequentially arranged on the n-type drift region (1) of the terminal region along the length direction of the terminal region n-type drift region (1).

2. The SiC MOSFET chip termination structure based on trench technology according to claim 1, characterized in that: The basic unit includes a surface p-well (2), a p-type buried layer (3), a trench perimeter p-well (4), a trench oxide layer (5), and a trench polysilicon layer (6); wherein, The n-type drift region (1) in the terminal region is ion implanted to form a surface p-well (2); A trench is formed in the middle of the surface p-well (2) by trench etching process. Ion implantation is performed at the bottom of the trench to form a p-type buried layer (3). Ion implantation is performed on the side of the trench to form a surrounding p-well (4). The trench is filled with oxide to form a trench oxide layer (5). The center of the trench oxide layer (5) is etched and filled with polysilicon to form a trench polysilicon layer (6).

3. The SiC MOSFET chip termination structure based on trench technology according to claim 2, characterized in that: The depth of the trench is not less than 1 μm.

4. The SiC MOSFET chip termination structure based on trench technology according to claim 1, characterized in that: Multiple basic units are arranged sequentially with equal or unequal spacing.

5. The SiC MOSFET chip termination structure based on trench technology according to claim 4, characterized in that: When multiple basic units are arranged sequentially with equal spacing, the higher the doping concentration of the n-type drift region in the terminal region, the smaller the spacing.

6. The SiC MOSFET chip termination structure based on trench technology according to claim 4, characterized in that: When multiple basic units are arranged sequentially with unequal spacing, the spacing increases as the distance from the active region increases.

7. The SiC MOSFET chip termination structure based on trench technology according to claim 4, characterized in that: A basic unit is composed of multiple basic units, which are arranged sequentially at unequal intervals; the further away from the active region, the larger the interval; the interval between two adjacent basic units in each basic unit is equal.

8. A method for fabricating the basic unit of a SiC MOSFET chip termination structure based on trench technology, characterized in that... include: A surface p-well (2) is formed by surface ion implantation in the n-type drift region (1) of the terminal region; A trench is formed in the middle of the surface p-well (2) by trench etching process, a p-type buried layer (3) is formed by ion implantation at the bottom of the trench, a surrounding p-well (4) is formed by ion implantation on the side of the trench, an oxide layer (5) is formed by filling the trench with oxide, and a polysilicon layer (6) is formed by etching the center of the trench oxide layer (5).

9. The method for preparing the basic unit according to claim 8, characterized in that: The depth of the trench is not less than 1 μm.

10. The method for preparing the basic unit according to claim 8, characterized in that: p-type impurities are ion-implanted at the bottom of the trench to form a p-type buried layer.

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