Display panel and display device

Abstract

According to the display panel and the display device provided by the invention, the first gate insulating layer covers the second doped part, and the first gate insulating layer does not cover the first doped part, so that the first doped part is easier to be etched or subjected to ion bombardment to generate electrons compared with the second doped part in the process of forming the display panel, and the display efficiency is improved. The effective channel length of the first active pattern is reduced due to diffusion of electrons to the first channel part, so that the threshold voltage of the oxide semiconductor transistor in the display area is biased negative, and hydrogen elements in other film layers are easy to diffuse to the first doping part, so that the oxide semiconductor transistor in the display area is biased negative. The threshold voltages of the oxide semiconductor transistors in the pixel driving circuit and the gate driving circuit are differentiated, and the display panel can perform normal display.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the existing display device has higher and higher requirements for display effect. In order to improve the display effect, the existing display device will adopt LTPO (Low Temperature Polysilicon Oxide) pixel circuit, but the LTPO pixel driving circuit needs more GOA (Gate On Array, Gate on Array) circuit output signal, which will cause the power consumption of the display device to increase, in order to reduce the power consumption of the display device, CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) GOA circuit will be used to reduce the number of GOA circuits. In the LTPO pixel driving circuit and the CMOS GOA circuit, the oxide semiconductor transistor in the LTPO pixel driving circuit needs to ensure that the threshold voltage is around 0 volts to achieve better PBTS (positive bias temperature stress, positive bias temperature stress), and the oxide semiconductor transistor in the CMOS GOA circuit needs to ensure that the threshold voltage is positive to avoid leakage. But in the actual production process, the threshold voltage of the oxide semiconductor transistor in the LTPO pixel driving circuit and the CMOS GOA circuit is close or even equal, which cannot differentiate the oxide semiconductor transistors in the two, resulting in display defects.

[0003] Therefore, the existing display device has the technical problem of display defects caused by the inability to differentiate the threshold voltage of the oxide semiconductor transistor in the LTPO pixel driving circuit and the CMOS GOA circuit. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of display defects caused by the inability to differentiate the threshold voltage of the oxide semiconductor transistor in the LTPO pixel driving circuit and the CMOS GOA circuit in the existing display device.

[0005] The embodiments of the present application provide a display panel, which comprises a display area and a gate driving circuit area arranged on at least one side of the display area, and the display panel comprises:

[0006] a substrate;

[0007] A first active layer is disposed on one side of the substrate. The first active layer includes a first active pattern disposed in the display area and a second active pattern disposed in the gate driving circuit area. The first active pattern includes a first doped portion, and the second active pattern includes a second doped portion.

[0008] A first gate insulating layer is disposed on the side of the first active layer away from the substrate;

[0009] A first metal layer is disposed on the side of the first gate insulating layer away from the first active layer;

[0010] The first active layer is made of an oxide semiconductor, the first gate insulating layer covers the second doped portion, and the first gate insulating layer does not cover the first doped portion.

[0011] In some embodiments, the first active pattern further includes a first channel portion, the first gate insulating layer in the display area covers the first channel portion, and the projection of the first gate insulating layer in the display area onto the substrate is located within the projection range of the first channel portion onto the substrate.

[0012] In some embodiments, the thickness of the first gate insulating layer disposed corresponding to the first channel portion is equal to the thickness of the first gate insulating layer disposed corresponding to the second doped portion.

[0013] In some embodiments, the second active pattern further includes a second channel portion, wherein the first gate insulating layer in the gate drive circuit region covers the second channel portion.

[0014] In some embodiments, the display area is provided with a pixel driving circuit, the pixel driving circuit comprising:

[0015] The first initialization transistor is connected to the first initialization signal line and is used to input the first initialization signal to the first node under the control of the first scan signal.

[0016] A switching transistor is used to input a data signal to the second node under the control of the second scan signal;

[0017] A driving transistor is connected to the first initialization transistor at a first node and to the switching transistor at a second node, for driving the light-emitting device to emit light under the control of the potentials of the first node and the second node;

[0018] A compensation transistor, connected to the driving transistor via the first node and the third node, is used to compensate the threshold voltage of the driving transistor under the control of the third scan signal.

[0019] Wherein, the first gate insulating layer does not cover the doped portion of at least one of the first initialization transistor and the compensation transistor.

[0020] In some embodiments, the gate driving circuit region includes an oxide semiconductor transistor, the first gate insulating layer does not cover the doped portion of the first initialization transistor, the first gate insulating layer does not cover the doped portion of the compensation transistor, the first gate insulating layer covers the doped portion of the oxide semiconductor transistor, and the pattern height of the source and drain of the oxide semiconductor transistor is greater than the pattern height of the source and drain of the first initialization transistor.

[0021] In some embodiments, the material of the first gate insulating layer includes silicon oxide.

[0022] In some embodiments, the display panel further includes a first interlayer insulating layer disposed on the side of the first metal layer away from the first active layer, and the material of the first interlayer insulating layer includes silicon nitride.

[0023] In some embodiments, the thickness of the first gate insulating layer ranges from 20 nanometers to 600 nanometers.

[0024] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0025] Beneficial effects: This application provides a display panel and a display device. The display panel covers the second doped portion with a first gate insulating layer and does not cover the first doped portion. During the formation of the display panel, the first doped portion is more easily etched or bombarded by ions to generate electrons than the second doped portion. The electrons diffuse into the first channel portion, which reduces the effective channel length of the first active pattern. This makes the threshold voltage of the oxide semiconductor transistor in the display area more negative. In addition, hydrogen elements in other film layers easily diffuse into the first doped portion, making the oxide semiconductor transistor in the display area more negative. This causes a difference in the threshold voltage of the oxide semiconductor transistor in the pixel driving circuit and the gate driving circuit, enabling the display panel to display normally. Attached Figure Description

[0026] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0027] Figure 1 A schematic diagram of a conventional display device provided in an embodiment of this application.

[0028] Figure 2 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0029] Figure 3 This is a circuit diagram of the pixel driving circuit provided in an embodiment of this application.

[0030] Figure 4 This is a timing diagram of the pixel driving circuit provided in an embodiment of this application.

[0031] Figure 5 A circuit diagram of the gate drive circuit provided in an embodiment of this application.

[0032] Figure 6 This is a schematic diagram of the display panel corresponding to the three steps in the method for preparing the display panel provided in the embodiments of this application.

[0033] Figure 7 This is a schematic diagram of the display panel corresponding to the other two steps in the method for preparing the display panel provided in the embodiments of this application.

[0034] Figure 8 This is a schematic diagram of the display panel corresponding to two steps in the method for preparing the display panel provided in the embodiments of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0036] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0039] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0040] like Figure 1 As shown, the existing display device includes a display area 141 and a GOA area 142. An LTPO pixel driving circuit is disposed within the display area 141, and a CMOS GOA circuit is disposed within the GOA area 142. Figure 1As shown, the display device includes a substrate 111, a light-shielding metal 112, a first insulating layer 113, a second insulating layer 114, a first semiconductor layer 115, a third insulating layer 116, a first gate layer 117, a fourth insulating layer 118, a second gate layer 119, a fifth insulating layer 120, a second semiconductor layer 121, a sixth insulating layer 122, a third gate layer 123, a seventh insulating layer 124, a first source / drain metal layer 125, an eighth insulating layer 126, a second source / drain metal layer 127, a ninth insulating layer 128, an anode layer 129, a tenth insulating layer 130, and an eleventh insulating layer 131, arranged sequentially. During the fabrication of display devices, the LTPO pixel driving circuit and the CMOS GOA circuit are formed simultaneously. Therefore, the oxide semiconductor transistors (OSTs) in the LTPO pixel driving circuit and the CMOS GOA circuit have the same structure and similar or even identical performance. However, the OSTs in the LTPO pixel driving circuit need to maintain a threshold voltage of around 0 volts to achieve good PBTS (Power Breakdown Time), while the OSTs in the CMOS GOA circuit need to maintain a forward-biased threshold voltage to avoid leakage. Therefore, current display device designs cannot simultaneously meet the requirements of both the OSTs in the LTPO pixel driving circuit and the CMOS GOA circuit, leading to display defects. Thus, existing display devices suffer from a technical problem where the threshold voltages of the OSTs in the LTPO pixel driving circuit and the CMOS GOA circuit cannot be differentiated, resulting in display defects.

[0041] This application provides a display panel and a display device to address the aforementioned technical problems.

[0042] like Figure 2 As shown, this application embodiment provides a display panel 2, which includes a display area 241 and a gate driving circuit area 242 disposed on at least one side of the display area 241. The display panel 2 includes:

[0043] Substrate 211;

[0044] A first active layer 221 is disposed on one side of the substrate 211. The first active layer 221 includes a first active pattern 301 disposed in the display area 241 and a second active pattern 302 disposed in the gate driving circuit area 242. The first active pattern 301 includes a first doped portion 301a and the second active pattern 302 includes a second doped portion 302a.

[0045] A first gate insulating layer 222 is disposed on the side of the first active layer 221 away from the substrate 211;

[0046] The first metal layer 223 is disposed on the side of the first gate insulating layer 222 away from the first active layer 221;

[0047] The first active layer 221 is made of oxide semiconductor, the first gate insulating layer 222 covers the second doped portion 302a, and the first gate insulating layer 222 does not cover the first doped portion 301a.

[0048] This application provides a display panel in which a first gate insulating layer covers a second doped portion, while the first gate insulating layer does not cover the first doped portion. This makes it easier for the first doped portion to be etched or bombarded by ions to generate electrons during the formation of the display panel compared to the second doped portion. The electrons diffuse into the first channel portion, reducing the effective channel length of the first active pattern. This causes the threshold voltage of the oxide semiconductor transistor in the display area to be negative. Furthermore, hydrogen elements in other film layers easily diffuse into the first doped portion, causing the oxide semiconductor transistor in the display area to be negative. This creates a difference in the threshold voltage of the oxide semiconductor transistor in the pixel driving circuit and the gate driving circuit, enabling the display panel to display normally.

[0049] Specifically, a pixel driving circuit can be set in the display area, and a gate driving circuit can be set in the gate driving circuit area.

[0050] Specifically, Figure 2 The example described uses the gate driving circuit area located on one side of the display area. However, the embodiments of this application are not limited to this. The gate driving circuit area can be located on multiple sides of the display panel, such as on both sides of the display panel.

[0051] Specifically, the gate driving circuit in the embodiments of this application can be a CMOS GOA circuit.

[0052] Specifically, it is understood that the "negative bias" mentioned in the embodiments of this application does not specifically refer to negative bias, but rather to the threshold voltage shifting towards a negative potential. The threshold voltage can be positive, 0, or negative. Similarly, the "positive bias" mentioned in the embodiments of this application does not specifically refer to positive bias, but rather to the threshold voltage shifting towards a positive potential. The threshold voltage can be positive, 0, or negative. For example, in existing display devices, the threshold voltage of the oxide semiconductor transistors in the gate driving circuit region and the display region is 0.5 volts. In the embodiments of this application, by differentiating the first gate insulating layer of the display region and the gate driving circuit region, for example, making the threshold voltage of the oxide semiconductor transistor in the display region 0 and the threshold voltage of the oxide semiconductor transistor in the gate driving circuit region 0.5 volts, it can be said that the threshold voltage of the oxide semiconductor transistor in the display region is negative, but it can be seen that the threshold voltage of the oxide semiconductor transistor in the display region is not negative.

[0053] Specifically, since the first gate insulating layer does not cover the first doped portion but covers the second doped portion, the threshold voltage of the oxide semiconductor transistor in the display area is negative, which satisfies the requirement that the oxide semiconductor transistor in the display area has good positive bias temperature stress. The threshold voltage of the oxide semiconductor transistor in the gate driving circuit area is positive, which satisfies the requirement that the oxide semiconductor transistor in the gate driving circuit area can be completely turned off without leakage. Thus, the different requirements of the oxide semiconductor transistors in the display area and the gate driving circuit area are taken into account, so that the display panel can display normally.

[0054] Specifically, the first doped region includes a first source doped region and a first drain doped region, and the second doped region includes a second source doped region and a second drain doped region.

[0055] Specifically, by omitting the first gate insulating layer on the first doped portion, the chemical bonds between the metal and oxygen in the first doped portion are more easily broken during the etching process of the first metal layer, generating electrons. These electrons diffuse into the channel, reducing the effective channel length and making the threshold voltage more negative compared to the threshold voltage of the oxide semiconductor transistor in the gate driving circuit region. Furthermore, without the protection of the first gate insulating layer during the doping process, the first doped portion suffers greater damage from bombardment by doped ions, generating more electrons and making its threshold voltage more negative compared to the threshold voltage of the oxide semiconductor transistor in the gate driving circuit region. Additionally, the diffusion of hydrogen elements from other film layers into the first doped portion further contributes to its more negative threshold voltage compared to the threshold voltage of the oxide semiconductor transistor in the gate driving circuit region. This differentiates the threshold voltages of the oxide semiconductor transistors in the display area and the gate driving circuit region, ensuring normal display on the display panel.

[0056] Specifically, with Figure 2 Taking the display panel shown as an example, it can be seen that the first doped part has no first gate insulating layer, while the second doped part has a first gate insulating layer. During the etching process of the first metal layer 223, the first doped part will be etched by plasma in the dry etching process, which will break the chemical bonds between the metal and oxygen in the first doped part, generating electrons. These electrons can easily diffuse into the channel, reducing the effective channel length and making the threshold voltage more negative. In addition, during the doping process, the first doped part in the display area is directly bombarded by doped ions. Compared with the second doped part in the gate driving circuit area, which is protected by the first gate insulating layer, it suffers greater damage, generates more electrons, and has a more negative threshold voltage. Furthermore, hydrogen in the first interlayer insulating layer 224 will diffuse into the doped part of the oxide semiconductor transistor. Since the first doped part in the display area is not shielded by the first gate insulating layer, it is more affected by hydrogen, making the threshold voltage more negative. This makes the oxide semiconductor transistor in the display area more negative than the oxide semiconductor transistor in the gate driving circuit area.

[0057] In some embodiments, such as Figure 2 As shown, the first active pattern 301 further includes a first channel portion 301b. The first gate insulating layer 222 in the display area 241 covers the first channel portion 301b, and the projection of the first gate insulating layer 222 on the substrate 211 of the display area 241 is located within the projection range of the first channel portion 301b on the substrate 211. By having the first gate insulating layer cover the first channel portion in the display area, thus protecting the first channel portion, and ensuring that the projection of the first gate insulating layer on the substrate is within the projection range of the first channel portion on the substrate, the first gate insulating layer in the display area, except for the first channel portion, can be removed. This allows other insulating layers to be disposed on the side and top surfaces of the first doped portion, thereby allowing hydrogen to diffuse into the first doped portion and further making the threshold voltage in the display area negative.

[0058] In some embodiments, such as Figure 2 As shown, the thickness of the first gate insulating layer 222 corresponding to the first channel portion 301b is equal to the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a. By making the thickness of the portion of the first gate insulating layer corresponding to the first channel portion equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion, when etching the first gate insulating layer, only one process is needed to remove the portion of the first gate insulating layer outside the first channel portion in the display area, making the process simpler. Furthermore, the threshold voltage of the oxide semiconductor transistor in the gate driving circuit area can be positively biased, thereby differentiating the threshold voltage of the oxide semiconductor transistor in the gate driving circuit area and the display area, allowing the display panel to display normally.

[0059] In some embodiments, such as Figure 2 As shown, the second active pattern 302 also includes a second channel portion 302b, and the first gate insulating layer 222 in the gate drive circuit region 242 covers the second channel portion 302b. By covering the second channel portion with the first gate insulating layer, the second channel portion can be protected.

[0060] In some embodiments, such as Figure 2As shown, the second active pattern 302 also includes a second channel portion 302b. The thickness of the first gate insulating layer 222 corresponding to the second channel portion 302b is equal to the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a. By making the thickness of the portion of the first gate insulating layer corresponding to the second channel portion equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion, the first gate insulating layer can protect the second doped portion and the second channel portion. Compared to the oxide semiconductor transistor in the display area, the threshold voltage of the oxide semiconductor transistor in the gate driving circuit area can be positively biased, thereby preventing leakage current from occurring in the oxide semiconductor transistor in the gate driving circuit area.

[0061] In some embodiments, such as Figure 2 As shown, within the gate drive circuit region 242, the projection of the first gate insulating layer 222 onto the substrate 211 coincides with the substrate. By aligning the projection of the first gate insulating layer onto the substrate within the gate drive circuit region with the substrate, the portion of the first gate insulating layer located in the gate drive circuit region protects the second doped portion and the second channel portion, thereby positively biasing the threshold voltage of the oxide semiconductor transistor in the gate drive circuit region and preventing leakage current from occurring in the oxide semiconductor transistor in the gate drive circuit region.

[0062] In some embodiments, such as Figure 2 , Figure 3 As shown, the display area 241 is provided with a pixel driving circuit 31, which includes:

[0063] The first initialization transistor T24 is connected to the first initialization signal line VI-G and is used to input the first initialization signal to the first node Q under the control of the first scan signal.

[0064] Switching transistor T22 is used to input data signals to the second node A under the control of the second scan signal;

[0065] The driving transistor T21 is connected to the first initialization transistor T24 at the first node Q and to the switching transistor T22 at the second node A, and is used to drive the light-emitting device LED to emit light under the control of the potentials of the first node Q and the second node A.

[0066] The compensation transistor T23 is connected to the driving transistor T21 through the first node Q and the third node B, and is used to compensate the threshold voltage of the driving transistor T21 under the control of the third scan signal.

[0067] In this configuration, the first gate insulating layer 222 does not cover the doped portion of at least one of the first initialization transistor T24 and the compensation transistor T23. By ensuring that the first gate insulating layer does not cover the doped portion of at least one of the first initialization transistor and the compensation transistor, the threshold voltage of at least one of the first initialization transistor and the compensation transistor can be adjusted, resulting in at least one of the initialization transistor and the compensation transistor having better PBTS, thereby improving the performance of the display panel.

[0068] Specifically, when the first gate insulating layer does not cover the first initialization transistor, it means that the active pattern of the first initialization transistor is the same as the design of the first active pattern. Similarly, when the first gate insulating layer does not cover the compensation transistor, it means that the active pattern of the compensation transistor is the same as the design of the first active pattern; that is, the first active pattern 301 includes the active pattern of at least one of the first initialization transistor T24 and the compensation transistor T23.

[0069] Specifically, in the embodiments of this application, when differentiating the threshold voltages of the oxide semiconductor transistors in the display area and the oxide semiconductor transistors in the gate driving circuit area, the threshold voltages of one oxide semiconductor transistor in the display area may differ from those of the oxide semiconductor transistors in the gate driving circuit area, or the threshold voltages of a class of oxide semiconductor transistors (e.g., all compensation transistors) in the display area may differ from those of the oxide semiconductor transistors in the gate driving circuit area, or the threshold voltages of all oxide semiconductor transistors in the display area may differ from those of the oxide semiconductor transistors in the gate driving circuit area.

[0070] Specifically, Figure 3 The example described uses a single-gate transistor as the first initialization transistor T24 and the compensation transistor T23, but the embodiments of this application are not limited to this. The first initialization transistor T24 and the compensation transistor T23 can be dual-gate transistors.

[0071] In some embodiments, the thickness of the first gate insulating layer 222 corresponding to the doped portion of one of the first initialization transistor T24 and the compensation transistor T23 is less than the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a; the thickness of the first gate insulating layer 222 corresponding to the doped portion of the other of the first initialization transistor T24 and the compensation transistor T23 is equal to the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a. When setting the first gate insulating layer, by adjusting the threshold voltage of one of the first initialization transistor and the compensation transistor, one of the first initialization transistor and the compensation transistor can have a better PBTS, thereby improving the performance of the display panel.

[0072] In some embodiments, the thickness of the first gate insulating layer 222, which is disposed corresponding to the doped portion of the first initialization transistor T24, is equal to the thickness of the first gate insulating layer 222 disposed corresponding to the doped portion of the compensation transistor T23. By making the thickness of the portion of the first gate insulating layer disposed corresponding to the doped portion of the first initialization transistor equal to the thickness of the portion of the first gate insulating layer disposed corresponding to the doped portion of the compensation transistor, the threshold voltages of both the first initialization transistor and the compensation transistor can be made negative, thereby enabling both the first initialization transistor and the compensation transistor to have better PBTS and improving the performance of the display panel.

[0073] Specifically, such as Figure 3 As shown, the pixel driving circuit 31 also includes a first light-emitting transistor T25, a second light-emitting transistor T26, and a second initialization transistor T27;

[0074] The first light-emitting transistor T25 and the driving transistor T21 are connected to the second node A, and are used to conduct the current from the first power supply signal line VDD to the driving transistor T21 under the control of the light-emitting control signal.

[0075] The second light-emitting transistor T26 is connected to the driving transistor T21 at the third node B, and is used to conduct the current flowing from the driving transistor T21 to the light-emitting device LED under the control of the light-emitting control signal.

[0076] One electrode of the second initialization transistor T27 is connected to the light-emitting device LED at the fourth node C, and the other electrode of the second initialization transistor T27 is connected to the second initialization signal line VI-ANO. The second initialization transistor T27 is used to input a second initialization signal to the anode of the light-emitting device LED under the control of the fourth scan signal.

[0077] Specifically, the driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor, and the second initialization transistor are low-temperature polycrystalline silicon semiconductor transistors, while the compensation transistor and the first initialization transistor are oxide semiconductor transistors, specifically metal oxide semiconductor transistors.

[0078] Specifically, the driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor, and the second initialization transistor are P-type transistors, while the first initialization transistor and the compensation transistor are N-type transistors.

[0079] Specifically, it can be understood that the first scan signal line Nscan(n-5) emits the first scan signal, the second scan signal line Pscan(n) emits the second scan signal, the third scan signal line Nscan(n) emits the third scan signal, the fourth scan signal line Pscan(n-1) emits the fourth scan signal, the first initialization signal line emits the first initialization signal, the second initialization signal line emits the second initialization signal, the data line emits the data signal, and the light emission control signal line emits the light emission control signal.

[0080] In some embodiments, such as Figure 3 As shown, the pixel driving circuit 31 also includes a storage capacitor Cst. One plate of the storage capacitor Cst is connected to the first power signal line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T21.

[0081] In some embodiments, the pixel driving circuit may further include a boost capacitor, one plate of which is connected to the first scan signal line, and the other plate of which is connected to the gate of the driving transistor.

[0082] Specifically, with Figure 3 Taking the pixel driving circuit shown as an example, the working principle of the pixel driving circuit is explained as follows: Figure 4 As shown, in the first stage S1, the first scan signal line Nscan(n-5) outputs a high potential, the first initialization transistor T24 is turned on, and the first initialization signal line VI-G outputs a first initialization signal to reset the first node Q. In the second stage S2, the second scan signal line Pscan(n) inputs a low potential, the third scan signal line Nscan(n) inputs a high potential, the switching transistor T22 and the compensation transistor T23 are turned on, the data line Data outputs a data signal to the first node Q, and at the same time, the fourth scan signal line Pscan(n-1) inputs a low potential, the second initialization transistor T27 is turned on, and the second initialization signal line VI-ANO outputs a second initialization signal to reset the fourth node C. In the third stage, the light emission control signal line EM outputs a low potential, the first light emission transistor T25 and the second light emission transistor T26 are turned on, and the first power supply signal line VDD writes a signal to the second node A, the third node B, and the fourth node C, causing the light-emitting device LED to emit light.

[0083] In some embodiments, such as Figures 2 to 5As shown, the gate driving circuit region 242 is provided with an oxide semiconductor transistor (e.g., a first-stage transistor T13). The first gate insulating layer 222 does not cover the doped portion of the first initialization transistor T24, nor does it cover the doped portion of the compensation transistor T23. The first gate insulating layer 222 covers the doped portion of the oxide semiconductor transistor (e.g., the first-stage transistor T13), and the pattern height H1 of the source and drain of the oxide semiconductor transistor is greater than the pattern height H2 of the source and drain of the first initialization transistor T24. By making the first gate insulating layer not cover the doped portions of the first initialization transistor and the compensation transistor, and instead covering the doped portion of the oxide semiconductor transistor in the gate driving circuit region, the height difference between the source and drain of the first initialization transistor and the doped portion of the first initialization transistor is less than the height difference between the source and drain of the oxide semiconductor transistor in the gate driving circuit region and the doped portion of the oxide semiconductor transistor, thus making the pattern height of the source and drain of the oxide semiconductor transistor greater than the pattern height of the source and drain of the first initialization transistor.

[0084] Specifically, it can be understood that when the first gate insulating layer does not cover the doped portions of the compensation transistor and the first initialization transistor, the pattern heights of the source and drain of the first initialization transistor are the same as the pattern heights of the source and drain of the compensation transistor. When the first gate insulating layer covers one of the doped portions of the compensation transistor and the first initialization transistor, and the first gate insulating layer does not cover the other of the doped portions of the compensation transistor and the first initialization transistor, the pattern heights of the source and drain of the transistor covered by the first gate insulating layer are greater than the pattern heights of the source and drain of the transistor not covered by the first gate insulating layer. Similarly, for the pattern heights of the source and drain of transistors in other gate driving circuits and pixel driving circuits, please refer to the above explanation.

[0085] In some embodiments, the material of the first gate insulating layer includes silicon oxide. By including silicon oxide in the material of the first gate insulating layer, the first gate insulating layer can protect the second doped portion and prevent hydrogen diffusion into the second doped portion from causing performance changes in the oxide semiconductor transistor.

[0086] In some embodiments, such as Figure 2 As shown, the display panel 2 further includes a first interlayer insulating layer 224, which is disposed on the side of the first metal layer 223 away from the first active layer 221. The material of the first interlayer insulating layer 224 includes silicon nitride. By making the material of the first interlayer insulating layer silicon nitride, hydrogen elements in the first interlayer insulating layer can diffuse into the first doped portion, making the threshold voltage of the oxide semiconductor transistor in the display area more negatively biased.

[0087] In some embodiments, the thickness H3 of the first gate insulating layer is in the range of 20 nanometers to 600 nanometers, so that the first gate insulating layer can protect the portion of the first active layer covered by it, and the thickness of the first gate insulating layer is not too large, which would cause the display panel to be too thick.

[0088] In some embodiments, such as Figure 2 , Figure 5 As shown, the gate drive circuit region 242 is provided with a gate drive circuit 32, which includes:

[0089] The stage transmission signal selection module 321 includes a first stage transmission transistor T13 and a second stage transmission transistor T12. The gates of the first stage transmission transistor T13 and the second stage transmission transistor T12 are connected to the stage transmission signal line STV. The first electrode of the first stage transmission transistor T13 is connected to the first low-potential signal line PVGL. The second electrodes of the first stage transmission transistor T13 and the second electrodes of the second stage transmission transistor T12 are connected to the fifth node O. The first electrode of the second stage transmission transistor T12 is connected to the first high-potential signal line PVGH.

[0090] The pull-up control module 322 includes a pull-up transistor T2, the gate of which is connected to the second clock signal line XCK, the first electrode of which is connected to the fifth node O, and the second electrode of which is connected to the sixth node K.

[0091] The first filtering module 323 includes a first filtering transistor T11 and a second storage capacitor C2. The gate of the first filtering transistor T11 is connected to a reset signal line RST on one plate of the second storage capacitor C2. The first electrode of the first filtering transistor T11 is connected to the sixth node K, and the second electrode of the first filtering transistor T11 is connected to the seventh node W on the other plate of the second storage capacitor C2.

[0092] The second filtering module 324 includes a second filtering transistor T8. The gate of the second filtering transistor T8 is connected to the first output terminal Nout[n-2] of the gate driving circuit of the two stages above. The first electrode of the second filtering transistor T8 is connected to the seventh node W, and the second electrode of the second filtering transistor is connected to the eighth node U.

[0093] The first inverting module 325 includes a first inverting transistor T3 and a second inverting transistor T1. The gates of the first inverting transistor T3 and the second inverting transistor T1 are connected to the sixth node K. The first electrode of the first inverting transistor T3 is connected to the first high-potential signal line PVGH. The second electrodes of the first inverting transistor T3 and the second electrodes of the second inverting transistor T1 are connected to the internal node P. The first electrode of the second inverting transistor T1 is connected to the first low-potential signal line PVGL.

[0094] Feedback module 326 includes a first feedback transistor T4 and a second feedback transistor T5. The gate of the first feedback transistor T4 is connected to the first clock signal line CK. The first electrode of the first feedback transistor T4 is connected to the sixth node K. The second electrode of the first feedback transistor T4 is connected to the second electrode of the second feedback transistor T5. The gate of the second feedback transistor T5 is connected to the internal node P. The first electrode of the second feedback transistor T5 is connected to the first high-potential signal line PVGH.

[0095] The voltage regulation module 327 includes a regulating transistor T14, the gate of the regulating transistor T14 is connected to the internal node P, the first electrode of the regulating transistor T14 is connected to the second low-potential signal line NVGL, and the second electrode of the regulating transistor T14 is connected to the sixth node K.

[0096] The first output module 328 includes a first output transistor T10 and a second output transistor T9. The gates of the first output transistor T10 and the second output transistor T9 are connected to the sixth node K. The first electrode of the first output transistor T10 is connected to the second low-potential signal line NVGL. The second electrodes of the first output transistor T10 and the second electrodes of the second output transistor T9 are connected to the first output terminal Nout[n]. The second electrode of the second output transistor is connected to the second high-potential signal line NVGH.

[0097] The second output module 329 includes a third output transistor T6 and a fourth output transistor T7. The gate of the third output transistor T6 is connected to the eighth node U. The first electrode of the third output transistor T6 is connected to the first clock signal line CK. The second electrode of the third output transistor T6 and the second electrode of the fourth output transistor T7 are connected to the second output terminal Pout[n]. The gate of the fourth output transistor T7 is connected to the internal node P. The first electrode of the fourth output transistor T7 is connected to the first high potential signal line PVGH.

[0098] Specifically, the gate drive circuit 32 also includes a first storage capacitor C1, one plate of the first storage capacitor C1 is connected to the eighth node U, and the other plate of the first storage capacitor C1 is connected to the second output terminal Pout[n].

[0099] Specifically, it can be understood that the first output terminal Nout[n] is connected to the third scan signal line Nscan(n), and the second output terminal Pout[n] is connected to the second scan signal line Pscan(n).

[0100] Specifically, the first-stage transfer transistor T13, the second inverting transistor T1, the first output transistor T10, and the regulating transistor T14 are oxide semiconductor transistors, while the second-stage transfer transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are low-temperature polycrystalline silicon semiconductor transistors.

[0101] Specifically, the first-stage transfer transistor T13, the second inverting transistor T1, the first output transistor T10, and the regulating transistor T14 are N-type transistors, while the second-stage transfer transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.

[0102] Specifically, the first-stage transmission transistor T13, the second inverting transistor T1, the first output transistor T10, and the regulating transistor T14 are dual-gate transistors.

[0103] In some embodiments, such as Figure 2 As shown, the display panel 2 also includes a light-shielding layer 212, a barrier layer 213, a buffer layer 214, a second active layer 215, a second gate insulating layer 216, a second metal layer 217, a third gate insulating layer 218, a third metal layer 219, a second interlayer insulating layer 220, a first interlayer insulating layer 224, a first source-drain layer 225, a first planarization layer 226, a second source-drain layer 227, a second planarization layer 228, a pixel electrode layer 229, a pixel definition layer 230, a light-emitting material layer, a common electrode layer, and a support pillar 231.

[0104] In some embodiments, the first electrode of the transistor in the above embodiments is the source and the second electrode is the drain; or the first electrode of the transistor in the above embodiments is the drain and the second electrode is the source.

[0105] In some embodiments, the material of the first active layer includes a metal oxide, and the material of the second active layer includes low-temperature polycrystalline silicon.

[0106] Specifically, the above embodiments have provided a detailed description of the structure of each film layer and transistor of the display panel, as well as the connection relationship between each film layer and transistor. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the thickness of the portion of the first gate insulating layer corresponding to the first channel portion is equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion, and the second active pattern also includes a second channel portion, and the thickness of the portion of the first gate insulating layer corresponding to the second channel portion is equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion.

[0107] Meanwhile, this application embodiment provides a method for manufacturing a display panel, the method comprising:

[0108] A substrate is provided, and a light-shielding layer, a barrier layer, a buffer layer, a second active layer, a second gate insulating layer, a second metal layer, a third gate insulating layer, a third metal layer, a second interlayer insulating layer, a first active layer, a first gate insulating layer, and a first metal layer are sequentially formed on the substrate; the structure of the display panel corresponding to this step is as follows. Figure 6 As shown in (a) in the middle;

[0109] Specifically, the substrate 211 may include multiple layers of flexible and inorganic layers that are stacked together. The flexible layers may be polyimide and the inorganic layers may be at least one of silicon nitride and silicon oxide.

[0110] Specifically, after providing the substrate 211, a metal layer can be formed on the substrate 211, and the metal layer can be etched to form a light-shielding layer 212. The material of the light-shielding layer 212 includes aluminum, titanium, molybdenum, copper, nickel, or their alloys or stacks.

[0111] Specifically, after the light-shielding layer is formed, a barrier layer 213 and a buffer layer 214 can be formed on the light-shielding layer. The material of the barrier layer 213 includes at least one of silicon nitride and silicon oxide, and the material of the buffer layer 214 includes at least one of silicon nitride and silicon oxide.

[0112] Specifically, after forming the buffer layer, a second active layer 215 can be formed on the buffer layer 214, and a pattern can be etched on the second active layer 215. The material of the second active layer includes silicon semiconductor, specifically low-temperature polycrystalline silicon.

[0113] Specifically, after forming the second active layer 215, a second gate insulating layer 216 can be formed on the second active layer 215. The material of the second gate insulating layer 216 includes at least one of silicon nitride and silicon oxide.

[0114] Specifically, after forming the second gate insulating layer 216, a second metal layer 217 can be formed on the second gate insulating layer 216, and a pattern can be etched on the second metal layer 217. The material of the second metal layer 217 includes aluminum, titanium, molybdenum, copper, nickel, or their alloys or stacks.

[0115] Specifically, after forming the second metal layer 217, a third gate insulating layer 218 can be formed, and the material of the third gate insulating layer 218 includes at least one of silicon nitride and silicon oxide.

[0116] Specifically, after forming the third gate insulating layer 218, a third metal layer 219 can be formed, and a pattern can be etched onto the third metal layer 219. The material of the third metal layer 219 includes aluminum, titanium, molybdenum, copper, nickel, or their alloys or stacks.

[0117] Specifically, after the third metal layer 219 is formed, a second interlayer insulating layer 220 can be formed, and the material of the second interlayer insulating layer 220 includes at least one of silicon nitride and silicon oxide.

[0118] Specifically, after the second interlayer insulating layer 220 is formed, a first active layer 221 can be formed, and a pattern can be etched onto the first active layer 221.

[0119] Specifically, after the first active layer 221 is formed, a first gate insulating layer 222 and a first metal layer 223 can be formed.

[0120] A photoresist 41 is formed on the first metal layer, and the photoresist is etched for the first time; the structure of the display panel corresponding to this step is as follows. Figure 6 As shown in (b);

[0121] Specifically, photoresist can be formed on the entire surface of the first metal layer, and then the photoresist can be etched through a semi-transparent photomask, so that the thickness of different areas of the photoresist is different, and some of the photoresist is completely etched away.

[0122] The first metal layer and the first gate insulating layer are etched; the structure of the display panel corresponding to this step is as follows: Figure 6 As shown in (c);

[0123] Specifically, it can be seen that portions of the first metal layer and the first gate insulating layer not covered by the photoresist are etched away, while the portions of the first metal layer and the first gate insulating layer covered by the photoresist are retained.

[0124] A second etching is performed on the photoresist; the corresponding structure of the display panel for this step is as follows: Figure 7 As shown in (a) in the middle;

[0125] Specifically, by etching the photoresist, the photoresist in the thinner areas is etched away, while the photoresist in the thicker areas is retained. Figure 7 As can be seen in (a), some of the photoresist was etched away, while some of the photoresist remained.

[0126] The first metal layer is etched; the structure of the display panel corresponding to this step is as follows: Figure 7 As shown in (b);

[0127] Specifically, the first metal layer in the area not covered by photoresist is etched, while the first metal layer in the area covered by photoresist is retained.

[0128] Remove photoresist; the corresponding display panel structure for this step is as follows: Figure 8 As shown in (a) in the middle;

[0129] A first interlayer insulating layer is formed on the first metal layer, and vias are formed by etching each insulating layer; the structure of the display panel corresponding to this step is as follows. Figure 8 As shown in (b);

[0130] Specifically, vias of different depths can be formed by two etching processes. For example, the first etching can form a via that penetrates to the first active layer, and the second etching can form a via that penetrates to the second active layer.

[0131] A first source / drain layer, a first planarization layer, a second source / drain layer, a second planarization layer, a pixel electrode layer, a pixel definition layer, and support pillars are formed on the first interlayer insulating layer; the structure of the display panel corresponding to this step is as follows. Figure 2 As shown.

[0132] Specifically, a first source / drain layer 225 can be formed on the first interlayer insulating layer, and the first source / drain layer 225 can be etched to form a pattern. The material of the first source / drain layer 225 includes aluminum, titanium, molybdenum, copper, nickel, or their alloys or stacks.

[0133] Specifically, after the first source / drain layer 225 is formed, a first planarization layer 226 can be formed, and the material of the first planarization layer 226 includes organic materials.

[0134] Specifically, after the first planarization layer 226 is formed, a second source / drain layer 227 can be formed, and a pattern can be etched onto the second source / drain layer 227. The material of the second source / drain layer 227 includes aluminum, titanium, molybdenum, copper, nickel, or their alloys or stacks.

[0135] Specifically, after forming the second source / drain layer 227, a second planarization layer 228 can be formed, and the material of the second planarization layer 228 includes organic materials.

[0136] Specifically, after forming the second planarization layer 228, a pixel electrode layer 229 can be formed, and the material of the pixel electrode layer 229 includes a stack of indium tin oxide and silver.

[0137] Specifically, after forming the pixel electrode layer 229, a pixel definition layer 230 can be formed on the pixel electrode layer 229, and vias can be formed by etching the pixel definition layer 230. The material of the pixel definition layer includes polyimide.

[0138] Specifically, after the pixel definition layer 230 is formed, support pillars 231 can be formed on the pixel definition layer 230.

[0139] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0140] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0141] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a gate driving circuit area disposed on at least one side of the display area. Substrate; A first active layer is disposed on one side of the substrate. The first active layer includes a first active pattern disposed in the display area and a second active pattern disposed in the gate driving circuit area. The first active pattern includes a first doped portion, and the second active pattern includes a second doped portion. A first gate insulating layer is disposed on the side of the first active layer away from the substrate; A first metal layer is disposed on the side of the first gate insulating layer away from the first active layer; The first active layer is made of an oxide semiconductor, the first gate insulating layer covers the second doped portion, and the first gate insulating layer does not cover the first doped portion.

2. The display panel as described in claim 1, characterized in that, The first active pattern further includes a first channel portion, wherein the first gate insulating layer in the display area covers the first channel portion, and the projection of the first gate insulating layer in the display area onto the substrate is located within the projection range of the first channel portion onto the substrate.

3. The display panel as described in claim 2, characterized in that, The thickness of the first gate insulating layer disposed corresponding to the first channel portion is equal to the thickness of the first gate insulating layer disposed corresponding to the second doped portion.

4. The display panel as described in claim 1, characterized in that, The second active pattern also includes a second channel portion, wherein the first gate insulating layer in the gate drive circuit region covers the second channel portion.

5. The display panel as described in claim 1, characterized in that, The display area is provided with a pixel driving circuit, which includes: The first initialization transistor is connected to the first initialization signal line and is used to input the first initialization signal to the first node under the control of the first scan signal. A switching transistor is used to input a data signal to the second node under the control of the second scan signal; A driving transistor is connected to the first initialization transistor at a first node and to the switching transistor at a second node, for driving the light-emitting device to emit light under the control of the potentials of the first node and the second node; A compensation transistor, connected to the driving transistor via the first node and the third node, is used to compensate the threshold voltage of the driving transistor under the control of the third scan signal. Wherein, the first gate insulating layer does not cover the doped portion of at least one of the first initialization transistor and the compensation transistor.

6. The display panel as described in claim 5, characterized in that, The gate driving circuit region is provided with an oxide semiconductor transistor. The first gate insulating layer does not cover the doped portion of the first initialization transistor, the first gate insulating layer does not cover the doped portion of the compensation transistor, the first gate insulating layer covers the doped portion of the oxide semiconductor transistor, and the pattern height of the source and drain of the oxide semiconductor transistor is greater than the pattern height of the source and drain of the first initialization transistor.

7. The display panel as described in claim 1, characterized in that, The material of the first gate insulating layer includes silicon oxide.

8. The display panel as described in claim 1, characterized in that, The display panel further includes a first interlayer insulating layer, which is disposed on the side of the first metal layer away from the first active layer, and the material of the first interlayer insulating layer includes silicon nitride.

9. The display panel as claimed in claim 1, characterized in that, The thickness of the first gate insulating layer ranges from 20 nanometers to 600 nanometers.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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