Display device

Abstract

The invention relates to a display device. The display device includes a pixel electrode and a common electrode disposed on a substrate. The organic layer is disposed on the pixel electrode and the common electrode. The light emitting element is disposed on the organic layer and includes a semiconductor stack and first and second contact electrodes. The first connection electrode connects the first contact electrode and the pixel electrode. The second connection electrode connects the second contact electrode and the common electrode. The first side electrode and the second side electrode are disposed on one side of the light emitting element and a top surface of the connection electrode. The first slope inclined layer and the second slope inclined layer are disposed on a side surface of the side electrode. The side electrode has a downward recessed structure between the side surface of the light emitting element and the slope inclined layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0067821, filed on May 24, 2024 with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to display devices having side electrodes on light-emitting elements and methods for manufacturing the display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays.

[0005] Light-emitting display devices can include organic light-emitting diode (OLED) display devices that use organic light-emitting diode (OLED) elements as light-emitting elements, and micro light-emitting display devices that use micro light-emitting diode (MILED) elements as light-emitting elements. Because micro light-emitting diode elements are made of inorganic materials, they can experience less degradation and have a longer lifespan compared to OLED elements. Summary of the Invention

[0006] The display device includes: a substrate; pixel electrodes and a common electrode disposed on the substrate; an organic layer disposed on the pixel electrodes and the common electrode; a light-emitting element disposed on the organic layer and including a semiconductor stack, a first contact electrode, and a second contact electrode, wherein the first contact electrode and the second contact electrode are disposed on one surface of the semiconductor stack; a first connecting electrode connected to the first contact electrode and the pixel electrode; a second connecting electrode connected to the second contact electrode and the common electrode; a first side electrode disposed on a first side of the light-emitting element and on the top surface of the first connecting electrode; a second side electrode disposed on a second side of the light-emitting element and on the top surface of the second connecting electrode; a first sloped layer disposed on the side surface of the first side electrode; and a second sloped layer disposed on the side surface of the second side electrode. The first side electrode and the second side electrode each have a downwardly recessed structure between the first side of the light-emitting element and the first sloped layer, and between the second side of the light-emitting element and the second sloped layer.

[0007] A method for manufacturing a display device includes transferring a light-emitting element, comprising a first contact electrode and a second contact electrode disposed on one surface of a semiconductor stack, onto a first connection electrode and a second connection electrode of a substrate. In an area where the light-emitting element is not disposed and is exposed, an electrode material layer and an insulating material layer are sequentially formed on the first connection electrode and the second connection electrode. A first sloped layer and a second sloped layer are formed on the side surface of the light-emitting element by etching the insulating material layer. The electrode material layer is etched to form a first side electrode and a second side electrode. The first side electrode and the second side electrode have a structure in which the first side electrode and the second side electrode are recessed downward between the side surface of the light-emitting element and the first sloped layer and the second sloped layer. Attached Figure Description

[0008] These and / or other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a perspective view of a display device according to an embodiment.

[0010] Figure 2 This is a layout diagram of a display device according to an embodiment.

[0011] Figure 3 This is a block diagram of a display device according to an embodiment.

[0012] Figure 4 This is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0013] Figure 5 This is a layout diagram of the pixels of a display area according to one embodiment.

[0014] Figure 6 This is an illustration of a display panel. Figure 5 The cross-sectional view of the example section corresponding to line I1-I1' in the diagram.

[0015] Figure 7 Detailed illustrations Figure 6 A cross-sectional view of an example of zone A in the diagram.

[0016] Figure 8 Detailed illustrations Figure 6 A cross-sectional view of an example of zone A in the diagram.

[0017] Figure 9 and Figure 10 Detailed illustrations Figure 6 A cross-sectional view of an example of zone A in the diagram.

[0018] Figure 11 It is a diagram. Figure 6 Detailed cross-sectional view of an example of zone A in the diagram.

[0019] Figure 12 This is a flowchart illustrating a method for manufacturing a display device according to one embodiment.

[0020] Figures 13 to 17 This is a cross-sectional view illustrating a method of manufacturing a display device according to one embodiment.

[0021] Figures 18 to 20 This is a cross-sectional view illustrating a method of manufacturing a display device according to one embodiment.

[0022] Figure 21 This is a perspective view illustrating a method of manufacturing a display device according to one embodiment.

[0023] Figures 22 to 24 This is a cross-sectional view illustrating a method of manufacturing a display device according to one embodiment.

[0024] Figure 25 This is a perspective view of a smartwatch including a display device according to one embodiment.

[0025] Figure 26 This is a perspective view of a virtual reality device including a display device according to one embodiment.

[0026] Figure 27 This is an exploded view of a virtual reality device including a display device according to one embodiment.

[0027] Figure 28 This is a perspective view of a virtual reality device including a display device according to one embodiment.

[0028] Figure 29 This is a perspective view illustrating a vehicle dashboard and central instrument panel including a display device according to one embodiment.

[0029] Figure 30 This is a perspective view of a transparent display device including a display apparatus according to one embodiment. Detailed Implementation

[0030] Embodiments will be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and are not necessarily to be construed as limiting. Throughout this disclosure and the drawings, the same reference numerals may indicate the same parts. While each drawing to scale may represent one or more specific embodiments of this disclosure such that relative lengths, thicknesses, and angles can be inferred from them, it will be understood that the invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. For example, these values ​​may be modified within the spirit and scope of this disclosure to allow for manufacturing limitations, etc.

[0031] To better describe the embodiments of this disclosure, some parts that are not relevant to the description may be omitted.

[0032] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on that other layer or substrate, or an intermediary layer may be present. In contrast, when an element is referred to as being "directly on" another element, an intermediary element may not be present.

[0033] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section obtained by vertically cutting a portion of the object from the side. The terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, and vice versa. Furthermore, the term "overlapping" can include layered placement, stacking, facing, extending, covering, or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "spaced apart," "separated," or "offset," and any other suitable equivalent that will be understood and appreciated by one of ordinary skill in the art. The term "facing" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as being indirectly opposite each other, although still facing each other.

[0034] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” or “up” are used herein to describe the relationship between one element or component illustrated in the accompanying drawings and another element or component. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. For example, if the device illustrated in the drawings is flipped, a device located “below” or “under” another device may be placed “above” that other device. Therefore, the illustrative term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0035] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “indirectly connected” or “indirectly coupled” to the other element through one or more intermediary elements between the element and the other element. It will be further understood that when the terms “comprising,” “having,” and / or “including” are used, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0036] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used herein to describe various elements, these elements are not necessarily limited to these terms. These terms are used to distinguish one element from another, or for the convenience of describing and explaining one element and another. For example, when “first element” is discussed in the specification, the first element may be referred to as “second element” or “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teachings herein.

[0037] Taking into account the measurements discussed and the errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable deviation of the specific value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0038] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a connected or separate sense and can be understood to be equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0039] In the following description, specific embodiments will be described with reference to the accompanying drawings.

[0040] Figure 1 This is a perspective view of the display device 10 according to an embodiment.

[0041] refer to Figure 1 The display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smartphones, tablet computers, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), as well as in various products such as televisions, laptop computers, computer monitors, digital billboards, and Internet of Things (IoT) devices.

[0042] The display device 10 may be an organic light-emitting diode (OLED) display, such as an organic light-emitting diode (OLED) display, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, or a light-emitting display using micron or nano light-emitting diodes (LEDs). The following description will primarily focus on the case where the display device 10 is a micron or nano light-emitting display, but this disclosure is not necessarily limited thereto. For ease of description, micron LEDs or nano LEDs will be referred to as light-emitting elements.

[0043] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply unit 500.

[0044] The display panel 100 may be shaped similarly to a rectangle having a pair of short sides extending in a first direction DR1 and a pair of long sides extending in a second direction DR2 intersecting the first direction DR1. Each corner where the short sides extending in the first direction DR1 intersect the long sides extending in the second direction DR2 may be rounded to have a predetermined curvature (thus forming a rounded rectangle shape), or may be a right angle (thus forming a regular rectangle). The planar shape of the display panel 100 is not necessarily limited to a quadrilateral shape, but may also be a circular shape, an elliptical shape, or other polygonal shapes. The display panel 100 may be formed flat, but embodiments are not necessarily limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having constant or varying curvatures. Furthermore, the display panel 100 may be formed to be flexible, such that the display panel 100 can be bent, folded, rolled up to a significant extent without cracking or otherwise being damaged.

[0045] The substrate SUB of the display panel 100 may include a main area MA and an auxiliary area SBA.

[0046] The main area MA may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA (e.g., surrounding the display area DA on at least both sides, or only close to one side of the display area DA). The display area DA may include a plurality of pixels for displaying the image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color, but embodiments of this specification are not necessarily limited thereto.

[0047] The secondary region SBA can protrude from one side of the primary region MA on the second direction DR2. Although the secondary region SBA is in Figure 1The sub-area SBA is shown unfolded, but it can also be bent. In this case, the sub-area SBA can be placed on the lower surface of the display panel 100. When the sub-area SBA is bent, it can overlap with the main area MA on a third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 can be disposed in the sub-area SBA.

[0048] The display driving circuit 250 can generate signals and voltages for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit and attached to the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. However, embodiments are not necessarily limited to these. For example, the display driving circuit 250 can also be attached to the circuit board 300 using a chip-on-film (COF) method.

[0049] The circuit board 300 can be attached to the end of the auxiliary area SBA of the display panel 100. Therefore, the circuit board 300 can be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip-on-film.

[0050] The power supply unit 500 can generate multiple panel drive voltages based on the power supply voltage from an external source. The power supply unit 500 can be formed as an integrated circuit and attached to the circuit board 300 using the COF method.

[0051] Figure 2 This is a layout diagram of the display device 10 according to an embodiment. Figure 2 The diagram shows the SBA subregion unfolded without bending.

[0052] refer to Figure 2 The display panel 100 may include a primary area MA and a secondary area SBA.

[0053] The main area MA may include the display area DA for displaying the image and the non-display area NDA surrounding the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be located at the center of the main area MA.

[0054] The display area DA may include multiple pixels PX for displaying images, and each of the pixels PX may include multiple subpixels SPX. Pixel PX may be defined as the smallest group of subpixels that can express any desired color and brightness.

[0055] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be an edge area of ​​the display panel 100.

[0056] The first scan driver SDC1 and the second scan driver SDC2 can be located in the non-display area NDA. The first scan driver SDC1 can be located on one side of the display panel 100 (e.g., the left side), and the second scan driver SDC2 can be located on the other side of the display panel 100 (e.g., the right side). However, the embodiments described in this specification are not necessarily limited to this.

[0057] Each of the first scan driver SDC1 and the second scan driver SDC2 can be electrically connected to the display driver circuit 250 via a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 can receive a scan control signal from the display driver circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0058] The secondary area SBA may protrude from one side of the primary area MA in the second direction DR2. The length of the secondary area SBA in the second direction DR2 may be less than the length of the primary area MA in the second direction DR2. The length of the secondary area SBA in the first direction DR1 may be less than the length of the primary area MA in the first direction DR1, or may be substantially equal to the length of the primary area MA in the first direction DR1. The secondary area SBA may be bent and placed below the display panel 100. In this case, the secondary area SBA may overlap with the primary area MA in the third direction DR3.

[0059] The auxiliary area SBA can include the connection area CA, the pad area PA, and the bend area BA.

[0060] The connecting area CA is a region that protrudes from one side of the main area MA in the second direction DR2. One side of the connecting area CA can contact the non-display area NDA of the main area MA, and the other side of the connecting area CA can contact the curved area BA.

[0061] The pad area PA is the area where the pads PD and the display driver circuit 250 are located. The display driver circuit 250 can be attached to the drive pads of the pad area PA using a conductive adhesive such as an anisotropic conductive film. Circuit board 300 (see...) Figure 1 The pads PD of the pad area PA can be attached using a conductive adhesive such as anisotropic conductive film. One side of the pad area PA can contact the bending area BA.

[0062] The bending region BA is a flexible region. When the bending region BA is bent, the pad region PA can be placed below the connector region CA and the main region MA. The bending region BA can be positioned between the connector region CA and the pad region PA. One side of the bending region BA can contact the connector region CA, and the other side of the bending region BA can contact the pad region PA.

[0063] Figure 3 This is a block diagram of the display device 10 according to an embodiment.

[0064] refer to Figure 3 The display area DA includes multiple sub-pixels SPX, multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL.

[0065] Subpixels (SPX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Scan lines (SL) and emission control lines (EL) can extend on the first direction DR1 and can be arranged on the second direction DR2. Data lines (DL) can extend on the second direction DR2 and can be arranged on the first direction DR1. Scan lines (SL) include multiple write scan lines (GWL), multiple control scan lines (GCL), multiple initialization scan lines (GIL), and multiple bias scan lines (GBL).

[0066] Each sub-pixel SPX can be connected to any of the write scan lines GWL, any of the control scan lines GCL, any of the initialization scan lines GIL, any of the bias scan lines GBL, any of the emitt control lines EL, and any of the data lines DL. Each sub-pixel SPX can receive the data voltage from the data line DL according to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0067] The non-display area NDA includes a first scan driver SDC1, a second scan driver SDC2, and a display driver circuit 250.

[0068] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, an initialization scan signal output unit 612, a bias scan signal output unit 613, and a transmit signal output unit 614. Each of the write scan signal output unit 611, the initialization scan signal output unit 612, the bias scan signal output unit 613, and the transmit signal output unit 614 may receive a scan timing control signal SCS from the timing controller 251.

[0069] The write scan signal output unit 611 can generate a write scan signal according to the scan timing control signal SCS of the timing controller 251, and output the write scan signal sequentially to the write scan line GWL.

[0070] The initialization scan signal output unit 612 can generate an initialization scan signal according to the scan timing control signal SCS, and output the initialization scan signal sequentially to the initialization scan line GIL. The bias scan signal output unit 613 can generate a bias scan signal according to the scan timing control signal SCS, and output the bias scan signal sequentially to the bias scan line GBL. The transmit signal output unit 614 can generate a transmit control signal according to the scan timing control signal SCS, and output the transmit control signal sequentially to the transmit control line EL.

[0071] The display driver circuit 250 includes a timing controller 251 and a data driver 252.

[0072] Data driver 252 can receive digital video data DATA and data timing control signal DCS from timing controller 251. Data driver 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to data line DL. In this case, sub-pixel SPX can be selected by the write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data voltage can be supplied to the selected sub-pixel SPX.

[0073] The timing controller 251 can receive digital video data DATA and timing signals from a permanent source. The timing controller 251 can generate scan timing control signals SCS and data timing control signals DCS for controlling the display panel 100 based on the timing signals. The timing controller 251 can output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing controller 251 can also output the digital video data DATA and data timing control signals DCS to the data driver 252.

[0074] The power supply unit 500 can generate multiple panel driving voltages based on the power supply voltage from an external source. For example, the power supply unit 500 can generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and supply them to the display panel 100.

[0075] Figure 4 This is an equivalent circuit diagram of the sub-pixel SPX according to an embodiment.

[0076] refer to Figure 4 According to an embodiment, the sub-pixel SPX can be connected to scan lines GWL, GIL, GCL, and GBL, emission control line EL, and data line DL. For example, the sub-pixel SPX can be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0077] According to an embodiment, the sub-pixel SPX includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes first to sixth transistors ST1 to ST6.

[0078] The driving transistor DT includes a gate electrode, a conductive layer, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current Ids (hereinafter referred to as the "driving current") flowing between the conductive layer and the second electrode based on the data voltage applied to the gate electrode.

[0079] The light-emitting element (LE) can be a micron-sized LED.

[0080] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE can be proportional to the driving current Ids. The anode of the light-emitting element LE can be connected to the conductive layer of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode can be connected to a second power supply voltage (e.g., ...). Figure 3 The second driving voltage (VSS) is applied to its second power supply line VSL.

[0081] Capacitor C1 is formed at the second electrode of the driving transistor DT and the first power supply voltage (e.g., Figure 3 A first driving voltage (VDD) is applied between the first power supply line (VDL) of the capacitor C1 and the second power supply voltage. The first power supply voltage may be at a higher level than the second power supply voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power supply line VDL.

[0082] like Figure 4 As shown in the diagram, the first to sixth transistors ST1 to ST6 and the driving transistor DT can all be formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layer of each of the first to sixth transistors ST1 to ST6 and the driving transistor DT can be made of polysilicon.

[0083] The gate electrodes of the first transistor ST1 and the second transistor ST2 can be connected to the write scan line GWL, the gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL, the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL, and the gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 can be connected to the emit control line EL. Since the first to sixth transistors ST1 to ST6 are formed as p-type MOSFETs, they can be turned on when the gate-low voltage scan signal and emit control signal are transmitted to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emit control line EL. The first electrode of the third transistor ST3 can be connected to a third power supply voltage (e.g., ...). Figure 3 The first initialization voltage (VINT) is applied to its first initialization voltage line VIL. Similarly, the first electrode of the fourth transistor ST4 can be connected to a fourth power supply voltage (e.g., ...). Figure 3 The second initialization voltage (VAINT) is applied to its second initialization voltage line (VAIL).

[0084] Alternatively, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed as p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be formed as n-type MOSFETs. The active layer of each of the driving transistors DT, ST2, ST4, ST5, and ST6 formed as p-type MOSFETs can be made of polysilicon, and the active layer of each of the first transistor ST1 and ST3 formed as n-type MOSFETs can be made of oxide semiconductor.

[0085] In this configuration, since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can turn on in response to a scan signal with a gate-high voltage, and the third transistor ST3 can turn on in response to a scan signal with a gate-high voltage. On the other hand, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can turn on in response to a scan signal with a gate-low voltage and an emitter control signal.

[0086] Alternatively, the fourth transistor ST4 can be formed as an n-type MOSFET. In this case, the active layer of the fourth transistor ST4 can be made of oxide semiconductor. When the fourth transistor ST4 is formed as an n-type MOSFET, the fourth transistor ST4 can be turned on in response to a scan signal of gate-high voltage.

[0087] Alternatively, the first to sixth transistors ST1 to ST6 and the driving transistor DT can all be formed as n-type MOSFETs. In this case, the active layer of each of the first to sixth transistors ST1 to ST6 and the driving transistor DT can be made of oxide semiconductor.

[0088] Figure 5 This is a layout diagram of the pixels PX of the display area DA according to one embodiment.

[0089] refer to Figure 5 Each of the plurality of pixels PX in the display area DA may include three sub-pixels SPX1, SPX2, and SPX3, but embodiments of this disclosure are not necessarily limited thereto and may include four sub-pixels. When each of the plurality of pixels PX includes three sub-pixels SPX1, SPX2, and SPX3, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may each be able to display a single color.

[0090] Multiple pixels PX can be arranged in a matrix. In each of the multiple pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged in the first direction DR1.

[0091] When each of the multiple pixels PX comprises three sub-pixels SPX1, SPX2, and SPX3, the first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. Here, the first color of light can be light in the blue band, the second color of light can be light in the green band, and the third color of light can be light in the red band. For example, the blue band can refer to light with a dominant peak wavelength in the band from approximately 370 nm to 460 nm, the green band can refer to light with a dominant peak wavelength in the band from approximately 480 nm to 560 nm, and the red band can refer to light with a dominant peak wavelength in the band from approximately 600 nm to 750 nm.

[0092] Alternatively, when each of the multiple pixels PX comprises four sub-pixels, the first sub-pixel may emit light of a first color, the second and fourth sub-pixels may emit light of a second color, and the third sub-pixel may emit light of a third color. Alternatively, the first sub-pixel may emit light of the first color, the second sub-pixel may emit light of the second color, the third sub-pixel may emit light of the third color, and the fourth sub-pixel may emit light of a fourth color. For example, the fourth color may be white light.

[0093] The first sub-pixel SPX1 includes a first pixel electrode PXE1, multiple light-emitting elements LE, a first common electrode CE1, and a first light conversion layer QDL1. The second sub-pixel SPX2 includes a second pixel electrode PXE2, multiple light-emitting elements LE, a second common electrode CE2, and a second light conversion layer QDL2. The third sub-pixel SPX3 includes a third pixel electrode PXE3, multiple light-emitting elements LE, a third common electrode CE3, and a light-transmitting layer TPL.

[0094] In each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, pixel electrodes PXE1, PXE2, and PXE3, as well as common electrodes CE1, CE2, and CE3, can be arranged on the second direction DR2. Each of the pixel electrodes PXE1, PXE2, and PXE3, as well as the common electrodes CE1, CE2, and CE3, can have a rectangular planar shape, but the embodiments of this disclosure are not necessarily limited thereto. The area of ​​the first pixel electrode PXE1 can be the same as the area of ​​the first common electrode CE1, the area of ​​the second pixel electrode PXE2 can be the same as the area of ​​the second common electrode CE2, and the area of ​​the third pixel electrode PXE3 can be the same as the area of ​​the third common electrode CE3, but the embodiments of this disclosure are not necessarily limited thereto.

[0095] For example, such as Figure 5 As shown, when the light conversion efficiency of the second light conversion layer QDL2 is lower than that of the first light conversion layer QDL1, the area of ​​the second pixel electrode PXE2 can be larger than the area of ​​the first pixel electrode PXE1, and the area of ​​the second common electrode CE2 can be larger than the area of ​​the first common electrode CE1. Furthermore, although the light-transmitting layer TPL transmits light from the light-emitting element LE as is, the first light conversion layer QDL1 needs to convert the light. Therefore, the area of ​​the first pixel electrode PXE1 can be larger than the area of ​​the third pixel electrode PXE3, and the area of ​​the first common electrode CE1 can be larger than the area of ​​the third common electrode CE3.

[0096] Each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to at least one transistor via a corresponding pixel connection hole in pixel connection holes CT1, CT2, and CT3. For example, each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to a fourth transistor of the corresponding sub-pixel. Figure 4 The conductive layer of ST4 and the sixth transistor (in the middle) Figure 4 The second electrode of ST6 in the middle.

[0097] The first common electrode CE1 can be connected to the second power line VSL to which the second driving voltage VSS is applied via the first common connection hole CT4. The second common electrode CE2 can be connected to the second power line VSL via the second common connection hole CT5. The third common electrode CE3 can be connected to the second power line VSL via the third common connection hole CT6. Therefore, the second driving voltage VSS can be applied to each of the common electrodes CE1, CE2, and CE3. Pixel electrodes PXE1, PXE2, and PXE3 can be referred to as anode electrodes or first electrodes, and common electrodes CE1, CE2, and CE3 can be referred to as cathode electrodes or second electrodes.

[0098] Multiple light-emitting elements (LEs) can be disposed on pixel electrodes PXE1, PXE2, and PXE3 and common electrodes CE1, CE2, and CE3. Each of the multiple light-emitting elements (LEs) can have a circular planar shape, but the embodiments of this disclosure are not necessarily limited to this. For example, each of the multiple light-emitting elements (LEs) can have a rectangular planar shape.

[0099] The first light conversion layer QDL1 can completely overlap with the first pixel electrode PXE1 and multiple light-emitting elements LE of the first sub-pixel SPX1. The area of ​​the first light conversion layer QDL1 can be larger than the sum of the areas of the first pixel electrode PXE1 and the first common electrode CE1. The first light conversion layer QDL1 can convert or shift the peak wavelength of the incident light to another specific peak wavelength and emit that light. For example, the first light conversion layer QDL1 can convert or shift the third light emitted from the multiple light-emitting elements LE of the first sub-pixel SPX1 into the first light.

[0100] The second light conversion layer QDL2 can completely overlap with the second pixel electrode PXE2 and multiple light-emitting elements LE of the second sub-pixel SPX2. The area of ​​the second light conversion layer QDL2 can be larger than the sum of the areas of the second pixel electrode PXE2 and the second common electrode CE2. The second light conversion layer QDL2 can convert or shift the peak wavelength of the incident light to another specific peak wavelength and emit that light. For example, the second light conversion layer QDL2 can convert or shift the third light emitted from the multiple light-emitting elements LE of the second sub-pixel SPX2 into a second light.

[0101] The light-transmitting layer TPL can completely overlap with the third pixel electrode PXE3 and multiple light-emitting elements LE of the third sub-pixel SPX3. The area of ​​the light-transmitting layer TPL can be larger than the sum of the areas of the third pixel electrode PXE3 and the third common electrode CE3. For example, the light-transmitting layer TPL can directly transmit third light emitted from the multiple light-emitting elements LE of the third sub-pixel SPX3.

[0102] When the light-emitting element LE of the first sub-pixel SPX1 emits light of the first color, the light-emitting element LE of the second sub-pixel SPX2 emits light of the second color, and the light-emitting element LE of the third sub-pixel SPX3 emits light of the third color, the light conversion layers QDL1 and QDL2 and the light-transmitting layer TPL can be omitted.

[0103] Figure 6 This is an illustration of a display panel. Figure 5 The cross-sectional view of the example section corresponding to line I1-I1' in the diagram. Figure 7 Detailed illustrations Figure 6 A cross-sectional view of an example of zone A in the diagram.

[0104] refer to Figure 6 and Figure 7 The substrate SUB can be made of an insulating material such as glass or polymer resin. If the substrate SUB is made of polymer resin, it can be a flexible substrate that can be stretched. The polymer resin can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0105] The barrier film (BR) can be disposed on the substrate (SUB). The barrier film (BR) is a film that protects the transistors of the thin-film transistor layer (TFTL) from moisture that permeates through the moisture-sensitive substrate (SUB). The barrier film (BR) can be composed of multiple inorganic films stacked alternately.

[0106] The thin-film transistor TFT1 can be disposed on the barrier film BR. The thin-film transistor TFT1 can be... Figure 4 The fourth transistor ST4 or the sixth transistor ST6 shown is illustrated. The thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0107] The first active layer ACT1 of the thin-film transistor TFT1 can be disposed on the barrier film BR. The first active layer ACT1 of the thin-film transistor TFT1 may include polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, or amorphous silicon. Alternatively, the first active layer ACT1 of the thin-film transistor TFT1 may include an oxide semiconductor comprising IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0108] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region on the third direction DR3, which is the thickness direction of the substrate SUB, that overlaps with the first gate electrode G1. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third direction DR3 that do not overlap with the first gate electrode G1. The first source region S1 and the first drain region D1 may be conductive regions in which the semiconductor material is doped with ions.

[0109] The first gate insulating film 131 can be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the thin film transistor TFT1.

[0110] A first gate metal layer may be disposed on a first gate insulating film 131. The first gate metal layer may include a first gate electrode G1 and a first capacitor electrode CAE1 of a thin-film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 on a third-direction DR3. Figure 6 In the diagram, the first gate electrode G1 and the first capacitor electrode CAE1 are shown as being disposed separately from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 can be connected to each other.

[0111] The second gate insulating film 132 can be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the thin film transistor TFT1.

[0112] A second gate metal layer can be disposed on the second gate insulating film 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 on the third-direction DR3. Since the second gate insulating film 132 has a predetermined dielectric constant, the capacitor ( Figure 4 C1 in the figure can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2 and a second gate insulating film 132 disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2.

[0113] The first interlayer insulating film 141 can be disposed on the second capacitor electrode CAE2.

[0114] A first data metal layer may be disposed on a first interlayer insulating film 141. The first data metal layer may include a first source connection electrode PCE1. The first source connection electrode PCE1 may be connected to a first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating film 131, the second gate insulating film 132 and the first interlayer insulating film 141.

[0115] The first planarization organic film 160 can be disposed on the first source connection electrode PCE1 to planarize the steps caused by the thin film transistor TFT1.

[0116] A second data metal layer may be disposed on the first planarized organic film 160. The second data metal layer may include a second source connection electrode PCE2. The second source connection electrode PCE2 may be connected to the first source connection electrode PCE1 through a second source contact hole PCT2 penetrating the first planarized organic film 160.

[0117] The second planarized organic film 180 can be disposed on the second source connection electrode PCE2.

[0118] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, and the first interlayer insulating film 141 can be made of, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0119] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer can be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0120] The first planarization organic membrane 160 and the second planarization organic membrane 180 can be formed from organic membranes including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0121] The light-emitting element layer can be disposed on the second planarized organic film 180. The light-emitting element layer may include pixel electrodes PXE1, PXE2, PXE3, light-emitting element LE, common electrodes CE1, CE2 and CE3 and the first organic layer 210.

[0122] A pixel electrode layer, including pixel electrodes PXE1, PXE2 and PXE3 and common electrodes CE1, CE2 and CE3, can be disposed on the second planarized organic film 180.

[0123] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can be connected through a connection hole penetrating the second planarized organic film 180. Figure 5CT1, CT2, and CT3 are connected to the second source connection electrode PCE2. Each of the pixel electrodes PXE1, PXE2, and PXE3 can be connected to the first source region S1 or the first drain region D1 of the thin-film transistor TFT1 via the first source connection electrode PCE1 and the second source connection electrode PCE2. Therefore, a voltage controlled by the thin-film transistor TFT1 can be applied to each of the pixel electrodes PXE1, PXE2, and PXE3.

[0124] Common electrodes CE1, CE2, and CE3 can be connected through a common connection hole ( Figure 5 CT4, CT5, and CT6 are connected to the second driving voltage. Figure 3 The VSS in the middle is applied to its second power line ( Figure 4 The first common electrode CE1 can be connected to the second power line through the first common connection port CT4 (VSL). Figure 4 (VSL in the middle). The second common electrode CE2 can be connected to the second power line through the second common connection hole CT5 ( Figure 4 The third common electrode CE3 can be connected to the second power line via the third common connection port CT6. Figure 4 (VSL in the middle). Therefore, the second driving voltage VSS can be applied to each of the common electrodes CE1, CE2 and CE3.

[0125] The pixel electrode layer can be formed as a single layer or multiple layers of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. For example, the pixel electrode layer can be made of copper (Cu) with low sheet resistance to reduce the resistance of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0126] A first organic layer 210 may be disposed on each pixel electrode layer. The first organic layer 210 is used to temporarily fix or adhere the top layer. For example, the first organic layer 210 may be a film for temporarily adhering the first connecting electrode CTEL1 and the second connecting electrode CTEL2 to each of the pixel electrodes PXE1, PXE2 and PXE3 and the common electrodes CE1, CE2 and CE3. To facilitate temporary adhesion, the thickness of the first organic layer 210 may be greater than the thickness of each of the pixel electrodes PXE1, PXE2 and PXE3 and the common electrodes CE1, CE2 and CE3, and greater than the thickness of the connecting electrodes CTEL1 and CTEL2.

[0127] The first organic layer 210 may be a photosensitive organic film such as a photoresist. Alternatively, the first organic layer 210 may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0128] Multiple light-emitting elements LE can be disposed on the first connecting electrode CTEL1 and the second connecting electrode CTEL2. Figure 6 and Figure 7 The illustrated light-emitting element LE is a flip-type micro LED. A flip-type micro LED refers to an LED in which contact electrodes CTE1 and CTE2 are formed on one side (e.g., the bottom side) of the light-emitting element LE.

[0129] Each of the multiple light-emitting elements (LEs) can be formed from an inorganic material such as gallium nitride (GaN).

[0130] Each of the plurality of light-emitting elements (LEs) can be formed by growth on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light-emitting elements (LEs) can be transferred directly from the semiconductor substrate to the pixel electrode layer of the display panel 100. Alternatively, the plurality of light-emitting elements (LEs) can be transferred to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100 by an electrostatic method using an electrostatic head or by an imprinting method using an elastic polymer material such as PDMS or silicone as a transfer substrate.

[0131] The light-emitting element LE may include a conductive layer E1, a semiconductor stack STC, a first contact electrode CTE1, a second contact electrode CTE2, and a protective film INS. The semiconductor stack STC may include a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 sequentially arranged on a third-direction DR3.

[0132] The conductive layer E1 can be disposed on the lower surface of the first semiconductor layer SEM1. Although Figure 7 The diagram shows a conductive layer E1 covering the entire lower surface of the first semiconductor layer SEM1, but the embodiments disclosed herein are not necessarily limited to this. In one example, the conductive layer E1 may be disposed on a portion of the lower surface of the first semiconductor layer SEM1. The conductive layer E1 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0133] The first semiconductor layer SEM1 can be disposed on the conductive layer E1. The first semiconductor layer SEM1 may include a semiconductor material layer doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr) or barium (Ba), for example gallium nitride (GaN).

[0134] In one embodiment, the first semiconductor layer SEM1 may have a multilayer structure. For example, the first semiconductor layer SEM1 may include a P-GaN layer and a P+GaN layer. The P+GaN layer may be disposed below the P-GaN layer. The P+GaN layer may be a layer overdoped with a first conductivity type dopant. The P+GaN layer may be formed on top with a thickness of several nanometers or tens of nanometers to aid in the formation of ohmic electrodes. P+GaN can help reduce the operating voltage by increasing the ohmic properties with the top metal via the tunneling effect.

[0135] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can emit light by causing electron-hole binding pairs to combine, based on the electrical signals applied via the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0136] The active layer MQW can include materials having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material with a multi-quantum well structure, the active layer MQW can have a structure in which multiple well layers and barrier layers are stacked alternately. In this case, the well layers can be formed of indium gallium nitride (InGaN), and the barrier layers can be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments disclosed herein are not necessarily limited to these.

[0137] Alternatively, the active layer MQW may have a structure in which semiconductor materials with high energy band gaps and semiconductor materials with low energy band gaps are stacked alternately, and may include other group 3 to 5 semiconductor materials depending on the wavelength range of the emitted light.

[0138] For example, when the active layer MQW includes InGaN, the color of the emitted light can vary depending on the indium (In) content. For instance, as the indium (In) content increases, the wavelength of the light emitted by the active layer can shift towards the red band, while as the indium (In) content decreases, the wavelength of the light emitted by the active layer can shift towards the blue band. For example, the indium (In) content in the active layer MQW of a light-emitting element LE that emits a third light (e.g., light in the blue band) can be approximately 10 wt% to 20 wt%.

[0139] The second semiconductor layer SEM2 can be disposed on the first semiconductor layer SEM1. The second semiconductor layer SEM2 can be a semiconductor material layer doped with a second conductivity type dopant such as silicon (Si), germanium (Ge), tin (Sn), etc., for example gallium nitride (GaN).

[0140] In one embodiment, the second semiconductor layer SEM2 may have a multilayer structure. For example, the second semiconductor layer SEM2 may include an N-GaN layer and an N+GaN layer disposed on the N-GaN layer. The N+GaN layer may be a layer overdoped with a second conductivity type dopant. The N+GaN layer can increase the overall uniform light emission of the light-emitting element LE by reducing electrical resistance and improving current distribution when forming ohmic electrodes.

[0141] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer used to suppress or prevent excessive electron inflow into the active layer MQW. For example, the electron blocking layer can be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer can be omitted.

[0142] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can serve as a layer to alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The superlattice layer can be omitted.

[0143] The protective film INS can be a film used to protect the bottom and side surfaces of the light-emitting element LE. The protective film INS can be disposed on the bottom and side surfaces of the conductive layer E1 and on the side surface of the semiconductor stack STC. For example, the protective film INS can be disposed on the bottom and side surfaces of the conductive layer E1, on the side surface of the first semiconductor layer SEM1, on the side surface of the active layer MQW, and on the side surface of the second semiconductor layer SEM2. The protective film INS can be made of, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) and / or alumina (AlO) x Inorganic membrane formation.

[0144] The aperture LEH exposing the second semiconductor layer SEM2 can be formed through the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW of the light-emitting element LE. The aperture LEH can have a circular planar shape, but the embodiments of this disclosure are not necessarily limited to this. For example, the aperture LEH can have a polygonal planar shape such as a rectangle or an elliptical shape.

[0145] Furthermore, the protective film INS can be disposed on the sidewalls of the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW exposed in the via LEH. The protective film INS may not cover the second semiconductor layer SEM2 in the via LEH. Therefore, the second semiconductor layer SEM2 can be exposed without being covered by the protective film INS.

[0146] The first contact electrode CTE1 can be disposed on the lower surface of the conductive layer E1. For example, the first contact electrode CTE1 can be disposed on the exposed lower surface of the conductive layer E1 without being covered by the protective film INS. Therefore, the first contact electrode CTE1 can be electrically connected to the conductive layer E1.

[0147] The second contact electrode CTE2 can be disposed on the lower surface of the conductive layer E1. The second contact electrode CTE2 can also be disposed on the protective film INS disposed in the hole LEH and on the second semiconductor layer SEM2 exposed in the hole LEH but not covered by the protective film INS. Therefore, the second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 in the hole LEH.

[0148] Each of the first contact electrode CTE1 and the second contact electrode CTE2 may comprise any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, each of the first contact electrode CTE1 and the second contact electrode CTE2 may be formed of a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to improve reflectivity.

[0149] Figure 6 and Figure 7 The first contact electrode CTE1 and the second contact electrode CTE2 of each of the illustrated light-emitting elements LE are disposed on the first organic layer 210, but the embodiments of this disclosure are not necessarily limited thereto. For example, the first organic layer 210 may be disposed on a portion of the bottom surface and a portion of the side surface of the first contact electrode CTE1 and a portion of the bottom surface and a portion of the side surface of the second contact electrode CTE2 of each of the light-emitting elements LE. Alternatively, the first organic layer 210 may be disposed on the side surface of the conductive layer E1 of each of the light-emitting elements LE. Alternatively, the first organic layer 210 may be disposed on the side surface of the first semiconductor layer SEM1, the side surface of the active layer MQW, and the side surface of the second semiconductor layer SEM2 of each of the light-emitting elements LE. In this case, the first organic layer 210 may be disposed on a portion of each side of the second semiconductor layer SEM2.

[0150] Each of the first contact electrode CTE1 and the second contact electrode CTE2 may be disposed on one side of the semiconductor stack STC, but the first contact electrode CTE1 and the second contact electrode CTE2 are configured to be spaced apart from each other.

[0151] The first connecting electrode CTEL1 can be disposed between the first contact electrode CTE1 and the first organic layer 210 and extend along the first organic layer 210 to the pixel electrodes PXE1, PXE2 and PXE3. The first connecting electrode CTEL1 connects the first contact electrode CTE1 of the light-emitting element LE to the pixel electrodes PXE1, PXE2 and PXE3.

[0152] The second connecting electrode CTEL2 can be disposed between the second contact electrode CTE2 and the first organic layer 210 and extend along the first organic layer 210 to the common electrodes CE1, CE2 and CE3. The second connecting electrode CTEL2 connects the second contact electrode CTE2 of the light-emitting element LE to the common electrodes CE1, CE2 and CE3.

[0153] Each of the first connecting electrode CTEL1 and the second connecting electrode CTEL2 may comprise any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, each of the first connecting electrode CTEL1 and the second connecting electrode CTEL2 may be formed of a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to improve reflectivity.

[0154] The first side electrode BE1 can be disposed on top of the first connecting electrode CTEL1 and on one side of the light-emitting element LE. The first side electrode BE1 can be disposed on a portion of the side surface of the light-emitting element LE. For example, the first side electrode BE1 can be disposed on a portion of the protective film INS of the light-emitting element LE.

[0155] The second side electrode BE2 can be disposed on top of the second connecting electrode CTEL2 and on one side of the light-emitting element LE. The second side electrode BE2 can be disposed on a portion of the side surface of the light-emitting element LE. For example, the second side electrode BE2 can be disposed on a portion of the protective film INS of the light-emitting element LE.

[0156] Each of the first side electrode BE1 and the second side electrode BE2 can be disposed on one side of the light-emitting element LE. Within the side surface of the light-emitting element LE, a region adjacent to the top surface of the semiconductor stack STC can be exposed and not covered by the first side electrode BE1 and the second side electrode BE2. For example, the distance DS1 between the top surface of the light-emitting element LE and the top surfaces of the side electrodes BE1 and BE2 in the third direction DR3 can be greater than approximately 100 nm, but is not necessarily limited to this.

[0157] Each of the first side electrode BE1 and the second side electrode BE2 may comprise any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the first side electrode BE1 and the second side electrode BE2 may be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0158] When each of the first side electrode BE1 and the second side electrode BE2 is made of a metallic material with high reflectivity, light emitted from the active layer MQW of the light-emitting element LE can be reflected from the first side electrode BE1 and the second side electrode BE2, and light traveling in the lateral direction of the light-emitting element LE can travel in the upward direction of the light-emitting element LE. Therefore, light loss of the light-emitting element LE can be reduced, and thus the light efficiency of the light-emitting element LE can be improved.

[0159] Here, the third-direction DR3 can be substantially the same as the height direction (or thickness direction) of the light-emitting element LE. This prevents lateral leakage current that might occur on the upper side of the light-emitting element LE when the first side electrode BE1 and the second side electrode BE2 are spaced apart from the top surface of the light-emitting element LE. When the first side electrode BE1 and the second side electrode BE2 are positioned on the top surface of the light-emitting element LE, lateral leakage current may occur if the protective film INS is partially etched away by subsequent processes, causing the side electrodes BE1 and BE2 to contact the semiconductor stack STC.

[0160] The first sloped layer SINS1 can be located on the first side electrode BE1, surrounding the side surface of the light-emitting element LE. Since the first sloped layer SINS1 is located on the first side electrode BE1, it does not need to contact other components such as the light-emitting element LE, the first organic layer 210, and the first contact electrode CTE1. The width of the first sloped layer SINS1 can narrow upwards, but the amount of reduction in width can decrease upwards. For example, the first sloped layer SINS1 can have a parabolic shape and bulge upwards with the light-emitting element LE located on one side, but it is not necessarily limited to this.

[0161] Each of the first sloped layer SINS1 and the second sloped layer SINS2 may be an organic layer comprising, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. Alternatively, each of the first sloped layer SINS1 and the second sloped layer SINS2 may be comprising, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x The inorganic layer. Alternatively, each of the first slope inclined layer SINS1 and the second slope inclined layer SINS2 can be formed from an organic-inorganic mixture.

[0162] The side surface of the light-emitting element LE, the first side electrode BE1, and the first sloped layer SINS1 may have a recessed structure in cross-section. For example, the recessed structure may be formed such that the distance DS1 between the top surface of the light-emitting element LE and the top surface of the first side electrode BE1 is greater than the distance DS2 between the extension of the top surface of the light-emitting element LE and the top of the first sloped layer SINS1. In this disclosure, "in cross-section" is defined as viewed in either the first direction DR1 or the second direction DR2.

[0163] The second sloped layer SINS2 can be located on the second side electrode BE2, surrounding the side surface of the light-emitting element LE. Since the second sloped layer SINS2 is located on the second side electrode BE2, it does not need to contact other components such as the light-emitting element LE, the first organic layer 210, and the second contact electrode CTE2. The width of the second sloped layer SINS2 can narrow upwards, but the amount of reduction in width can decrease upwards. For example, the second sloped layer SINS2 can have a parabolic shape and bulge upwards with the light-emitting element LE located on one side, but it is not necessarily limited to this.

[0164] The side surface of the light-emitting element LE, the second side electrode BE2, and the second sloped layer SINS2 may have a recessed structure in cross-section. For example, the recessed structure may be a structure in which the distance DS2 between the top surface of the light-emitting element LE and the top surface of the second side electrode BE2 is a greater distance than the distance DS2 between the extension of the top surface of the light-emitting element LE and the top of the second sloped layer SINS2.

[0165] The first dummy electrode DE1 may be disposed on the first connecting electrode CTEL1, on at least a portion of the first pixel electrode PXE1, and on one side of the first organic layer 210. The first dummy tilt layer DINS1 may be disposed on the first dummy electrode DE1.

[0166] The second dummy electrode DE2 can be disposed on the second connecting electrode CTEL2, on at least a portion of the first common electrode CE1, and on one side of the first organic layer 210. The second dummy tilted layer DINS2 can be disposed on the second dummy electrode DE2.

[0167] The width of each of the first dummy tilted layer DINS1 and the second dummy tilted layer DINS2 may narrow as it moves upward, but the amount of reduction in width may decrease as it moves upward. For example, each of the first dummy tilted layer DINS1 and the second dummy tilted layer DINS2 may have a raised shape, with the light-emitting element LE disposed on one side, but is not necessarily limited to this.

[0168] The first dummy tilt layer DINS1 and the second dummy tilt layer DINS2 are formed during the same process as the first slope tilt layer SINS1 and the second slope tilt layer SINS2, and are formed in the same manner, therefore they can include the same materials. Thus, each of the first dummy tilt layer DINS1 and the second dummy tilt layer DINS2 can be an organic layer including materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. Alternatively, each of the first dummy tilt layer DINS1 and the second dummy tilt layer DINS2 can be an organic layer including, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x The inorganic layer. Alternatively, each of the first dummy tilted layer DINS1 and the second dummy tilted layer DINS2 may also be formed of an organic-inorganic mixture.

[0169] The first dummy tilt layer DINS1 and the second dummy tilt layer DINS2 can be omitted.

[0170] The second organic film 211 can cover multiple light-emitting elements (LEs). Furthermore, the second organic film 211 can cover the first sloped layer SINS1, the second sloped layer SINS2, the first connecting electrode CTEL1, the second connecting electrode CTEL2, the first dummy sloped layer DINS1, and the second dummy sloped layer DINS2, but embodiments of this disclosure are not necessarily limited thereto. In one example, the entire first sloped layer SINS1 and the second sloped layer SINS2 can be covered by the second organic film 211. The top surface of each of the multiple light-emitting elements (LEs) can be exposed and not covered by the second organic film 211. In an example, the second organic film 211 can comprise multiple stacked organic films. The second organic film 211 is a layer used to planarize the steps caused by the multiple light-emitting elements (LEs). The second organic film 211 can be formed as a monolayer when its height covers most of the side surfaces of each of the multiple light-emitting elements (LEs).

[0171] The second organic membrane 211 can be formed from an organic membrane including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0172] The first capping layer CAP1 can be disposed on the second organic film 211 and the light-emitting element LE.

[0173] A light-shielding layer BM, a first light conversion layer QDL1, a second light conversion layer QDL2, and a light-transmitting layer TPL can be disposed on a first capping layer CAP1. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL can be formed through compartments in the light-shielding layer BM. Therefore, the first light conversion layer QDL1 can be disposed in the first sub-pixel SPX1 and on the first capping layer CAP1, the second light conversion layer QDL2 can be disposed in the second sub-pixel SPX2 and on the first capping layer CAP1, and the light-transmitting layer TPL can be disposed in the third sub-pixel SPX3 and on the first capping layer CAP1. The light-shielding layer BM can be disposed on the third-direction DR3 without overlapping with multiple light-emitting elements LE.

[0174] The first light conversion layer QDL1 can convert a portion of third light (e.g., light in the blue band) incident from the light-emitting element LE into first light (e.g., light in the red band). The first light conversion layer QDL1 may include a first substrate resin BRS1 and first wavelength conversion particles WCP1. The first substrate resin BRS1 may include a light-transmitting organic material. The first wavelength conversion particles WCP1 can convert a portion of the third light (e.g., light in the blue band) incident from the light-emitting element LE into first light (e.g., light in the red band).

[0175] The second light conversion layer QDL2 can convert a portion of the third light (e.g., light in the blue band) incident from the light-emitting element LE into a second light (e.g., light in the green band). The second light conversion layer QDL2 may include a second substrate resin BRS2 and second wavelength conversion particles WCP2. The second substrate resin BRS2 may include a light-transmitting organic material. The second wavelength conversion particles WCP2 can convert a portion of the third light (e.g., light in the blue band) incident from the light-emitting element LE into the second light (e.g., light in the green band).

[0176] The light-transmitting layer (TPL) may include light-transmitting organic materials.

[0177] For example, the first substrate resin BRS1, the second substrate resin BRS2, ​​and the light-transmitting layer TPL may include epoxy resin, acrylic resin, calomel resin, or imide resin. The first wavelength conversion particle WCP1 and the second wavelength conversion particle WCP2 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0178] The light-shielding layer BM may comprise a first light-shielding layer BM1 and a second light-shielding layer BM2 stacked sequentially. The length of the first light-shielding layer BM1 in the first direction DR1 or the length of the first light-shielding layer BM1 in the second direction DR2 may be wider than the length of the second light-shielding layer BM2 in the first direction DR1 or the length of the second light-shielding layer BM2 in the second direction DR2. The first light-shielding layer BM1 and the second light-shielding layer BM2 may be formed of an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The first light-shielding layer BM1 and the second light-shielding layer BM2 may comprise a light-shielding material to prevent light from the light-emitting element LE from one sub-pixel from traveling to adjacent sub-pixels. For example, the first light-shielding layer BM1 and the second light-shielding layer BM2 may comprise an inorganic black pigment such as carbon black or an organic black pigment.

[0179] The second capping layer CAP2 can be disposed on the first capping layer CAP1 and the light-shielding layer BM. The second capping layer CAP2 can be disposed on the side surface and top surface of the light-shielding layer BM. For example, the second capping layer CAP2 can be disposed on one side of the first light-shielding layer BM1 and on the side surface and top surface of the second light-shielding layer BM2.

[0180] The reflective film RF can be disposed between the light-shielding layer BM and the first light conversion layer QDL1, between the light-shielding layer BM and the second light conversion layer QDL2, and between the light-shielding layer BM and the light-transmitting layer TPL. The reflective film RF can be disposed on a second capping layer CAP2, located on one side of the first light-shielding layer BM1 and one side of the second light-shielding layer BM2. The reflective film RF is used to reflect light propagating in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0181] The reflective coating RF can include highly reflective metallic materials such as aluminum (Al). The thickness of the reflective coating RF can be approximately 0.1 μm.

[0182] Alternatively, the reflective film RF may comprise a first layer and a second layer of M pairs (M being an integer greater than 2) having different refractive indices to function as a distributed Bragg reflector (DBR). In this case, the M first layers and M second layers can be arranged alternately. The first and second layers may be made of, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0183] The third capping layer CAP3 can be disposed on the second capping layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0184] The first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3 can be made of, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x An inorganic film is formed. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3.

[0185] A fourth organic membrane 213 may be disposed on the third capping layer CAP3. Multiple color filters CF1, CF2, and CF3 may be disposed on the fourth organic membrane 213. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0186] The first color filter CF1, disposed in the first sub-pixel SPX1, can transmit first light (e.g., light in the red band) and absorb or block third light (e.g., light in the blue band). Therefore, the first color filter CF1 can transmit the first light (e.g., light in the red band) that has been converted by the first light conversion layer QDL1 from the third light emitted from the light-emitting element LE (e.g., light in the blue band), and absorb or block the third light (e.g., light in the blue band) that has not been converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can emit first light (e.g., light in the red band).

[0187] The second color filter CF2, disposed in the second sub-pixel SPX2, can transmit second light (e.g., light in the green band) and absorb or block third light (e.g., light in the blue band). Therefore, the second color filter CF2 can transmit the second light (e.g., light in the green band) emitted from the light-emitting element LE that has been converted by the second light conversion layer QDL2, and absorb or block the third light (e.g., light in the blue band) that has not been converted by the second light conversion layer QDL2. Thus, the second sub-pixel SPX2 can emit second light (e.g., light in the green band).

[0188] A third color filter CF3 disposed in the third sub-pixel SPX3 can transmit third light (e.g., light in the blue band). Therefore, the third color filter CF3 can transmit third light (e.g., light in the blue band) emitted from the light-emitting element LE and passing through the light-transmitting layer TPL. Therefore, the third sub-pixel SPX3 can emit third light (e.g., light in the blue band).

[0189] The first color filter CF1, the second color filter CF2, and the third color filter CF3, which overlap on the third-direction DR3, can overlap with the light-shielding layer BM on the third-direction DR3.

[0190] The fifth organic membrane 214 can be disposed on multiple color filters CF1, CF2 and CF3 for planarization.

[0191] The fourth organic membrane 213 and the fifth organic membrane 214 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, etc.

[0192] Figure 8 Detailed illustrations Figure 6 A cross-sectional view of an example of zone A in the diagram.

[0193] Figure 8 Implementation examples and Figure 7 The difference in the embodiments is that the first slope-inclined layer SINS1 and the second slope-inclined layer SINS2 have concave shapes. Figure 8In the middle, omission and Figure 7 The embodiments are described repeatedly, and the description will focus on the embodiments. Figure 7 The differences between the embodiments are as follows. Without describing the elements in detail with reference to the accompanying drawings, it will be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0194] refer to Figure 8 The first sloped layer SINS1 can be located on the first side electrode BE1, surrounding the side surface of the light-emitting element LE. Since the first sloped layer SINS1 is located on the first side electrode BE1, it does not need to contact other components such as the light-emitting element LE, the first organic layer 210, and the first contact electrode CTE1. The width of the first sloped layer SINS1 can narrow as it moves upwards, but the amount of reduction in width can increase as it moves upwards. For example, the first sloped layer SINS1 can have a parabolic shape and be concave downwards so that the light-emitting element LE is located on one side, but it is not necessarily limited to this.

[0195] The second sloped layer SINS2 can be located on the second side electrode BE2, surrounding the side surface of the light-emitting element LE. Because the second sloped layer SINS2 is located on the second side electrode BE2, it does not need to contact other components such as the light-emitting element LE, the first organic layer 210, and the second contact electrode CTE2. The width of the second sloped layer SINS2 can narrow as it moves upwards, but the amount of reduction in width can increase as it moves upwards. For example, the second sloped layer SINS2 can have a parabolic shape and be concave downwards so that the light-emitting element LE is located on one side, but it is not necessarily limited to this.

[0196] Figure 9 and Figure 10 Detailed illustrations Figure 6 A cross-sectional view of an example of zone A in the diagram.

[0197] Figure 9 and Figure 10 Implementation examples and Figure 7 The difference in this embodiment is that the first side electrode BE1 and the second side electrode BE2 do not cover the second semiconductor layer SEM2. Figure 9 and Figure 10 In the middle, omission and Figure 7 The embodiments are described repeatedly, and the description will focus on the embodiments. Figure 7 The differences between the embodiments are as follows. Therefore, without describing the elements in detail with reference to the accompanying drawings, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0198] refer to Figure 9Each of the first side electrode BE1 and the second side electrode BE2 may not cover the second semiconductor layer SEM2. Each of the first side electrode BE1 and the second side electrode BE2 may be set at the height of the boundary between the second semiconductor layer SEM2 and the active layer MQW.

[0199] refer to Figure 10 Each of the first side electrode BE1 and the second side electrode BE2 may not cover the second semiconductor layer SEM2 and the active layer MQW. Each of the first side electrode BE1 and the second side electrode BE2 may be set to the height of the boundary between the active layer MQW and the first semiconductor layer SEM1.

[0200] like Figure 9 and Figure 10 As shown, the regions adjacent to the top surface of the semiconductor stack STC on each side of the light-emitting element LE can be exposed without being covered by the first side electrode BE1 and the second side electrode BE2. The exposed regions not covered by the first side electrode BE1 and the second side electrode BE2 can completely or partially comprise the second semiconductor layer SEM2 and the active layer MQW. Regardless of the size of the exposed regions, the light-emitting element LE, the first side electrode BE1, the first sloped layer SINS1, and the light-emitting element LE, the second side electrode BE2, and the second sloped layer SINS2 can all have recessed structures in cross-section. For example, the recessed structure can be a structure in which the distance DS1 between the top surface of the light-emitting element LE and the top surface of the first side electrode BE1 is formed to be farther than the distance DS2 between the extension of the top surface of the light-emitting element LE and the top of the first sloped layer SINS1. Furthermore, the distance DS1 between the top surface of the light-emitting element LE and the top surface of the second side electrode BE2 can be formed to be farther than the distance DS2 between the extension of the top surface of the light-emitting element LE and the top of the second sloped layer SINS2.

[0201] Figure 11 It is a diagram. Figure 6 Detailed cross-sectional view of an example of zone A in the diagram.

[0202] Figure 11 Implementation examples and Figure 7 The difference in the embodiment is that the semiconductor stack STC further includes a third semiconductor layer SEM3 having a light extraction pattern LEP. Figure 11 In the middle, omission and Figure 7 The embodiments are described repeatedly, and the description will focus on the embodiments. Figure 7 The differences between the embodiments are as follows. Therefore, without describing the elements in detail with reference to the accompanying drawings, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0203] refer to Figure 11The semiconductor stack STC of the light-emitting element (LE) may further include a third semiconductor layer SEM3. The third semiconductor layer SEM3 may be referred to as an undoped semiconductor layer, which is a semiconductor material layer in which the n-type dopant is below a predetermined threshold. For example, the third semiconductor layer SEM3 may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), wherein the n-type dopant is below a predetermined threshold.

[0204] The light extraction pattern (LEP) can be formed on the top surface of the semiconductor stack STC. In one example, the LEP can be formed on the top surface of the third semiconductor layer SEM3.

[0205] The light extraction pattern (LEP) can be a pattern used to improve the efficiency of light emitted from the top surface of the light-emitting element (LE). The LEP can be a recessed pattern formed as a hemisphere or semi-ellipsoid. The LEP can also be a recessed pattern with a semi-circular or semi-elliptical cross-sectional shape. The maximum length Lmax of the LEP in the third direction DR3 can be approximately 100 nm. Furthermore, the distance between adjacent LEPs can be less than approximately 100 nm.

[0206] The light-extractable patterned LEP can be formed from an organic film including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. Alternatively, the light-extractable patterned LEP can be formed from, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) and / or alumina (AlO) x Inorganic membrane formation.

[0207] Figure 12 This is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Figures 13 to 17 This is a cross-sectional view used to illustrate a method of manufacturing a display device according to one embodiment.

[0208] In the following text, reference will be made to Figures 12 to 17 A method for manufacturing a display device according to one embodiment is described in detail. Figures 13 to 17 In the text, for ease of description, and Figure 7 A cross section corresponding to one embodiment is shown.

[0209] First, such as Figure 13As shown, the light-emitting element LE is transferred to a substrate having a first connection electrode CTEL1 and a second connection electrode CTEL2 disposed on the first organic layer 210. Figure 6 (in SUB) on ( Figure 12 Step S110 in the process.

[0210] Each of the multiple light-emitting elements (LEs) can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The multiple LEs can be transferred directly from the semiconductor substrate to the pixel electrode PXE1 of the display panel. Alternatively, the multiple LEs can be transferred to the pixel electrode PXE1 of the display panel by an electrostatic method using an electrostatic head or by an imprinting method using an elastic polymer material such as PDMS or silicone as the transfer substrate.

[0211] When the first organic layer 210 is a photosensitive organic film such as a photoresist, after curing (soft baking) the first organic layer 210 at a first temperature, the first connecting electrode CTEL1 and the second connecting electrode CTEL2 can be placed, and the first organic layer 210 can be completely cured at a second temperature higher than the first temperature. The first temperature can be approximately 100 degrees Celsius, and the second temperature can be approximately 230 degrees Celsius, but the embodiments disclosed herein are not necessarily limited to these. Furthermore, the process of completely curing the first organic layer 210 at the second temperature can be performed for approximately 30 minutes.

[0212] Secondly, such as Figure 14 and Figure 15 As shown, the electrode material layer BEL and the insulating material layer SINSL are formed on the surfaces of the light-emitting element LE, the first connecting electrode CTEL1, and the second connecting electrode CTEL2. Figure 12 Step S120 in the process.

[0213] For example, the electrode material layer BEL can be completely deposited on the second planarized organic film 180 (see...). Figure 6 The electrode material layer BEL can be formed to cover not only one surface and side surfaces of the light-emitting element LE, but also the first connecting electrode CTEL1 and the second connecting electrode CTEL2.

[0214] The insulating material layer (SINSL) is formed to completely cover the electrode material layer (BEL). The insulating material layer (SINSL) can be formed to be thicker than the electrode material layer (BEL). For example, the insulating material layer (SINSL) can be formed by depositing SiN. x Formed as The thickness.

[0215] Third, such as Figure 16 As shown, the insulating material layer SINSL is etched to form a first sloped layer SINS1 and a second sloped layer SINS2. Figure 12 (Step S130). The insulating material layer SINSL can be etched using a dry etching method. In the case of dry etching, anisotropic etching is possible and can be applied to vertical etching. When using a dry etching method, the etching gas can be chlorine (Cl2) or oxygen (O2), but is not necessarily limited to these. For example, a large voltage difference is generated on the third-direction DR3 without a separate mask, and the insulating material layer SINSL is etched using an etching gas. In this case, the etching gas is moved on the third-direction DR3 by voltage control, for example, from top to bottom, and the insulating material layer SINSL can be etched. As a result, even without being protected by a mask pattern, the insulating material layer SINSL disposed on one side of the light-emitting element LE, the insulating material layer SINSL disposed on the top surface of the first connecting electrode CTEL1 adjacent to one side of the light-emitting element LE, and the insulating material layer SINSL disposed on the top surface of the second connecting electrode CTEL2 adjacent to one side of the light-emitting element LE can be retained without being etched.

[0216] Therefore, the insulating material layer SINSL disposed on the top of the light-emitting element LE and on the top of the first connecting electrode CTEL1 and the second connecting electrode CTEL2 is etched. The insulating material layer SINSL disposed on one side of the light-emitting element LE, the insulating material layer SINSL disposed on the top surface of the first connecting electrode CTEL1 adjacent to one side of the light-emitting element LE, and the insulating material layer SINSL disposed on the top surface of the second connecting electrode CTEL2 adjacent to one side of the light-emitting element LE can be retained without being etched by anisotropic etching. Therefore, the first slope layer SINS1, the second slope layer SINS2, the first dummy slope layer DINS1, and the second dummy slope layer DINS2 are formed. Furthermore, the insulating material layer SINSL disposed on one side of the first organic layer 210, the insulating material layer SINSL disposed on the top surface of the first connecting electrode CTEL1 adjacent to one side of the first organic layer 210, and the insulating material layer SINSL disposed on the top surface of the second connecting electrode CTEL2 adjacent to one side of the first organic layer 210 can be etched without anisotropic etching. The height of the remaining insulating material layer SINSL can be adjusted by the concentration and time of the etching gas.

[0217] Fourth, such as Figure 17 As shown, the electrode material layer BEL is etched to form the first side electrode BE1 and the second side electrode BE2. Figure 12 Step S140 in the process.

[0218] The electrode material layer BEL is removed by etching it to the outside via a wet etching method, without depositing the first sloped layer SINS1, the second sloped layer SINS2, the first dummy sloped layer DINS1, and the second dummy sloped layer DINS2. Therefore, the electrode material layer BEL on the top surface of the light-emitting element LE and the electrode material layer BEL on the side adjacent to the top surface of the light-emitting element LE are removed. Furthermore, a portion of the top surface of the electrode material layer BEL is removed to form the first side electrode BE1 and the second side electrode BE2.

[0219] Due to wet etching, the upper portion of the first side electrode BE1 between the light-emitting element LE and the first sloped layer SINS1 can be recessed downwards. Furthermore, the upper portion of the second side electrode BE2 between the light-emitting element LE and the second sloped layer SINS2 can be recessed downwards. For example, on the third direction DR3, the distance DS1 between the top surface of the light-emitting element LE and the side electrodes BE1 and BE2 (see...) Figure 7 The distance DS2 between the top surface of the light-emitting element LE and the first sloped layer SINS1 can be longer than the distance between the two surfaces (see [reference]). Figure 7 ).

[0220] The first side electrode BE1, the second side electrode BE2, the first sloped layer SINS1, and the second sloped layer SINS2 formed in this way stably support the side surface of the light-emitting element LE.

[0221] Figures 18 to 24 This is an example diagram illustrating a method of manufacturing a display device according to one embodiment.

[0222] In the following text, reference will be made to Figure 12 as well as Figures 18 to 24 A method for manufacturing a display device according to one embodiment is described in detail. For ease of explanation, Figures 18 to 24 Diagram and Figure 8 The corresponding cross-sectional view and perspective view of the embodiment.

[0223] First, such as Figure 18 As shown, the light-emitting element LE is transferred to a substrate having a first connection electrode CTEL1 and a second connection electrode CTEL2 disposed on the first organic layer 210. Figure 6 (in SUB) on ( Figure 12 Step S110 in the process.

[0224] Secondly, such as Figures 19 to 22 As shown, the electrode material layer BEL and the insulating material layer SINSL are formed on the light-emitting element LE, the first connecting electrode CTEL1, and the second connecting electrode CTEL2. Figure 12 Step S120 in the process.

[0225] For example, such as Figure 19 As shown, the electrode material layer BEL can be completely deposited on the second planarized organic film 180 (see Figure 180). Figure 6 The electrode material layer BEL can be formed to cover not only one surface and side surfaces of the light-emitting element LE, but also the first connecting electrode CTEL1 and the second connecting electrode CTEL2.

[0226] Next, as Figure 20 and Figure 21 As shown, the electrode material layer BEL is separated into two spaced-apart first electrode material layer BEL1 and second electrode material layer BEL2 using an etching process with a photomask. For example, the area protected by the photomask can be retained without being etched, while the area not protected by the photomask can be etched.

[0227] Then, the photomask can be removed by an ashing process.

[0228] Next, an insulating material layer SINSL is formed to cover all electrode material layers BEL1 and BEL2. The insulating material layer SINSL can be formed to be thicker than the electrode material layers BEL1 and BEL2. For example, the insulating material layer SINSL can be formed by depositing SiN. x Formed as The thickness.

[0229] Third, such as Figure 23 As shown, a portion of the insulating material layer SINSL is etched to form a first sloped layer SINS1 and a second sloped layer SINS2. Figure 12(Step S130). The insulating material layer SINSL can be etched by dry etching. In the case of dry etching, anisotropic etching is possible and can be applied to vertical etching. When using a dry etching method, the etching gas can be chlorine (Cl2) or oxygen (O2), but is not necessarily limited to these. For example, a large voltage difference is formed on the third-direction DR3 without a separate mask, and the insulating material layer SINSL is etched using an etching gas. In this case, the etching gas moves on the third-direction DR3 by voltage control, for example, from top to bottom, and can etch the insulating material layer SINSL. Therefore, the insulating material layer SINSL disposed on the light-emitting element LE and disposed on the first connecting electrode CTEL1 and the second connecting electrode CTEL2 are etched. The insulating material layer SINSL disposed on one side of the light-emitting element LE, the insulating material layer SINSL disposed on the top surface of the first connecting electrode CTEL1 adjacent to one side of the light-emitting element LE, and the insulating material layer SINSL disposed on the top surface of the second connecting electrode CTEL2 adjacent to one side of the light-emitting element LE can be etched without anisotropic etching. As a result, a first slope inclined layer SINS1, a second slope inclined layer SINS2, a first dummy inclined layer DINS1, and a second dummy inclined layer DINS2 are formed.

[0230] Furthermore, the insulating material layer SINSL disposed on one side of the first organic layer 210, the insulating material layer SINSL disposed on the top surface of the first connecting electrode CTEL1 adjacent to one side of the first organic layer 210, and the insulating material layer SINSL disposed on the top surface of the second connecting electrode CTEL2 adjacent to one side of the first organic layer 210 can be etched without anisotropic etching. The height of the remaining insulating material layers SINSL can be adjusted by the concentration and time of the etching gas.

[0231] Fourth, such as Figure 24 As shown, the electrode material layer BEL is etched to form the first side electrode BE1 and the second side electrode BE2. Figure 12 Step S140 in the process.

[0232] The electrode material layer BEL is removed by etching the externally exposed electrode material layer BEL without the first sloped layer SINS1, the second sloped layer SINS2, the first dummy sloped layer DINS1, and the second dummy sloped layer DINS2 arranged thereon via a wet etching method. Therefore, the electrode material layer BEL on the top surface of the light-emitting element LE and the electrode material layer BEL on the side adjacent to the top surface of the light-emitting element LE are removed. Furthermore, a portion of the top surface of the first side electrode BE1 and the second side electrode BE2 is removed to form the first dummy electrode DE1 and the second dummy electrode DE2.

[0233] Due to wet etching, the upper part of the first side electrode BE1 between the light-emitting element LE and the first sloped layer SINS1 can be recessed downwards. Furthermore, the upper part of the second side electrode BE2 between the light-emitting element LE and the second sloped layer SINS2 can be recessed downwards.

[0234] The first side electrode BE1, the second side electrode BE2, the first sloped layer SINS1, and the second sloped layer SINS2 formed in this way stably support the side surface of the light-emitting element LE.

[0235] Figure 6 The light-shielding layer BM, wavelength conversion layers QDL1 and QDL2, light-transmitting layer TPL, and color filters CF1 to CF3 shown can be formed sequentially.

[0236] For example, refer to Figure 24 and Figure 6 A first capping layer CAP1 is formed on the second organic film 211 and the light-emitting element LE, and a first light-shielding layer BM1 and a second light-shielding layer BM2 are formed on the first capping layer CAP1 so as not to overlap with the light-emitting element LE on the third-direction DR3. Then, a second capping layer CAP2 is formed to cover the first light-shielding layer BM1, the second light-shielding layer BM2 and the first capping layer CAP1. Then, a reflective film RF is formed to cover the second capping layer CAP2 disposed on the first light-shielding layer BM1 and the second light-shielding layer BM2.

[0237] Then, a first light conversion layer QDL1 is formed in each of the first sub-pixels SPX1, a second light conversion layer QDL2 is formed in each of the second sub-pixels SPX2, and a light-transmitting layer TPL is formed in each of the third sub-pixels SPX3. Then, a third capping layer CAP3 is formed to cover the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL. Then, a fourth organic film 213 is formed on the third capping layer CAP3.

[0238] Then, a first color filter CF1 is formed on the fourth organic film 213 to overlap with the first light conversion layer QDL1 on the third-direction DR3, a second color filter CF2 is formed to overlap with the second light conversion layer QDL2 on the third-direction DR3, and a third color filter CF3 is formed to overlap with the light-transmitting layer TPL on the third-direction DR3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can all be formed in the region on the third-direction DR3 that overlaps with the first light-shielding layer BM1 and the second light-shielding layer BM2.

[0239] Then, the fifth organic membrane 214 is formed on the first color filter CF1, the second color filter CF2 and the third color filter CF3.

[0240] Figure 25 This is a perspective view of a smartwatch 1000_1 including a display device 10_1 according to one embodiment.

[0241] refer to Figure 25 The display device 10_1 according to the embodiment can be applied to a smartwatch 1000_1, which is a type of smart device.

[0242] Figure 26 and Figure 27 This is an example view of a virtual reality (VR) device including a display device according to one embodiment.

[0243] refer to Figure 26 and Figure 27 According to an embodiment, the VR device's head-mounted display device 1000_2 includes a first display device 10_2, a second display device 10_3, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical element 1510, a second optical element 1520, and a control circuit board 1600.

[0244] The first display device 10_2 provides an image to the user's left eye, and the second display device 10_3 provides an image to the user's right eye. Each of the first display device 10_2 and the second display device 10_3 is associated with a reference. Figure 1 and Figure 2 The described display device 10 is substantially the same. Therefore, the description of the first display device 10_2 and the second display device 10_3 will be omitted. Thus, without describing the elements in detail with reference to the accompanying drawings, it can be understood that the elements are at least similar to the corresponding elements described elsewhere in this disclosure.

[0245] The first optical element 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical element 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical element 1510 and the second optical element 1520 may include at least one convex lens.

[0246] The intermediate frame 1400 can be disposed between the first display device 10_2 and the control circuit board 1600, and can also be disposed between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 supports and fixes the first display device 10_2, the second display device 10_3, and the control circuit board 1600.

[0247] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 via connectors. The control circuit board 1600 can convert image sources received from external sources into digital video data (see...). Figure 3 ), and transmits digital video data DATA to the first display device 10_2 and the second display device 10_3 via a connector.

[0248] The control circuit board 1600 can transmit digital video data DATA corresponding to a left image optimized for the user's left eye to the first display device 10_2, and digital video data DATA corresponding to a right image optimized for the user's right eye to the second display device 10_3. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_2 and the second display device 10_3.

[0249] The display device housing 1100 houses a first display device 10_2, a second display device 10_3, a middle frame 1400, a first optical element 1510, a second optical element 1520, and a control circuit board 1600. A cover 1200 is positioned to cover the open surface of the display device housing 1100. The cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Although in Figure 26 and Figure 27 The first eyepiece 1210 and the second eyepiece 1220 are provided separately, but the embodiments in this specification are not necessarily limited to this. The first eyepiece 1210 and the second eyepiece 1220 can also be combined into one.

[0250] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical element 1510, and the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical element 1520. Therefore, the user can view the image of the first display device 10_2 magnified into a virtual image by the first optical element 1510 through the first eyepiece 1210, and can view the image of the second display device 10_3 magnified into a virtual image by the second optical element 1520 through the second eyepiece 1220.

[0251] The headband 1300 secures the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing 1200 are respectively positioned over the user's left and right eyes. When the display device housing 1100 is made lightweight and compact, the head-mounted display device 1000_2 may include, for example... Figure 28 The eyeglasses frame shown is not the headband 1300.

[0252] Furthermore, the head-mounted display device 1000_2 may further include a battery for providing power, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) port, a display port, or a High Definition Multimedia Interface (HDMI) port, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0253] Figure 28 This is a perspective view illustrating a VR device 1000_3 including a display device 10_4 according to one embodiment. Figure 28 The illustration shows that the display device 10_4 according to the embodiment has been applied to the VR device 1000_3 thereon.

[0254] refer to Figure 28 According to an embodiment, the VR device 1000_3 may be a device in the form of glasses. According to an embodiment, the VR device 1000_3 may include a display device 10_4, a left lens 10a, a right lens 10b, a support frame 20, eyeglass temples 30a and 30b, a reflector 40, and a display device housing 50.

[0255] exist Figure 28 In the illustration, VR device 1000_3 is shown as an example of a glasses-type display device including eyeglass temples 30a and 30b. For example, VR device 1000_3 according to the embodiment is not necessarily limited to... Figure 28 The VR device shown in the image can be applied to various other electronic devices in various forms.

[0256] The display device housing 50 may include a display device 10_4 and a reflector 40. The image displayed on the display device 10_4 can be reflected by the reflector 40 and provided to the user's right eye via the right lens 10b. Therefore, the user can view the VR image displayed on the display device 10_4 through their right eye.

[0257] Despite Figure 28 The display device housing 50 is located at the right end of the support frame 20, but the embodiments described herein are not necessarily limited to this. For example, the display device housing 50 may also be located at the left end of the support frame 20. In this case, the image displayed on the display device 10_4 can be reflected by the reflector 40 and provided to the user's left eye through the left lens 10a. Therefore, the user can view the VR image displayed on the display device 10_4 through their left eye. Alternatively, the display device housing 50 may be located at both the right and left ends of the support frame 20. In this case, the user can view the VR image displayed on the display device 10_4 through both their left and right eyes.

[0258] Figure 29 This is a perspective view illustrating a vehicle dashboard and central instrument panel including display devices 10_a to 10_e according to an embodiment. Figure 29 The illustrations show that the display devices 10_a to 10_e according to the embodiments have been applied to the vehicles thereunder.

[0259] refer to Figure 29 According to an embodiment, display devices 10_a to 10_c can be applied to a vehicle's dashboard, a vehicle's central instrument panel, or a central information display (CID) mounted on the vehicle's instrument panel. Furthermore, according to an embodiment, display devices 10_d and 10_e can be applied to interior mirror displays that replace the vehicle's rearview mirror.

[0260] Figure 30 This is a perspective view of a transparent display device including display device 10_5 according to an embodiment.

[0261] refer to Figure 30 According to an embodiment, the display device 10_5 can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_5, but also view the object RS or background located behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion or may be made of a light-transmitting material.

[0262] In the display device and the method of manufacturing the display device according to the embodiment, the contact electrodes of the light-emitting element are spaced apart from the upper surface of the semiconductor stack. Therefore, it is possible to prevent the contact electrodes exposed on the upper surface of the semiconductor stack from being stripped by chemical solutions or the like.

[0263] However, the effects of this disclosure are not necessarily limited to those set forth herein. The above and other effects of this disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, comprising: substrate; Pixel electrodes and common electrodes are disposed on the substrate; An organic layer is disposed on the pixel electrode and the common electrode; A light-emitting element is disposed on the organic layer and includes a semiconductor stack, a first contact electrode, and a second contact electrode, wherein the first contact electrode and the second contact electrode are disposed on one surface of the semiconductor stack; A first connecting electrode is connected to the first contact electrode and the pixel electrode; The second connecting electrode is connected to the second contact electrode and the common electrode; The first side electrode is disposed on the first side of the light-emitting element and the top surface of the first connecting electrode; The second side electrode is disposed on the second side of the light-emitting element and the top surface of the second connecting electrode; A first inclined layer is disposed on the side surface of the first side electrode; and A second inclined layer is disposed on the side surface of the second side electrode. The first side electrode and the second side electrode each have a downward recessed structure between the first side of the light-emitting element and the first sloped layer, and between the second side of the light-emitting element and the second sloped layer, respectively.

2. The display device according to claim 1, wherein, The recessed structure is a structure in which the distance between the top surface of the light-emitting element and the top surface of the first side electrode is longer than the distance between the extension of the top surface of the light-emitting element and the top of the first sloped layer.

3. The display device according to claim 1, wherein, The light-emitting element further includes: A conductive layer is disposed between the organic layer and the semiconductor stack; and A protective film is disposed on at least one side of the conductive layer and on each side of the semiconductor stack. The first contact electrode is disposed on the protective film and connected to the exposed portion of the conductive layer that is not covered by the protective film. The second contact electrode is disposed on the protective film and in a hole that penetrates a portion of the semiconductor stack and the conductive layer.

4. The display device according to claim 3, wherein, The semiconductor stack includes: A first semiconductor layer is disposed on the organic layer and includes a semiconductor material layer doped with a first conductivity type dopant. An active layer is disposed on the first semiconductor layer; and A second semiconductor layer is disposed on the active layer and includes a semiconductor material layer doped with a second conductivity type dopant. Wherein, the hole penetrating the portion of the semiconductor stack exposes the second semiconductor layer, and The second contact electrode is in contact with the exposed second semiconductor layer.

5. The display device according to claim 4, wherein, The first connection electrode is disposed between the first contact electrode and the organic layer, and extends to the pixel electrode on which the organic layer is not disposed. The second connecting electrode is disposed between the second contact electrode and the organic layer, and extends to the common electrode on which the organic layer is not disposed. The first side electrode and the second side electrode are disposed on the entire side surface of the conductive layer, the entire side surface of the first semiconductor layer, and the entire side surface of the active layer, and are disposed on a portion of the side surface of the second semiconductor layer.

6. The display device according to claim 4, wherein, The first connection electrode is disposed between the first contact electrode and the organic layer, and extends to the pixel electrode on which the organic layer is not disposed. The second connecting electrode is disposed between the second contact electrode and the organic layer, and extends to the common electrode on which the organic layer is not disposed. The first side electrode and the second side electrode are disposed on the entire side surface of the conductive layer, the entire side surface of the first semiconductor layer, and the entire side surface of the active layer. In this configuration, the entire side surface of the second semiconductor layer is exposed.

7. The display device according to claim 4, wherein, The first connection electrode is disposed between the first contact electrode and the organic layer, and extends to the pixel electrode on which the organic layer is not disposed. The second connecting electrode is disposed between the second contact electrode and the organic layer, and extends to the common electrode on which the organic layer is not disposed. The first side electrode and the second side electrode are disposed on the entire side surface of the conductive layer and the entire side surface of the first semiconductor layer, and expose the entire side surface of the active layer and the entire side surface of the second semiconductor layer.

8. The display device according to any one of claims 1 to 7, wherein, The width of each of the first and second sloped layers decreases upwards, and the amount of the decrease in width decreases or increases upwards.

9. The display device according to any one of claims 1 to 7, further comprising: The first dummy electrode is disposed on the first side surface of the organic layer and the top surface of the first connecting electrode; and The second dummy electrode is disposed on the second side surface of the organic layer and the top surface of the second connecting electrode. The first connecting electrode, the second connecting electrode, the first dummy electrode, and the second dummy electrode are made of the same material.

10. The display device according to claim 9, comprising: The first dummy tilted layer is disposed on the side surface and the top surface of the first dummy electrode; and The second dummy tilted layer is disposed on the side surface and top surface of the second dummy electrode. The first slope inclined layer, the second slope inclined layer, the first dummy inclined layer, and the second dummy inclined layer all consist of the same material.

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