Display device, method of manufacturing display device, and electronic device including display device

Abstract

The invention relates to a display device, a method of manufacturing the display device, and an electronic device including the display device. The display device includes a substrate including a light emitting area and a non-light emitting area surrounding the light emitting area. The anode electrodes are disposed on the substrate and overlap the light emitting regions, respectively. The first insulating layer is disposed between the substrate and the anode electrode, and includes a trench overlapping the non-emission region. The second insulating layer is disposed between the first insulating layer and the anode electrode. The second insulating layer includes first openings respectively overlapping some of the trenches and fills the remaining trenches.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0066067, filed on May 21, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices. Specifically, this disclosure relates to display devices, methods of manufacturing display devices, and electronic devices including display devices. Background Technology

[0004] With the development of information technology, display devices used to share information with users have become increasingly important. Although many different types of display devices are used in electronic devices, common examples include liquid crystal display (LCD) devices, organic light-emitting diode (OLED) display devices, and so on. Summary of the Invention

[0005] The display device includes a substrate comprising a light-emitting region and a non-light-emitting region surrounding the light-emitting region. An anode electrode is disposed on the substrate and overlaps with the light-emitting region. A first insulating layer is disposed between the substrate and the anode electrode and includes trenches overlapping the non-light-emitting region. A second insulating layer is disposed between the first insulating layer and the anode electrode. The second insulating layer includes first openings that overlap with some of the trenches and fills the remaining trenches.

[0006] The trench may include a first trench defined between adjacent anode electrodes in the anode electrode. A second trench may be spaced apart from the anode electrode and the first trench in a plan view.

[0007] The second insulating layer can fill the second trench, and the first opening can overlap with the first trench respectively.

[0008] The display device may also include a passivation layer disposed between the first insulating layer and the second insulating layer and comprising a material different from the material of the first insulating layer.

[0009] The passivation layer can define a second opening that overlaps with the trench.

[0010] Each of the second openings and each of the grooves can have an undercut shape.

[0011] The display device may also include a light-emitting layer disposed on the anode electrode.

[0012] The light-emitting layer can be disconnected in the region overlapping with the first trench.

[0013] The display device may also include a cathode electrode disposed on the light-emitting layer.

[0014] The cathode electrode can be disconnected in the region overlapping with the first trench.

[0015] A method for manufacturing a display device includes: forming a first insulating layer on a substrate, the substrate including a light-emitting region and a non-light-emitting region surrounding the light-emitting region; forming trenches in the first insulating layer that overlap with the non-light-emitting region; forming a second insulating layer on the first insulating layer to fill the trenches; forming first openings in the second insulating layer by removing portions of the second insulating layer that overlap with some of the trenches; and forming anode electrodes on the second insulating layer that overlap with the light-emitting region.

[0016] The trench may include a first trench and a second trench, and forming the trench may include: forming a first trench between adjacent light-emitting regions in the light-emitting region; and forming a second trench in a plan view that is spaced apart from the light-emitting region and the first trench.

[0017] Forming the first opening may include removing portions of the second insulating layer that overlap with the first trench.

[0018] The method may further include: after forming the first insulating layer and before forming trenches in the first insulating layer, forming a passivation layer on the first insulating layer using a material different from the material of the first insulating layer.

[0019] The method may further include forming a second opening in the passivation layer that overlaps with the non-luminescent region before forming the trench.

[0020] A trench can be formed by removing the portion of the first insulating layer that overlaps with the second opening through an ashing process.

[0021] Each of the second openings and each of the grooves can be formed to have an undercut shape.

[0022] The method may further include: forming a light-emitting layer on the anode electrode such that the light-emitting layer is interrupted in the region overlapping with the first trench.

[0023] The method may further include: forming a cathode electrode on the light-emitting layer such that the cathode electrode is disconnected in the region overlapping with the first trench.

[0024] The first insulating layer can be made of organic materials, and the passivation layer can be made of inorganic materials.

[0025] An electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data, wherein the display device includes: a substrate including a light-emitting region and a non-light-emitting region surrounding the light-emitting region; an anode electrode disposed on the substrate and overlapping the light-emitting region; a first insulating layer disposed between the substrate and the anode electrode and including trenches overlapping the non-light-emitting region; and a second insulating layer disposed between the first insulating layer and the anode electrode, the second insulating layer including first openings overlapping some of the trenches and filling the other trenches in the trenches. Attached Figure Description

[0026] A more complete understanding of this disclosure and its many accompanying aspects will be readily obtained by referring to the following detailed description taken in conjunction with the accompanying drawings, and a better understanding of this disclosure and its many accompanying aspects will be gained.

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 This illustrates an embodiment. Figure 1 A block diagram of one of the sub-pixels.

[0029] Figure 3 This illustrates an embodiment. Figure 2 The circuit diagram of the sub-pixel.

[0030] Figure 4 This illustrates an embodiment. Figure 1 Top view of the display panel.

[0031] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of the display panel.

[0032] Figure 6 This is a cross-sectional view showing the light-emitting structure according to an embodiment.

[0033] Figure 7 This is a cross-sectional view showing the light-emitting structure according to an embodiment.

[0034] Figure 8 This is a top plan view showing pixels according to an embodiment of the present disclosure.

[0035] Figure 9 It is along Figure 8 A sectional view taken from line I-I'.

[0036] Figures 10 to 21 This is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0037] Figure 22 This is a block diagram of an electronic device according to an embodiment.

[0038] Figure 23 Schematic diagrams illustrating various embodiments of the electronic device are shown. Detailed Implementation

[0039] Various modifications can be made to this disclosure, and this disclosure can take many forms. Embodiments of this disclosure will be detailed and described in the following specification and accompanying drawings. However, this disclosure is not necessarily limited to the specific embodiments set forth herein, and should be understood to include all embodiments falling within the spirit and scope of this disclosure, including modifications, equivalents, and substitutions.

[0040] In describing each drawing, the same reference numerals are used for the same constituent elements. While each drawing may represent one or more specific embodiments of the present disclosure, each drawing is drawn to scale so that relative lengths, thicknesses, and angles can be inferred from them. It is to be understood that the invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be varied within the spirit and scope of the present disclosure, for example, thereby allowing for manufacturing limitations, etc. Terms such as first, second, etc., may be used to describe various constituent elements and are not necessarily construed as limiting these constituent elements. These terms may be used to distinguish one constituent element from another. For example, a first constituent element may be referred to as a second constituent element, and similarly, a second constituent element may be referred to as a first constituent element, without departing from the scope of the present disclosure.

[0041] In this application, it should be understood that the terms "comprising," "including," "having," or "configuration" indicate the presence of the features, quantities, steps, operations, constituent elements, portions, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, constituent elements, portions, or combinations thereof. It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" another element, the element may be directly on said other element, or an intervening element may be present. In this specification, when a portion of a layer, film, region, area, plate, etc., is referred to as being formed "on" another portion, the formation direction is not limited to the upper direction, but includes the lateral or lower direction. Conversely, when an element such as a layer, film, region, area, plate, etc., is referred to as being "below" another element, the element may be directly below said other element, or an intervening element may be present.

[0042] In the following description, singular forms include plural forms unless the context clearly indicates singular only.

[0043] Figure 1 A block diagram of a display device according to an embodiment of the present disclosure is shown.

[0044] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0045] The display panel 110 includes sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to the m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to the n-th data line DLn. Here, m and n are positive integers greater than 1.

[0046] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, the subpixels SP can each produce light of a specific color, such as red, green, blue, cyan, magenta, yellow, etc. Two or more subpixels SP can be collectively identified as a single pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can be combined to form a single pixel PXL.

[0047] Gate driver 120 is connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to the first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals in timing synchronization with applied data signals, etc.

[0048] In one embodiment, first light emission control lines EL1 to m-th light emission control lines ELm can also be provided connected to the sub-pixels SP in the row direction. In this case, the gate driver 120 may include a light emission control driver configured to control the first light emission control lines EL1 to m-th light emission control lines ELm, and the light emission control driver can operate under the control of the controller 150.

[0049] The gate driver 120 may be disposed on one side of the display panel 110. However, the implementation is not necessarily limited to this. For example, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, and these drivers may be disposed on one side of the display panel 110 and on the opposite side of the display panel 110. As described above, the gate driver 120 may be disposed in various forms around the display panel 110 according to the implementation.

[0050] Data driver 130 is connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In an embodiment, data control signal DCS may include source start pulse, source shift clock, source output enable signal, etc.

[0051] The data driver 130 can use voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image is displayed on the display panel 110.

[0052] In one embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0053] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to the constituent elements of display device 100. For example, voltage generator 140 can be configured to generate multiple voltages by receiving an input voltage from a source external to display device 100, adjusting the received voltage, and calibrating the adjusted voltage.

[0054] Voltage generator 140 can generate a first electrical voltage VDD and a second electrical voltage VSS, and can provide the generated first electrical voltage VDD and second electrical voltage VSS to the sub-pixel SP. The first electrical voltage VDD can have a relatively high voltage level, and the second electrical voltage VSS can have a lower voltage level than the first electrical voltage VDD. In an embodiment, the first electrical voltage VDD or the second electrical voltage VSS can be provided by an external device of the display device 100.

[0055] Furthermore, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing the electrical characteristics of the transistor and / or light-emitting element of the sub-pixel SP, a predetermined reference voltage can be applied to the first data line DL1 to the nth data line DLn, and voltage generator 140 can generate this reference voltage.

[0056] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0057] The controller 150 can convert the input image data IMG into image data DATA suitable for use with the display device 100 or display panel 110. In one embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to sub-pixels SP suitable for use with row units.

[0058] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, the data driver 130, voltage generator 140, and / or controller 150 may be configured as components separate from the driver integrated circuit (DIC).

[0059] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the ambient temperature and generate temperature data TEP representing the sensed temperature. In an embodiment, the temperature sensor 160 may be adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0060] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In one embodiment, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can control the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0061] Figure 2 This illustrates an embodiment. Figure 1 A block diagram of one of the sub-pixels. Figure 2 In Figure 1 Among the sub-pixels SP, sub-pixels SPij set in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) are shown as an example.

[0062] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0063] The light-emitting element (LD) is connected between the first power voltage node VDDN and the second power voltage node VSSN. In this case, the first power voltage node VDDN is the transmission... Figure 1 The first power voltage node VDD, and the second power voltage node VSSN are the transmission nodes. Figure 1 The node of the second power voltage VSS.

[0064] The anode AND of the light-emitting element LD can be connected to the first power voltage node VDDN via the sub-pixel circuit SPC, and the cathode CTD of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode AND of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0065] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm Figure 1 The i-th light emission control line ELi among the first light emission control line EL1 to the m-th light emission control line ELm, and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. The sub-pixel circuit SPC is configured to control the light-emitting element LD based on the signals received through these signal lines.

[0066] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an implementation, as... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the respective sub-gate lines.

[0067] The sub-pixel circuit (SPC) can operate in response to a light emission control signal received via the i-th light emission control line (ELi). In an embodiment, the i-th light emission control line (ELi) may include one or more sub-light emission control lines. When the i-th light emission control line (ELi) includes two or more sub-light emission control lines, the sub-pixel circuit (SPC) can operate in response to a light emission control signal received via the respective sub-light emission control line.

[0068] The sub-pixel circuit SPC can receive data signals via the j-th data line DLj. The SPC can store a voltage corresponding to the data signal in response to the gate signal received via the first sub-gate line SGL1 and / or the second sub-gate line SGL2. In response to the light emission control signal received via the i-th light emission control line ELi, the SPC can adjust the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0069] Figure 3 This illustrates an embodiment. Figure 2 The circuit diagram of the sub-pixel.

[0070] refer to Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0071] The sub-pixel circuit (SPC) can be connected to the i-th gate line GLi', the i-th light emission control line ELi', and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' may also include a third sub-gate line SGL3. Compared to... Figure 2 Compared to the i-th light emission control line ELi, the i-th light emission control line ELi' may include a first sub-light emission control line SEL1 and a second sub-light emission control line SEL2.

[0072] The sub-pixel circuit SPC may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0073] The first transistor T1 is connected between the first power voltage node VDDN and the first node N1. The gate (or gate electrode) of the first transistor T1 is connected to the second node N2, and therefore, the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0074] The second transistor T2 is connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 is connected to the first sub-gate line SGL1, and therefore, the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0075] The third transistor T3 is connected between the first node N1 and the second node N2. The gate of the third transistor T3 is connected to the second sub-gate line SGL2, and therefore, the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0076] The fourth transistor T4 is connected between the first node N1 and the anode AND of the light-emitting element LD. The gate of the fourth transistor T4 is connected to the second sub-light-emitting control line SEL2, and therefore, the fourth transistor T4 can be turned on in response to the light-emitting control signal of the second sub-light-emitting control line SEL2.

[0077] The fifth transistor T5 is connected between the anode AND of the light-emitting element LD and the initialization voltage node VinTN. The initialization voltage node VinTN is configured to transmit the initialization voltage. In this embodiment, the initialization voltage can be generated by… Figure 1 The voltage generator 140 provides the initial voltage. In an embodiment, the initial voltage can be provided to the display device 100 by an external device. The gate of the fifth transistor T5 is connected to the third sub-gate line SGL3, and therefore, the fifth transistor T5 can be turned on in response to the gate signal of the third sub-gate line SGL3.

[0078] The sixth transistor T6 is connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 is connected to the first sub-light emission control line SEL1, and therefore, the sixth transistor T6 can be turned on in response to the light emission control signal of the first sub-light emission control line SEL1.

[0079] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power voltage node VDDN and the second node N2.

[0080] As described above, the sub-pixel circuit SPC may include first transistors T1 to sixth transistors T6, a first capacitor C1, and a second capacitor C2. However, the implementation is not necessarily limited to this. The sub-pixel circuit SPC can be implemented as one of various circuits including multiple transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the implementation of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-light emission control lines included in the i-th light emission control line ELi' can be varied.

[0081] The first transistor T1 through the sixth transistor T6 can be P-type transistors. Each of the first transistor T1 through the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the implementation is not necessarily limited to this. For example, at least one of the first transistor T1 through the sixth transistor T6 can be replaced with an N-type transistor.

[0082] In the implementation, the first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor and oxide semiconductor.

[0083] The light-emitting element (LD) may include an anode electrode AND, a cathode electrode CTD, and a light-emitting layer. The light-emitting layer may be disposed between the anode electrode AND and the cathode electrode CTD. After the data signal transmitted through the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on when the light emission control signals of the first sub-light emission control line SEL1 and the second sub-light emission control line SEL2 are at a low level. Furthermore, the first transistor T1 may be turned on according to the voltage of the second node N2, and therefore, current may flow from the first power voltage node VDDN to the second power voltage node VSSN. The light-emitting element LD may emit light according to the amount of flowing current.

[0084] Figure 4 This illustrates an embodiment. Figure 1 Top view of the display panel.

[0085] refer to Figure 4 As Figure 1 The display panel DP of the embodiment of the display panel 110 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0086] The display panel (DP) may include a substrate (SUB), sub-pixels (SP), and pads (PD).

[0087] Subpixels SP are disposed on the substrate SUB in the display area DA. The subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the implementation is not necessarily limited to this. For example, the subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the subpixels SP can be arranged in... Shape settings, where, This is an arrangement of light-emitting areas manufactured by Samsung. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0088] Two or more of the multiple sub-pixels SP can form a single pixel PXL.

[0089] The components used to control the sub-pixel SP can be disposed on the substrate SUB in the non-display area NDA. For example, wiring connected to the sub-pixel SP (such as...) Figure 1The first gate line GL1 to the m gate line GLm and the first data line DL1 to the nth data line DLn can be set in the non-display area NDA.

[0090] Figure 1 The gate driver 120, data driver 130, voltage generator 140, controller 150, and / or temperature sensor 160 can be integrated into the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 can be mounted on the display panel DP and can be located in the non-display area NDA. In one embodiment, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In another embodiment, the temperature sensor 160 can be located in the non-display area NDA to detect the temperature of the display panel DP.

[0091] The pad PD is disposed on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wiring. For example, the pad PD can be connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0092] The pad PD can connect the display panel DP to the display device 100 (see...). Figure 1 Other constituent elements. In an embodiment, the voltages and signals required for the operation of the constituent elements included in the display panel DP can be transmitted from the pads PD via... Figure 1 The driver integrated circuit (DIC) is provided. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad PD. For example, a first power voltage VDD and a second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0093] In one implementation, the circuit board can be electrically connected to the pads (PD) using a conductive adhesive such as an anisotropic conductive film. In this case, the circuit board can be a flexible film or a flexible printed circuit board (FPCB) made of a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board to be electrically connected to the pads (PD).

[0094] In implementations, the display area DA can have various shapes. The display area DA can have a closed loop shape with sides including straight lines and / or curves. For example, the display area DA can have shapes such as polygonal shapes, circular shapes, semi-circular shapes, and elliptical shapes.

[0095] In some embodiments, the display panel DP may have a flat display surface. In some embodiments, the display panel DP may have a display surface that is at least partially rounded. In some embodiments, the display panel DP may be flexible, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0096] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of the display panel. Figure 5 In the diagram, for clarity and conciseness, the display panel DP is schematically shown. Figure 4 The portions corresponding to pixels PXL1 and PXL2 within the pixel PXL. The portions corresponding to the remaining pixels of the display panel DP can be configured similarly.

[0097] refer to Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1 to a third sub-pixel SP3. However, the implementation is not necessarily limited to this. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0098] exist Figure 5 In the diagram, when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2, the first sub-pixel SP1 to the third sub-pixel SP3 are shown as having a quadrilateral shape and the same size. However, the implementation is not necessarily limited to this. The first sub-pixel SP1 to the third sub-pixel SP3 can be modified to have various shapes.

[0099] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), an outer coating layer (OC), and a cover window (CW).

[0100] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB can include a glass substrate. As an example, the substrate SUB can include a polyimide (PI) substrate. For example, the substrate SUB can include a silicon wafer substrate formed using semiconductor processes.

[0101] In embodiments, the substrate SUB can be made of a flexible material that is bendable or foldable, and can have a single-layer or multi-layer structure. For example, flexible materials may include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and / or cellulose acetate propionate. However, embodiments are not necessarily limited to this.

[0102] A pixel circuit layer (PCL) is disposed on a substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may be used as at least some of circuit elements, wiring, etc.

[0103] The conductive pattern may include copper, but implementations are not necessarily limited to this.

[0104] The circuit elements may include a sub-pixel circuit SPC for each of the first sub-pixel SP1 to the third sub-pixel SP3 (see [link to circuit diagram]). Figure 2 The sub-pixel circuit (SPC) may include transistors and one or more capacitors. Each transistor may include a semiconductor portion and a gate electrode overlapping the semiconductor portion, the semiconductor portion including a source region, a drain region, and a channel region. In an embodiment, when the substrate SUB is a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern in the pixel circuit layer PCL. In an embodiment, when the substrate SUB is a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other on a third direction DR3, wherein an insulating layer is present between the electrodes.

[0105] The wiring of the pixel circuit layer (PCL) may include signal lines, such as gate lines, light emission control lines, and data lines, connected to each of the first sub-pixels SP1 to the third sub-pixels SP3. The wiring may also include connections to... Figure 2 The wiring for the first power voltage node VDDN. Additionally, the wiring may include connections to... Figure 2 Wiring of the second power voltage node VSSN.

[0106] The light-emitting element layer (LDL) may include an anode electrode (AND), a pixel-defining film (PDL), a light-emitting layer (EML), and a cathode electrode (CTD).

[0107] The anode AND can be disposed on the pixel circuit layer PCL. The anode AND can contact the circuit elements of the pixel circuit layer PCL. The anode AND can include an opaque conductive material capable of reflecting light, but the implementation is not necessarily limited to this.

[0108] A pixel-defining film (PDL) is disposed on the anode electrode AND. The PDL may include an opening OP that exposes a portion of each of the anode electrodes AND. The opening OP of the PDL can be understood as a light-emitting region corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0109] In this embodiment, the pixel-defining film (PDL) may include an inorganic material. In this case, the pixel-defining film (PDL) may include multiple stacked inorganic layers. For example, the pixel-defining film (PDL) may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x In an implementation, the pixel-defining film (PDL) may include organic materials. However, the materials of the pixel-defining film (PDL) are not necessarily limited to this.

[0110] The light-emitting layer (EML) can be disposed on a portion of the pixel-defined film (PDL) of the anode electrode AND that is exposed by an opening (OP). The EML may include an organic light-emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0111] In one implementation, the light-emitting layer EML can fill the opening OP of the pixel-defining film PDL and can be disposed entirely on the upper part of the pixel-defining film PDL. For example, the light-emitting layer EML can extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least some of the functional layers in the light-emitting layer EML can be broken or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, the implementation is not necessarily limited to this. For example, the portions of the light-emitting layer EML corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 are partially separated from each other, and each of these portions can overlap with the opening OP of the pixel-defining film PDL.

[0112] The cathode electrode CTD can be disposed on the emissive layer EML. The cathode electrode CTD can extend across the first sub-pixel SP1 to the third sub-pixel SP3. Therefore, the cathode electrode CTD can be configured as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3. Similar to the emissive layer EML, the cathode electrode CTD can also be broken or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3.

[0113] The cathode electrode CTD can be a thin metal layer with a thickness sufficient to transmit light emitted from the emissive layer EML. The cathode electrode CTD can be made of a metallic material or a transparent conductive material and can be relatively thin. In embodiments, the cathode electrode CTD can include various transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and / or gallium tin oxide. In embodiments, the cathode electrode CTD can include silver (Ag) and / or magnesium (Mg). However, the material of the cathode electrode CTD is not necessarily limited to these.

[0114] One of the anode electrode AND, the portion of the light-emitting layer EML overlapping the anode electrode AND, and the portion of the cathode electrode CTD overlapping the anode electrode AND can be understood as configuring a light-emitting element LD (see [link]). Figure 2 For example, each of the light-emitting elements in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AND, a portion of the light-emitting layer EML overlapping the anode electrode AND, and a portion of the cathode electrode CTD overlapping the anode electrode AND. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AND and electrons injected from the cathode electrode CTD are transported to the light-emitting layer EML to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer EML. The wavelength range of the generated light can be determined according to the configuration of the light-emitting layer EML.

[0115] The encapsulation layer TFE is disposed on the cathode electrode CTD. The encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In embodiments, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic films may include silicon nitride, silicon oxide, or silicon oxynitride (SiO2). x N y For example, organic films can include organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene. However, the materials of the organic and inorganic films of the encapsulation layer TFE are not necessarily limited to these.

[0116] The encapsulation layer TFE may also include aluminum oxide (AlO) xA thin film containing aluminum oxide can be disposed on the upper surface of the TFE encapsulation layer facing the optical functional layer OFL and / or the lower surface of the TFE encapsulation layer facing the light-emitting element layer LDL to improve the encapsulation efficiency of the TFE encapsulation layer.

[0117] Thin films containing alumina can be formed by atomic layer deposition (ALD). However, implementation is not necessarily limited to this. The encapsulation layer TFE can also comprise thin films made of various materials suitable for improving encapsulation efficiency.

[0118] The optical functional layer (OFL) is disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0119] A color filter layer (CFL) is disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL is configured to selectively output light within a wavelength range corresponding to each sub-pixel or light of a color corresponding to each sub-pixel by filtering light emitted from the emissive layer (EML). The CFL includes color filters (CF) corresponding to first sub-pixels SP1 through third sub-pixels SP3, respectively, and each of the color filters (CF) allows light within a wavelength range corresponding to the sub-pixel to pass through. For example, the color filter (CF) corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter (CF) corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter (CF) corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the emissive layer (EML) of each sub-pixel, at least some of the color filters (CF) may be omitted.

[0120] A lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixels SP1 through SP3, respectively. Each of the lenses LS can improve light output efficiency by directing light emitted from the emissive layer EML along a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the outer coating OC. In embodiments, the lenses LS may include organic materials. In embodiments, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not necessarily limited to these.

[0121] In this implementation, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA can be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel-defining film PDL. For example, in the central region of the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS can be aligned with or overlap with the center of the opening OP of the corresponding pixel-defining film PDL. For example, in the central region of the display area DA, the opening OP of the pixel-defining film PDL can completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS can be shifted in a planar direction from the center of the opening OP of the corresponding pixel-defining film PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel-defining film PDL can partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, light emitted from the emissive layer EML can be effectively output in the normal direction of the display surface. Light emitted from the emissive layer EML at the outside of the display area DA can be effectively output in a direction tilted at a predetermined angle relative to the normal direction of the display surface.

[0122] An outer coating OC can be disposed on the lens array LA. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting layer EML, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layers from foreign matter such as dust and moisture. For example, the outer coating OC can include inorganic and / or organic insulating films. For example, the outer coating OC can include epoxy resin, but implementations are not necessarily limited to this. The outer coating OC can have a lower refractive index than the lens array LA.

[0123] A cover window (CW) may be disposed on the outer coating (OC). The cover window (CW) is configured to protect the layer beneath it. The cover window (CW) may have a higher refractive index than the outer coating (OC). The cover window (CW) may include glass, but the implementation is not necessarily limited to this. For example, the cover window (CW) may be encapsulation glass configured to protect the constituent elements disposed thereunder. In some implementations, the cover window (CW) may be omitted.

[0124] Figure 6 This is a cross-sectional view showing the light-emitting structure according to an embodiment.

[0125] refer to Figure 6 The light-emitting layer EML can have a series structure in which the first light-emitting part EU1 and the second light-emitting part EU2 are stacked.

[0126] Each of the first light-emitting portion EU1 and the second light-emitting portion EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting portion EU1 may include a first light-emitting layer EML1, a first electron transport portion ETU1, and a first hole transport portion HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport portion ETU1 and the first hole transport portion HTU1. The second light-emitting portion EU2 may include a second light-emitting layer EML2, a second electron transport portion ETU2, and a second hole transport portion HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport portion ETU2 and the second hole transport portion HTU2.

[0127] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include a hole injection layer and / or a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc., as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0128] Each of the first electron transport section ETU1 and the second electron transport section ETU2 may include an electron injection layer and / or an electron transport layer, and may further include an electron buffer layer and a hole blocking layer as needed. The first electron transport section ETU1 and the second electron transport section ETU2 may have the same configuration or different configurations.

[0129] A connecting layer, which can be provided in the form of a charge generation layer CGL, can be disposed between the first light-emitting portion EU1 and the second light-emitting portion EU2 to connect the first light-emitting portion EU1 and the second light-emitting portion EU2 to each other. In an embodiment, the charge generation layer CGL can have a stacked structure of p-type dopant layers and n-type dopant layers. For example, the p-type dopant layer can include p-type dopants such as HAT-CN, TCNQ, and NDP-9, and the n-type dopant layer can include alkali metals, alkaline earth metals, lanthanides, or combinations thereof. However, the embodiment is not necessarily limited to this.

[0130] In one embodiment, the first emissive layer EML1 and the second emissive layer EML2 can produce light of different colors. Light emitted from each of the first emissive layer EML1 and the second emissive layer EML2 can be mixed to be identified as white light. For example, the first emissive layer EML1 can produce blue light, and the second emissive layer EML2 can produce yellow light. In another embodiment, the second emissive layer EML2 may include a structure in which a first sub-emissive layer configured to produce red light and a second sub-emissive layer configured to produce green light are stacked. The red and green light can be mixed to provide yellow light. In this case, an intermediate layer configured to perform the function of transporting holes and / or preventing the transport of electrons may also be disposed between the first and second sub-emissive layers.

[0131] In this embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same color.

[0132] The light-emitting layer (EML) can be formed by vacuum deposition, inkjet printing, etc., but the implementation method is not necessarily limited to these methods.

[0133] Figure 7 This is a cross-sectional view showing the light-emitting structure according to an embodiment.

[0134] refer to Figure 7 The light-emitting layer EML' can have a series structure in which the first light-emitting portion EU1' to the third light-emitting portion EU3' are stacked.

[0135] Each of the first light-emitting portions EU1' to the third light-emitting portions EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting portion EU1' may include a first light-emitting layer EML1', a first electron transport portion ETU1', and a first hole transport portion HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport portion ETU1' and the first hole transport portion HTU1'. The second light-emitting portion EU2' may include a second light-emitting layer EML2', a second electron transport portion ETU2', and a second hole transport portion HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport portion ETU2' and the second hole transport portion HTU2'. The third light-emitting portion EU3' may include a third light-emitting layer EML3', a third electron transport portion ETU3', and a third hole transport portion HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport portion ETU3' and the third hole transport portion HTU3'.

[0136] Each of the first hole transport section HTU1' to the third hole transport section HTU3' may include a hole injection layer and / or a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc., as needed. The first hole transport section HTU1' to the third hole transport section HTU3' may have the same configuration or different configurations.

[0137] Each of the first electron transport section ETU1' to the third electron transport section ETU3' may include an electron injection layer and / or an electron transport layer, and may further include an electron buffer layer and a hole blocking layer as needed. The first electron transport section ETU1' to the third electron transport section ETU3' may have the same configuration or different configurations.

[0138] The first charge generation layer CGL1' is disposed between the first light-emitting portion EU1' and the second light-emitting portion EU2'. The second charge generation layer CGL2' is disposed between the second light-emitting portion EU2' and the third light-emitting portion EU3'.

[0139] In this embodiment, the first light-emitting layer EML1' to the third light-emitting layer EML3' can produce light of different colors. The light emitted by each of the first light-emitting layer EML1' to the third light-emitting layer EML3' can be mixed to be observed as white light. For example, the first light-emitting layer EML1' can produce blue light, the second light-emitting layer EML2' can produce green light, and the third light-emitting layer EML3' can produce red light.

[0140] In an implementation, two or more of the first light-emitting layers EML1' to the third light-emitting layers EML3' can produce light of the same color.

[0141] Figure 8 This is a top plan view showing pixels according to an embodiment of the present disclosure.

[0142] For ease of explanation, Figure 8 Only the anode electrode AND, the first trench TRC1, and the second trench TRC2 are shown.

[0143] refer to Figure 8 Pixel PXL may include first sub-pixels SP1 to third sub-pixels SP3 disposed on the first direction DR1. Pixel PXL may include a light-emitting region EMA and a non-light-emitting region NEA surrounding the light-emitting region EMA.

[0144] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0145] The first luminescent region EMA1 can be where light emanates from the luminescent layer EML (see...). Figure 5 The second emitting region EMA2 can be the region in which light is emitted from the portion of the emitting layer EML corresponding to the second sub-pixel SP1. The third emitting region EMA3 can be the region in which light is emitted from the portion of the emitting layer EML corresponding to the third sub-pixel SP3.

[0146] The first anode electrode AND1 can be disposed in the first light-emitting region EMA1. The second anode electrode AND2 can be disposed in the second light-emitting region EMA2. The third anode electrode AND3 can be disposed in the third light-emitting region EMA3.

[0147] In one implementation, pixel PXL may include a trench TRC that overlaps with the non-light-emitting region NEA. The trench TRC may include a first trench TRC1 and a second trench TRC2.

[0148] The first trench TRC1 can be defined between adjacent anode electrodes AND. For example, the first trench TRC1 can be defined between adjacent light-emitting regions EMA. The first trench TRC1 can be provided not only between light-emitting regions EMA in a single pixel PXL, but also between adjacent pixels PXL.

[0149] The first trench TRC1 may extend between the light-emitting regions EMA in either the first direction DR1 or the second direction DR2. For example, the first trench TRC1 and the light-emitting regions EMA may completely overlap each other in the first direction DR1. The first trench TRC1 is disposed between adjacent light-emitting regions EMA and completely overlaps with the light-emitting regions EMA in the first direction DR1, such that the light-emitting layer EML disposed on the anode electrode AND can be completely separated between adjacent light-emitting regions EMA (see...). Figure 9 ).

[0150] In a plan view, the second trench TRC2 can be spaced apart from the anode electrode AND and the first trench TRC1. Unlike the first trench TRC1, the second trench TRC2 is not configured to disconnect the light-emitting layer EML, therefore the second trench TRC2 can have various shapes.

[0151] exist Figure 8In the diagram, each of the first light-emitting regions EMA1 to the third light-emitting regions EMA3 is represented by a dashed box defined along the edge of the anode electrode AND that overlaps with each of the first light-emitting regions EMA1 to the third light-emitting regions EMA3.

[0152] For example, the pixel defining film may cover the edges of the first anode electrode AND1 to the third anode electrode AND3, and the portions of the first anode electrode AND1 to the third anode electrode AND3 not covered by the pixel defining film can be understood as the first light-emitting region EMA1 to the third light-emitting region EMA3. However, the embodiments according to this disclosure are not necessarily limited thereto. For example, it can be understood that the first light-emitting region EMA1 to the third light-emitting region EMA3 is defined by a first trench TRC1. For example, the first light-emitting region EMA1 to the third light-emitting region EMA3 may be separated by the first trench TRC1, and the non-light-emitting region NEA may overlap with the first trench TRC1. The first light-emitting region EMA1 may be defined by at least one first trench TRC1 disposed between the first anode electrode AND1 and an anode electrode adjacent to the first anode electrode AND1 (e.g., the second anode electrode AND2, and the third anode electrode AND3 adjacent to another pixel PXL). The second light-emitting region EMA2 may be defined by at least one first trench TRC1 disposed between the second anode electrode AND2 and an anode electrode adjacent to the second anode electrode AND2 (e.g., the first anode electrode AND1 and the third anode electrode AND3). The third light-emitting region EMA3 may be defined by at least one first trench TRC1 disposed between the third anode electrode AND3 and an anode electrode adjacent to the third anode electrode AND3 (e.g., the second anode electrode AND2, and the first anode electrode AND1 of another pixel PXL). As another example, each of the first light-emitting regions EMA1 to the third light-emitting region EMA3 may be defined as having a region in which an anode electrode AND corresponding to each of the first light-emitting regions EMA1 to the third light-emitting region EMA3 is disposed.

[0153] Therefore, the first light-emitting region EMA1 to the third light-emitting region EMA3 can be defined in various ways. In the following text, for better understanding and ease of description, the first light-emitting region EMA1 to the third light-emitting region EMA3 are respectively described as being defined by the portions of the first anode electrode AND1 to the third anode electrode AND3 that are not covered by the pixel-defining film.

[0154] Figure 9 It shows along Figure 8 A sectional view taken from line I-I'.

[0155] refer to Figure 8 and Figure 9The pixel circuit layer PCL can be disposed on the substrate SUB. The pixel circuit layer PCL may include a back metal layer BML, a first capacitor electrode CPE1, a buffer layer BFR, a second active electrode ACT2, a third active electrode ACT3, a gate insulating layer GI, a second gate electrode GAT2, a third gate electrode GAT3, a second capacitor electrode CPE2, an interlayer insulating layer ILD, a first connection electrode CP1, a first passivation layer PVX1, a first insulating layer ISL1, a second connection electrode CP2, a second passivation layer PVX2, and a second insulating layer ISL2.

[0156] The back metal layer BML and the first capacitor electrode CPE1 can be disposed on the substrate SUB. The buffer layer BFR can be disposed on the substrate SUB, and the buffer layer BFR covers the back metal layer BML and the first capacitor electrode CPE1.

[0157] The second active electrode ACT2 and the third active electrode ACT3 can be disposed on the buffer layer BFR. The gate insulating layer GI can be disposed on each of the second active electrode ACT2 and the third active electrode ACT3. The gate insulating layer GI can have an island shape. The second gate electrode GAT2 can be disposed on the gate insulating layer GI on the second active electrode ACT2. The second active electrode ACT2 and the second gate electrode GAT2 can form a second transistor. The third gate electrode GAT3 can be disposed on the gate insulating layer GI on the third active electrode ACT3. The third active electrode ACT3 and the third gate electrode GAT3 can form a third transistor.

[0158] The gate insulating layer GI can also be disposed on the buffer layer BFR. The second capacitor electrode CPE2 can be disposed on the gate insulating layer GI on the buffer layer BFR. The second capacitor electrode CPE2 overlaps with the first capacitor electrode CPE1 and can form a capacitor.

[0159] The interlayer insulating layer (ILD) can be disposed on the buffer layer (BFR), and the ILD covers the second active electrode (ACT2), the third active electrode (ACT3), the second capacitor electrode (CPE2), the gate insulating layer (GI), the second gate electrode (GAT2), and the third gate electrode (GAT3).

[0160] The first connecting electrode CP1 can be disposed on the interlayer insulating layer (ILD). The first connecting electrode CP1 can be connected to the second active electrode ACT2, the third active electrode ACT3, and the back metal layer (BML) disposed thereunder. The first passivation layer PVX1 can be disposed on the interlayer insulating layer (ILD) and can cover the first connecting electrode CP1. Along the contour of the first connecting electrode CP1, the first passivation layer PVX1 can have substantially the same thickness.

[0161] A first insulating layer ISL1 may be disposed on a first passivation layer PVX1. The first insulating layer ISL1 can planarize the upper surface. In an embodiment, the first insulating layer ISL1 may include an organic material.

[0162] In one embodiment, the first insulating layer ISL1 may include a trench TRC overlapping the non-emitting region NEA. The trench TRC may include a first trench TRC1 and a second trench TRC2. The first trench TRC1 may be defined between adjacent emitting regions EMA. The second trench TRC2 may be defined in a region spaced apart from the emitting regions EMA and the first trench TRC1 in a plan view. Gases formed in the first insulating layer ISL1 during the process can be discharged through the first trench TRC1 and the second trench TRC2.

[0163] The second connecting electrode CP2 can be disposed on the first insulating layer ISL1. The second connecting electrode CP2 can be connected to the first connecting electrode CP1 below it.

[0164] A second passivation layer PVX2 may be disposed on the first insulating layer ISL1, and the second passivation layer PVX2 covers the second connection electrode CP2. Unlike the first insulating layer ISL1, the second passivation layer PVX2 may include an inorganic material. Along the contour of the second connection electrode CP2, the second passivation layer PVX2 may have substantially the same thickness.

[0165] In one embodiment, the second passivation layer PVX2 may define a second opening OP2 that overlaps with the trench TRC of the first insulating layer ISL1. The overlapping second opening OP2 and the trench TRC may each have an undercut shape. For example, the area of ​​each of the second openings OP2 may be smaller than the area of ​​each of the trench TRC. Therefore, the second passivation layer PVX2 adjacent to the second opening OP2 may protrude from the first insulating layer ISL1 adjacent to the trench TRC.

[0166] The second insulating layer ISL2 can be disposed on the second passivation layer PVX2. The second insulating layer ISL2 may include an organic material. The second insulating layer ISL2 can planarize the upper surface.

[0167] In one embodiment, the second insulating layer ISL2 may include first openings OP1 that overlap with some of the trenches TRC. The second insulating layer ISL2 may fill the remaining portion of the trenches TRC except for the portion overlapping with the first openings OP1. In this case, some of the trenches TRC may be the first trenches TRC1. For example, the second insulating layer ISL2 may define first openings OP1 that overlap with the first trenches TRC1 and may fill the second trenches TRC2.

[0168] Therefore, the overlapping first trench TRC1, the second opening OP2 and the first opening OP1 can form a large trench, and the overlapping second trench TRC2 and the second opening OP2 can be filled by the second insulating layer ISL2 to flatten it.

[0169] The light-emitting element layer (LDL) can be disposed on the second insulating layer (ISL2). The LDL may include a second anode electrode (AND2), a third anode electrode (AND3), a pixel defining film (PDL), a light-emitting layer (EML), and a cathode electrode (CTD).

[0170] The anode AND can be disposed on the second insulating layer ISL2. The second anode AND2 and the third anode AND3 can overlap with the second light-emitting region EMA2 and the third light-emitting region EMA3, respectively. The second anode AND2 and the third anode AND3 can be connected to the second connecting electrode CP2, respectively.

[0171] A pixel-defining film (PDL) can be disposed on the anode electrode AND. The PDL can define an opening that exposes a portion of each of the anode electrodes AND. The PDL can only cover the edges of each of the anode electrodes AND and can be partially disposed. For example, the PDL may not overlap with the first trench TRC1, the second opening OP2, and the first opening OP1.

[0172] The light-emitting layer EML can be disposed on the second insulating layer ISL2, the anode electrode AND, and the pixel defining film PDL. The light-emitting layer EML can extend entirely on the anode electrode AND and the pixel defining film PDL, and can be interrupted in the region overlapping with the first trench TRC1. For example, the light-emitting layer EML can be interrupted in the non-light-emitting region NEA between adjacent light-emitting regions EMA. Therefore, the light-emitting layer EML includes... Figure 6 and Figure 7 The charge generation layers CGL, CGL1', and CGL2' can be disconnected between the luminescent regions EMA.

[0173] The cathode electrode CTD can be disposed on the light-emitting layer EML. Similar to the light-emitting layer EML, the cathode electrode CTD can extend entirely on the light-emitting layer EML and can be disconnected in the region overlapping with the first trench TRC1. For example, the cathode electrode CTD can be partially disconnected in the non-light-emitting region NEA between adjacent light-emitting regions EMA. The cathode electrode CTD is fully connected on the light-emitting layer EML, allowing the light-emitting layer EML to be disconnected without affecting the voltage transmission of the cathode electrode CTD.

[0174] In this embodiment, the light-emitting layer EML is disconnected due to the trench TRC defined in the lower insulating layer (e.g., the first insulating layer ISL1 and the second insulating layer ISL2) and the passivation layer (e.g., the second passivation layer PVX2), such that the charge-generating layers CGL, CGL1', and CGL2' included in the light-emitting layer EML can be disconnected between the light-emitting regions EMA. Therefore, when the sub-pixels included in the pixel emit light, color mixing between sub-pixels can be prevented, and leakage current can be prevented. Furthermore, the structure of the display panel can be simplified by disconnecting the light-emitting layer EML without adding a separate layer.

[0175] Figures 10 to 21 This is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0176] Figures 10 to 21 The manufacturing process is shown according to the above reference. Figures 1 to 9 The method of the display device 100 according to the described embodiment. Therefore, without referring to the figures for detailed description of the elements, it can be understood that the elements are at least similar to corresponding elements already described elsewhere in this disclosure.

[0177] refer to Figure 10 A back metal layer BML and a first capacitor electrode CPE1 can be formed on a substrate SUB, the substrate SUB including a light-emitting region EMA and a non-light-emitting region NEA surrounding the light-emitting region EMA. A buffer layer BFR can be formed on the substrate SUB, the buffer layer BFR covering the back metal layer BML and the first capacitor electrode CPE1.

[0178] A second active electrode ACT2 and a third active electrode ACT3 can be formed on the buffer layer BFR. A gate insulating layer GI can be formed on each of the second active electrode ACT2 and the third active electrode ACT3. In this case, the gate insulating layer GI can be formed in an island shape. However, the embodiments according to this disclosure are not necessarily limited to this. A second gate electrode GAT2 can be formed on the gate insulating layer GI on the second active electrode ACT2. The second active electrode ACT2 and the second gate electrode GAT2 can form a second transistor. A third gate electrode GAT3 can be formed on the gate insulating layer GI on the third active electrode ACT3. The third active electrode ACT3 and the third gate electrode GAT3 can form a third transistor.

[0179] A gate insulating layer GI can also be formed on the buffer layer BFR. A second capacitor electrode CPE2 can be formed on the gate insulating layer GI on the buffer layer BFR. The second capacitor electrode CPE2 overlaps with the first capacitor electrode CPE1 and can form a capacitor.

[0180] An interlayer insulating layer (ILD) can be formed on the buffer layer BFR, which covers the second active electrode ACT2, the third active electrode ACT3, the second capacitor electrode CPE2, the gate insulating layer GI, the second gate electrode GAT2, and the third gate electrode GAT3.

[0181] A first connection electrode CP1 can be formed on the interlayer insulating layer (ILD). The first connection electrode CP1 can be connected to a second active electrode ACT2, a third active electrode ACT3, and a back metal layer (BML) disposed beneath it via contact holes formed in the ILD and / or the buffer layer (BFR). A first passivation layer (PVX1) can be formed on the ILD and can cover the first connection electrode CP1. Furthermore, contact holes for contact can be formed in the first passivation layer (PVX1).

[0182] refer to Figure 11 The first insulating layer ISL1 can be completely formed on the first passivation layer PVX1. In this embodiment, the first insulating layer ISL1 can be made of an organic material. Furthermore, contact holes overlapping with the contact holes of the first passivation layer PVX1 can be formed in the first insulating layer ISL1.

[0183] refer to Figure 12 A second connection electrode CP2 can be formed on the first insulating layer ISL1. The second connection electrode CP2 can be connected to the first connection electrode CP1 below it through contact holes formed in the first passivation layer PVX1 and the first insulating layer ISL1.

[0184] refer to Figure 13 A second passivation layer PVX2 can be formed on the first insulating layer ISL1, and the second passivation layer PVX2 covers the second connection electrode CP2. The second passivation layer PVX2 can be made of an inorganic material that is a different material from the first insulating layer ISL1.

[0185] refer to Figure 14 Contact holes overlapping with the second connecting electrode CP2 and second openings OP2 overlapping with the non-light-emitting region NEA can be formed in the second passivation layer PVX2. Some of the second openings OP2 can be formed between adjacent light-emitting regions EMA, and other openings in the second openings OP2 can be formed in the non-light-emitting region NEA except between adjacent light-emitting regions EMA.

[0186] refer to Figure 15 A trench TRC can be formed in the first insulating layer ISL1 that overlaps with the non-light-emitting region NEA.

[0187] In one implementation, the portion of the first insulating layer ISL1 overlapping with the second opening OP2 can be removed using a dry ashing process to form the trench TRC. In this case, etching selectivity between organic and inorganic materials can be used. For example, the etching degree of the first insulating layer ISL1, which includes organic materials, can be greater than the etching degree of the second passivation layer PVX2, which includes inorganic materials.

[0188] Therefore, in the plan view, each of the trenches TRC of the first insulating layer ISL1 can be formed to have an area larger than each of the second openings OP2 of the second passivation layer PVX2. For example, each of the second openings OP2 of the second passivation layer PVX2 and each of the trenches TRC of the first insulating layer ISL1 can be formed to have an undercut shape.

[0189] The trench TRC can be configured with a first trench TRC1 and a second trench TRC2. The first trench TRC1 can be a trench TRC formed between adjacent light-emitting regions EMA. The first trench TRC1 can be formed to extend along the length of the light-emitting regions EMA between adjacent light-emitting regions EMA. The second trench TRC2 can be a trench TRC formed to be spaced apart from the light-emitting regions EMA and the first trench TRC1 in a plan view. For example, the trench TRC other than the first trench TRC1 formed between the light-emitting regions EMA can be the second trench TRC2 (see [link]). Figure 8 ).

[0190] refer to Figure 16 A second insulating layer ISL2 can be formed on the second passivation layer PVX2. The second insulating layer ISL2 can be formed by completely filling the trench TRC of the first insulating layer ISL1, the second opening OP2 of the second passivation layer PVX2, and the contact hole.

[0191] refer to Figure 17 A contact hole overlapping with the second connecting electrode CP2 and a first opening OP1 overlapping with the second opening OP2 and the first trench TRC1 can be formed by removing a portion of the second insulating layer ISL2.

[0192] For example, a first opening OP1 can be formed in the second insulating layer ISL2 by removing portions of the second insulating layer ISL2 that overlap with some of the trenches TRC. In this case, "some" in the trenches TRC can refer to the first trench TRC1. For example, the first opening OP1 can be formed in the regions that overlap with the first trench TRC1 and the second opening OP2, respectively.

[0193] In this case, since the second trench TRC2 is used to discharge the gas generated in the first insulating layer ISL1 and is not located between the light-emitting areas EMA, the light-emitting layer EML cannot be disconnected (see...). Figure 20 Therefore, the second trench TRC2 can be filled with the second insulating layer ISL2 to flatten it.

[0194] refer to Figure 18 An anode electrode AND can be formed on the second insulating layer ISL2. The anode electrode AND can be formed to overlap with the light-emitting region EMA. For example, the second anode electrode AND2 can overlap with the second light-emitting region EMA2, and the third anode electrode AND3 can overlap with the third light-emitting region EMA3. The anode electrode AND can be connected to the second connection electrode CP2 below it through contact holes formed in the second passivation layer PVX2 and the second insulating layer ISL2.

[0195] refer to Figure 19 A pixel-defining film (PDL) can be formed on the second insulating layer (ISL2) and the anode electrode (AND). An opening can be formed in the pixel-defining film (PDL) to expose a portion of each of the anode electrodes (AND). The pixel-defining film (PDL) can cover only the edges of each of the anode electrodes (AND) and can be formed in a region that does not overlap with the first trench (TRC1), the second opening (OP2), and the first opening (OP1).

[0196] refer to Figure 20 The light-emitting layer EML can be formed on the second insulating layer ISL2, the anode electrode AND, and the pixel-defining film PDL. The light-emitting layer EML can be completely deposited in the light-emitting region EMA and the non-light-emitting region NEA using an aperture mask.

[0197] Even when the luminescent layer EML is fully deposited, it may be difficult for the luminescent layer EML to fully extend and deposit within each of the first trenches TRC1 due to the undercut shape of each of the second openings OP2 and each of the first trenches TRC1. Therefore, the luminescent layer EML may be interrupted in the regions of the first trenches TRC1 that overlap with the first insulating layer ISL1, respectively. For example, since the second passivation layer PVX2 adjacent to the second opening OP2 protrudes from the first insulating layer ISL1 adjacent to the first trench TRC1, the luminescent layer EML extends and deposits only up to the side surface of the second opening OP2, and may not extend further but may be interrupted in the first trench TRC1.

[0198] Therefore, the light-emitting layer (EML) can be partially disconnected between adjacent light-emitting regions (EMAs). For example, the light-emitting layer (EML) can be partially disconnected between adjacent anode electrodes (ANDs).

[0199] refer to Figure 21The cathode electrode CTD can be formed on the light-emitting layer EML. Alternatively, the cathode electrode CTD can be completely deposited in the light-emitting region EMA and the non-light-emitting region NEA using an aperture mask.

[0200] Even when the cathode electrode CTD is fully deposited, the cathode electrode CTD can be disconnected in the region where it overlaps with the first trench TRC1 of the first insulating layer ISL1, because each of the second openings OP2 and each of the first trenches TRC1 has an undercut shape.

[0201] Therefore, the cathode electrode CTD can be partially disconnected between adjacent luminescent regions EMA. For example, the cathode electrode CTD can be partially disconnected between adjacent anode electrodes AND. However, the cathode electrode CTD can extend completely except for the region overlapping with the first trench TRC1.

[0202] In this implementation, even when the light-emitting layer EML is completely deposited within the light-emitting region EMA and the non-light-emitting region NEA, the EML is partially disconnected between the light-emitting regions EMA due to the undercut shapes of the first trench TRC1, the second opening OP2, and the first opening OP1. This prevents color mixing between the light-emitting regions EMA and prevents leakage current. Furthermore, by forming the first trench TRC1, the second opening OP2, and the first opening OP1 in existing layers (e.g., the first insulating layer ISL1, the second passivation layer PVX2, and the second insulating layer ISL2), no additional processes and masks are required to form separate layers, thereby reducing process costs and improving process efficiency.

[0203] The display device according to the embodiments can be applied to various types of electronic devices. In the embodiments, the electronic device includes the above-described display device, and may also include other modules or devices with additional functions in addition to the display device.

[0204] Figure 22 This is a block diagram of an electronic device according to an embodiment. (Reference) Figure 22 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0205] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. For example, processor 12 may be configured to provide Figure 1 The input image data is IMG.

[0206] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0207] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module. The power conversion module converts the power supplied by the power supply module and generates power for operating the electronic device 10.

[0208] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the embodiment described above. Furthermore, in terms of function, some of the modules included in a single module may be included in the display device, and other modules included in a single module may be disposed separately from the display device. For example, the display module 11 is included in the display device, while the processor 12, memory 13, and power module 14 are not included in the display device and, alternatively, are disposed separately in the electronic device 10.

[0209] Figure 23 Schematic diagrams illustrating various embodiments of the electronic device are shown.

[0210] refer to Figure 23 Various types of electronic devices that implement the application of display devices may include electronic devices that display images, such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e; wearable electronic devices that include display modules, such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c; and automotive electronic devices that include display modules, such as central information displays (CIDs) and interior mirror displays located on the dashboard, center instrument panel, and dashboard of a vehicle 10_3.

[0211] The technical concepts of this disclosure have been specifically described according to various embodiments; however, it should be noted that the foregoing embodiments are provided for illustration only and are not intended to necessarily limit this disclosure. Those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope of this disclosure.

[0212] All changes or modifications to the embodiments described herein and their equivalents shall be construed as being included within the scope of this disclosure.

Claims

1. A display device, comprising: A substrate, comprising a light-emitting region and a non-light-emitting region surrounding the light-emitting region; An anode electrode is disposed on the substrate and overlaps with the light-emitting region; A first insulating layer is disposed between the substrate and the anode electrode, and includes a trench that overlaps with the non-light-emitting region; as well as A second insulating layer is disposed between the first insulating layer and the anode electrode. The second insulating layer includes first openings that overlap with some of the trenches and fill other trenches in the trenches.

2. The display device according to claim 1, wherein, The trench includes: A first trench is defined between adjacent anode electrodes in the anode electrode; and The second trench is spaced apart from the anode electrode and the first trench in the plan view.

3. The display device according to claim 2, in, The second insulating layer fills the second trench, and The first opening overlaps with the first groove.

4. The display device according to claim 2 further includes a passivation layer disposed between the first insulating layer and the second insulating layer and comprising a material different from the material of the first insulating layer.

5. The display device according to claim 4, wherein, The passivation layer defines a second opening that overlaps with the trench.

6. The display device according to claim 5, wherein, Each of the second openings and each of the grooves has an undercut shape.

7. The display device according to claim 6 further includes a light-emitting layer disposed on the anode electrode.

8. The display device according to claim 7, wherein, The light-emitting layer is interrupted in the region overlapping with the first trench.

9. The display device according to claim 8 further includes a cathode electrode disposed on the light-emitting layer.

10. The display device according to claim 9, wherein, The cathode electrode is disconnected in the region that overlaps with the first trench.

11. A method for manufacturing a display device, comprising: A first insulating layer is formed on a substrate, the substrate including a light-emitting region and a non-light-emitting region surrounding the light-emitting region; A trench is formed in the first insulating layer that overlaps with the non-light-emitting area; A second insulating layer is formed on the first insulating layer to fill the trench; A first opening is formed in the second insulating layer by removing some of the portions of the second insulating layer that overlap with the trench; as well as Anode electrodes are formed on the second insulating layer, each overlapping the light-emitting region.

12. The method according to claim 11, in, The trench includes a first trench and a second trench, and The formation of the trench includes: The first trench is formed between adjacent light-emitting areas in the light-emitting area; and The second groove is formed in the plan view and is spaced apart from the light-emitting area and the first groove.

13. The method according to claim 12, wherein, Forming the first opening includes removing portions of the second insulating layer that overlap with the first trench.

14. The method of claim 13, further comprising: After the first insulating layer is formed and before the trench is formed in the first insulating layer, a passivation layer is formed on the first insulating layer using a material different from the material of the first insulating layer.

15. The method of claim 14, further comprising: Before forming the trench, a second opening is formed in the passivation layer that overlaps with the non-luminescent region.

16. The method according to claim 15, wherein, The trench is formed by removing the portion of the first insulating layer that overlaps with the second opening via an ashing process.

17. The method according to claim 16, wherein, Each of the second openings and each of the grooves is formed to have an undercut shape.

18. The method of claim 17, further comprising: A light-emitting layer is formed on the anode electrode such that the light-emitting layer is broken in the region overlapping with the first trench; as well as A cathode electrode is formed on the light-emitting layer such that the cathode electrode is disconnected in the region overlapping with the first trench.

19. The method according to claim 14, in, The first insulating layer is made of organic material, and The passivation layer is made of inorganic material.

20. An electronic device comprising: A processor used to provide input image data; as well as A display device for displaying an image based on the input image. The display device includes: A substrate, comprising a light-emitting region and a non-light-emitting region surrounding the light-emitting region; An anode electrode is disposed on the substrate and overlaps with the light-emitting region; A first insulating layer is disposed between the substrate and the anode electrode, and includes trenches overlapping the non-light-emitting region; and A second insulating layer is disposed between the first insulating layer and the anode electrode. The second insulating layer includes first openings that overlap with some of the trenches and fill other trenches in the trenches.

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