Electronic component fault management method and system

Abstract

The invention relates to the technical field of fault detection, in particular to an electronic component fault management method and system. The method comprises the following steps: collecting real-time data and constructing a real-time fault monitoring data set; reading historical data and constructing a historical reference data set; comparing the real-time fault monitoring data set with the historical reference data set item by item in a corresponding time window to obtain a drift amplitude, and mapping according to the drift amplitude to generate a reverse excitation amplitude instruction; a reverse current signal according to the reverse excitation amplitude instruction is injected into the loop node to be measured, and a Hall null drift amount is determined according to Hall output; outputting an electronic disturbance quantity based on the Hall null drift quantity; therefore, through dynamic data cooperation and an active excitation response mechanism, the problems of missing detection recessive degradation, misjudgment transient interference and single diagnosis dimension of traditional fault management are solved, and the hidden danger recognition precision and the protection reliability are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of fault detection technology, and in particular to a method and system for managing faults in electronic components. Background Technology

[0002] Existing electronic component fault management technologies have limitations: their reliance on fixed threshold judgment mechanisms makes it difficult to adapt to the natural drift of component performance with aging, resulting in the inability to promptly detect progressive faults such as slow insulation degradation, while transient interference can easily trigger malfunctions and shutdowns; monitoring dimensions are limited, such as focusing only on current or temperature parameters, failing to effectively identify micro-arcs caused by contact point degradation or localized overheating caused by magnetic saturation, while equipment status code verification is susceptible to electromagnetic interference, leading to misjudgments; and the response method is passive, typically performing power-off protection after complete insulation failure or overload, lacking pre-fault warning capabilities and safe adjustment under the premise of ensuring load operation. Control measures and historical operating data have not been effectively used for benchmark correction in real-time diagnosis; there are bottlenecks at the hardware level, the sampling rate of high-precision magnetic field detection is insufficient to capture transient anomalies, active excitation and response analysis based on discrete hardware introduces significant delays, and multi-node collaborative diagnosis is limited by the communication and computing overhead of centralized processing architecture; the depth of fault diagnosis is insufficient, the system often only provides simple fault status indications, and cannot distinguish between long-term aging (such as increased equivalent resistance of capacitors) and sudden damage (such as transistor breakdown), key electrical waveform information at the time of fault occurrence is missing, and the dynamic correlation between environmental factors (temperature and humidity) and electrical parameters also lacks quantitative analysis. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for managing electronic component failures to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, an electronic component fault management method is provided, the method comprising the following steps:

[0005] Step S1: Collect real-time data and build a real-time fault monitoring dataset; read historical data and build a historical benchmark dataset;

[0006] Step S2: Compare the real-time fault monitoring dataset and the historical benchmark dataset item by item within the corresponding time window to obtain the drift amplitude, and generate the inverse excitation amplitude command based on the drift amplitude mapping;

[0007] Step S3: Inject the reverse current signal according to the reverse excitation amplitude command into the node of the circuit under test, and determine the Hall zero drift based on the Hall output; output the electronic disturbance based on the Hall zero drift.

[0008] Step S4: Obtain the insulation response bit value; compare the electronic disturbance quantity with the insulation response bit value. If the comparison result falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormal mark is generated and protection measures are implemented.

[0009] This specification provides an electronic component fault management system for executing the above-described electronic component fault management method. The electronic component fault management system includes:

[0010] The data acquisition module is used to collect real-time data and build a real-time fault monitoring dataset; and to read historical data and build a historical benchmark dataset.

[0011] The drift calculation module is used to compare the real-time fault monitoring dataset and the historical benchmark dataset item by item within the corresponding time window to obtain the drift amplitude, and generate the inverse excitation amplitude command based on the drift amplitude mapping.

[0012] The excitation and zero-drift module is used to inject a reverse current signal into the node of the circuit under test according to the reverse excitation amplitude command, and determine the Hall zero-drift amount based on the Hall output; and output the electronic disturbance amount based on the Hall zero-drift amount.

[0013] The response detection module is used to obtain the insulation response bit value; the electronic disturbance quantity is compared with the insulation response bit value. If the comparison result falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormal mark is generated and protection measures are implemented.

[0014] The beneficial effect of this invention is that it constructs a closed-loop data flow from real-time perception to active intervention. First, it uses spatially aligned real-time triples and dynamically updated historical benchmark datasets to form the basis for drift analysis, overcoming the shortcomings of traditional fixed thresholds that cannot track the gradual degradation of components, and enabling the quantification and capture of hidden risks such as slow decline in insulation performance.

[0015] Secondly, by integrating differences in current, voltage, and status codes and suppressing drift amplitudes caused by environmental interference, multi-dimensional electrical characteristics are compressed into precise reverse excitation commands. This drives the hardware to inject strictly synchronized reverse current pulses. This not only transforms traditional passive monitoring into active diagnosis but also extracts hidden magnetic field offset information through Hall zero drift. Subsequently, an electronic disturbance quantity is derived using modulation technology triggered by positive and negative terminal misalignment. This parameter integrates spatial response characteristics and insulation status data, enabling intelligent discrimination of aging trends and sudden faults in dynamic threshold testing. When the disturbance response and insulation degradation degree meet the expected correlation model, safe operation continues, while abnormal correlation triggers millisecond-level shutdown protection and records a complete fault snapshot.

[0016] The resulting data chain significantly improves the early fault detection rate, reduces false alarms caused by environmental fluctuations, and saves key waveforms at the moment of a fault for precise source tracing, providing quantifiable decision-making basis for predictive maintenance of high-reliability electronic systems. Therefore, this invention, through dynamic data collaboration and proactive stimulus response mechanisms, solves the problems of missed detections of hidden degradation, misjudgments of transient interference, and limited diagnostic dimensions in traditional fault management, significantly improving the accuracy of hazard identification and the reliability of protection. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the steps of a method for managing faults in electronic components.

[0018] Figure 2 This is a schematic diagram of current ternary group monitoring;

[0019] Figure 3 This is a schematic diagram of the architecture of an electronic component fault management system.

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical method of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0022] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0023] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] To achieve the above objectives, please refer to Figures 1 to 3 A method for managing faults in electronic components, the method comprising the following steps:

[0025] Step S1: Collect real-time data and build a real-time fault monitoring dataset; read historical data and build a historical benchmark dataset;

[0026] Step S2: Compare the real-time fault monitoring dataset and the historical benchmark dataset item by item within the corresponding time window to obtain the drift amplitude, and generate the inverse excitation amplitude command based on the drift amplitude mapping;

[0027] Step S3: Inject the reverse current signal according to the reverse excitation amplitude command into the node of the circuit under test, and determine the Hall zero drift based on the Hall output; output the electronic disturbance based on the Hall zero drift.

[0028] Step S4: Obtain the insulation response bit value; compare the electronic disturbance quantity with the insulation response bit value. If the comparison result falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormal mark is generated and protection measures are implemented.

[0029] In this embodiment of the invention, reference Figure 1 The diagram shown is a flowchart illustrating the steps of an electronic component fault management method according to the present invention. In this example, the electronic component fault management method includes the following steps:

[0030] Step S1: Collect real-time data and build a real-time fault monitoring dataset; read historical data and build a historical benchmark dataset;

[0031] Preferably, step S1 further includes:

[0032] The real-time current and voltage values ​​are collected sequentially from the starting section, middle section and end section along the node of the circuit under test, and the corresponding feedback status codes are read independently. The real-time values ​​and single codes collected from the starting section, middle section and end section are concatenated with the single codes in the section order to form a real-time triplet to form a real-time fault monitoring dataset.

[0033] Most importantly, historical database records are retrieved, and the archived current value, archived voltage value, and archived status code corresponding to the same starting segment, middle segment, and ending segment are selected in sequence. The archived values ​​and single codes of each historical segment are then concatenated in the same segment order to form a historical benchmark triplet sequence to construct a historical benchmark dataset.

[0034] In this embodiment, on the real-time side, a sensor network deployed in selected sections synchronously acquires the current value, voltage value, and status code returned by the device for each section in spatial order (start-middle-end). These three heterogeneous data elements collected from the same section are combined into a real-time triplet. (For example, the three real-time triplets arranged in segment order—start, middle, and end—are then concatenated to form a real-time fault monitoring dataset, the core structure of which is an ordered, multi-dimensional time-series segment containing spatial location information.) On the historical side, based on the same spatial node definition (start, middle, and end) as the real-time monitoring, archived current values, archived voltage values, and archived status codes recorded for the corresponding section at specific times or under normal conditions in the past are precisely retrieved from the historical database. Similarly, the historical data for each section is combined into a historical baseline triplet. (For example, multiple historical baseline triplets arranged in the same spatial order (from different historical moments) are aggregated into a historical baseline dataset.)

[0035] In one implementation of the present invention, it is assumed that there is an important power supply circuit that needs to be monitored, and a set of measuring devices is installed at the beginning (starting section), the middle (intermediate section), and the end (final section) of this circuit.

[0036] Real-time data acquisition:

[0037] At this moment, the starting device measures a current of 0.5 amperes (A) and a voltage of 220 volts (V), and reports a status of "normal" (status code 0).

[0038] Meanwhile, the intermediate device measured a current of 0.48A, a voltage of 219V, and a status code of 0 (normal).

[0039] Meanwhile, the terminal device measured a current of 0.47A, a voltage of 218V, and a status code of 0 (normal).

[0040] Pack the initial data into a single data packet: (0.5,220,0).

[0041] Pack the intermediate data into another data packet: (0.48,219,0).

[0042] Pack the data at the end into a third data packet: (0.47,218,0).

[0043] Finally, these three data packets are concatenated in sequence: [(0.5,220,0),(0.48,219,0),(0.47,218,0)]. This is the real-time fault monitoring dataset, reflecting the current, voltage, and equipment status of the circuit from beginning to end.

[0044] Historical data retrieval:

[0045] Query the records (archived data) of the same three locations on this circuit at 12 noon every day for the past month.

[0046] For example, find the record from yesterday noon: beginning (0.51,221,0), middle (0.49,220,0), end (0.48,219,0).

[0047] Then find the record from noon the day before yesterday: beginning (0.50,220,0), middle (0.48,219,0), end (0.47,218,0).

[0048] Take the noon data found (e.g., 30 days), and package each day into a historical data package in the order of beginning -> middle -> end.

[0049] Finally, all the historical data packets from these 30 days were collected to form a historical baseline dataset. This dataset represents the typical current, voltage, and state of this circuit at these three key locations during normal operation (every day at noon).

[0050] like Figure 2 The diagram shown is a monitoring illustration of real-time triplet and historical baseline triplet sequences.

[0051] Preferably, step S2 includes the following:

[0052] The real-time fault monitoring dataset and the historical benchmark dataset are compared and corrected item by item, and the corrected data is used to calculate the drift amplitude. The formula for calculating the drift amplitude is as follows:

[0053]

[0054] Among them, D * This represents the drift amplitude; p∈{I,V,C} represents the real-time triplet involved in the synthesis: current, voltage, and status code; This indicates the corrected calibration data; w p The p-th term represents the weight, set based on fault sensitivity and information entropy assessment; E represents the environmental disturbance factor; η represents the environmental impact adjustment coefficient; clamp(,-A max A max () represents the amplitude limiting function;

[0055] The lower eight bits of the drift amplitude are used to locate the inverse excitation level of the preset pulse amplitude table with the lower eight bits of the current detection sequence number.

[0056] The reverse excitation amplitude instruction is generated by writing the reverse excitation level into the amplitude instruction register.

[0057] In this embodiment, the real-time fault monitoring dataset (containing ordered triples of three segments: start, middle, and end) is compared item by item with the historical benchmark dataset (containing historical triple sequences of the same segment). For each data element (current T, voltage V, status code) in the real-time triple, the difference is calculated with the corresponding reference value (such as mean, typical value, or other statistics) in the historical benchmark dataset to obtain preliminary correction data. Subsequently, these preliminary correction data undergo necessary processing, including filtering, normalization, or standardization based on historical statistics, to obtain the corrected correction data.

[0058] Next, these corrected data are weighted and summed according to their physical characteristics, fault sensitivity (reflected by weights), and their own information content (assessed by information entropy) to obtain a comprehensive offset. To reduce the impact of environmental disturbances (such as temperature and humidity) on the results, the offset is corrected by an environmental inhibition factor E, thereby more accurately reflecting the actual abnormal conditions of the system.

[0059] To ensure the safety and effectiveness of subsequent hardware operations, the system applies a limiting function to the offset, constraining it within a preset safety range [-A_max, A_max]. After processing, the lower 8 bits of this value are extracted (equivalent to modulo 256) and logically mapped (e.g., bitwise XOR, concatenation, or lookup table indexing) with the lower 8 bits of the current detection sequence number to determine the reverse excitation level in the preset pulse amplitude table. Finally, the system generates a hardware drive instruction with the corresponding amplitude based on the level and writes it to the amplitude register to drive the signal generator, compensation circuit, or actuator to output a reverse excitation signal of the specified amplitude, thereby achieving potential fault suppression or system state adjustment.

[0060] In one implementation of the present invention, it is divided into three steps.

[0061] 1. Item-by-item comparison and correction:

[0062] The computer compares real-time values ​​with historical averages.

[0063] Initial section current: 0.5A (real-time), 0.51A (historical average), the difference is δI start = -0.01A (Real-time low).

[0064] Initial section voltage: 221V-δV start = -1V.

[0065] Start segment status code: 0-δC start =0 (same state).

[0066] The same method is used to calculate δI, δV, and δC for the middle and end segments. Assume that after correction, we get: δI = [-0.01, -0.01, -0.01]A, δV = [-1, -1, -1]V, δC = [0, 0, 0] (the correction process is simplified here).

[0067] 2. Calculate the drift amplitude D * :

[0068] The system assigns weights to current I, voltage V, and status code C. It assumes that voltage changes are more important: w I =0.3, w V =0.6, w C =0.1.

[0069] The correction values ​​for all segments are then summed using a weighted average.

[0070] Current contribution: 0.3 × (-0.01A - 0.01A - 0.01A) = 0.3 × (-0.03A) = -0.009

[0071] Voltage contribution: 0.6 × (-1V - 1V - 1V) = 0.6 × (-3V) = -1.8

[0072] Status code contribution: 0.1 × (0 + 0 + 0) = 0

[0073] Preliminary overall offset = -0.009 + (-1.8) + 0 = -1.809

[0074] Assume the current environmental disturbance factor E (e.g., the temperature is a bit high) is 0.5, and the adjustment coefficient η is 0.2.

[0075] Environmental inhibition term: 1 + 0.2 × 0.5 = 1.1

[0076] Initial drift value = -1.809 / 1.1 ≈ -1.6445

[0077] Assume the maximum allowable amplitude A_max = 5.0. The amplitude limiting function ensures the result is between [-5.0, 5.0], so the final D* ≈ -1.6445 (within the range).

[0078] 3. Generate inverse stimulus instructions:

[0079] Extracting the lower 8 bits of D*≈-1.6445: Floating-point number storage in computers is complex, but conceptually it can be understood as extracting some "tail feature" of the value or quantizing it into an integer between 0 and 255. Assume that after processing, its lower 8 bits are equivalent to 0xA3 (hexadecimal, equivalent to decimal 163).

[0080] Assuming the current detection sequence number is 1001, its lower 8 bits are 0xE9 (decimal 233).

[0081] Perform some operation on the two lower 8 bits (0xA3 and 0xE9) (e.g., bitwise XOR 0xA3XOR 0xE9 = 0x4A (decimal 74)), and use the result 0x4A as an index to look up the preset pulse amplitude table.

[0082] The pulse amplitude table predefines the "reverse excitation level" and specific drive amplitude parameters corresponding to different index values ​​(0-255). For example, if the table lookup shows index 74 as "reverse excitation level 3," this level requires an output compensation signal with an amplitude of -2.5V (the negative sign indicates reverse).

[0083] The -2.5V amplitude parameter is written into a dedicated amplitude instruction register. After the hardware circuit (such as a programmable waveform generator) reads this register value, it needs to generate a reverse excitation signal with an amplitude of -2.5V and apply this signal to a specific point on the loop in an attempt to cancel the detected negative drift (generally low voltage) and bring the system state closer to the historical reference.

[0084] Preferably, step S2 includes the following:

[0085] Step S3, injecting the reverse current signal according to the reverse excitation amplitude command into the node of the circuit under test, includes:

[0086] The reverse current pulse is determined based on the reverse excitation level, wherein the reverse current pulse includes the pulse leading edge and the pulse width;

[0087] The reverse current pulse, based on the reverse excitation amplitude command, is injected into the node of the circuit under test. The leading edge of the reverse current pulse is aligned with the starting edge of the detection cycle, and the pulse width of the reverse current pulse is limited to the same detection cycle to obtain the data of the circuit to be injected.

[0088] The data of the circuit to be injected is input to the node of the circuit under test for overflow latching to obtain the Hall zero drift quantity.

[0089] In this embodiment, based on the reverse excitation level corresponding to the reverse excitation amplitude command (which is determined by looking up a table), the key pulse time parameters corresponding to that level are parsed from a preset parameter mapping relationship. These parameters include the pulse leading edge (the start time or slope characteristic of the current rising from zero to the target amplitude) and the pulse width (the duration for which the current is maintained at the target amplitude). These time parameters define the basic timing sequence of the pulse signal.

[0090] Subsequently, based on the target current amplitude specified in the reverse excitation amplitude command (e.g., -2.5A), and using the resolved leading edge and width parameters, corresponding loop injection data is generated within a digital signal processor (DSP) or dedicated pulse generation unit. This data precisely describes the amplitude, leading edge, and width of the target current pulse and is passed to the drive circuit as a digital command sequence or configuration parameter set. To ensure synchronization between the injected signal and the system's main detection clock, the pulse leading edge must be time-aligned with the start edge of the current detection cycle, and the pulse width is limited to a single detection cycle. This ensures complete pulse injection and that subsequent signal acquisition is completed within a specified time window, avoiding cross-cycle interference.

[0091] After the generated data of the loop to be injected is transmitted to the driving circuit (such as a DAC and power amplifier), an actual reverse current pulse is generated at the node of the loop under test. During the pulse injection process, a Hall effect sensor deployed near the loop node captures the changes in the magnetic field generated by the current in real time. To prevent the sensor from saturating during the pulse peak and to accurately capture the magnetic field changes, the system employs an overflow latching technique for the Hall sensor output signal. That is, when the signal exceeds the ADC range, a limiting circuit is used to prevent clipping distortion, and the sensor output value is latched when the pulse ends or stabilizes slightly later. This value is used as the Hall zero drift.

[0092] In one implementation of this embodiment, it is assumed that after step S2, the final reverse excitation amplitude command obtained by the system is: "Generate a reverse current pulse with an amplitude of -2.5 amperes (A) and a level of 3". The current detection period is 10 milliseconds (ms).

[0093] So, we know that “Level 3” corresponds to a specific pulse shape: for example, the pulse leading edge is required to be very steep, rising from 0A to -2.5A within 0.1ms; the pulse width is 2ms (i.e. the time to maintain a current of -2.5A).

[0094] Generate injection instructions & strict synchronization:

[0095] The system internally prepares the command: "At the start of the next detection cycle, immediately (leading edge aligned) initiate a current pulse: rise to -2.5A within 0.1ms, then maintain -2.5A for a full 2ms, and finally drop back to 0A before the end of the cycle." This command is the data for the circuit to be injected.

[0096] Key points: This pulse must begin rising precisely at the 0th millisecond (start edge) of the next 10ms detection cycle, and the entire pulse (rise + hold) must be completed before the 10ms mark (width limited within the cycle). For example: starting at 0ms, reaching -2.5A in 0.1ms, holding for 2.1ms, and then falling back. In this way, the pulse is completely contained within 0-10ms.

[0097] Injected current pulse:

[0098] At 0ms of the next cycle, the drive circuit starts working.

[0099] 0ms-0.1ms: The current drops rapidly and linearly from 0A to -2.5A (leading edge).

[0100] 0.1ms-2.1ms: The current remains stable at -2.5A (width).

[0101] 2.1ms to 2.5ms: The current quickly returns to 0A (falling edge, implicit instruction requirement, to ensure completion within the cycle).

[0102] Capture Hall signal & clear overflow latch to obtain zero drift:

[0103] During current pulse injection, the magnetic field at the loop node changes drastically.

[0104] When a large current of -2.5A flows through, the resulting strong magnetic field causes the Hall sensor's output voltage to reach its limit (e.g., 4.9V, close to its maximum 5V range). The system's protection circuitry ensures that this voltage does not exceed 5V (clipping) to prevent signal distortion.

[0105] At a stable moment after the pulse ends and the current returns to 0A (e.g., at the 5th ms of the detection cycle), the system sends a "grab" signal, let's say 1.23V. This 1.23V is the Hall zero-drift value latched by the system.

[0106] It should be added that, ideally, when the loop current is 0, the magnetic field measured by the Hall sensor should be 0, and the output should also be 0V (zero point). This 1.23V indicates that the zero point of the magnetic field at this node has drifted (zero drift) - due to the presence of stray magnetic fields nearby, sensor errors, or some kind of fault in the loop (such as local magnetization).

[0107] Preferably, the electronic perturbation quantity output based on Hall zero drift in step S3 includes:

[0108] The positive and negative terminals of the circuit node under test generate circuit fault sequences respectively, and the triggering is staggered.

[0109] The pulse width is scaled in the direction of the current at the positive terminal, and the pulse leading edge is applied in the opposite direction at the negative terminal to obtain the disturbance of the circuit under test.

[0110] The absolute value coupling of the disturbance quantity of the circuit under test is performed to output the electronic disturbance quantity.

[0111] In this embodiment, based on the magnitude and sign (if applicable) of the Hall zero drift quantity (a voltage or digital quantity), corresponding circuit fault sequences are generated at the positive and negative terminals of the node in the circuit under test. This sequence typically consists of a series of voltage or current pulses simulating faults or disturbances.

[0112] Crucially, the pulse sequences generated at the positive and negative terminals are triggered at different times. That is, the start time (or critical edge) is intentionally offset by a preset or determined small time interval to avoid the signals from completely overlapping in space or time, causing mutual cancellation or measurement confusion.

[0113] Apply direction-dependent modulation to the pulse sequence at the positive terminal: Based on the actual current direction of the node in the loop (e.g., defined as the positive direction), scale the pulse width according to the current direction. Specifically, multiply the pulse duration (pulse width) by a scaling factor S determined by both the pulse duration and direction information. + +, so that the pulse width W+ = W_base × S + (W_base is the base pulse width). Simultaneously, reverse modulation is applied to the pulse sequence at the negative terminal: modulation is applied in the opposite direction to the current, specifically by applying the pulse leading edge in the opposite direction, that is, changing the rising edge of the pulse (if it is a positive pulse) to a falling edge, or vice versa (changing the pulse polarity). At the same time, its pulse width W- is also modulated, but the rule is different from or the same as that at the positive terminal. After this directional modulation, the output at the positive terminal becomes a pulse sequence with a scaled pulse width W+, and the output at the negative terminal becomes a pulse sequence with a reverse leading edge (and a scaled pulse width W-). Together, they constitute the disturbance quantity of the circuit under test.

[0114] The modulated pulse sequence signals at both ends are subjected to absolute value coupling: this operation is usually achieved through a full-wave rectifier circuit or a mathematical function, which converts both positive and negative input signals (regardless of polarity) into positive signals, and then superimposes (couples) them. The signal after this processing is the final output electronic perturbation.

[0115] In one implementation of this embodiment, the Hall zero drift value of 1.23V generated earlier is used.

[0116] The system decides to generate a voltage pulse sequence simulating a fault at the positive terminal: for example, a square wave with a base shape of +3V height and a width of 2ms. Simultaneously, a similar fault pulse sequence is generated at the negative terminal: a square wave with a base shape of -3V height and a width of 2ms (note the negative voltage).

[0117] Next, the pulse at the negative terminal starts 0.5ms later than the pulse at the positive terminal. Therefore, the pulse at the positive terminal starts at T=0ms, and the pulse at the negative terminal starts at T=0.5ms.

[0118] The pulse width is scaled according to the current direction. Assume a scaling factor S.+ The decision is made, and the rules are as follows.

[0119] Calculate: S + =1-(1.23 / 5)=1-0.246=0.754. Therefore, the actual pulse width W+ of the positive terminal pulse is approximately 1.51ms, which is 2ms*0.754. The pulse height remains +3V.

[0120] The pulse leading edge is applied in the opposite direction. The original negative pulse transitioned from -3V (low level) to 0V (high level). For a negative pulse of -3V, its leading edge is a drop from 0V to -3V. Therefore, the negative pulse is modulated into a positive pulse that rises from -3V (low level) to 0V (high level), with its base height becoming +3V (relative to its reference point), and the pulse width W is assumed to remain at 2ms (modulation rules differ).

[0121] Positive signal: A +3V pulse that starts at 0ms and lasts for 1.51ms.

[0122] Negative terminal signal: A +3V pulse that starts at 0.5ms and lasts for 2ms (after being modulated by the inverted leading edge, it is now a positive pulse).

[0123] Input these two signals into an absolute coupler (think of it as a special circuit):

[0124] This circuit first performs absolute value processing on each input signal.

[0125] Then, the two processed signals are superimposed (coupled) together. During the time interval from 0.5ms to 1.51ms, the two +3V pulses overlap, resulting in +6V. During other time intervals, there is only one pulse, which is +3V.

[0126] The final output electronic disturbance E_disturbance is a voltage waveform:

[0127] 0ms-0.5ms: +3V (positive terminal pulse only)

[0128] 0.5ms-1.51ms: +6V (positive and negative pulses superimposed)

[0129] 1.51ms-2.5ms: +3V (only the remaining portion of the negative terminal pulse)

[0130] Preferably, the electronic perturbation quantity output based on Hall zero drift in step S3 includes:

[0131] Step S4 includes the following steps:

[0132] Step S41: Obtain the insulation response bit value;

[0133] Step S42: Perform a threshold test using the electronic disturbance quantity and the insulation response value to obtain the fault judgment difference;

[0134] Step S43: If the fault judgment difference falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormality mark is generated and protection measures are implemented.

[0135] Step S44: Construct an electronic component management report based on the fault judgment difference and anomaly markers.

[0136] Preferably, step S43 includes:

[0137] Extract the instantaneous difference from the fault diagnosis difference;

[0138] Perform a trend consistency test on the fault diagnosis difference;

[0139] When the peak value of multiple fault judgment differences exceeds the preset allowable range, and the instantaneous difference trend consistency test fails, an anomaly marking action is triggered and an anomaly frame is recorded.

[0140] When the peak value of multiple fault judgment differences does not exceed the preset allowable range, and the instantaneous difference trend consistency test is successful, it is recorded as normal aging and continuous load monitoring is performed.

[0141] Preferably, the protective measures include:

[0142] Generate an anomaly marker and encapsulate it with the current detection cycle number into an anomaly frame;

[0143] Triggering an instantaneous shutdown command causes the load current to drop to zero before the next clock edge, and after shutdown is completed, the abnormal frame is synchronously uploaded to the management terminal.

[0144] In one implementation of this embodiment, a digital value representing the insulation status of the circuit under test or its key components (such as cable connectors or power devices) is acquired through a dedicated sensor or diagnostic circuit—the insulation response bit value R_insulation (e.g., an ADC reading reflecting the equivalent value of insulation resistance, an encoded value representing the magnitude of leakage current, or a status flag bit output by the insulation test circuit).

[0145] The electronic disturbance (typically an analog voltage waveform or a digital sequence converted by an ADC) is subjected to a real-time or periodic threshold test against the insulation response potential value R_insulation. This test is not a simple static comparison but a dynamic calculation: for example, the peak value, RMS value, or specific characteristic value within a detection period is compared to a threshold value (Threshold(R_insulation)) dynamically adjusted by R_insulation, and the difference Δ = Feature(E) is calculated. disturbance-Threshold(R_insulation), this difference is the fault judgment difference △fault.

[0146] The system analyzes the Δfault sequence obtained from several consecutive detection cycles, both current and recent. Firstly, it extracts the instantaneous difference, i.e., the Δfault value of the current cycle. Secondly, it performs a trend consistency test on the Δfault sequence, such as calculating its slope, variance, or fit with a preset aging / failure model within a certain time window, to determine whether its changes conform to the characteristics of normal aging (slow, consistent, and predictable). The diagnostic rule is: if the peak values ​​of Δfault in multiple consecutive cycles (e.g., the most recent 5) do not exceed the preset allowable range [Δmin, Δmax] (this range represents the allowable fluctuations during normal aging), and the trend consistency test is successful (i.e., the trend conforms to the preset normal aging model), then it is determined to be normal aging. The system only records relevant data and continuously monitors under load (maintaining normal operating current). Conversely, if the peak values ​​of △_fault in multiple consecutive periods exceed the allowable range, or if the instantaneous difference trend consistency test fails (such as abrupt changes, oscillations, or non-compliance with the model), a fault determination is triggered, an anomaly marker (a flag bit or a specific code) is generated, and an anomaly frame containing the current △_fault value, timestamp, and relevant raw data (such as E_disturbance, R_insulation) is recorded.

[0147] After confirming the fault, the generated anomaly flag and the unique sequence number of the current detection cycle are encapsulated into a structured anomaly frame data packet. Immediately afterwards, the system triggers a momentary shutdown command, which forces the load current flowing through the circuit under test to rapidly drop to zero amperes before the next system master clock edge through hardware control logic (such as driving the MOSFET gate) (achieving hardware-level fast protection).

[0148] After the current is confirmed to be off, this abnormal frame is synchronously uploaded to the management terminal (such as a host computer or cloud platform) via a communication interface (such as CAN or Ethernet). Finally, based on the data such as the Δ_fault sequence, abnormal marker records (if any), insulation response bit value history, and shutdown event information throughout the monitoring process, the data is summarized and analyzed to construct a structured electronic component management report. This report includes information such as health status assessment, fault records, and aging trend prediction for maintenance decision-making.

[0149] In one implementation of this embodiment, if the peak values ​​do not exceed the limit and the trend is normal, the system records it as normal aging, and the motor continues to run (continuous load monitoring), only the data from this instance is archived.

[0150] Finally, by summarizing the data from this incident and previous aging data, a report was generated: "Motor power supply circuit: Insulation fault occurred at 14:30:02 on 2023-10-27 (code: XX), and the circuit has been shut down urgently. Historical data shows that the insulation resistance has a slow aging trend (from 85 to 60 before the incident), and it is recommended to replace the cable."

[0151] like Figure 3 The diagram shown is a schematic of the framework of an electronic component fault management system.

[0152] Data acquisition module 101: Responsible for collecting real-time data and reading historical data to build a monitoring dataset;

[0153] Drift calculation module 102: performs data comparison and analysis, calculates drift amplitude, and generates excitation commands;

[0154] Excitation and Zero Drift Module 103: Performs reverse current signal injection and Hall zero drift detection;

[0155] Response detection module 104: Performs final fault diagnosis and protection measures.

[0156] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0157] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for managing faults in electronic components, characterized in that, Includes the following steps: Step S1: Collect real-time data and build a real-time fault monitoring dataset; read historical data and build a historical benchmark dataset; Step S2: Compare the real-time fault monitoring dataset and the historical benchmark dataset item by item within the corresponding time window to obtain the drift amplitude, and generate the inverse excitation amplitude command based on the drift amplitude mapping; Step S3: Inject the reverse current signal according to the reverse excitation amplitude command into the node of the circuit under test, and determine the Hall zero drift based on the Hall output; output the electronic disturbance based on the Hall zero drift. Step S4: Obtain the insulation response bit value; compare the electronic disturbance quantity with the insulation response bit value. If the comparison result falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormal mark is generated and protection measures are implemented.

2. The electronic component fault management method as described in claim 1, characterized in that, Step S1 also includes: The real-time current and voltage values ​​are collected sequentially from the starting section, middle section and end section along the node of the circuit under test, and the corresponding feedback status codes are read independently. The real-time values ​​and single codes collected from the starting section, middle section and end section are concatenated with the single codes in the section order to form a real-time triplet to form a real-time fault monitoring dataset.

3. The electronic component fault management method as described in claim 1, characterized in that, Step S2 includes the following: The real-time fault monitoring dataset and the historical benchmark dataset are compared and corrected item by item, and the corrected data is used to calculate the drift amplitude. The formula for calculating the drift amplitude is as follows: Among them, D * This represents the drift amplitude; p∈{I,V,C} represents the real-time triplet involved in the synthesis: current, voltage, and status code; This indicates the corrected calibration data; w p The p-th term represents the weight, set based on fault sensitivity and information entropy assessment; E represents the environmental disturbance factor; η represents the environmental impact adjustment coefficient; clamp(,-A max A max () represents the amplitude limiting function; The lower eight bits of the drift amplitude are used to locate the inverse excitation level of the preset pulse amplitude table with the lower eight bits of the current detection sequence number. The reverse excitation amplitude instruction is generated by writing the reverse excitation level into the amplitude instruction register.

4. The electronic component fault management method as described in claim 1, characterized in that, Step S3, injecting the reverse current signal according to the reverse excitation amplitude command into the node of the circuit under test, includes: The reverse current pulse is determined based on the reverse excitation level, wherein the reverse current pulse includes the pulse leading edge and the pulse width; The reverse current pulse, based on the reverse excitation amplitude command, is injected into the node of the circuit under test. The leading edge of the reverse current pulse is aligned with the starting edge of the detection cycle, and the pulse width of the reverse current pulse is limited to the same detection cycle to obtain the data of the circuit to be injected. The data of the circuit to be injected is input to the node of the circuit under test for overflow latching to obtain the Hall zero drift quantity.

5. The electronic component fault management method as described in claim 4, characterized in that, The process of inputting the data to be injected into the node of the circuit under test for overflow latching includes: The overflow bit and valid data bit of the Hall zero drift are determined by subtracting the current value detected by the Hall sensor from the bus current value of the data to be injected into the circuit bit bit by bit. Output the overflow bit of the Hall zero drift value to the value flag register, and output the valid data bits of the Hall zero drift value to the zero drift temporary register. The valid data bits of the zero-drift temporary register are de-overflowed. The de-overflow process masks the carry effect of the overflow bit on the valid data, preserves the original valid bit sequence, and obtains the Hall zero-drift value.

6. The electronic component fault management method as described in claim 1, characterized in that, The electronic perturbation quantity output based on Hall zero drift in step S3 includes: The positive and negative terminals of the circuit node under test generate circuit fault sequences respectively, and the triggering is staggered. The pulse width is scaled in the direction of the current at the positive terminal, and the pulse leading edge is applied in the opposite direction at the negative terminal to obtain the disturbance of the circuit under test. The absolute value coupling of the disturbance quantity of the circuit under test is performed to output the electronic disturbance quantity.

7. The electronic component fault management method as described in claim 1, characterized in that, Step S4 includes the following steps: Step S41: Obtain the insulation response bit value; Step S42: Perform a threshold test using the electronic disturbance quantity and the insulation response value to obtain the fault judgment difference; Step S43: If the fault judgment difference falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormality mark is generated and protection measures are implemented. Step S44: Construct an electronic component management report based on the fault judgment difference and anomaly markers.

8. The electronic component fault management method as described in claim 1, characterized in that, Step S43 includes: Extract the instantaneous difference from the fault diagnosis difference; Perform a trend consistency test on the fault diagnosis difference; When the peak value of multiple fault judgment differences exceeds the preset allowable range, and the instantaneous difference trend consistency test fails, an anomaly marking action is triggered and an anomaly frame is recorded. When the peak value of multiple fault judgment differences does not exceed the preset allowable range, and the instantaneous difference trend consistency test is successful, it is recorded as normal aging and continuous load monitoring is performed.

9. The electronic component fault management method as described in claim 7, characterized in that, The implementation of protection measures includes: Generate an anomaly marker and encapsulate it with the current detection cycle number into an anomaly frame; Triggering an instantaneous shutdown command causes the load current to drop to zero before the next clock edge, and after shutdown is completed, the abnormal frame is synchronously uploaded to the management terminal.

10. An electronic component fault management system, characterized in that, For performing the electronic component fault management method as described in claim 1, the electronic component fault management system includes: The data acquisition module is used to collect real-time data and build a real-time fault monitoring dataset; and to read historical data and build a historical benchmark dataset. The drift calculation module is used to compare the real-time fault monitoring dataset and the historical benchmark dataset item by item within the corresponding time window to obtain the drift amplitude, and generate the inverse excitation amplitude command based on the drift amplitude mapping. The excitation and zero-drift module is used to inject a reverse current signal into the node of the circuit under test according to the reverse excitation amplitude command, and determine the Hall zero-drift amount based on the Hall output; and output the electronic disturbance amount based on the Hall zero-drift amount. The response detection module is used to obtain the insulation response bit value; the electronic disturbance quantity is compared with the insulation response bit value. If the comparison result falls within the preset allowable range, it is recorded as normal aging and continuous load monitoring is performed; otherwise, an abnormal mark is generated and protection measures are implemented.

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