Task execution method and device, processing unit and processing chip

Abstract

The embodiment of the invention discloses a task execution method and device, a processing unit and a processing chip, the task execution method is suitable for the task execution device, the task execution device comprises a scheduling unit and the processing unit, and the task execution method can comprise the following steps: firstly, scheduling the scheduling unit and the processing unit; the scheduling unit determines target address information of a target sub-graph of a target algorithm matched with the current task and issues the target address information to the processing unit, and then the processing unit loads the target sub-graph from the storage unit according to the target address information and executes an instruction corresponding to the target sub-graph. By implementing the method, the task execution efficiency of the task execution device can be improved.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a task execution method, apparatus, processing unit and processing chip. Background Technology

[0002] With continuous technological advancements and innovations, the software functions of electronic devices (such as smartphones, tablets, and smartwatches) are becoming increasingly powerful. These powerful software functions largely rely on complex computational tasks (such as image recognition, speech recognition, and natural language processing). Therefore, improving task execution efficiency has become a pressing technical challenge for the industry. Summary of the Invention

[0003] This application provides a task execution method, apparatus, processing unit, and processing chip, which can improve the task execution efficiency of the task execution apparatus.

[0004] A first aspect of this application provides a task execution method, the method being applicable to a task execution device, the task execution device including a scheduling unit and a processing unit, the method comprising:

[0005] The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task, and sends the target address information to the processing unit.

[0006] The processing unit loads the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms;

[0007] The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0008] A second aspect of this application provides a task execution method, applicable to a task execution device, the task execution device including a scheduling unit and a processing unit, the method comprising:

[0009] The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task;

[0010] The scheduling unit loads the target subgraph from the storage unit according to the target address information and sends the target subgraph to the processing unit; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms;

[0011] The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0012] A third aspect of this application provides a task execution method, applicable to a processing unit in a task execution device, the method comprising:

[0013] Receive the target address information of the target subgraph of the target algorithm that matches the current task;

[0014] Based on the target address information, the target subgraph is loaded from the storage unit; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms;

[0015] Execute the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0016] A fourth aspect of this application provides a task execution apparatus, including a scheduling unit and a processing unit;

[0017] The scheduling unit is used to determine the target address information of the target subgraph of the target algorithm that matches the current task, and to send the target address information to the processing unit.

[0018] The processing unit is used to load the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms;

[0019] The processing unit is further configured to execute the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0020] A fifth aspect of this application provides a processing unit, including:

[0021] The receiving module is used to receive the target address information of the target subgraph of the target algorithm that matches the current task;

[0022] A subgraph loading module is used to load the target subgraph from the storage unit according to the target address information; wherein the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms;

[0023] An execution module is used to execute the instructions corresponding to the target subgraphs; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0024] A sixth aspect of this application provides a processing chip, including:

[0025] Memory containing executable program code;

[0026] and the processor coupled to the memory;

[0027] The processor calls the executable program code stored in the memory, and when the executable program code is executed by the processor, the processor implements the method as described in the first or second aspect of the embodiments of this application.

[0028] A seventh aspect of this application provides a computer-readable storage medium having executable program code stored thereon, wherein when the executable program code is executed by a processor, it implements the method described in the first or second aspect of this application.

[0029] The eighth aspect of this application discloses a computer program product that, when run on a computer, causes the computer to execute the method described in the first or second aspect of this application.

[0030] The ninth aspect of this application discloses an application publishing platform for publishing computer program products, wherein when the computer program product is run on a computer, the computer executes the method described in the first or second aspect of this application.

[0031] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0032] In this embodiment of the application, the storage unit stores pre-compiled subgraphs corresponding to each of the multiple algorithms. During the execution of the task, the task execution device first determines the target address information of the target subgraph of the target algorithm that matches the current task and sends the target address information to the processing unit. Then, the processing unit loads the target subgraph from the storage unit according to the target address information and executes the instructions corresponding to the target subgraph.

[0033] By implementing this method, the algorithm modules of each algorithm executed by the task execution device are pre-compiled to obtain subgraphs for each algorithm. Then, the union of these subgraphs is calculated, and the resulting subgraphs are stored in a storage unit. During task execution, the scheduling unit can send the target address information of the target subgraph of the target algorithm matching the current task to the processing unit. The processing unit can directly load the target subgraph of the target algorithm from the storage unit and execute the corresponding instructions without waiting for the scheduling unit to send the target subgraph. This significantly improves the efficiency of the processing unit in obtaining the target subgraph, thereby enhancing the task execution efficiency of the task execution device. Furthermore, since the subgraphs stored in the storage unit are the union of the subgraphs of each algorithm, this saves the storage space required by the task execution device. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments and the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and other drawings can be obtained based on these drawings.

[0035] Figure 1A This is a structural block diagram of the task execution device 10 disclosed in the embodiments of this application;

[0036] Figure 1B This is a structural block diagram of the processing unit 120 disclosed in the embodiments of this application;

[0037] Figure 2 This is a flowchart illustrating a task execution method disclosed in an embodiment of this application;

[0038] Figure 3 This is a diagram illustrating the relationship between the sub-graphs, operators, and instructions disclosed in the embodiments of this application;

[0039] Figure 4 This is another flowchart illustrating the task execution method disclosed in the embodiments of this application;

[0040] Figure 5A This is a schematic diagram of the pointer information transmission disclosed in an embodiment of this application;

[0041] Figure 5B This is another schematic diagram illustrating the transmission of pointer information disclosed in the embodiments of this application;

[0042] Figure 6 This is another flowchart illustrating the task execution method disclosed in the embodiments of this application;

[0043] Figure 7 This is a mapping diagram of pointers to subgraphs of the target algorithm disclosed in the embodiments of this application;

[0044] Figure 8 This is another flowchart illustrating the task execution method disclosed in the embodiments of this application;

[0045] Figure 9 This is a device illustration of a processing unit disclosed in an embodiment of this application;

[0046] Figure 10 This is a structural diagram of a processing chip disclosed in an embodiment of this application. Detailed Implementation

[0047] This application provides a task execution method, apparatus, processing unit, and processing chip, which can improve the task execution efficiency of the task execution apparatus.

[0048] To enable those skilled in the art to better understand the present application, the technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. All embodiments based on the present application should fall within the scope of protection of the present application.

[0049] It should be noted that, in this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0050] "At least one" means one or more, while "more" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0051] The following is a clarification of the proper nouns used in this application:

[0052] Microcontroller Unit (MCU): Also known as a microcontroller or single-chip computer, it is a microcomputer that integrates a central processing unit (CPU), memory, input / output (I / O) interfaces, and other components on a single chip.

[0053] CPU: The core component of a computer system, responsible for executing computer instructions and processing data. It is the brain of the computer, controlling all its operations.

[0054] Neural Processing Unit (NPU): A microprocessor specifically designed to accelerate machine learning (ML) tasks. Its main goal is to optimize tasks involving artificial neural networks (ANNs).

[0055] Advanced Peripheral Bus (APB) is part of the advanced microcontroller bus architecture protocol family and belongs to the most basic bus protocol.

[0056] Network on Chip (NOC): This is a new communication method for System-on-Chip (SoC) and a major component of multi-core technology.

[0057] An Advanced eXtensible Interface (AXI) bus standard protocol: a high-performance, high-bandwidth, low-latency on-chip bus protocol.

[0058] Storage unit: Primarily used to store instructions and data, it can directly interact with the CPU, providing fast data access and storage.

[0059] Digital Signal Processor (DSP): A microprocessor with a special structure, mainly used to implement various digital signal processing algorithms in real time and at high speed.

[0060] GPU (Graphics Processing Unit): Originally designed for graphics rendering tasks, GPUs have been widely used for deep learning and other large-scale computing tasks due to their powerful parallel computing capabilities and high programmability. GPUs have a large number of computing cores that can efficiently perform matrix operations and convolution operations, thus greatly accelerating the training and inference processes of neural networks.

[0061] ASIC (Application-Specific Integrated Circuit): ASICs are chips customized for specific applications, including ASICs for deep learning and neural network computing. Compared to GPUs and NPUs, ASICs can offer higher energy efficiency and performance because they are designed for specific tasks, maximizing hardware architecture and resource utilization.

[0062] FPGA (Field-Programmable Gate Array): An FPGA is a programmable hardware device that can be configured to perform specific computational tasks as needed. In the field of deep learning, FPGAs can be programmed to implement various neural network structures and algorithms, thereby providing higher performance and energy efficiency than traditional CPUs. The flexibility of FPGAs allows them to adapt to different neural network models and application scenarios.

[0063] Electronic devices typically utilize task execution devices, consisting of scheduling and processing units, to perform complex computational tasks such as image recognition, speech recognition, and natural language processing. An exemplary structural diagram of a task execution device can be found below. Figure 1A .like Figure 1A The task execution device 10 shown includes a scheduling unit 110 and a processing unit 120.

[0064] Currently, the specific content of the task execution device 10 when executing a computation task typically includes: the scheduling unit 110 first determines the algorithm that matches the current task, then compiles the algorithm module that matches the algorithm to obtain each subgraph of the algorithm, and then sends each subgraph of the algorithm to the processing unit 120, which executes the instructions corresponding to each subgraph of the algorithm.

[0065] In practice, it has been found that compiling algorithm modules is usually time-consuming. Therefore, the scheduling unit 110 needs a long time to obtain the subgraphs of the algorithm that match the current task. This often leads to poor real-time performance of the task execution device 10 when executing tasks.

[0066] To address this issue, this application provides a task execution scheme in which the algorithm modules of each algorithm executed by the task execution device are pre-compiled to obtain subgraphs of each algorithm. Then, the union of the subgraphs of each algorithm is calculated, and finally, the subgraphs obtained after the union are stored in the storage unit of the electronic device. In this way, for the same subgraph of different algorithms, only one needs to be stored in the storage unit, which helps to save the storage space required by the task execution device.

[0067] Based on this, during the execution of a task, the scheduling unit 110 can send the target address information of the target subgraph of the target algorithm that matches the current task to the processing unit 120. The processing unit 120 can directly load the target subgraph of the target algorithm from the storage unit according to the target address information and execute the instructions corresponding to the target subgraph without waiting for the target subgraph to be sent by the scheduling unit. This greatly improves the efficiency of the processing unit 120 in obtaining the target subgraph, and thus helps to improve the task execution efficiency of the task execution device.

[0068] In this application embodiment, the task execution device 10 may include, but is not limited to, any kind of hardware unit: NPU, GPU, ASIC and FPGA, etc.

[0069] For example, when the task execution device 10 is an NPU, the scheduling unit may include an MCU or a DSP, and the processing unit may include an artificial intelligence (AI) acceleration unit.

[0070] In the embodiments of this application, the electronic device may include general handheld screen electronic devices, such as mobile phones, smartphones, portable terminals, terminals, personal digital assistants (PDAs), portable multimedia players (PMPs), laptops, notebooks, wireless broadband (Wibro) terminals, tablet computers (PCs), smart PCs, and in-vehicle computers, etc.

[0071] Electronic devices can also include wearable devices. Wearable devices are portable electronic devices that can be worn directly on the user's body or integrated into the user's clothing or accessories. Wearable devices are not just hardware devices; they can also achieve powerful intelligent functions through software support, data interaction, and cloud server interaction, such as computing, positioning, and alarm functions. They can also connect to mobile phones and various terminals. Wearable devices can include, but are not limited to, wrist-supported devices (such as watches, wristbands, etc.), foot-supported devices (such as shoes, socks, or other leg-wearing products), head-supported devices (such as glasses, helmets, headbands, etc.), as well as smart clothing, backpacks, canes, accessories, and other non-mainstream product forms.

[0072] In some embodiments, communication between the processing unit 120 and the storage unit of the electronic device may be based on a NOC (Network Object Configuration). An exemplary structural diagram of the processing unit 120 can be found below. Figure 1B .like Figure 1B As shown, the processing unit 120 includes an interface 1201, a storage module 1202, a read modifier (AXI_RM) 1203, and an instruction dispatcher 1204. The processing unit 120 uses the interface 1201 to obtain target address information from the scheduling unit 110 and stores this target address information in the storage module 1202. Then, the read modifier (AXI_RM) 1203 loads the target subgraph from the storage unit according to the target address information. The instruction dispatcher 1204 can be used to obtain the instruction corresponding to the loaded target subgraph and send the instruction to the execution unit (not shown) for execution.

[0073] The task execution method disclosed in this application will be described below with reference to specific implementation methods.

[0074] Please see Figure 2 , Figure 2 This is a flowchart illustrating a task execution method disclosed in an embodiment of this application.

[0075] like Figure 2 The task execution method shown may include the following steps:

[0076] 201. The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task.

[0077] In the embodiments of this application, the target algorithm may refer to any preset algorithm that matches the current task.

[0078] In the embodiments of this application, the target subgraph of the target algorithm is composed of at least one operator included in the target algorithm.

[0079] It is understandable that any algorithm can include multiple operators, one or more operators can form a subgraph of the algorithm, and any operator corresponds to one or more instructions.

[0080] It should be noted that the relationship between operators, subgraphs, and instructions can be found in the following... Figure 3 .like Figure 3 As shown, sub-graph 1 consists of operator 1, operator 2 and operator 3. Operator 1 corresponds to instruction 1, instruction 2 and instruction 3 respectively, operator 2 corresponds to instruction 4 and instruction 5 respectively, and operator 3 corresponds to instruction 6, instruction 7 and instruction 8 respectively.

[0081] In the embodiments of this application, the target address information can be used to determine the pointer of the target subgraph in the storage unit of the electronic device, the pointer being used to indicate the storage address of at least one operator included in the target subgraph in the storage unit.

[0082] In some embodiments, the target address information may include pointer information of the target subgraph in the storage unit, or mapped address information of the pointers of the target subgraphs in the storage unit, which is not limited in this application embodiment. The pointer information may include pointers of the target subgraphs in the storage unit. The mapped address information may be obtained by mapping the addresses of the pointers of each target subgraph in the storage unit, and this mapped address information is used to determine the storage address of the pointers of each target subgraph in the storage unit.

[0083] It should be noted that when the target address information includes pointer information, please refer to the following... Figure 4 The illustrated embodiment. For cases where the target address information includes mapped address information, please refer to the following... Figure 6 The example shown.

[0084] In this embodiment of the application, the storage unit of the electronic device may be the main memory of the electronic device.

[0085] In some embodiments, prior to step 201, the scheduling unit may also determine a target algorithm that matches the current task.

[0086] In some embodiments, the scheduling unit may determine the target algorithm that matches the current task by obtaining reference information of the current task and determining the target algorithm that matches the reference information of the current task based on the mapping relationship between various preset algorithms and the corresponding reference information.

[0087] In the embodiments of this application, the reference information may include, but is not limited to, at least one of the following: task type, application scenario, and hardware characteristics of the processing unit.

[0088] In the embodiments of this application, the task type may refer to the type of the current task. For example, image recognition, speech recognition, or natural language processing. It should be understood that when the reference information includes the task type, the target algorithm determined by the scheduling unit may be an algorithm that matches the task type of the current task.

[0089] In the embodiments of this application, the hardware characteristics of the processing unit may include, but are not limited to, parallel processing capabilities and / or optimized instruction sets. Parallel processing capability refers to the processing unit's ability to perform parallel computations. Optimized instruction sets refer to instruction sets optimized by the processing unit for at least one algorithm, which can accelerate specific computational tasks and reduce the overhead of data movement and transformation.

[0090] It should be understood that, when the reference information includes the hardware characteristics of the processing unit, if the hardware characteristics include parallel processing capabilities, the target algorithm determined by the scheduling unit is an algorithm that fully utilizes the parallel computing capabilities of the processing unit to improve computational efficiency and throughput. If the hardware characteristics include an optimized instruction set, the target algorithm determined by the scheduling unit is an algorithm that can fully utilize the optimized instruction set of the processing unit to achieve even higher computational efficiency.

[0091] Application scenario refers to the usage scenario of electronic devices. It should be understood that, when the reference information includes the application scenario, the target algorithm determined by the scheduling unit can be an algorithm that matches the application scenario of the current task.

[0092] The following examples illustrate the algorithm for determining targets based on application scenarios:

[0093] For example, the preset algorithm of an electronic device includes two face detection algorithms: one with face rotation and the other without. The algorithm with face rotation is suitable for application scenario 1, detecting faces in images or videos at arbitrary rotation angles. The algorithm without face rotation is suitable for application scenario 2, detecting faces in images or videos at a fixed angle (e.g., frontal view). Therefore, when the current task is in application scenario 1, the target algorithm is the algorithm with face rotation; when the current task is in application scenario 2, the target algorithm is the algorithm without face rotation.

[0094] For example, when an electronic device performs an image processing task, if the output format of the image corresponding to the application scenario of the current task is different from the input format of the image, then the selected target algorithm for image processing includes an algorithm module for image format conversion.

[0095] In this embodiment of the application, the mapping relationship between multiple preset algorithms and corresponding reference information can be stored in an algorithm relationship table. The algorithm relationship table stores the algorithm identifiers of multiple algorithms and the reference information that matches each algorithm identifier.

[0096] It should be noted that the algorithm identifier is used to uniquely identify an algorithm, and the algorithm identifier may include, but is not limited to, at least one of the following: numbers, letters, and special characters.

[0097] In some embodiments, the scheduling unit may determine the target address information of the target subgraph of the target algorithm by determining the target address information of the target algorithm based on the mapping relationship between multiple algorithms and the address information of the corresponding subgraphs.

[0098] It is understandable that the mapping relationship between the above-mentioned algorithms and the address information of the corresponding subgraphs can be stored in an address relationship table. This address relationship table can include the algorithm identifiers of multiple algorithms and the address information corresponding to each algorithm identifier.

[0099] 202. The scheduling unit sends the target address information to the processing unit.

[0100] In this embodiment, the communication between the scheduling unit 110 and the processing unit 120 can be based on the Serial Peripheral Interface (SPI) or the APB interface, and this embodiment does not limit it.

[0101] Understandably, the scheduling unit sends the target address information to the processing unit through the SPI / APB interface.

[0102] 203. The processing unit loads the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms.

[0103] It is understandable that the processing unit loading the target subgraph from the storage unit based on the target address information could mean that the processing unit loading the operators corresponding to the target subgraph from the storage unit based on the target address information.

[0104] In some embodiments, loading a target subgraph from a storage unit based on target address information may include: the processing unit generating a subgraph loading command based on the target address information and a preset access method, and loading the target subgraph from the storage unit in response to the subgraph loading command. The preset access method may include, but is not limited to, AXI or AHB.

[0105] In some embodiments, before step 203, the multiple operators included in each of the multiple algorithms in step 203 may be combined into one or more subgraphs, and the union of the subgraphs of each algorithm may be stored in the storage unit.

[0106] In some embodiments, the multiple operators included in each of the multiple algorithms in step 203 are combined into one or more subgraphs, and the union of the subgraphs of each algorithm is stored in the storage unit. The execution entity may be a scheduling unit or the main CPU of an electronic device, and this application embodiment does not limit it.

[0107] In some embodiments, the scheduling unit can also configure the processing unit. The configuration of the processing unit by the scheduling unit may include, but is not limited to, at least one of the following: operating mode, parameters, and interrupts.

[0108] In some embodiments, the processing unit may also verify the format of the target address information, and continue to execute step 203 only when the format verification of the target address information is successful, which can effectively reduce the probability of errors when executing the task.

[0109] In some embodiments, the processing unit may load the target subgraph in a first-in-first-out (FIFO) or direct memory access (DMA) manner, and this application embodiment does not limit the method.

[0110] 204. The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0111] In this embodiment, the instruction executed by the processing unit corresponding to the target subgraph may refer to the instruction executed by the processing unit corresponding to each operator of the target subgraph. It is understood that the instruction executed by the processing unit corresponding to the target subgraph may include: instructions for the processing unit to determine each operator corresponding to the target subgraph, and instructions for executing each operator corresponding to the target subgraph.

[0112] By implementing Figure 2 The task execution method shown can have the following beneficial effects:

[0113] (1) The algorithm modules of each algorithm executed by the task execution device are pre-compiled to obtain the subgraphs of each algorithm. Then, the union of the subgraphs of each algorithm is calculated, and the subgraphs after the union are stored in the storage unit. In this way, during the execution of the task, the scheduling unit can send the target address information of the target subgraph of the target algorithm that matches the current task to the processing unit. The processing unit can directly load the target subgraph of the target algorithm from the storage unit and execute the instructions corresponding to the target subgraph without waiting for the target subgraph to be sent by the scheduling unit. This greatly improves the efficiency of the processing unit in obtaining the target subgraph, which in turn helps to improve the task execution efficiency of the task execution device. Furthermore, the subgraphs stored in the storage unit are the union of the subgraphs of each algorithm, which helps to save the storage space required by the task execution device.

[0114] (2) The scheduling unit and the processing unit are completely decoupled. The scheduling unit and the processing unit can work in parallel, which can greatly improve the execution efficiency and performance of tasks, and also minimize idle time, thus greatly improving the utilization efficiency of system resources.

[0115] (3) It can also reduce the communication frequency between the scheduling unit and the processing unit, thereby improving the reliability and stability of the system.

[0116] (4) The processing unit focuses on the details of accessing the underlying storage unit, which reduces the processing unit's dependence on the outside, thereby reducing the vulnerability of the system and improving the security of the system.

[0117] (5) It also makes it easier to add new functional modules and functional combinations to the processing unit, so that the processing unit can better adapt to changes and improve the scalability of the system.

[0118] The following is combined Figure 4 This section explains the case where the target address information includes pointer information of the target subgraph in the memory unit. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is another flowchart illustrating the task execution method disclosed in the embodiments of this application. For example... Figure 4 The task execution method shown may include the following steps:

[0119] 401. The scheduling unit determines the pointer information of the target subgraph of the target algorithm that matches the current task in the storage unit.

[0120] It should be noted that for explanations regarding the method by which the scheduling unit determines the target algorithm and the relevant explanations of the target subgraph, please refer to [link to relevant documentation]. Figure 2 The corresponding descriptions in the illustrated embodiments will not be repeated here.

[0121] In the embodiments of this application, the pointer information may include a pointer to the target subgraph in the storage unit. It is understood that when there is only one target subgraph in the target algorithm, the target address information may include a pointer to that target subgraph. When there are multiple target subgraphs in the target algorithm, the target address information may include a pointer queue composed of pointers to each target subgraph in the storage unit, and the order of the pointers in the pointer queue corresponds to the execution order of each target subgraph in the target algorithm.

[0122] The pointer queue will be explained below with examples:

[0123] For example, the subgraph sequence corresponding to algorithm A is: sub Figure 2 ,son Figure 4 ,son Figure 3 , among which, sub Figure 2 The pointer in the memory unit is P0, and the child pointer is P0. Figure 4 The pointer in the memory unit is P1, and the child pointer is P1. Figure 3 If the pointer in the storage unit is P2, then the pointer queue is P0, P1, P2.

[0124] For example, the subgraph sequence corresponding to algorithm B is: subgraph 1, subgraph 2, subgraph 3, subgraph 4, subgraph 5, subgraph 6, subgraph 7, subgraph 8, subgraph 9, subgraph 10, subgraph 11, subgraph 12, subgraph 13, subgraph 14, subgraph 15, subgraph 16, subgraph 17, subgraph 18, subgraph 19, subgraph 12, subgraph Figure 2 ,son Figure 3 In this context, the pointer to sub-graph 1 in the memory unit is P3. Figure 2 The pointer in the memory unit is P0, and the child pointer is P0. Figure 3 If the pointer in the storage unit is P2, then the pointer queue is P3, P0, P2.

[0125] 402. The scheduling unit sends pointer information to the processing unit.

[0126] The following example illustrates the sending of indication information when there are multiple target subgraphs.

[0127] Please see Figure 5A , Figure 5A This diagram illustrates the transmission of pointer information when the target algorithm is algorithm A. For example... Figure 5A As shown, the scheduling unit sends pointer queues P0, P1, and P2 to the processing unit.

[0128] Please see Figure 5B , Figure 5B This diagram illustrates the transmission of pointer information when the target algorithm is algorithm B. For example... Figure 5B As shown, the scheduling unit sends pointer queues P3, P0, and P2 to the processing unit.

[0129] 403. The processing unit loads the target subgraph from the storage unit according to the pointer information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms.

[0130] Understandably, when there is only one target subgraph, the processing unit can load the corresponding operators from the storage unit based on the pointer of the target subgraph. When there are multiple target subgraphs, the processing unit can load each target subgraph sequentially from the storage unit based on the order of the pointers of each target subgraph in the pointer queue.

[0131] For information on retrieving and storing subgraphs within a storage unit, please refer to [link to relevant documentation]. Figure 2 The relevant descriptions in the illustrated embodiments will not be repeated here.

[0132] 404. The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0133] It should be noted that when there are multiple target subgraphs, the processing unit can load the next target subgraph after confirming that the instructions corresponding to the previous target subgraph have been executed, until all target subgraphs of the target algorithm have been executed.

[0134] It should be noted that the order of the pointers of each target subgraph in the pointer queue is consistent with the execution order of each target subgraph in the target algorithm. This ensures that the loading and execution of each target subgraph are consistent with the execution order of each target subgraph in the target algorithm, which in turn helps to ensure the accurate execution of the task.

[0135] The following section uses Algorithm A and Algorithm B as examples to introduce the process of loading and executing target subgraphs when there are multiple target subgraphs.

[0136] Algorithm A: The processing unit first loads the sub-processor from P0. Figure 2 and execute the sub Figure 2 The corresponding instructions, and in the sub Figure 2 After the corresponding instructions have been executed, the child is loaded from P1. Figure 4 and execute the sub Figure 4 The corresponding instructions, and in the sub Figure 4 After the corresponding instructions have been executed, the child is loaded from P2. Figure 3 and execute the sub Figure 3 The corresponding instructions.

[0137] Algorithm B: The processing unit first loads subgraph 1 from P3 and executes the instructions corresponding to subgraph 1. After the instructions corresponding to subgraph 1 have been executed, it then loads subgraph 1 from P0. Figure 2 and execute the sub Figure 2 The corresponding instructions, and in the sub Figure 2 After the corresponding instructions have been executed, the child is loaded from P2. Figure 3 and execute the sub Figure 3 The corresponding instructions.

[0138] It should be noted that the implementation Figure 4 The task execution method shown has, in addition to having Figure 2 In addition to the beneficial effects shown, since the processing unit sends pointer information of the target subgraph in the storage unit to the processing unit, the processing unit can directly load the target subgraph from the storage address, which helps to improve the loading efficiency of the target subgraph.

[0139] The following is combined Figure 6 This section explains the case where the target address information includes the mapped address information of the pointers to the target subgraph in the memory unit. Please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is another flowchart illustrating the task execution method disclosed in the embodiments of this application. For example... Figure 6 The task execution method shown may include the following steps:

[0140] 601. The scheduling unit determines the mapping address information of the pointers in the storage unit of the target subgraph of the target algorithm that matches the current task.

[0141] It is understandable that the mapping address information is obtained by mapping the pointers of each target subgraph in the memory unit, and this mapping address information is used to determine the storage address of the pointers of each target subgraph in the memory unit.

[0142] In this embodiment of the application, when there are multiple target subgraphs, the mapping addresses of two target subgraphs whose execution order is adjacent in the target algorithm are adjacent.

[0143] When there are multiple target subgraphs, in some embodiments, the mapping address information may include, but is not limited to, any of the following:

[0144] The mapping address information may include the mapping address of the target subgraph that is executed first in the execution order, and the address length of the mapping addresses of each of the above target subgraphs;

[0145] or,

[0146] The mapping address information can include the mapping address of the target subgraph that is executed first and the mapping address of the target subgraph that is executed last.

[0147] or,

[0148] The mapping address information may include the mapping address of the target subgraph that is executed last in the execution order, and the address length of the mapping address of each target subgraph.

[0149] The following is combined Figure 7 The process of mapping the address of the pointer in the memory unit of the target subgraph is explained:

[0150] like Figure 7 As shown, the storage unit stores sub-Figure 1 and sub-Figure 2. Figure 2 ,son Figure 3 and son Figure 4 The subgraph sequence corresponding to algorithm A is as follows: Figure 2 ,son Figure 4 ,son Figure 3 The subgraph sequence corresponding to Algorithm B is: Subgraph 1, Subgraph 2, Subgraph 3, Subgraph 4, Subgraph 5, Subgraph 6, Subgraph 7, Subgraph 8, Subgraph 9, Subgraph 10, Subgraph 11, Subgraph 12, Subgraph 13, Subgraph 14, Subgraph 15, Subgraph 16, Subgraph 17, Subgraph 18, Subgraph 19, Subgraph 12, Subgraph Figure 2 ,son Figure 3 .

[0151] Here, address 1, address 2, and address 3 are three consecutive storage addresses in the storage unit. The mapping process of the pointers in the subgraph of Algorithm A is as follows: Figure 2 Pointer P0 is mapped to address 1, sub Figure 4 Pointer P1 to mapped address 2, sub Figure 3 The pointer P2 is mapped to address 3.

[0152] Here, addresses 5, 6, and 7 are three consecutive memory addresses in the memory unit. The mapping process of the pointers in the subgraph of Algorithm B is as follows: pointer P3 of subgraph 1 is mapped to address 5, and so on. Figure 2 Pointer P0 is mapped to address 6, sub Figure 3 The pointer P2 is mapped to address 7.

[0153] The following example, shown in Figure 7, illustrates the target address information:

[0154] Given that the target address information includes the mapping address of the target subgraph that appears first in the execution order, and the address length of the mapping address of at least one of the aforementioned target subgraphs, the target address information for Algorithm A includes address 1 and address length 3. The target address information for Algorithm B includes address 5 and address length 3.

[0155] When the target address information includes the mapping addresses of the target subgraphs executed first and last: Algorithm A's target address information includes addresses 1-3. Algorithm B's target address information includes addresses 5-7.

[0156] When the target address information includes the mapping address of the target subgraph that is executed last in the execution order, and the address length of the mapping address of at least one of the aforementioned target subgraphs: the target address information for Algorithm A includes address 3 and address length 3. The target address information for Algorithm B includes address 7 and address length 3.

[0157] 602. The scheduling unit sends the mapping address information to the processing unit.

[0158] 603. The processing unit loads the target subgraph from the storage unit according to the mapping address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms.

[0159] It should be noted that for information on retrieving and storing subgraphs within a storage unit, please refer to [link to relevant documentation]. Figure 2 The relevant descriptions in the illustrated embodiments will not be repeated here.

[0160] In this embodiment of the application, the processing unit loading the target subgraph from the storage unit according to the mapping address information may include:

[0161] The processing unit determines the mapping address of the pointer of each target subgraph in the storage unit based on the mapping address information, obtains the pointer of each target subgraph in the storage unit from the mapping address, and loads each target subgraph according to the pointer.

[0162] 604. The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0163] In the embodiments of this application, when there are multiple target subgraphs, the processing unit can load the next target subgraph after confirming that the instruction corresponding to the previous target subgraph has been executed, until all target subgraphs of the target algorithm have been executed.

[0164] The following uses Algorithm A and Algorithm B as examples to introduce the loading and execution of each target subgraph:

[0165] Algorithm A: The processing unit first reads the sub-value from address 1. Figure 2 The pointer P0 is then loaded from P0. Figure 2 Finally, execute the sub-process. Figure 2 The corresponding instruction. In the sub- Figure 2 After the corresponding instruction is executed, the processing unit first reads the sub-instruction from address 2. Figure 4 The pointer P1 is used to load the child from P1. Figure 4 Finally, execute the sub-process. Figure 4 The corresponding instruction. In the sub- Figure 4 After the corresponding instruction is executed, the processing unit first reads the sub-instruction from address 3. Figure 3 Pointer P2, then load the child from P2. Figure 3 Finally, execute the sub-process. Figure 3 The corresponding instructions.

[0166] Algorithm A: The processing unit first reads the pointer P3 of subgraph 1 from address 5, then loads subgraph 1 from P3, and finally executes the instruction corresponding to subgraph 1. After the instruction corresponding to subgraph 1 is executed, the processing unit first reads the pointer P3 of subgraph 1 from address 6. Figure 2 The pointer P0 is then loaded from P0. Figure 2 Finally, execute the sub-process. Figure 2 The corresponding instruction. In the sub- Figure 2 After the corresponding instruction is executed, the processing unit first reads the sub-instruction from address 7. Figure 3 Pointer P2, then load the child from P2. Figure 3 Finally, execute the sub-process. Figure 3 The corresponding instructions.

[0167] It should be noted that the implementation Figure 6 The task execution method shown has, in addition to having Figure 2 In addition to the beneficial effects shown, since the processing unit sends the mapping address information of the pointer of the target subgraph in the storage unit to the processing unit, it can ensure that the loading order of the target subgraph is consistent with the execution order of the target subgraph in the target algorithm, which is conducive to improving the accuracy of task execution.

[0168] In some embodiments, when the task execution device executes a task, the loading of the target subgraph of the target algorithm can also be performed by the scheduling unit. When the scheduling unit loads the target subgraph, it sends the loaded target subgraph to the processing unit, which then executes the instructions corresponding to the target subgraph. The corresponding task execution method can be found below. Figure 8 .

[0169] Please see Figure 8 , Figure 8This is another flowchart illustrating the task execution method disclosed in the embodiments of this application. For example... Figure 8 The task execution method shown may include the following steps:

[0170] 801. The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task.

[0171] It should be noted that for detailed information on step 801, please refer to [link / reference needed]. Figure 2 The description of step 201 in the illustrated embodiment will not be repeated here.

[0172] 802. The scheduling unit loads the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs corresponding to each algorithm in multiple algorithms.

[0173] It should be noted that the method of loading the target subgraph by the scheduling unit can be found in the above description of the method of loading the target subgraph by the processing unit, and will not be repeated here.

[0174] It is understandable that when there are multiple target subgraphs, the scheduling unit can load the next target subgraph from the storage unit and send it to the processing unit after determining that the processing unit has finished executing the instructions corresponding to the previous target subgraph.

[0175] 803. The scheduling unit sends the target sub-graph to the processing unit.

[0176] 804. The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0177] By implementing Figure 8 The method described above pre-compiles the algorithm modules of each algorithm executed by the task execution device to obtain subgraphs for each algorithm. Then, it calculates the union of these subgraphs and stores the resulting subgraphs in a storage unit. During task execution, the scheduling unit can directly load the target subgraph of the target algorithm from the storage unit based on its target address information, significantly improving the efficiency of target subgraph retrieval and consequently enhancing the task execution efficiency of the task execution device. Furthermore, the scheduling unit sends the loaded target subgraph to the processing unit, which then executes the corresponding instructions. This eliminates the need for the processing unit to concern itself with the details of underlying storage unit access, simplifying its design and reducing its workload and power consumption.

[0178] Please see Figure 9 , Figure 9 This is a device illustration of a processing unit disclosed in an embodiment of this application. For example... Figure 9The processing unit shown may include a receiving module 901, a subgraph loading module 902, and an execution module 903; wherein:

[0179] The receiving module 901 is used to receive the target address information of the target subgraph of the target algorithm that matches the current task;

[0180] The subgraph loading module 902 is used to load the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs corresponding to each algorithm in multiple algorithms;

[0181] The execution module 903 is used to execute the instructions corresponding to the target subgraphs; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0182] In some embodiments, the target address information includes pointer information of the target subgraph in the storage unit.

[0183] In some embodiments, when there are multiple target subgraphs, the pointer information is a pointer queue consisting of pointers of each target subgraph in the storage unit, and the order of the pointers of each target subgraph in the pointer queue is consistent with the execution order of each target subgraph in the target algorithm.

[0184] In some embodiments, the target address information includes the mapping address information of the pointers of the target subgraphs in the storage unit, and the mapping address information is used to determine the storage address of the pointers of each target subgraph.

[0185] In some embodiments, the algorithm includes multiple operators, one or more operators form a subgraph, and each operator corresponds to one or more instructions; the target subgraph corresponds to at least one operator.

[0186] In some embodiments, the processing unit includes an AI accelerator.

[0187] Please see Figure 10 , Figure 10 This is a structural illustration of a processing chip disclosed in an embodiment of this application. For example... Figure 10 The processing chip shown may include: a memory 1001 storing executable program code, and a processor 1002 coupled to the memory 1001.

[0188] In this embodiment of the application, the processor 1002 has the following functions:

[0189] The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task, and sends the target address information to the processing unit.

[0190] The processing unit loads the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms;

[0191] The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0192] In this embodiment of the application, the target address information includes pointer information of the target subgraph in the storage unit.

[0193] In this embodiment of the application, when there are multiple target subgraphs, the pointer information is a pointer queue composed of pointers of each target subgraph in the storage unit. The order of the pointers of each target subgraph in the pointer queue is consistent with the execution order of each target subgraph in the target algorithm.

[0194] In this embodiment of the application, the target address information includes the mapping address information of the pointers of the target subgraphs in the storage unit. The mapping address information is used to determine the storage address of the pointers of each target subgraph.

[0195] In the embodiments of this application, the algorithm includes multiple operators, one or more operators form a subgraph, and the operator corresponds to one or more instructions; the target subgraph corresponds to at least one operator.

[0196] In this embodiment of the application, the processing unit includes an AI accelerator.

[0197] In this embodiment of the application, the processor 1002 also has the following functions:

[0198] The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task based on the mapping relationship between multiple algorithms and the address information of their corresponding subgraphs.

[0199] In this embodiment of the application, the processor 1002 also has the following functions:

[0200] The scheduling unit obtains reference information for the current task, which includes at least one of the following: task type, application scenario, and processing unit hardware characteristics.

[0201] The scheduling unit determines the target algorithm that matches the reference information of the current task based on the mapping relationship between various preset algorithms and corresponding reference information.

[0202] In this embodiment of the application, the processor 1002 also has the following functions:

[0203] Combine multiple operators included in the algorithm into one or more subgraphs;

[0204] The union of the subgraphs of each algorithm in multiple algorithms is stored in the storage unit.

[0205] In this embodiment of the application, the processor 1002 also has the following functions:

[0206] The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task;

[0207] The scheduling unit loads the target subgraph from the storage unit based on the target address information and sends the target subgraph to the processing unit; the subgraph in the storage unit is the union of the subgraphs corresponding to each algorithm in multiple algorithms;

[0208] The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

[0209] This application discloses a computer-readable storage medium storing executable program code thereon. When the executable program code is executed by a processor, it implements the methods described in this application embodiment.

[0210] This application discloses a computer program product that, when run on a computer, enables the computer to implement the methods described in this application.

[0211] This application discloses an application publishing platform for publishing computer program products. When the computer program product is run on a computer, the computer implements the methods described above in this application.

[0212] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium, storage medium, and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0213] It should be understood that the phrases "one embodiment," "an embodiment," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be repeated here.

[0214] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0215] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0216] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0217] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules. They may be located in one place or distributed across multiple network units. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0218] In addition, each functional module in the various embodiments of this application can be integrated into one processing unit, or each module can be a separate unit, or two or more modules can be integrated into one unit; the integrated modules can be implemented in hardware or in the form of hardware plus software functional units.

[0219] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0220] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0221] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0222] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0223] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0224] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A task execution method, characterized in that, The method is applicable to a task execution device, the task execution device including a scheduling unit and a processing unit, and the method includes: The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task, and sends the target address information to the processing unit. The processing unit loads the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms; The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

2. The method according to claim 1, characterized in that, The target address information includes the pointer information of the target subgraph in the storage unit.

3. The method according to claim 2, characterized in that, When there are multiple target subgraphs, the pointer information is a pointer queue composed of pointers of each target subgraph in the storage unit. The order of the pointers of each target subgraph in the pointer queue is consistent with the execution order of each target subgraph in the target algorithm.

4. The method according to claim 1, characterized in that, The target address information includes the mapping address information of the pointers of the target subgraphs in the storage unit, and the mapping address information is used to determine the storage address of the pointers of each target subgraph.

5. The method according to any one of claims 1-4, characterized in that, The algorithm includes multiple operators, and one or more of the operators form a subgraph. Each operator corresponds to one or more instructions. The target subgraph corresponds to at least one operator.

6. The method according to any one of claims 1-4, characterized in that, The processing unit includes an AI accelerator.

7. The method according to any one of claims 1-4, characterized in that, The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task, including: The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task based on the mapping relationship between multiple algorithms and the address information of their corresponding subgraphs.

8. The method according to any one of claims 1-4, characterized in that, Before the scheduling unit determines the target address information of the target subgraph of the target algorithm matching the current task, the method further includes: The scheduling unit obtains reference information for the current task, and the reference information includes at least one of the following: task type, application scenario, and hardware characteristics of the processing unit; The scheduling unit determines the target algorithm that matches the reference information of the current task based on the mapping relationship between various preset algorithms and corresponding reference information.

9. The method according to any one of claims 1-4, characterized in that, The method further includes: The algorithm combines multiple operators into one or more subgraphs; The union of the subgraphs of each algorithm in multiple algorithms is stored in the storage unit.

10. A task execution method, characterized in that, The method is applicable to a task execution device, the task execution device including a scheduling unit and a processing unit, and the method includes: The scheduling unit determines the target address information of the target subgraph of the target algorithm that matches the current task; The scheduling unit loads the target subgraph from the storage unit according to the target address information and sends the target subgraph to the processing unit; wherein, the subgraph in the storage unit is the union of the subgraphs corresponding to each algorithm in multiple algorithms; The processing unit executes the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

11. A task execution method, characterized in that, The method is applicable to a processing unit in a task execution device, and the method includes: Receive the target address information of the target subgraph of the target algorithm that matches the current task; Based on the target address information, the target subgraph is loaded from the storage unit; wherein, the subgraph in the storage unit is the union of the subgraphs corresponding to each algorithm in multiple algorithms; Execute the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

12. A task execution device, characterized in that: Includes a scheduling unit and a processing unit; The scheduling unit is used to determine the target address information of the target subgraph of the target algorithm that matches the current task, and to send the target address information to the processing unit. The processing unit is used to load the target subgraph from the storage unit according to the target address information; wherein, the subgraph in the storage unit is the union of the subgraphs of each of the multiple algorithms; The processing unit is further configured to execute the instructions corresponding to the target subgraph; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

13. A processing unit, characterized in that, include: The receiving module is used to receive the target address information of the target subgraph of the target algorithm that matches the current task; A subgraph loading module is used to load the target subgraph from the storage unit according to the target address information; wherein the subgraph in the storage unit is the union of the subgraphs corresponding to each of the multiple algorithms; An execution module is used to execute the instructions corresponding to the target subgraphs; wherein the execution order of the instructions corresponding to each target subgraph is consistent with the execution order of each target subgraph in the target algorithm.

14. A processing chip, characterized in that, include: Memory containing executable program code; and the processor coupled to the memory; The processor calls the executable program code stored in the memory, and when the executable program code is executed by the processor, the processor implements the method as described in any one of claims 1 to 10.

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