A method and system for accelerating ROM read operation based on low-power dynamic optimization

Abstract

This invention provides a low-power dynamic optimization-based ROM read acceleration method and system, relating to the field of computer storage access technology. The method includes: acquiring the target ROM address sequence, constructing an address dependency mapping table, recursively expanding the address access path, identifying loop patterns, measuring address jump probabilities, determining the prefetch set and constructing an address-time access matrix, extracting feature vectors, calculating address importance scores, and solving for the optimal prefetch subset and order. This achieves efficient ROM data prefetching, reduces access latency, minimizes invalid prefetching, optimizes system energy consumption, and improves data read efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer storage access technology, and in particular to a method and system for accelerating ROM read operation based on low-power dynamic optimization. Background Technology

[0002] With the widespread application of computer systems and embedded devices, ROM, as an important storage device, is widely used to store program code and fixed data. ROM has advantages such as non-volatility and fast data access speed, and is often used in scenarios such as BIOS, microcontroller program storage, and embedded system firmware. However, compared with the CPU processing speed, the access speed of ROM is still relatively slow, which has become a bottleneck for improving system performance.

[0003] Traditional technologies typically employ caching mechanisms to preload frequently accessed data into faster memory. Existing ROM acceleration methods mainly include static prefetching, sequential prefetching, and history-based prefetching. However, these methods still suffer from limited ability to identify complex dynamic access patterns, particularly for programs with conditional branches and loop structures. This results in low prediction accuracy, leading to inefficient prefetching, a lack of dynamic awareness of system operating status and energy consumption, an inability to effectively balance performance and power consumption, and a failure to fully consider address dependencies and the periodicity of access patterns, thus hindering the accurate identification and retention of truly important data. Summary of the Invention

[0004] This invention provides a ROM read acceleration method and system based on low-power dynamic optimization, which can at least solve some of the problems existing in the prior art.

[0005] A first aspect of this invention provides a ROM read acceleration method based on low-power dynamic optimization, comprising:

[0006] Obtain the target ROM address sequence to be read, and perform a timing scan on the target ROM address sequence to determine the reference relationship and reuse relationship to obtain an address dependency mapping table;

[0007] Based on the set of successor addresses in the address dependency mapping table, the successor addresses of the currently visited addresses are recursively expanded at multiple levels. The access closed-loop address subsequences are identified and the loop pattern is marked. The repeated access cycle is predicted and the probability distribution of branch jump nodes is calculated. Based on the probability distribution, the address expansion depth is determined to obtain the prefetch address set.

[0008] Data is read from the ROM according to the prefetch address set and loaded into the cache area to obtain time-sensitive cache data. Target data is retrieved from the time-sensitive cache data and an access execution record is generated.

[0009] Based on the access execution records, an address-time access matrix is ​​constructed and singular value decomposition is performed to extract principal component feature vectors. Based on the principal component feature vectors, the importance scores of addresses in the prefetch address set are calculated. Based on the importance scores, the optimal address subset is solved using a knapsack problem solving algorithm, and the optimal address subset is topologically sorted to determine the prefetch order, resulting in an efficient prefetch execution scheme, which is then output.

[0010] In one alternative implementation,

[0011] Obtaining the target ROM address sequence to be read, and performing a timing scan on the target ROM address sequence to determine the reference relationship and reuse relationship to obtain the address dependency mapping table includes:

[0012] A timing scan is performed on the target ROM address sequence to be read, and the target ROM address sequence is divided into multiple time window segments according to the access time order;

[0013] Extract the sequential and jump dependencies between addresses within each time window segment;

[0014] Identify recurring addresses in multiple time window segments, count the occurrence interval of the recurring addresses in different time window segments, and label the occurrence interval as a multiplexing cycle feature to the corresponding address.

[0015] Based on the sequential dependency and jump dependency, a predecessor address set and a successor address set are constructed for each address. The reuse cycle feature is embedded into the predecessor address set and the successor address set to obtain an address dependency mapping table containing the reuse cycle feature.

[0016] In one alternative implementation,

[0017] Based on the set of successor addresses in the address dependency mapping table, a multi-level recursive expansion is performed on the successor addresses of the currently visited addresses to identify the accessed closed-loop address subsequences and mark the loop pattern, including:

[0018] Select a successor address from the set of successor addresses of the currently visited address as the current expanded node, and extract the set of successor addresses of the current expanded node for the next level of expansion;

[0019] During each expansion process, the current expansion node is compared one by one with all the preceding nodes in the previous expansion path. When the current expansion node is found to be the same as any preceding node in the previous expansion path, the complete address sequence between the preceding node and the current expansion node is extracted as the access closed-loop address subsequence.

[0020] Each address in the access closed-loop address subsequence is marked with a loop start mark and a loop end mark, wherein the preceding node is marked as a loop start mark, the current expanded node is marked as a loop end mark, and the address in the access closed-loop address subsequence located between the preceding node and the current expanded node is marked as a loop middle node mark;

[0021] The loop start marker, the loop end marker, and the loop intermediate node marker are combined into a loop pattern label, and the loop pattern label is associated with the access closed loop address subsequence.

[0022] In one alternative implementation,

[0023] Predicting the recurrence cycle and calculating the probability distribution of branch jump nodes, and determining the address expansion depth based on the probability distribution to obtain the prefetch address set includes:

[0024] Each address in the access closed-loop address subsequence is taken as a state node. The number of transitions from the state node to the successor state node and the total number of transitions are counted and the state transition probability is calculated to construct a Markov state transition matrix. Multi-step state transition prediction is performed through the Markov state transition matrix and the cumulative number of transition steps when returning to the initial state node is recorded to obtain the repeated access period. The access probability distribution is calculated based on the repeated access period.

[0025] Based on the access probability distribution, nodes with multiple successor addresses in the address dependency mapping table are identified as branch jump nodes, and the transfer probability of each branch jump node pointing to each successor address is calculated to obtain the probability distribution of the branch jump node.

[0026] Based on the probability distribution of the branch jump nodes, recursively expand to obtain the successor address branches and use the accessed address sequence as the branch access pattern feature. Based on the branch access pattern feature, calculate the similarity of the successor address branches and divide the successor address branches with similarity higher than a preset similarity threshold into the same cluster. Based on the cluster, calculate the cluster-level transfer probability of each successor address branch in the cluster and allocate an expansion depth quota to each cluster.

[0027] Batch expansion is performed based on the expansion depth quota. When the recursion level of any successor address branch in the cluster reaches the expansion depth quota, the expansion stops and the addresses traversed during the expansion process are collected to obtain the prefetch address set.

[0028] In one alternative implementation,

[0029] Data is read from the ROM according to the prefetch address set and loaded into the cache area to obtain time-lapse cache data. Retrieving target data from the time-lapse cache data and generating an access execution record includes:

[0030] The prefetch address set is aligned and extended according to the memory block boundaries of the ROM to form an aligned address set, and the addresses of adjacent memory blocks in the aligned address set are merged into a continuous read range;

[0031] According to the continuous read range, a batch read request is initiated to the ROM, the read data is loaded into the cache area, and the load timestamp of each storage block and the predicted cache expiration time are recorded to form time-sensitive cache data;

[0032] Receive a read request and extract the target address from the read request. Based on the target address, retrieve the corresponding storage block in the time-lapse cache data and determine whether the time difference between the current time and the loading timestamp of the storage block exceeds the predicted cache expiration time.

[0033] If the cache hit does not exceed the limit, the target data corresponding to the target address is extracted from the storage block and a cache hit flag is recorded. If the cache hit exceeds the limit, the target data corresponding to the target address is reread from the ROM and a cache miss flag is recorded. An access execution record is generated based on the cache hit flag, the cache miss flag, the target address corresponding to the read request, and the access timestamp.

[0034] In one alternative implementation,

[0035] Based on the access execution records, an address-time access matrix is ​​constructed, and singular value decomposition is performed to extract principal component feature vectors. Based on the principal component feature vectors, importance scores are calculated for addresses in the prefetched address set, including:

[0036] Extract cache hit addresses, cache miss addresses, and corresponding access timestamps from the access execution records, and construct an address-time access matrix using the address number as the row index and the access timestamp as the column index.

[0037] The address-time access matrix is ​​sparsified, retaining elements with non-zero access counts. The sparsified address-time access matrix is ​​then decomposed using a truncated singular value decomposition algorithm to obtain a left singular matrix and a singular value diagonal matrix. Singular values ​​are extracted from the singular value diagonal matrix to calculate the cumulative singular value contribution rate and determine the principal component dimension. Column vectors corresponding to the principal component dimension are extracted from the left singular matrix to obtain the principal component feature vector.

[0038] Project the row vector corresponding to each address in the prefetched address set into the feature space formed by the principal component feature vectors to obtain the projection vector. Calculate the projection components of the projection vector on different principal component feature vectors. Perform nonlinear transformation and weighted summation on the projection components to obtain the importance score corresponding to each address.

[0039] In one alternative implementation,

[0040] Based on the importance score, the optimal address subset is solved using a knapsack problem algorithm, and the optimal address subset is topologically sorted to determine the prefetching order, resulting in an efficient prefetching execution scheme, which includes:

[0041] Using addresses in the prefetched address set as options and the importance score as the value, the knapsack capacity is set based on the capacity of the cache area. An initial decision matrix is ​​constructed using a dynamic programming algorithm. The initial decision matrix is ​​filled by traversing address by address and comparing the matrix element values ​​at each address. The complete decision matrix is ​​obtained by backtracking based on the complete decision matrix and determining whether the current address is selected. The selected address is extracted and added to the address set. The backtracking continues until the first address is reached to obtain the optimal address subset.

[0042] Extract the access dependencies between different addresses in the optimal address subset and construct an adjacency list. Determine the in-degree value of each address in the optimal address subset based on the dependency adjacency list to obtain a set of address in-degree values.

[0043] Addresses with an in-degree value of zero from the set of address in-degree values ​​are added to the queue to be processed, resulting in an initial queue to be processed. Addresses are then sequentially retrieved from the initial queue to be processed and added to the prefetch order sequence. The subsequent address pointed to by the retrieved address is obtained according to the dependency adjacency list, and the in-degree value of the subsequent address is decremented by one. It is then determined whether the in-degree value of the subsequent address is zero. If it is zero, the subsequent address is added to the queue to be processed. This process of retrieving and adding addresses is repeated to obtain the prefetch order. The optimal address subset and the prefetch order are then encapsulated to obtain an efficient prefetch execution scheme and output.

[0044] A second aspect of the present invention provides a ROM read acceleration system based on low-power dynamic optimization, comprising:

[0045] The first unit is used to obtain the target ROM address sequence to be read, and to perform a timing scan on the target ROM address sequence to determine the reference relationship and reuse relationship to obtain an address dependency mapping table;

[0046] The second unit is used to perform multi-level recursive expansion of the successor address of the currently visited address based on the successor address set in the address dependency mapping table, identify the access closed-loop address subsequence and mark the loop pattern, predict the repeated access cycle and calculate the probability distribution of the branch jump node, and determine the address expansion depth based on the probability distribution to obtain the prefetch address set.

[0047] The third unit is used to read data from the ROM according to the prefetch address set and load it into the cache area to obtain time-sensitive cache data, retrieve target data from the time-sensitive cache data and generate access execution records;

[0048] The fourth unit is used to construct an address-time access matrix based on the access execution records and extract principal component feature vectors by performing singular value decomposition. Based on the principal component feature vectors, the unit calculates the importance score of the addresses in the prefetch address set. Based on the importance score, the unit solves the optimal address subset using a knapsack problem algorithm and performs topological sorting on the optimal address subset to determine the prefetch order, thereby obtaining an efficient prefetch execution scheme and outputting it.

[0049] A third aspect of the present invention provides an electronic device, comprising:

[0050] A processor and a memory for storing processor-executable instructions, wherein the processor is configured to invoke instructions stored in the memory to perform the aforementioned method.

[0051] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0052] In this invention, by constructing an address dependency mapping table and performing multi-level recursive expansion, the cyclic patterns of ROM access can be effectively identified, enabling accurate prediction of address access sequences and improving the accuracy of data prefetching. Principal component features are extracted using singular value decomposition (SVD), and the optimal prefetch address subset is determined through a knapsack problem algorithm. This solves the resource waste problem caused by blind loading in traditional prefetching methods, achieving an efficient data prefetching strategy within limited cache space. The prefetching strategy is dynamically adjusted based on access execution records, and the prefetching order is determined according to address importance scores, enabling the system to adaptively optimize according to actual access patterns. This effectively reduces ROM read power consumption while improving data access speed. Attached Figure Description

[0053] Figure 1 This is a flowchart illustrating the ROM read acceleration method based on low-power dynamic optimization according to an embodiment of the present invention.

[0054] Figure 2 This is a flowchart illustrating the address importance score calculation process of the ROM read acceleration method based on low-power dynamic optimization in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0057] Figure 1 This is a flowchart illustrating the ROM read acceleration method based on low-power dynamic optimization according to an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes:

[0058] Obtain the target ROM address sequence to be read, and perform a timing scan on the target ROM address sequence to determine the reference relationship and reuse relationship to obtain an address dependency mapping table;

[0059] Based on the set of successor addresses in the address dependency mapping table, the successor addresses of the currently visited addresses are recursively expanded at multiple levels. The access closed-loop address subsequences are identified and the loop pattern is marked. The repeated access cycle is predicted and the probability distribution of branch jump nodes is calculated. Based on the probability distribution, the address expansion depth is determined to obtain the prefetch address set.

[0060] Data is read from the ROM according to the prefetch address set and loaded into the cache area to obtain time-sensitive cache data. Target data is retrieved from the time-sensitive cache data and an access execution record is generated.

[0061] Based on the access execution records, an address-time access matrix is ​​constructed and singular value decomposition is performed to extract principal component feature vectors. Based on the principal component feature vectors, the importance scores of addresses in the prefetch address set are calculated. Based on the importance scores, the optimal address subset is solved using a knapsack problem solving algorithm, and the optimal address subset is topologically sorted to determine the prefetch order, resulting in an efficient prefetch execution scheme, which is then output.

[0062] In one alternative implementation,

[0063] Obtaining the target ROM address sequence to be read, and performing a timing scan on the target ROM address sequence to determine the reference relationship and reuse relationship to obtain the address dependency mapping table includes:

[0064] A timing scan is performed on the target ROM address sequence to be read, and the target ROM address sequence is divided into multiple time window segments according to the access time order;

[0065] Extract the sequential and jump dependencies between addresses within each time window segment;

[0066] Identify recurring addresses in multiple time window segments, count the occurrence interval of the recurring addresses in different time window segments, and label the occurrence interval as a multiplexing cycle feature to the corresponding address.

[0067] Based on the sequential dependency and jump dependency, a predecessor address set and a successor address set are constructed for each address. The reuse cycle feature is embedded into the predecessor address set and the successor address set to obtain an address dependency mapping table containing the reuse cycle feature.

[0068] The target ROM address sequence to be read is time-scanned, and the address sequence is divided into multiple time window segments according to the access time order. The division of time window segments can be based on a fixed duration or a fixed number of addresses. For example, address accesses within 100ms consecutively can be divided into one time window segment, or 500 consecutive address accesses can be divided into one time window segment. Suppose that during the execution of an application, the following ROM address access sequence is recorded: 0x4000, 0x4004, 0x4008, 0x400C, 0x5000, 0x5004, 0x4000, 0x4004, 0x4008, 0x5100. This can be divided into two time window segments: the first segment contains the first 5 addresses, and the second segment contains the last 5 addresses.

[0069] Within each time window segment, sequential dependencies and jump dependencies between addresses are extracted. Sequential dependencies refer to consecutively accessed address pairs, such as accessing address B immediately after address A, which is recorded as dependency (A→B). Jump dependencies refer to non-consecutive address pairs accessed through conditional or unconditional jump instructions. Jump instructions and their target addresses are identified through instruction decoding and execution flow analysis and recorded as jump dependencies. For the first time window segment in the example above, the extracted sequential dependencies are: (0x4000→0x4004), (0x4004→0x4008), (0x4008→0x400C), (0x400C→0x5000), (0x5000→0x5004); if a conditional jump instruction is detected at address 0x4008 with a target address of 0x5000, an additional jump dependency (0x4008→0x5000) is recorded.

[0070] Repeated addresses are identified across multiple time windows, and the intervals between their occurrence in different time windows are statistically analyzed. These intervals are then used as multiplexing periodicity features and labeled to the corresponding addresses. For addresses 0x4000, 0x4004, and 0x4008 in the previous example, they appear in both the first and second time windows. Assuming the time interval between these two windows is 200ms, 200ms is used as the multiplexing periodicity feature for these three addresses. If address 0x4000 is observed to be accessed multiple times at approximately 200ms intervals in a longer sequence, the reliability of this periodicity feature is further confirmed, and it can be recorded as {Address: 0x4000, Multiplexing Period: 200ms, Confidence: 85%}.

[0071] Based on the extracted dependencies, a predecessor address set and a successor address set are constructed for each address. The predecessor address set contains all addresses that may be accessed before the target address, and the successor address set contains all addresses that may be accessed after the target address. For address 0x4008, the predecessor address set is {0x4004}, and the successor address set is {0x400C, 0x5000}. The reuse cycle feature is embedded into the predecessor and successor address sets to obtain an address dependency mapping table containing the reuse cycle feature. The format of the mapping table entries is: {current address, predecessor address set [{address, dependency type, reuse cycle, confidence}...], successor address set [{address, dependency type, reuse cycle, confidence}...]}. Taking 0x4008 as an example, the mapping table entries are: {Current address: 0x4008, Predecessor address set: [{Address: 0x4004, Dependency type: Sequential, Reuse period: 200ms, Credibility: 85%}], Successor address set: [{Address: 0x400C, Dependency type: Sequential, Reuse period: 200ms, Credibility: 85%}, {Address: 0x5000, Dependency type: Jump, Reuse period: null, Credibility: 40%}]}.

[0072] In this embodiment, by performing a time-series scan of the target ROM address sequence and dividing it into multiple time window segments according to the access time order, the ROM address access behavior can be segmented and expressed in the time dimension, improving the timing accuracy of access pattern extraction. By extracting the sequential dependency and jump dependency between addresses within each time window segment, the causal relationship and dynamic jump characteristics of address access can be reflected more comprehensively, enhancing the structured expression capability of address access patterns. By identifying recurring addresses in multiple time window segments and calculating their occurrence intervals, and labeling the occurrence intervals as reuse cycle features to the corresponding addresses, the periodicity and reuse patterns of address access can be captured, enhancing the ability to identify the periodic features of access behavior.

[0073] In one alternative implementation,

[0074] Based on the set of successor addresses in the address dependency mapping table, a multi-level recursive expansion is performed on the successor addresses of the currently visited addresses to identify the accessed closed-loop address subsequences and mark the loop pattern, including:

[0075] Select a successor address from the set of successor addresses of the currently visited address as the current expanded node, and extract the set of successor addresses of the current expanded node for the next level of expansion;

[0076] During each expansion process, the current expansion node is compared one by one with all the preceding nodes in the previous expansion path. When the current expansion node is found to be the same as any preceding node in the previous expansion path, the complete address sequence between the preceding node and the current expansion node is extracted as the access closed-loop address subsequence.

[0077] Each address in the access closed-loop address subsequence is marked with a loop start mark and a loop end mark, wherein the preceding node is marked as a loop start mark, the current expanded node is marked as a loop end mark, and the address in the access closed-loop address subsequence located between the preceding node and the current expanded node is marked as a loop middle node mark;

[0078] The loop start marker, the loop end marker, and the loop intermediate node marker are combined into a loop pattern label, and the loop pattern label is associated with the access closed loop address subsequence.

[0079] Starting from the currently accessed address, an address in the set of successor addresses corresponding to the accessed address is selected as the current expansion node. The set of successor addresses of the current expansion node is then extracted for the next level of expansion, forming an address access path. Taking a specific ROM access sequence as an example, assuming the currently accessed address is 0x4000, and its set of successor addresses is {0x4004, 0x5000}, 0x4004 is selected as the current expansion node, and then the set of successor addresses of 0x4004, {0x4008, 0x6000}, is extracted for the next level of expansion.

[0080] The expansion process employs a depth-first search strategy. After each expansion, the current expanded node is compared one by one with all preceding nodes in the previous expansion path. When the current expanded node is found to be identical to any preceding node in the previous expansion path, it indicates that an access loop has been discovered. For example, in the expansion path 0x4000→0x4004→0x4008→0x400C→0x4010→0x4004, the current expanded node 0x4004 is identical to the preceding node 0x4004. In this case, the complete address sequence 0x4004→0x4008→0x400C→0x4010→0x4004 between the preceding node 0x4004 and the current expanded node 0x4004 is extracted as the access loop address subsequence.

[0081] Each address in the accessed closed-loop address subsequence is marked with a loop characteristic marker. The preceding node (the first 0x4004 in this example) is marked as the start of the loop, the current expanded node (the second 0x4004 in this example) is marked as the end of the loop, and the addresses in the accessed closed-loop address subsequence located between the preceding node and the current expanded node (0x4008, 0x400C, 0x4010 in this example) are marked as intermediate nodes of the loop. The marking information can be represented as: {address: 0x4004, marker type: loop start}, {address: 0x4008, marker type: intermediate node of the loop}, {address: 0x400C, marker type: intermediate node of the loop}, {address: 0x4010, marker type: intermediate node of the loop}, {address: 0x4004, marker type: loop end}.

[0082] The loop start marker, loop end marker, and loop intermediate node marker are combined into a loop pattern label, which is then associated with the accessed closed-loop address subsequence. The loop pattern label includes: loop start address, loop end address, loop body address sequence, and loop characteristics (such as loop length, number of instructions within the loop body, etc.). For the example above, the loop pattern label is: {Loop start address: 0x4004, Loop end address: 0x4004, Loop body address sequence: [0x4008, 0x400C, 0x4010], Loop length: 4, Number of instructions within the loop body: 12}. If the same loop pattern is observed to appear multiple times, the frequency and reliability information of the loop occurrence can also be recorded.

[0083] In this embodiment, by comparing the current expanded node with all preceding nodes in the previous expanded path and extracting the closed-loop address subsequence during each expanded process, the loop structure in the access process can be automatically identified, improving the detection accuracy of the closed-loop access pattern. By marking the loop start, loop end, and loop middle nodes of each address in the access closed-loop address subsequence, the loop structure is clearly marked in the sequence, enhancing the identifiability and structured expression of the loop pattern. By combining the loop markers into loop pattern markers and associating them with the access closed-loop address subsequence, the loop pattern and address sequence are effectively bound together, improving the analyzability of ROM access loop behavior and the accuracy of subsequent optimization or prediction.

[0084] In one alternative implementation,

[0085] Predicting the recurrence cycle and calculating the probability distribution of branch jump nodes, and determining the address expansion depth based on the probability distribution to obtain the prefetch address set includes:

[0086] Each address in the access closed-loop address subsequence is taken as a state node. The number of transitions from the state node to the successor state node and the total number of transitions are counted and the state transition probability is calculated to construct a Markov state transition matrix. Multi-step state transition prediction is performed through the Markov state transition matrix and the cumulative number of transition steps when returning to the initial state node is recorded to obtain the repeated access period. The access probability distribution is calculated based on the repeated access period.

[0087] Based on the access probability distribution, nodes with multiple successor addresses in the address dependency mapping table are identified as branch jump nodes, and the transfer probability of each branch jump node pointing to each successor address is calculated to obtain the probability distribution of the branch jump node.

[0088] Based on the probability distribution of the branch jump nodes, recursively expand to obtain the successor address branches and use the accessed address sequence as the branch access pattern feature. Based on the branch access pattern feature, calculate the similarity of the successor address branches and divide the successor address branches with similarity higher than a preset similarity threshold into the same cluster. Based on the cluster, calculate the cluster-level transfer probability of each successor address branch in the cluster and allocate an expansion depth quota to each cluster.

[0089] Batch expansion is performed based on the expansion depth quota. When the recursion level of any successor address branch in the cluster reaches the expansion depth quota, the expansion stops and the addresses traversed during the expansion process are collected to obtain the prefetch address set.

[0090] After identifying the access loop address subsequence, each address in the subsequence is treated as a state node. Based on historical access data, the transitions between state nodes are statistically analyzed. For each pair of adjacent state nodes, the state transition probability is calculated, which is the number of times the current state node transitions to a specific successor state node divided by the total number of transitions from the current state node. Taking a specific loop access sequence as an example, assuming that the successor addresses of address 0x4004 include 0x4008 and 0x5000, in 100 accesses, 80 transitions are to 0x4008 and 20 transitions are to 0x5000, then the state transition probabilities are 0.8 and 0.2, respectively. This process is repeated for each state node to construct a complete Markov state transition matrix, where each element represents the transition probability between the corresponding states.

[0091] Multi-step state transition prediction is performed using Markov state transition matrices. Starting from a specific state node, multiple consecutive state transitions are simulated based on the transition probabilities. The cumulative number of transition steps when returning to the initial state node is recorded to obtain the recurrence period. For example, starting from state node 0x4004, multiple simulations show that it takes an average of 12 state transitions to return to 0x4004, therefore the recurrence period for this state is 12. Based on the recurrence period, the address access probability distribution is calculated, which is the probability of accessing a specific address at a specific time in the future.

[0092] Based on the access probability distribution, nodes with multiple successor addresses in the address dependency mapping table are identified as branch jump nodes. Branch jump nodes typically correspond to conditional branch instructions, such as conditional jump instructions. The transfer probability of each successor address pointed to by the branch jump node is calculated, forming the probability distribution of the branch jump node. For example, for the conditional branch instruction at address 0x4020, its successor addresses are 0x4024 and 0x5000. The transfer probabilities calculated based on historical data are 0.65 and 0.35, respectively. Then the probability distribution of this branch jump node is {0x4024: 0.65, 0x5000: 0.35}.

[0093] Based on the probability distribution of branch jump nodes, recursive expansion is performed to obtain possible successor address branch paths. Each branch path contains the address sequence accessed along a specific path starting from the branch jump node, thus obtaining branch access pattern characteristics. For example, starting from 0x4020, possible branch paths include: path A (0x4020→0x4024→0x4028→0x402C) and path B (0x4020→0x5000→0x5004→0x5008→0x500C).

[0094] The similarity between branches with different successor addresses is calculated by comparing the characteristics of branch access patterns. Similarity calculation can employ algorithms such as Jaccard similarity and cosine similarity, or a similarity metric specific to ROM access patterns can be designed. If the similarity between two branches is higher than a preset similarity threshold (e.g., 0.7), they are grouped into the same cluster. For example, if the similarity between path A and path B is 0.3, which is lower than the threshold of 0.7, they are grouped into different clusters; if the similarity between path C (0x4020→0x5000→0x5004→0x5100→0x5104) and path B is 0.8, which is higher than the threshold of 0.7, then path B and path C are grouped into the same cluster.

[0095] For each cluster, calculate the cluster-level transition probability of each successor address branch within the cluster, i.e., the probability of selecting that branch. The cluster-level transition probability can be calculated based on the frequency of each branch being selected in historical data, or it can be determined by combining the transition probability of the branch jump node and the similarity between branches. For example, for a cluster containing paths B and C, if path B appears 150 times and path C appears 50 times in historical data, the cluster-level transition probabilities are 0.75 and 0.25, respectively.

[0096] Based on cluster-level transition probabilities and system resource constraints, unfold depth quotas are allocated to each cluster. The unfold depth quota determines the maximum number of levels a branch of the corresponding cluster can unfold in the prefetch decision. Clusters with higher transition probabilities receive larger unfold depth quotas to prioritize code paths that are more likely to be executed. For example, if the total unfold depth quota is 100, and two clusters have cluster-level transition probabilities of 0.8 and 0.2 respectively, then they receive unfold depth quotas of 80 and 20 respectively.

[0097] Batch expansion is performed based on the allocated expansion depth quota. For each cluster's successor address branch, expansion is performed using either a depth-first or breadth-first strategy, collecting all addresses traversed during the expansion process. The expansion process for a cluster stops when the recursion level of any successor address branch reaches the expansion depth quota. Finally, the addresses collected during the expansion of all clusters are merged to form a prefetched address set. For example, a cluster with an expansion depth quota of 80 might expand to the address set {0x5000, 0x5004, 0x5008, 0x500C, 0x5100, 0x5104, ...}; a cluster with an expansion depth quota of 20 might expand to the address set {0x4024, 0x4028, 0x402C, ...}. The merged prefetch address set is {0x5000, 0x5004, 0x5008, 0x500C, 0x5100, 0x5104, 0x4024, 0x4028, 0x402C, ...}.

[0098] In this embodiment, by identifying branch jump nodes with multiple successor addresses based on access probability distribution and calculating the transition probability to each successor address, the preferred patterns of address branch behavior can be accurately captured, improving the accuracy of branch path prediction. By recursively expanding based on the probability distribution of branch jump nodes and constructing branch access pattern features, a systematic expansion and structured representation of complex access branches is achieved, enhancing the analytical capability for multi-branch access behavior. Furthermore, by calculating the similarity of successor address branches based on branch access pattern features, performing clustering, calculating cluster-level transition probabilities, and allocating expansion depth quotas, access branches can be rationally organized and prioritized based on similarity, thereby improving the accuracy and coverage efficiency of the prefetched address set.

[0099] In one alternative implementation,

[0100] Data is read from the ROM according to the prefetch address set and loaded into the cache area to obtain time-lapse cache data. Retrieving target data from the time-lapse cache data and generating an access execution record includes:

[0101] The prefetch address set is aligned and extended according to the memory block boundaries of the ROM to form an aligned address set, and the addresses of adjacent memory blocks in the aligned address set are merged into a continuous read range;

[0102] According to the continuous read range, a batch read request is initiated to the ROM, the read data is loaded into the cache area, and the load timestamp of each storage block and the predicted cache expiration time are recorded to form time-sensitive cache data;

[0103] Receive a read request and extract the target address from the read request. Based on the target address, retrieve the corresponding storage block in the time-lapse cache data and determine whether the time difference between the current time and the loading timestamp of the storage block exceeds the predicted cache expiration time.

[0104] If the cache hit does not exceed the limit, the target data corresponding to the target address is extracted from the storage block and a cache hit flag is recorded. If the cache hit exceeds the limit, the target data corresponding to the target address is reread from the ROM and a cache miss flag is recorded. An access execution record is generated based on the cache hit flag, the cache miss flag, the target address corresponding to the read request, and the access timestamp.

[0105] Based on the obtained prefetch address set, the ROM is aligned and extended according to the memory block boundaries to form an aligned address set. ROMs typically use memory blocks as the basic access unit; directly accessing a single unaligned address may result in additional read overhead. The memory block size depends on the specific ROM hardware implementation, with common configurations being 16 bytes, 32 bytes, or 64 bytes. The alignment and extension process involves calculating the starting address of the memory block to which each address in the prefetch address set belongs, and then including all addresses of that memory block into the aligned address set. For example, if the ROM's memory block size is 16 bytes, and the prefetch address set contains addresses 0x4005 and 0x4023, then the aligned address set is {0x4000-0x400F, 0x4020-0x402F}, where 0x4000 and 0x4020 are the starting addresses of their respective memory blocks.

[0106] The merging process combines adjacent memory blocks in the aligned address set into a contiguous read range. Adjacent memory blocks refer to those with consecutive physical addresses, such as two 16-byte blocks starting at addresses 0x4000 and 0x4010. The merging process involves scanning the aligned address set, identifying sequences of contiguous memory blocks, and combining them into a contiguous read range. For example, if the aligned address set contains {0x4000-0x400F, 0x4010-0x401F, 0x4020-0x402F, 0x5000-0x500F, 0x5010-0x501F}, they can be merged into a contiguous read range {0x4000-0x402F, 0x5000-0x501F}. The merging criterion is: if the difference between the starting addresses of two memory blocks is exactly equal to the block size, they can be merged into a contiguous read range.

[0107] Based on the determined continuous read range, a batch read request is initiated to the ROM. The batch read request includes the read start address and the read data length. The ROM controller executes the actual read operation according to the parameters. The read data is loaded into a preset cache area, and a load timestamp and predicted cache expiration time are recorded for each memory block, forming time-sensitive cache data. The load timestamp records the system time when the data was loaded into the cache; the predicted cache expiration time is calculated based on historical access patterns, Markov state transition prediction results, and cache replacement strategies. For example, if data in the address range 0x4000-0x402F is loaded into the cache at system time 10:15:30.500, and its effective usage time is predicted to be 200ms based on historical access patterns, then the cache record for this memory block is {Start Address: 0x4000, End Address: 0x402F, Load Timestamp: 10:15:30.500, Predicted Expiration Time: 200ms}.

[0108] When a ROM read request is received from the CPU or other components, the target address in the request is extracted, and the corresponding memory block is retrieved from the cache data based on that address. The retrieval process uses an address mapping algorithm to map the target address to a memory block in the cache. For example, if the target address of the read request is 0x4018, the data block in the cache with a storage range of 0x4000-0x402F can be located through address mapping. The time difference between the current system time and the load timestamp of this memory block is then checked to see if it exceeds the predicted cache expiration time. The time difference is calculated by subtracting the load timestamp from the current system time in milliseconds. For example, if the current system time is 10:15:30.650 and the load timestamp is 10:15:30.500, the time difference is 150ms, which is less than the predicted expiration time of 200ms, indicating that the cache is still valid.

[0109] If the time difference does not exceed the predicted cache expiration time, it indicates that the cached data is still valid. The target data corresponding to the target address can be directly extracted from the cache storage block, and a cache hit flag is recorded. Target data extraction is calculated using the offset between the target address and the starting address of the storage block. For example, the offset between the target address 0x4018 and the starting address of the storage block 0x4000 is 0x18 (24 bytes), and the data is extracted from the 24th byte of the cached data. The cache hit flag contains information such as the target address, access time, and hit status, such as {Address: 0x4018, Time: 10:15:30.650, Status: Hit}.

[0110] If the time difference exceeds the predicted cache expiration time, it indicates that the cached data may have expired. The target data corresponding to the target address needs to be reread from ROM, and a cache miss flag should be recorded. For example, if the current system time is 10:15:30.750 and the load timestamp is 10:15:30.500, the time difference is 250ms, exceeding the predicted expiration time by 200ms. Therefore, the cache is considered expired, and the data needs to be reread from ROM. The cache miss flag is recorded as {Address: 0x4018, Time: 10:15:30.750, Status: Miss}.

[0111] An access execution record is generated based on the cache hit flag, cache miss flag, target address corresponding to the read request, and access timestamp. The access execution record contains complete access information. For example, a typical access execution record format is: {Request ID: 12345, Address: 0x4018, Request Time: 10:15:30.645, Completion Time: 10:15:30.650, Cache Status: Hit, Read Latency: 5ms}.

[0112] In this embodiment, by aligning and expanding the prefetch address set according to the ROM storage block boundary and merging adjacent storage block addresses into a continuous read range, batching and alignment processing of ROM access requests is achieved. This reduces the addressing overhead caused by discrete reads and improves data reading efficiency. By initiating batch read requests to the ROM based on the continuous read range and loading data into the cache area, the loading timestamp and the predicted cache expiration time are recorded to form time-sensitive cache data. This enables cache management to have time-sensitive control capabilities, improving cache utilization and data validity. By retrieving time-sensitive cache data based on the target address and determining whether the cache is invalid when receiving a read request, the cache hit status can be dynamically determined, thereby achieving efficient data access decisions.

[0113] In one alternative implementation,

[0114] Based on the access execution records, an address-time access matrix is ​​constructed, and singular value decomposition is performed to extract principal component feature vectors. Based on the principal component feature vectors, importance scores are calculated for addresses in the prefetched address set, including:

[0115] Extract cache hit addresses, cache miss addresses, and corresponding access timestamps from the access execution records, and construct an address-time access matrix using the address number as the row index and the access timestamp as the column index.

[0116] The address-time access matrix is ​​sparsified, retaining elements with non-zero access counts. The sparsified address-time access matrix is ​​then decomposed using a truncated singular value decomposition algorithm to obtain a left singular matrix and a singular value diagonal matrix. Singular values ​​are extracted from the singular value diagonal matrix to calculate the cumulative singular value contribution rate and determine the principal component dimension. Column vectors corresponding to the principal component dimension are extracted from the left singular matrix to obtain the principal component feature vector.

[0117] Project the row vector corresponding to each address in the prefetched address set into the feature space formed by the principal component feature vectors to obtain the projection vector. Calculate the projection components of the projection vector on different principal component feature vectors. Perform nonlinear transformation and weighted summation on the projection components to obtain the importance score corresponding to each address.

[0118] Extract cache hit addresses, cache miss addresses, and corresponding access timestamps from the generated access execution records. Construct an address-time access matrix using address numbers as row indices and access timestamps as column indices. The address-time access matrix represents the access status of different addresses at different times, with each element representing the number of times or access status of the corresponding address at that time. For example, assuming the system monitors the access status of 5 different addresses (0x4000, 0x4100, 0x4200, 0x4300, 0x4400) at 10 time points, a 5-row, 10-column address-time access matrix can be constructed. If address 0x4000 is accessed twice at time t1 and the cache is hit, the corresponding element in the matrix has a value of 2; if address 0x4200 is accessed once at time t3 but the cache is not hit, the corresponding element has a value of -1, indicating a cache miss.

[0119] The constructed address-time access matrix is ​​sparsified by retaining elements with non-zero access counts and removing columns for unaccessed time points and rows for unaccessed addresses. In practical applications, most addresses are not accessed at most time points, so the address-time access matrix is ​​usually highly sparse. For example, in the previous example, if address 0x4300 is not accessed at any time point, the corresponding row in the matrix can be deleted; if no address is accessed at time point t5, the corresponding column can be deleted. The sparsified matrix may then have dimensions of 4 rows and 9 columns.

[0120] The truncated singular value decomposition (SVD) algorithm is used to decompose the sparsified address-time access matrix, yielding a left singular matrix, a singular value diagonal matrix, and a right singular matrix. SVD is a powerful matrix decomposition technique capable of revealing the inherent structural features of data. In this implementation, the left singular matrix represents the eigenvectors in the address space, the singular value diagonal matrix represents the importance of each eigenvector, and the right singular matrix represents the eigenvectors in the time space. For example, performing SVD on a sparsified 4×9 address-time access matrix may yield a 4×4 left singular matrix, a 4×4 singular value diagonal matrix, and a 4×9 right singular matrix.

[0121] Singular values ​​are extracted from the singular value diagonal matrix, the cumulative singular value contribution rate is calculated, and the principal component dimensions are determined. The cumulative singular value contribution rate is the proportion of the sum of the top k singular values ​​(arranged in descending order) to the sum of all singular values. The determination of the principal component dimensions is based on a preset cumulative contribution rate threshold. Typically, the number of dimensions that achieves a cumulative contribution rate of 85% or 90% is selected. For example, if the singular values ​​are [10.5, 5.2, 2.1, 0.8], with a sum of 18.6, then the cumulative contribution rate of the first two singular values ​​is (10.5 + 5.2) / 18.6 ≈ 84.4%. If the threshold is set to 85%, then the dimensions corresponding to the first three singular values ​​should be selected as the principal component dimensions, in which case the cumulative contribution rate is (10.5 + 5.2 + 2.1) / 18.6 ≈ 95.7%.

[0122] The principal component eigenvectors are obtained by extracting column vectors corresponding to the principal component dimensions from the left singular matrix. These eigenvectors represent the main directions of change in the address space and can capture the essential characteristics of address access patterns. In the previous example, the principal component dimension is 3, so the first three columns are extracted from the left singular matrix as the principal component eigenvectors. Assuming the first three columns of the left singular matrix are [[0.5, 0.3, 0.2], [0.4, -0.6, 0.1], [0.6, 0.4, -0.5], [0.2, -0.3, -0.8]], then three principal component eigenvectors are obtained: [0.5, 0.4, 0.6, 0.2], [0.3, -0.6, 0.4, -0.3], and [0.2, 0.1, -0.5, -0.8].

[0123] The row vector corresponding to each address in the prefetched address set in the address-time access matrix is ​​projected onto the feature space formed by the principal component eigenvectors to obtain the projection vector. The projection process involves calculating the inner product of the row vector with each principal component eigenvector. The result represents the projection component of the address in each principal component direction. For example, if the row vector corresponding to address 0x4000 in the address-time access matrix is ​​[3, 0, 2, 0, 1, 0, 0, 4, 0], after calculating the inner product with the three principal component eigenvectors, the projection component [5.2, -1.8, 2.5] is obtained, representing the projection value of the address in the three principal component directions.

[0124] The importance score for each address is obtained by performing a nonlinear transformation and weighted summation on the projected components. The nonlinear transformation can be squaring, taking the absolute value, or applying a sigmoid function. During weighted summation, singular values ​​are typically used as weights to ensure that projections along the important principal component directions contribute more. For example, squaring the projected components [5.2, -1.8, 2.5] yields [27.04, 3.24, 6.25], which are then multiplied by the corresponding singular values ​​[10.5, 5.2, 2.1] to obtain [283.92, 16.85, 13.13]. Summing these values ​​yields an importance score of 313.9.

[0125] In this embodiment, by extracting cache hit addresses, miss addresses, and access timestamps from access execution records and constructing an address-time access matrix, a structured representation of address access behavior in the time dimension is achieved, providing a unified data foundation for subsequent access feature analysis. By sparsifying the address-time access matrix and combining it with a truncated singular value decomposition algorithm for matrix decomposition, the main variation features can be extracted from high-dimensional access data, effectively reducing data redundancy and highlighting key access patterns. By calculating the cumulative contribution rate of singular values ​​to determine the principal component dimension and extracting the corresponding principal component feature vector, the dominant feature direction of access behavior can be adaptively identified, improving the representativeness and robustness of feature extraction. By projecting the row vectors of the prefetched address set onto the principal component feature space and performing nonlinear transformation and weighted summation on the projected components to obtain the address importance score, the access importance of each address can be comprehensively evaluated based on multi-dimensional features, achieving refined quantification of address priority.

[0126] Figure 2 This is a flowchart illustrating the address importance score calculation process of the ROM read acceleration method based on low-power dynamic optimization in an embodiment of the present invention.

[0127] In one alternative implementation,

[0128] Based on the importance score, the optimal address subset is solved using a knapsack problem algorithm, and the optimal address subset is topologically sorted to determine the prefetching order, resulting in an efficient prefetching execution scheme, which includes:

[0129] Using addresses in the prefetched address set as options and the importance score as the value, the knapsack capacity is set based on the capacity of the cache area. An initial decision matrix is ​​constructed using a dynamic programming algorithm. The initial decision matrix is ​​filled by traversing address by address and comparing the matrix element values ​​at each address. The complete decision matrix is ​​obtained by backtracking based on the complete decision matrix and determining whether the current address is selected. The selected address is extracted and added to the address set. The backtracking continues until the first address is reached to obtain the optimal address subset.

[0130] Extract the access dependencies between different addresses in the optimal address subset and construct an adjacency list. Determine the in-degree value of each address in the optimal address subset based on the dependency adjacency list to obtain a set of address in-degree values.

[0131] Addresses with an in-degree value of zero from the set of address in-degree values ​​are added to the queue to be processed, resulting in an initial queue to be processed. Addresses are then sequentially retrieved from the initial queue to be processed and added to the prefetch order sequence. The subsequent address pointed to by the retrieved address is obtained according to the dependency adjacency list, and the in-degree value of the subsequent address is decremented by one. It is then determined whether the in-degree value of the subsequent address is zero. If it is zero, the subsequent address is added to the queue to be processed. This process of retrieving and adding addresses is repeated to obtain the prefetch order. The optimal address subset and the prefetch order are then encapsulated to obtain an efficient prefetch execution scheme and output.

[0132] Based on the prefetched address set and corresponding importance scores, the prefetching problem is modeled as a 0-1 knapsack problem. Addresses in the prefetched address set are the options, importance scores are the values, and the cache capacity is set as the knapsack capacity. Each address is associated with a storage block of fixed size, which can be considered as each option having the same weight. For example, if the prefetched address set contains {0x4000, 0x4100, 0x4200, 0x4300, 0x4400}, with corresponding importance scores of {313.9, 205.6, 158.2, 275.1, 98.7}, each address corresponding to a 16-byte storage block, and a cache capacity of 64 bytes, then a maximum of 4 addresses can be selected for prefetching.

[0133] An initial decision matrix is ​​constructed using a dynamic programming algorithm. The number of rows in the initial decision matrix equals the size of the prefetch address set, and the number of columns equals the maximum number of storage blocks that the cache can hold. Each element in the matrix represents the maximum total value obtainable from the current position to the last address under a specific capacity constraint. Initially, the last row of the matrix is ​​known, representing the optimal decision when only the last address is considered; the values ​​of the remaining rows are obtained recursively through dynamic programming. Taking the previous example, the initial decision matrix is ​​5×4 in size, and the values ​​of the last row are [0, 98.7, 98.7, 98.7], representing the optimal value of address 0x4400 when the capacities are 0, 1, 2, and 3 storage blocks, respectively.

[0134] The initial decision matrix is ​​filled by traversing each address and comparing the values ​​of matrix elements at each address to obtain the complete decision matrix. Specifically, for position (i, j) in the matrix, the values ​​of "not selecting the current address" and "selecting the current address" need to be compared, and the larger one is taken as the value of that position. The value of "not selecting the current address" is equal to the value of position (i+1, j); the value of "selecting the current address" is equal to the importance score of the current address plus the value of position (i+1, j-1), provided that j≥1. When calculating the value of position (4, 2) in the fourth row, the value of "not selecting address 0x4300" (i.e., the value of position (5, 2) is 98.7) and the value of "selecting address 0x4300" (i.e., 275.1 + the value of position (5, 1) 98.7 = 373.8) is compared, and the larger value of 373.8 is taken as the value of position (4, 2). This process is repeated row by row and column by column to obtain the complete decision matrix.

[0135] The process involves backtracking from the complete decision matrix to determine if the current address has been selected. The selected address is then extracted and added to the address set. This backtracking continues until the first address is reached, yielding the optimal subset of addresses. The backtracking process begins at the top-left corner of the matrix (1, n), where n is the maximum capacity. The values ​​at position (i, j) and position (i+1, j) are compared. If they are equal, address i is not selected, and backtracking continues to position (i+1, j). If they are not equal, address i is selected, added to the optimal subset of addresses, and backtracking continues to position (i+1, j-1). In the previous example, assuming the top-left corner value of the filled decision matrix is ​​795.5, backtracking from position (1, 4) reveals that this value is not equal to the value at position (2, 4), indicating that address 0x4000 is selected. 0x4000 is added to the optimal subset of addresses, and backtracking continues to position (2, 3). Repeat this process to finally obtain the optimal address subset {0x4000, 0x4100, 0x4300}, with a total value of 313.9 + 205.6 + 275.1 = 794.6.

[0136] Based on the existing dependency adjacency list, the in-degree value of each address in the optimal address subset is determined, resulting in a set of address in-degree values. The in-degree value indicates how many other addresses directly depend on the current address, i.e., how many addresses must be visited before the current address. The in-degree value is calculated by traversing the adjacency list. For each address contained in the adjacency list, its in-degree value is incremented by one. For example, if the dependency adjacency list is {0x4000: [0x4100, 0x4200], 0x4100: [], 0x4200: [0x4100]}, then the in-degree value of address 0x4100 is 2 (depended on by 0x4000 and 0x4200), the in-degree value of address 0x4200 is 1 (depended on by 0x4000), and the in-degree value of address 0x4000 is 0 (not depended on by any address).

[0137] Addresses with an in-degree value of zero from the set of in-degree values ​​are added to the processing queue to obtain the initial processing queue. An in-degree value of zero indicates that the address does not depend on any other address in the optimal address subset and can be prefetched first. For example, in the previous example, the initial processing queue is [0x4000].

[0138] Addresses are sequentially retrieved from the initial queue and added to the prefetch sequence. The subsequent addresses pointed to by the retrieved addresses are obtained according to the dependency adjacency list, and their in-degree values ​​are decremented by one. The in-degree value of each subsequent address is checked for zero; if it is, it is added to the queue. This process of retrieving and adding addresses is repeated until the queue is empty, resulting in a complete prefetch sequence. For example, 0x4000 is retrieved from the queue and added to the prefetch sequence. Its subsequent addresses 0x4100 and 0x4200 are obtained according to the adjacency list, and their in-degree values ​​are decremented by one, resulting in a new set of in-degree values: {0x4100: 1, 0x4200: 0, 0x4000: 0}. At this point, the in-degree value of 0x4200 is zero, so it is added to the queue, which becomes [0x4200]. Processing continues until the final prefetch sequence [0x4000, 0x4200, 0x4100].

[0139] The optimal address subset and prefetch order are encapsulated to obtain an efficient prefetch execution scheme, which is then output. The execution scheme includes information such as the prefetch address list, prefetch order, expected cache hit rate, and power consumption estimate. For example, an efficient prefetch execution scheme can be represented as {prefetch addresses: [0x4000, 0x4100, 0x4300], prefetch order: [0x4000, 0x4300, 0x4100], expected hit rate: 92%, power consumption estimate: low}.

[0140] In this embodiment, address optimization modeling under limited cache space is achieved by using addresses in the prefetch address set as options, importance scores as values, and knapsack capacity in conjunction with cache capacity. This can balance prefetch benefits and cache usage globally, improving resource utilization efficiency in address selection. By using a dynamic programming algorithm to construct an initial decision matrix and filling the complete decision matrix by comparing matrix element values ​​during address-by-address traversal, the optimal solution can be quickly obtained under multiple constraints, improving the optimality and computational efficiency of address selection decisions. By backtracking based on the complete decision matrix to extract selected addresses and generate an optimal address subset, the optimal prefetch target is accurately extracted, ensuring that addresses that contribute the most to system performance are preferentially retained in the cache.

[0141] A second aspect of the present invention provides a ROM read acceleration system based on low-power dynamic optimization, comprising:

[0142] The first unit is used to obtain the target ROM address sequence to be read, and to perform a timing scan on the target ROM address sequence to determine the reference relationship and reuse relationship to obtain an address dependency mapping table;

[0143] The second unit is used to perform multi-level recursive expansion of the successor address of the currently visited address based on the successor address set in the address dependency mapping table, identify the access closed-loop address subsequence and mark the loop pattern, predict the repeated access cycle and calculate the probability distribution of the branch jump node, and determine the address expansion depth based on the probability distribution to obtain the prefetch address set.

[0144] The third unit is used to read data from the ROM according to the prefetch address set and load it into the cache area to obtain time-sensitive cache data, retrieve target data from the time-sensitive cache data and generate access execution records;

[0145] The fourth unit is used to construct an address-time access matrix based on the access execution records and extract principal component feature vectors by performing singular value decomposition. Based on the principal component feature vectors, the unit calculates the importance score of the addresses in the prefetch address set. Based on the importance score, the unit solves the optimal address subset using a knapsack problem algorithm and performs topological sorting on the optimal address subset to determine the prefetch order, thereby obtaining an efficient prefetch execution scheme and outputting it.

[0146] A third aspect of the present invention provides an electronic device, comprising:

[0147] A processor and a memory for storing processor-executable instructions, wherein the processor is configured to invoke instructions stored in the memory to perform the aforementioned method.

[0148] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0149] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A ROM read acceleration method based on low-power dynamic optimization, characterized in that, The method comprises the following steps: acquiring a target ROM address sequence to be read, performing time sequence scanning on the target ROM address sequence to determine reference relationship and multiplexing relationship to obtain an address dependency mapping table, which comprises the following steps: performing time sequence scanning on the target ROM address sequence to be read, and dividing the target ROM address sequence into a plurality of time window segments according to the order of access time; extracting the sequential dependency relationship and the jump dependency relationship between addresses in each time window segment; identifying repeatedly appearing addresses in the plurality of time window segments, and counting the appearance interval of the repeatedly appearing addresses in different time window segments, and marking the appearance interval as a multiplexing period feature to the corresponding address; constructing a predecessor address set and a successor address set for each address according to the sequential dependency relationship and the jump dependency relationship, embedding the multiplexing period feature into the predecessor address set and the successor address set to obtain an address dependency mapping table containing a multiplexing period feature; based on the successor address set in the address dependency mapping table, performing multi-level recursive expansion on the successor address of the current accessed address, identifying an access closed loop address subsequence and performing a loop mode marking, predicting a repeated access period and calculating a probability distribution of a branch jump node, determining an address expansion depth based on the probability distribution to obtain a prefetch address set; reading data from the ROM according to the prefetch address set and loading the data into a cache area to obtain time-sensitive cache data, retrieving target data in the time-sensitive cache data and generating an access execution record; based on the access execution record, constructing an address-time access matrix and performing singular value decomposition to extract a principal component feature vector, calculating an importance score for the addresses in the prefetch address set based on the principal component feature vector, solving an optimal address subset based on the importance score through a knapsack problem solving algorithm, and determining a prefetch order by topological sorting of the optimal address subset to obtain an efficient prefetch execution scheme and output.

2. The method of claim 1, wherein, based on the successor address set in the address dependency mapping table, performing multi-level recursive expansion on the successor address of the current accessed address, identifying an access closed loop address subsequence and performing a loop mode marking comprises the following steps: selecting a successor address from the successor address set of the current accessed address as a current expansion node, and extracting the successor address set of the current expansion node for the next level expansion; in each expansion process, the current expansion node is compared with all previous nodes in the previous expansion path one by one, when it is detected that the current expansion node is the same as any previous node in the previous expansion path, the complete address sequence between the previous node and the current expansion node is extracted as an access closed loop address subsequence; each address in the access closed loop address subsequence is marked with a loop start marker and a loop end marker, wherein the previous node is marked as a loop start marker, the current expansion node is marked as a loop end marker, and the addresses between the previous node and the current expansion node in the access closed loop address subsequence are marked as loop intermediate node markers; combining the loop start marker, the loop end marker and the loop intermediate node marker into a loop pattern annotation and associating the loop pattern annotation to the access closed loop address subsequence.

3. The method of claim 1, wherein, predicting a repeat access period and calculating a probability distribution of branch jump nodes, determining an address expansion depth based on the probability distribution to obtain a prefetch address set including: counting the number of transitions from each address in the access closed loop address subsequence to a successor state node and the total number of transitions and calculating a state transition probability to construct a Markov state transition matrix, predicting multi-step state transitions through the Markov state transition matrix and recording the cumulative transition steps when returning to the start state node to obtain a repeat access period, and calculating an access probability distribution based on the repeat access period; identifying nodes with multiple successor addresses in the address dependency mapping table as branch jump nodes based on the access probability distribution, calculating the transition probability of each successor address pointed to by the branch jump nodes to obtain a probability distribution of the branch jump nodes; recursively expanding based on the probability distribution of the branch jump nodes to obtain successor address branches and taking the accessed address sequence as a branch access pattern feature, calculating the similarity of the successor address branches based on the branch access pattern feature and dividing the successor address branches with a similarity higher than a preset similarity threshold to the same clustering cluster, calculating the cluster-level transition probability of each successor address branch in the clustering cluster and allocating an expansion depth quota to each clustering cluster; based on the expansion depth quota, performing batch expansion, stopping expansion when the recursion level of any successor address branch in the clustering cluster reaches the expansion depth quota, and collecting the addresses traversed in the expansion process to obtain a prefetch address set.

4. The method of claim 1, wherein, reading data from the ROM according to the prefetch address set and loading it into a cache area to obtain time-sensitive cache data, and retrieving target data in the time-sensitive cache data and generating an access execution record including: aligning and expanding the prefetch address set according to the storage block boundary of the ROM to form an aligned address set, and merging the addresses of adjacent storage blocks in the aligned address set into a continuous reading range; initiating a batch reading request to the ROM according to the continuous reading range, loading the read data into the cache area and recording the loading timestamp and the predicted cache invalidation time of each storage block to constitute time-sensitive cache data; receiving a read request and extracting the target address in the read request, retrieving the corresponding storage block in the time-sensitive cache data based on the target address, and determining whether the time difference between the current time of the storage block and the loading timestamp exceeds the predicted cache invalidation time; if not, extracting the target data corresponding to the target address from the storage block and recording a cache hit identifier, and if so, re-reading the target data corresponding to the target address from the ROM and recording a cache miss identifier, and generating an access execution record based on the cache hit identifier, the cache miss identifier, and the target address and access timestamp corresponding to the read request.

5. The method of claim 1, wherein, Based on the access execution record, an address-time access matrix is constructed and singular value decomposition is performed to extract a principal component feature vector, and based on the principal component feature vector, an importance score is calculated for an address in the prefetch address set, including: From the access execution record, cache hit addresses, cache miss addresses, and corresponding access timestamps are extracted, an address-time access matrix is constructed with address numbers as row indexes and access timestamps as column indexes; The address-time access matrix is sparsified to retain elements with non-zero access frequencies, and a truncated singular value decomposition algorithm is used to decompose the sparsified address-time access matrix to obtain a left singular matrix and a singular value diagonal matrix, the singular values are extracted from the singular value diagonal matrix to calculate the cumulative singular value contribution rate and determine the principal component dimension, and column vectors corresponding to the principal component dimension are extracted from the left singular matrix to obtain the principal component feature vector; Each address in the prefetch address set is projected into the feature space formed by the principal component feature vector to obtain a projection vector, and the projection components of the projection vector on different principal component feature vectors are calculated, and the projection components are nonlinearly transformed and weighted to obtain the importance score corresponding to each address.

6. The method of claim 1, wherein, Based on the importance score, an optimal address subset is solved by a knapsack problem solving algorithm, and a topological order of the optimal address subset is determined to obtain a prefetch order, and an efficient prefetch execution scheme is obtained and output, including: The addresses in the prefetch address set are used as selectable items, and the importance scores are used as values, the capacity of the cache area is set as the knapsack capacity, an initial decision matrix is constructed by a dynamic programming algorithm, and the initial decision matrix is filled by comparing the matrix element values at each address to obtain a complete decision matrix, the complete decision matrix is used for reverse backtracking to determine whether the current address is selected, the selected addresses are extracted and added to an address set, and the backtracking is continued to the first address to obtain an optimal address subset; The access dependency relationships between different addresses in the optimal address subset are extracted and an adjacency list is constructed, and the in-degree values of each address in the optimal address subset are determined based on the dependency adjacency list to obtain an address in-degree value set; The addresses with in-degree values of zero in the address in-degree value set are added to a processing queue to obtain an initial processing queue, addresses are sequentially taken out of the initial processing queue and added to a prefetch order sequence, subsequent addresses pointed to by the taken-out addresses are obtained according to the dependency adjacency list, and the in-degree values of the subsequent addresses are reduced by one, it is judged whether the in-degree values of the subsequent addresses are zero, if yes, the subsequent addresses are added to the processing queue, the prefetch order is repeatedly taken out and added, and the optimal address subset and the prefetch order are encapsulated to obtain an efficient prefetch execution scheme and output.

7. A ROM read acceleration system based on low power dynamic optimization for implementing the method of any of the preceding claims 1-6, characterized in that, including: A first unit is configured to obtain a target ROM address sequence to be read, perform time sequence scanning on the target ROM address sequence, determine reference relationships and multiplexing relationships, and obtain an address dependency mapping table. a second unit configured to perform multi-level recursive unfolding on the successor addresses of the current visited addresses based on the successor address set in the address dependence mapping table, identify the access closed-loop address subsequence and perform cycle pattern labeling, predict the repeated access period and calculate the probability distribution of the branch jump node, determine the address unfolding depth based on the probability distribution to obtain a prefetch address set; a third unit configured to read data from the ROM according to the prefetch address set and load the data into a cache area to obtain time-sensitive cache data, search for target data in the time-sensitive cache data and generate an access execution record; a fourth unit configured to construct an address-time access matrix based on the access execution record and perform singular value decomposition to extract a principal component feature vector, calculate the importance score of the addresses in the prefetch address set based on the principal component feature vector, solve the optimal address subset by a knapsack problem solving algorithm based on the importance score and perform topological sorting on the optimal address subset to determine the prefetch order, obtain an efficient prefetch execution scheme and output.

8. An electronic device, comprising: comprise: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method of any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon computer program instructions, wherein, The computer program instructions, when executed by the processor, implement the method of any one of claims 1 to 6.

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