Processor and data cache method thereof, electronic device, and storage medium

Abstract

A processor, its data caching method, electronic device, and storage medium are disclosed. The processor includes a first cache module, which comprises N cache line groups. A first counter corresponding to each cache line group is used to count the number of hit tests for cache lines in the cache line group, and a second counter corresponding to each cache line group is used to count the number of times data is consumed from cache lines in the cache line group. The method includes: performing a hit test on a first cache line in the first cache line group; if the hit test result of the first cache line is a loss, sending a data retrieval request to a lower-level storage module of the first cache module, the data retrieval request including the count copy value corresponding to the first cache line; and retrieving target data from the lower-level storage module in response to the value of the second counter corresponding to the first cache line group being greater than or equal to the count copy value corresponding to the first cache line. The solution provided by this invention can reduce the number of required counters, which is beneficial for reducing chip area.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a processor and its data caching method, electronic device, and storage medium. Background Technology

[0002] Cache memory is used in computer systems to buffer data for computing units such as the Central Processing Unit (CPU) or Graphics Processing Unit (GPU). In traditional blocking caching mechanisms, if a cache miss occurs, the processor must wait for the data to be returned from the next level of storage before processing the next request. This mechanism results in long wait times for the processor, leading to low efficiency. Therefore, non-blocking caching mechanisms were developed to address this issue.

[0003] Compared to blocking caching mechanisms, non-blocking caching mechanisms introduce MissStatus Holding Registers (MSHRs) to store information about unresolved cache misses. When a cache miss occurs, the request can be sent directly to the next lower-level cache without waiting for the data from the previous request to return, thus significantly improving the processor's data processing efficiency. However, the addition of MSHRs to store cache miss information in non-blocking caching mechanisms increases chip area and requires further optimization. Summary of the Invention

[0004] One of the technical objectives of this invention is to provide a data caching method for a processor that can reduce the number of counters in the chip, thereby enabling non-blocking caching while reducing chip area.

[0005] In view of this, embodiments of the present invention provide a caching method for a processor. The processor includes a first cache module, which includes N cache line groups, where N is a positive integer. Each cache line group includes at least two cache lines. A first counter corresponding to each cache line group is used to count the number of hit tests for the cache lines in the cache line group, and a second counter corresponding to each cache line group is used to count the number of data consumptions for the cache lines in the cache line group. The method includes: performing a hit test on a first cache line in the first cache line group, wherein the first cache line group is any one of the N cache line groups, and the first cache line... The cache line is any one of the cache lines in the first cache line group. If the hit test result of the first cache line is a loss, a data retrieval request is sent to the lower-level storage module of the first cache module. The data retrieval request includes the count copy value corresponding to the first cache line. The count copy value corresponding to the first cache line is updated after the hit test is performed on the first cache line. The count copy value is a copy of the value of the first counter. In response to the second counter corresponding to the first cache line group being greater than or equal to the count copy value corresponding to the first cache line, the target data is retrieved from the lower-level storage module and written into the first cache line.

[0006] Optionally, in response to performing a hit test on any cache line in the first cache line group, the value of the first counter corresponding to the first cache line group is updated; after the value of the first counter is updated, the value of the first counter is copied and the copied value is used as the count copy value corresponding to the cache line for which the hit test was performed.

[0007] Optionally, if the hit test result of the first cache line is a loss, then after sending the data retrieval request, the value of the first counter is copied and the copied value is used as the count copy value corresponding to the first cache line.

[0008] Optionally, the first counter is an M-bit counter, wherein the most significant L bits of the M bits are status bits, the value of which is denoted as the version; the least significant (ML) bits of the M bits are count bits, the value of which is denoted as the count value; M is a positive integer greater than 1; L is a positive integer, and L < M; updating the value of the first counter includes: if the count value of the first counter before the update is (2... M-L If -1), then increment the version of the first counter by 1 and set the count value of the first counter to zero.

[0009] Optional, L=2.

[0010] Optionally, before updating the version and count value of the first counter, the method includes: updating the value of the first counter corresponding to the first cache line group to (2) in response to the first cache line group. M-L -1), determine the cache line to be dragged from the first cache line group, the version in the count copy value corresponding to the cache line to be dragged is less than the current version of the first counter; modify the version in the count copy value corresponding to the cache line to be dragged to X-1, where X represents the current version of the first counter.

[0011] Optionally, before updating the version and count value of the first counter, the method further includes: setting the count value in the count copy value corresponding to the cache line to be dragged to zero.

[0012] This invention also provides a graphics processor, comprising: a first cache module, the first cache module comprising N cache line groups, where N is a positive integer, each cache line group comprising at least two cache lines, a first counter corresponding to each cache line group for counting the number of hit tests of the cache lines in the cache line group, and a second counter corresponding to each cache line group for counting the number of data consumptions of the cache lines in the cache line group; and a processing unit for executing the steps of the above-described data caching method.

[0013] This invention also provides an electronic device, which includes: a graphics processor; and a main memory.

[0014] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when run by a processor, performs the steps of the data caching method described above.

[0015] Optionally, the main memory includes the second counter.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0017] In the embodiment of this invention, the first cache module in the processor includes at least one cache line group. A first counter corresponding to each cache line group is used to count the number of hit tests for cache lines within the cache line group, and a second counter corresponding to each cache line group is used to count the number of data consumptions for cache lines within the cache line group. Based on the first and second counters set for each cache line group, the first cache module in the processor implements non-blocking caching for each cache line within the cache line group. In other words, in the embodiment of this invention, cache lines in the first cache module are grouped, and cache lines belonging to the same cache line group share a first counter and a second counter to implement a non-blocking caching mechanism. Compared to the above-mentioned scheme that sets two counters for each cache line, the scheme of this embodiment significantly reduces the number of counters required to implement non-blocking caching, which is beneficial for reducing chip area. Furthermore, due to the reduced number of counters, the amount of data exchanged with lower-level storage modules is also reduced, which is beneficial for saving resources.

[0018] Furthermore, in this embodiment, after performing the hit test, it is first determined whether the hit test result is a data loss. If it is a data loss, the count copy value is updated after sending the data retrieval request; if it is a hit, the count copy value is updated directly. Compared to the scheme that updates the count copy value first and then sends the data retrieval request, the above scheme can make the count copy value in the sent data retrieval request smaller, which is beneficial for retrieving the target data from the lower-level storage module as early as possible, thereby improving the processor's data processing efficiency.

[0019] Furthermore, in the embodiment of the present invention, the most significant L bits of the M bits of the first counter are defined as status bits, and a drag-and-drop mechanism is provided. The drag-and-drop mechanism ensures that the distance between the count copy values ​​corresponding to different cache lines is within the allowable range, avoiding the situation where the count copy values ​​of different cache lines become chaotic due to the overflow of the first counter, thereby achieving the effect of infinite counting of the counter with a finite number of bits.

[0020] Furthermore, in the embodiment of the present invention, compared with the scheme in which (ML) bit values ​​can remain unchanged, modifying (ML) bit values ​​other than L status bits to 0 can minimize the increase in the count copy value, so as to obtain the data returned by the lower storage module as soon as possible and avoid excessive waiting time. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the hardware architecture to which a data caching method is applicable in an embodiment of the present invention;

[0022] Figure 2 This is a flowchart illustrating a data caching method according to an embodiment of the present invention;

[0023] Figure 3 This is a partial flowchart of a data caching method according to an embodiment of the present invention;

[0024] Figure 4 This is a partial flowchart of another data caching method in an embodiment of the present invention;

[0025] Figure 5 This is a partial flowchart of another data caching method in an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the architecture of a processor according to an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of the architecture of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0028] A cache line is the smallest unit of data caching in a processor. In one non-blocking caching mechanism, two counters, denoted as `ref_cnt` and `post_cnt`, can be set for each cache line. Taking cache line 0 as an example, `ref_cnt` for line 0 counts the number of hit tests for line 0. Whenever a hit test for line 0 results in a miss, the current value of `ref_cnt` is sent to the next-level storage module. Furthermore, `post_cnt` for line 0 counts the number of times data from line 0 is consumed. The next-level storage module determines when to return data from line 0 based on the comparison between `ref_cnt` and `post_cnt`. This implementation requires two counters for each cache line, resulting in a relatively large number of counters.

[0029] In view of this, in the solution of this embodiment of the invention, the first cache module in the processor includes at least one cache line group. A first counter corresponding to each cache line group is used to count the number of hit tests for cache lines in the cache line group, and a second counter corresponding to each cache line group is used to count the number of data consumptions for cache lines in the cache line group. Based on the first and second counters set for the cache line groups, the first cache module in the processor implements non-blocking caching for each cache line in the cache line group. That is, in the solution of this embodiment of the invention, cache lines in the first cache module are grouped, and cache lines belonging to the same cache line group share a first counter and a second counter to implement the non-blocking caching mechanism. Compared to the above-mentioned solution that sets two counters for each cache line, the solution of this embodiment of the invention significantly reduces the number of counters required to implement non-blocking caching, which is beneficial for reducing chip area. Furthermore, due to the reduction in the number of counters, the amount of data exchanged with the lower-level storage module is also reduced, which is beneficial for saving resources.

[0030] It should be noted that the processor mentioned in this article may refer to a graphics processing unit (GPU).

[0031] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] Reference Figure 1 , Figure 1 This is a schematic diagram of the hardware architecture applicable to a data caching method in an embodiment of the present invention. For example... Figure 1 As shown, the data caching method provided in this embodiment of the invention can be used to implement data caching of a first cache module. The first cache module is a high-speed cache module built into the processor. Specifically, the first cache module can be any level cache in the processor's multi-level cache architecture. Taking a level two cache architecture as an example, the first cache module can be a level zero cache (L0Cache), or it can be a level one cache (L1 Cache), etc., but it is not limited to these.

[0033] During processor runtime, if the required data is not found in the first cache module, the processor continues searching for the required data in the next lower-level storage module. If the first cache module is the last level cache in a multi-level cache architecture, then the next lower-level storage module refers to main memory. Main memory can also be called RAM. The last level cache refers to the last level cache in a multi-level cache architecture. For example, in a two-level cache architecture, the last level cache is L1 Cache, and in a three-level cache architecture, it is L2 Cache. If the first cache module is any cache other than the last level cache in a multi-level cache architecture, then the next lower-level storage module refers to the next level cache after the first cache module. For example, in a two-level cache architecture, the first cache module is L0 Cache, and the next lower-level storage module is L1 Cache. For example, in a three-level cache architecture, the first cache module is L0Cache, and the lower-level storage module of the first cache module is L1 Cache; or, the first cache module is L1 Cache, and the lower-level storage module of the first cache module is L2 Cache.

[0034] In this embodiment of the invention, cache lines in the first cache module are managed in groups. Specifically, the first cache module may include N cache line groups, each cache line group including at least two cache lines, where N is a positive integer greater than or equal to 1. The number of cache lines in different cache line groups may be the same or different.

[0035] like Figure 1 As shown, the first cache module includes two cache line groups, where each cache line group contains four cache lines. It should be noted that... Figure 1 This invention provides only one illustrative hardware architecture diagram of a data caching method applicable to an embodiment of the present invention. The embodiments of the present invention do not limit the number of cache line groups included in the first cache module, nor the number of cache lines contained in each cache line group. It should also be noted that the embodiments of the present invention do not limit the method for grouping cache lines. For example, cache lines in the first cache module can be grouped according to the number of cache lines contained in a pre-defined cache line group and based on the index of the cache lines.

[0036] Furthermore, the first cache module also includes a first counter, which corresponds one-to-one with a cache line group. For example... Figure 1 As shown, the first counter 0 corresponds to cache line group 0, and the first counter 1 corresponds to cache line group 1.

[0037] In the scheme of this embodiment of the invention, the first counter corresponding to each cache line group is used to count the number of hit tests performed on cache lines in the cache line group. Figure 1 Taking the first counter 0 in the cache as an example, as long as a hit test is performed on any cache line in cache line group 0, the value of the first counter 0 will be incremented by 1.

[0038] Furthermore, if the hit test result is a hit, it means that the required data was found in the cache line. If the hit test result is a miss, it means that the required data was not found in the cache line, and the first cache module sends a data retrieval request to the lower-level storage module.

[0039] Specifically, the lower-level storage module can be configured with a request queue, which can be a First-Input First-Out (FIFO) queue. Data retrieval requests from the first cache module can be written into the FIFO queue. The lower-level storage module can process the data retrieval requests in the request queue one by one to send the required data to the first cache module.

[0040] For example, the request queue can correspond one-to-one with the cache line groups in the first cache module, and the request queue can be used to store data retrieval requests for the corresponding cache line groups. Figure 1 As shown, queue 0 corresponds to cache line group 0, and queue 1 corresponds to cache line group 1.

[0041] For example, data retrieval requests from different cache line groups can also be stored in the same request queue, and this embodiment of the invention does not limit this.

[0042] Furthermore, the lower-level storage module of the first cache module may include a second counter, and the second counter corresponds one-to-one with the cache line group in the first cache module. For example... Figure 1 As shown, second counter 0 corresponds to cache line group 0, and second counter 1 corresponds to cache line group 1. In the scheme of this embodiment, the second counter corresponding to each cache line group is used to count the number of times data is consumed in the cache lines of the cache line group. Figure 1 Taking the second counter 0 in the cache line group 0 as an example, the value of the second counter 0 is incremented by 1 whenever any data in any cache line is consumed. Consuming data in a cache line can refer to the processor using the data stored in the cache line. After the data in a cache line is consumed, new data can be written to the cache line.

[0043] Specifically, whenever data in a cache line group is consumed, the first cache module transmits a counting signal to the lower-level storage module, and the second counter corresponding to that cache line in the lower-level storage module can count based on the received counting signal.

[0044] In the embodiment of the present invention, each data acquisition request may include a copy count value, which is a copy of the value of a first counter. Whenever the value of a second counter is greater than or equal to the copy count value in the data acquisition request, the lower-level storage module may return the data requested by the data acquisition request to the first cache module.

[0045] The following is combined Figures 2 to 5 The data caching method in the embodiments of the present invention will be described in more detail below.

[0046] Reference Figure 2 , Figure 2 This is a flowchart illustrating a data caching method provided in an embodiment of the present invention. It should be noted that... Figure 2 Taking the first cache line group in the first cache module as an example, the first cache line group can be any cache line group in the first cache module. That is, Figure 2 The method shown can be applied to each cache line group in the first cache module. Figure 2 The methods shown may include S21 to S23.

[0047] S21: Perform a hit test on the first cache line in the first cache line group;

[0048] S22: If the hit test result of the first cache line is a loss, a data retrieval request is sent to the lower-level storage module of the first cache module. The data retrieval request includes the copy count value corresponding to the first cache line.

[0049] S23, in response to the value of the second counter corresponding to the first cache line group being greater than or equal to the count copy value corresponding to the first cache line, the target data is obtained from the lower-level storage module and written to the first cache line.

[0050] In S21, a hit test is performed on the first cache line in the first cache line group. The first cache line can be any cache line in the first cache line group. Each time a hit test is performed on any cache line in the first cache line group, the value of the first counter is incremented by one.

[0051] Furthermore, in the scheme of this embodiment of the invention, after performing a hit test on the first cache line, the count copy value corresponding to the first cache line is also updated. The updated count copy value is a copy of the current value of the first counter. Specifically, after each hit test is performed on a cache line in the first cache line group, the count copy value corresponding to the cache line corresponding to that hit test is updated.

[0052] In practice, a corresponding register can be set up for each cache line. This register can be used to store the copy counter value corresponding to the cache line. Whenever a hit test is performed on a cache line and the value of the first counter is updated, the updated value of the first counter is recorded in the register corresponding to that cache line, thereby updating the copy counter value corresponding to that cache line.

[0053] Combination Figure 1 ,by Figure 1 Taking cache line group 0 as an example, assuming the nth hit test is for line 0, after the first counter is updated to n, the copy count value corresponding to line 0 is also updated to n, while the copy count values ​​corresponding to other cache lines remain unchanged, where n is a positive integer. Assuming the (n+1)th hit test is for line 3, after the first counter is updated to n+1, the copy count value corresponding to line 3 is also updated to n+1, while the copy count values ​​corresponding to other cache lines remain unchanged.

[0054] It should be noted that, in the scheme of this embodiment of the invention, regardless of whether the result of each hit test is a hit or a miss, the copy count value corresponding to the cache line corresponding to the hit test is updated.

[0055] If the hit test result executed in S21 is a loss, it means that there is no data required by the processor in the first cache line, and data needs to be requested from the lower-level storage module of the first cache module.

[0056] Specifically, in S22, a data retrieval request is sent to the first cache module. This data retrieval request includes a copy count value corresponding to the first cache line. Furthermore, the data retrieval request may also include an index of the first cache line, which indicates that the data retrieval request is used to request data from the first cache line.

[0057] In the scheme of this embodiment of the invention, whenever the hit test result of a cache line in the first cache line group is a loss, a data retrieval request can be sent, without relying on the fact that the data requested by the previous data retrieval request has already been returned. For example, assuming that the nth hit test result is a loss, and the (n+1)th hit test result is also a loss, then after obtaining the (n+1)th hit test result, regardless of whether the data corresponding to the nth hit test has been returned, a data retrieval request corresponding to the (n+1)th hit test result can be sent.

[0058] For the data retrieval request sent in S22, in S23, when the value of the second counter corresponding to the first cache line group is greater than or equal to the count copy value corresponding to the first cache line, the lower-level storage module sends the target data to the first cache module and writes the target data into the first cache line.

[0059] Combination Figure 1 For the most recent data retrieval request about to be dequeued in the request queue, if the value of the second counter corresponding to the cache line group from which the data retrieval request originated is greater than or equal to the count copy value in the data retrieval request, then the lower-level storage module returns the data requested by the data retrieval request. Figure 1 Taking queue 0 as an example, the most recent data retrieval request that is about to be dequeued is data retrieval request 0 of group 0. When the value of the second counter 0 is greater than or equal to the count copy value in data retrieval request 0, the data requested by data retrieval request 0 is returned, and data retrieval request 0 is deleted from queue 0.

[0060] From the above, Figure 2 The scheme shown provides a method for implementing non-blocking caching based on a first counter and a second counter set by cache line groups.

[0061] Furthermore, in one embodiment of the present invention, after each hit test, the copy count value corresponding to the cache line can be updated first, and then a data retrieval request can be sent. For details regarding this embodiment, please refer to the following description. Figure 3 Related descriptions.

[0062] In another embodiment of the invention, after each hit test, a data retrieval request can be sent first, followed by updating the copy count value corresponding to the cache line. For details regarding this embodiment, please refer to the following section... Figure 4 Related descriptions.

[0063] Reference Figure 3 , Figure 3 This is a partial flowchart of a data caching method according to an embodiment of the present invention. Figure 3 The proposed solution may include the following steps:

[0064] S31, Perform a hit test and update the value of the first counter;

[0065] S32, Update the copy count value corresponding to the cache line of the hit test;

[0066] After updating the value of the first counter in S31, the count copy value of the cache line for this hit test can be updated accordingly. Assuming that the nth hit test is performed in S31, and the nth hit test is a hit test for line 0, then after the first counter is updated to n, the count copy value corresponding to line 0 in S32 is also updated to n.

[0067] Continue executing S33 after S32.

[0068] S33, determine whether the hit test result is a loss;

[0069] Specifically, it checks whether the result of the hit test performed in S31 is a loss. If the result of the check in S33 is yes, then proceed to S34. If the result of the check in S33 is no, then return to S31 and continue to perform the next hit test.

[0070] S34, Send a data acquisition request, which includes a count copy value.

[0071] Specifically, the data retrieval request may include the count copy value corresponding to the cache line corresponding to the hit test in S32. Continuing the example above, assuming that the nth hit test is performed in S31 and the result of the nth hit test is a loss, the data retrieval request sent in S34 includes the count copy value n.

[0072] After S34, return to S31 to continue the next hit test.

[0073] Reference Figure 4 , Figure 4 This is a partial flowchart of another data caching method in an embodiment of the present invention. Figure 4 The method shown includes the following steps:

[0074] S41, Perform a hit test and update the value of the first counter;

[0075] S42 determines whether the hit test result is a loss.

[0076] Specifically, determine whether the hit test performed in S41 results in a loss. If the result of S42 is yes, then proceed to S43. If the result of S42 is no, then proceed to S44.

[0077] S43, Send a data acquisition request, which includes a count copy value.

[0078] Specifically, the data retrieval request may include the copy count value corresponding to the cache line of the hit test executed in S41. Since the copy count value has not been updated when S43 is executed, the copy count value in S43 is the copy count value before the update.

[0079] Continuing the example above, suppose S41 performs the nth hit test, which is a hit test on line 0, and the result of the nth hit test is a loss. Then, the count copy value included in the data retrieval request in S43 is the count copy value corresponding to line 0 before the update. Assuming the count copy value corresponding to line 0 before the update is m, then the count copy value in the data retrieval request in S43 is m, where m < n.

[0080] After executing S43, continue executing S44.

[0081] S44, Update the copy count value corresponding to the first cache line.

[0082] In S44, the copy count value of the cached line in this hit test is updated. Continuing the example above, suppose that the nth hit test was performed in S41, and the nth hit test is a hit test for line 0. Suppose that the copy count value of line 0 before the update was m, in S44, the copy count value of line 0 is updated from m to n.

[0083] After executing S44, return to S41 to continue executing the next hit test.

[0084] Based on the above, taking the nth hit test as an example, if we use Figure 3 In the scheme shown, the count copy value in the data acquisition request is n. If the following is adopted... Figure 4 In the illustrated scheme, the count copy value in the data acquisition request is m, where m < n. Since the timing of data return from the lower-level storage module must satisfy the condition that the value of the second counter is greater than or equal to the count copy value in the data acquisition request, therefore, compared to... Figure 3 The proposed solution Figure 4 The scheme shown has a smaller copy count in the data acquisition request, which is beneficial for obtaining the target data from the lower-level storage module as early as possible, thereby improving the processor's data processing efficiency.

[0085] Referring to Table 1, Table 1 provides... Figure 4 A specific example of the scheme shown.

[0086] Table 1

[0087]

[0088] The schemes shown in Table 1 are as follows: Figure 1 Taking cache line group 0 as an example. As shown in Table 1, the first hit test is performed on line 0. Since the result of the first hit test is a hit, no data retrieval request needs to be sent. Furthermore, the second hit test is performed on line 1. Since Table 1 uses... Figure 4 The proposed solution involves first sending a data retrieval request. Since the copy counter value corresponding to line1 has not yet been updated, the copy counter value corresponding to line1 in the data cache request is 0. After sending the data cache request, the copy counter value corresponding to line1 is updated to 2.

[0089] Furthermore, as shown in Table 1, after the value of the second counter is updated, the data requested by the data retrieval request whose count copy value is less than or equal to the value of the second counter can be returned.

[0090] Furthermore, considering that the number of bits in the counter is finite, let's assume the first counter is an M-bit counter, where M is a positive integer greater than 1, and the maximum value of the first counter is... If the value of the first counter continues to increase, an overflow problem will occur. If an overflow occurs, the count copy values ​​corresponding to different cache lines will become disordered, leading to errors in the data caching process. For example, with M=10, as the hit test continues to execute, the execution of the second... 10 During the hit test, the value of the first counter should actually be updated to 2. 10 Since the first counter is a 10-bit counter, its binary value is 0. Assume the second... 10 If the hit test is performed on line0, the copy counter value corresponding to line0 will be updated to 0. Assuming the copy counter value for line1 was 2 in the previous transmission... 5 At this point, the count copy values ​​corresponding to line0 and line1 are disordered.

[0091] In view of this, in the embodiment of the present invention, the most significant L bits out of the M bits are used as state bits, and the decimal numbers corresponding to the values ​​of the L bits are the versions. Referring to Table 2, Table 2 provides an example of the values ​​of the state bits and their corresponding versions when L=2.

[0092] Table 2

[0093]

[0094] Therefore, the M bits of the first counter consist of two parts: L high-order status bits and (ML) low-order ordinary bits. The "ordinary bits" can also be called "count bits." Here, L is a positive integer, and L < M. In this embodiment, the values ​​of the L status bits are denoted as the version, and the values ​​of the (ML) count bits are denoted as the count value.

[0095] As mentioned above, whenever a hit test is performed on any cache line in the first cache line group, the value of the first counter is updated. Specifically, updating the value of the first counter includes: if the value of the first counter before the update is (2... M -L If the value of the first counter is less than (2 -1), then the version number of the first counter is incremented by 1, and the count value of the first counter is set to zero. That is, the value of the status bit is incremented by 1, and the values ​​of all count bits of the first counter are set to zero. If the count value of the first counter before the update is less than (2 -1), then the version number of the first counter is incremented by 1, and the count value of the first counter is set to zero. M -L If -1), then the version of the first counter remains unchanged, and the count value is incremented by 1.

[0096] In one example, L=2, M=5, when the value of the first counter is 10111 (i.e., the version of the first counter is 10) and the count value of the first counter is 111, updating the value of the first counter means updating its value to 11000. That is, incrementing the version by 1 and setting the count value to zero.

[0097] Based on this bit definition, embodiments of the present invention also provide a drag-and-drop mechanism, which ensures that the distance between the count copy values ​​corresponding to different cache lines is within an allowed range, thereby achieving the effect of infinite counting of the counter with a finite number of bits.

[0098] Reference Figure 5 , Figure 5 This is a flowchart illustrating another data caching method in an embodiment of the present invention. Figure 5 The methods shown include S51 and S52.

[0099] S51: In response to the fact that the value of the first counter corresponding to the first cache line group meets the version change condition, the cache line to be dragged is determined from the first cache line group.

[0100] S52, Increase the version of the copy counter value corresponding to the cache line to be dragged.

[0101] Specifically, the version change condition refers to the value of the first counter being the maximum value of the current version. The maximum value for each version means that (ML) bits are all 1, that is, all M bits except the L status bits are 1. In other words, the version change condition means that the count value of the first counter is (2... M-L -1).

[0102] In S51, when the value of the first counter corresponding to the first cache line group is the maximum value of the current version, it indicates that the value of the first counter is about to enter the next version. At this time, the cache line to be dragged is determined from the first cache line group. The version of the count copy value corresponding to the cache line to be dragged is less than the version of the current first counter. Therefore, in S52, the version of the count copy value corresponding to the cache line to be dragged is increased. By increasing the version of the count copy value, it is ensured that the difference between the version of the count copy value and the version of the first counter value is less than 2. L .

[0103] Specifically, the difference between the version with the increased copy count corresponding to the cache line to be dragged and the next version of the first counter is K. K can be a pre-set natural number, and K < 2. LIn one specific implementation, the version of the count copy value is dragged to ensure that the difference between the version of the count copy value and the version of the first counter value is less than or equal to 1. That is, in S51, cache lines with count copy values ​​lower than the current version can be identified as cache lines to be dragged, and in S52, the version of the cache line to be dragged can be modified to the current version, or the version of the cache line to be dragged can be modified to the next version of the current version.

[0104] In practice, modifying the version means modifying the value of the status bits. For example, assuming the current version of the first counter is X, where X is the decimal number corresponding to L status bits, then the version in the count copy value corresponding to the cache line to be dragged can be modified to X-1.

[0105] Furthermore, in the M bits of the count copy value of the cache line to be dragged, besides modifying the values ​​of L status bits, the remaining (ML) bits can remain unchanged. Alternatively, the remaining (ML) bits can be modified to 0. Compared to the option of keeping the remaining (ML) bits unchanged, modifying the remaining (ML) bits to 0 minimizes the increase in the count copy value, allowing for faster retrieval of data from the lower-level storage module and avoiding excessively long waiting times.

[0106] In one example, L=2, M=5, the cache line to be dragged is a cache line whose version of the count copy value is less than the current version of the first counter. Increasing the version means modifying the version of the count copy value to the current version. For example, when the value of the first counter is 10111, the count copy value corresponding to line0 is 00001, and the count copy value corresponding to line1 is 10001. Therefore, line0 can be determined as the cache line to be dragged, and the count copy value corresponding to line0 can be modified to 10000.

[0107] Therefore, in the embodiment of the present invention, the most significant L bits of the M bits of the first counter are defined as status bits, and a drag-and-drop mechanism is provided. The drag-and-drop mechanism ensures that the distance between the count copy values ​​corresponding to different cache lines is within the allowable range, avoiding the situation where the count copy values ​​of different cache lines become chaotic due to the overflow of the first counter, thereby achieving the effect of infinite counting of the counter with a finite number of bits.

[0108] Reference Figure 6 , Figure 6 This is a schematic diagram of the architecture of a processor according to an embodiment of the present invention. Figure 6 As shown, the processor 60 may include a first cache module 61 and an arithmetic unit 62, wherein the arithmetic unit 62 may be used to execute the data caching method described above.

[0109] The processor 60 may have a multi-level cache architecture, wherein the first cache module 61 may be the last-level cache in the multi-level cache. Alternatively, the first cache module 61 may be any cache in the multi-level cache other than the last-level cache. If the first cache module 61 is any cache in the multi-level cache other than the last-level cache, the processor 60 may also include a lower-level storage module of the first cache module, and the processor 60 may also include a first counter and a second counter.

[0110] In a specific implementation, the processor 60 may be a central processing unit (CPU) or a graphics processing unit (GPU).

[0111] about Figure 6 Further details about the processor 60 shown can be found in the description above, and will not be repeated here.

[0112] Reference Figure 7 , Figure 7 This is a schematic diagram of the architecture of an electronic device according to an embodiment of the present invention. Figure 7 As shown, the electronic device 70 may include a graphics processor 60 and a main memory 71. The graphics processor 60 may include a first cache module 61 and a processing unit 62, the processing unit 62 being used to execute the data caching method described above.

[0113] Specifically, if the first cache module 61 is the last-level cache in the graphics processor 60, the main memory 71 may also include a second counter corresponding to each cache line group in the first cache module 61.

[0114] about Figure 7 Further details about the electronic device 70 shown can be found in the above description and will not be repeated here.

[0115] It should be noted that the various embodiments, possible implementation methods, possible methods of implementation, various examples, and solutions in various situations provided in this article can be used individually or in combination to achieve different technical effects.

[0116] It is understood that, in specific implementations, the method can be implemented using a software program that runs in a processor integrated within the chip or chip module; or, the method can be implemented using hardware or a combination of hardware and software.

[0117] It should be understood that in the embodiments of this application, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0118] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0119] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatus, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0121] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically included separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or in a combination of hardware and software functional units. For example, for various devices or products applied to or integrated into a chip, each module / unit can be implemented using hardware such as circuits, or at least some modules / units can be implemented using software programs running on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware such as circuits; for various devices or products applied to or integrated into a chip module, each module / unit can be implemented using hardware such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0122] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0123] In this application's embodiments, "multiple" refers to two or more. The descriptions of "first," "second," etc., appearing in this application's embodiments are merely illustrative and for distinguishing the described objects; they do not indicate any order and do not imply a specific limitation on the number of devices in this application's embodiments, nor do they constitute any limitation on the embodiments of this application. Although the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of data caching for a processor, the method comprising: The processor comprises a first cache module, the first cache module comprises N cache line groups, N is a positive integer, each cache line group comprises at least two cache lines, a first counter corresponding to each cache line group is used for counting the number of hit tests of the cache lines in the cache line group, and a second counter corresponding to each cache line group is used for counting the number of data consumptions of the cache lines in the cache line group, and the method comprises: performing a hit test on a first cache line in a first cache line group, wherein the first cache line group is any one of the N cache line groups, and the hit test is performed on any one of the cache lines in the first cache line group; if the hit test result of the first cache line is a miss, sending a data acquisition request to a lower-level storage module of the first cache module, the data acquisition request comprising a count copy value corresponding to the first cache line, the count copy value corresponding to the first cache line being updated after the hit test on the first cache line, and the count copy value being a copy of the value of the first counter; in response to the value of the second counter corresponding to the first cache line group being greater than or equal to the count copy value corresponding to the first cache line, acquiring target data from the lower-level storage module and writing the target data into the first cache line.

2. The data caching method of claim 1, wherein, in response to performing a hit test on any one of the cache lines in the first cache line group, updating the value of the first counter corresponding to the first cache line group; after updating the value of the first counter, copying the value of the first counter and taking the copied value as the count copy value corresponding to the cache line on which the hit test is performed.

3. The data caching method of claim 2, wherein, if the hit test result of the first cache line is a miss, after sending the data acquisition request, copying the value of the first counter and taking the copied value as the count copy value corresponding to the first cache line.

4. The data caching method of claim 2, wherein, the first counter is an M-bit counter, wherein L bits of the highest bits in the M bits are state bits, the value of the state bits is denoted as a version, (M-L) bits of the lowest bits in the M bits are count bits, the value of the count bits is denoted as a count value, M is a positive integer greater than 1, L is a positive integer, and L updating the value of the first counter comprises: If the count value of said first counter before the update is (2 M-L -1), the version of said first counter is incremented by 1 and the count value of said first counter is set to zero.

5. The data caching method of claim 4, wherein, L=2。 6. The data caching method of claim 4, wherein, before updating the version and the count value of the first counter, the method comprises: determining a cache line to be dragged from the first cache line group in response to a count value of the first counter being (2 M-L -1), the cache line to be dragged corresponding to a version in a count copy value smaller than a current version of the first counter; modifying the version in the count copy value corresponding to the cache line to be dragged to X-1, wherein X represents the current version of the first counter.

7. The data caching method of claim 6, wherein, before updating the version and the count value of the first counter, the method further comprises: setting the count value in the count copy value corresponding to the cache line to be dragged to zero.

8. A graphics processor, comprising: comprises: a first cache module, the first cache module comprises N cache line groups, N is a positive integer, each cache line group comprises at least two cache lines, a first counter corresponding to each cache line group is used for counting the number of hit tests of the cache lines in the cache line group, and a second counter corresponding to each cache line group is used for counting the number of data consumptions of the cache lines in the cache line group; An arithmetic unit for performing the steps of the data cache method of the processor of any of claims 1 to 7.

9. An electronic device, comprising: The electronic device comprises: The graphics processor of claim 8; A main memory.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when run by a processor, performs the steps of the data cache method of any of claims 1 to 7.

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