A path-tracing-based scene rendering method, device, equipment and medium

Abstract

The application discloses a path tracking-based scene rendering method and device, equipment and medium, and relates to the technical field of image rendering. The method comprises the following steps: obtaining rendering information transmitted by a target host, and constructing a target acceleration scene structure based on the rendering information and a target thread of a target processor; allocating corresponding pixel rendering tasks to a plurality of threads based on a preset task allocation rule and a local preset storage structure, and determining a task allocation amount of each round; executing respective corresponding pixel rendering tasks by the plurality of threads by using a preset path tracking technology, the target acceleration scene structure and the rendering information, then rendering a number of pixel points corresponding to the task allocation amount of the next round in the current unrendered pixels according to the preset task allocation rule and a preset load balancing strategy, until the plurality of to-be-rendered pixels are all rendered; and transmitting the plurality of rendered pixels to the target host, so that the target host obtains a rendered scene for a target scene model based on the plurality of rendered pixels.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image rendering, in particular to a scene rendering method and device based on path tracing, equipment and medium. BACKGROUND

[0002] Path tracing is a very important technology in rendering, which is used to render high-fidelity images and plays an important role in animation production, games and other fields. Usually, the rendering is performed using the Monte Carlo method through the SIMD (Single Instruction Multiple Data) and SIMT (Single Instruction Multiple Threads) architectures, but due to the inherent characteristics of frequent branching and irregular memory access, the control divergence problem of the tree-shaped data structure representing the scene in the algorithm is prone to occur, the utilization efficiency of the architecture hardware is low, which cannot fully exert its advantages, and there is a phenomenon of unbalanced load, which greatly affects the performance.

[0003] In summary, how to solve the memory divergence and load imbalance problems existing in the path tracing rendering process is a technical problem to be solved at present. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a scene rendering method and device based on path tracing, equipment and medium, which can solve the memory divergence and load imbalance problems existing in the path tracing rendering process. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a scene rendering method based on path tracing, applied to a target processor of MIMD architecture, comprising:

[0006] Obtaining rendering information related to a target scene model to be rendered transmitted by a target host, and constructing a target acceleration scene structure based on the rendering information and a target thread of the target processor; the target thread is a thread of the target processor for initializing the target acceleration scene structure; the target acceleration scene structure is a bounding box tree composed of a plurality of bounding boxes;

[0007] Allocating corresponding pixel rendering tasks to the plurality of threads based on a preset task allocation rule and a local preset storage structure, and determining a corresponding task allocation amount per round; the pixel rendering task is a task for rendering any one pixel point of a plurality of pixels to be rendered in the target scene model, and corresponds to the thread one by one;

[0008] The rendering information and the target processor are used to construct a target acceleration scene structure, and the target acceleration scene structure is used to execute the pixel rendering task corresponding to each thread.

[0009] The target host is transmitted with the rendered pixels, so that the target host obtains a rendered scene for the target scene model based on the rendered pixels.

[0010] Optionally, the target acceleration scene structure is constructed based on the rendering information and the target thread of the target processor, including:

[0011] The triangle patch data structure array in the rendering information is determined; the triangle patch data structure array is loaded by a plurality of triangle patch information corresponding to the target scene model, and the plurality of triangle patch information is obtained by analyzing the target scene model by the target host;

[0012] The number of bounding boxes is determined based on the number of vector units of the local, and a first bounding box data structure of independent bounding boxes is defined;

[0013] A second bounding box data structure of a target multi-way bounding box is defined; the target multi-way bounding box is a combined bounding box composed of a preset number of independent bounding boxes as child nodes; the preset number is consistent with the number of bounding boxes;

[0014] The target multi-way bounding box and the target data structure are defined as bounding box nodes by the target thread of the target processor, and the bounding box nodes, the first bounding box data structure and the second bounding box data structure are constructed to obtain the constructed target acceleration scene structure; the target data structure is a data structure of a pointer pointing to the preset number of child nodes.

[0015] Optionally, the target multi-way bounding box and the target data structure are defined as bounding box nodes, and the bounding box nodes, the first bounding box data structure and the second bounding box data structure are constructed to obtain the constructed target acceleration scene structure, including:

[0016] The triangle patch data structure array is divided into the preset number of target subsets;

[0017] constructing a corresponding bounding box node for each of the target subsets respectively, and storing the bounding box nodes into a first target stack; the bounding box node is a node constructed by the target k-d tree and a target data structure; the target data structure is a data structure of pointers pointing to the preset number of the child nodes;

[0018] performing the operations of the dividing into the preset number of target subsets and the constructing a corresponding bounding box node for each of the target subsets respectively and storing the bounding box nodes into a first target stack on the bounding box nodes in the first target stack in a recursive manner, until it is detected that the number of triangular facets in a divided target subset is not higher than the preset number, and the bounding box node currently constructed is determined as a leaf node;

[0019] constructing the independent bounding box based on the spatial coordinates of the triangular facets in the leaf node and the first bounding box data structure, and performing a merging operation on the independent bounding box according to the second bounding box data structure, so as to fill the leaf node with the target k-d tree constructed, to obtain a target acceleration scene structure containing the bounding box node.

[0020] Optionally, the assigning of the corresponding pixel rendering tasks to the plurality of threads based on the preset task allocation rule and the local preset storage structure comprises:

[0021] determining a resolution of the target scene model in the rendering information and a local preset storage structure;

[0022] dividing the plurality of threads according to the preset storage structure and the resolution, and controlling threads sharing a same cache level in the plurality of threads to be responsible for pixel point rendering tasks of spatially adjacent pixel points in the target scene model;

[0023] obtaining thread numbers corresponding to the plurality of threads respectively and level numbers of the cache levels to which the plurality of threads are divided based on a preset function, and determining pixel point spatial positions corresponding to the pixel point rendering tasks respectively responsible by the plurality of threads based on the thread numbers and the level numbers, so that the plurality of threads execute the pixel rendering tasks respectively responsible by the plurality of threads according to the pixel point spatial positions;

[0024] determining a corresponding task allocation amount per round according to the cache level division of the plurality of threads.

[0025] Optionally, the assigning of the corresponding pixel rendering tasks to the plurality of threads based on the preset task allocation rule and the local preset storage structure comprises:

[0026] determining a resolution of the target scene model in the rendering information, and judging whether a height or a width of the resolution is a multiple of the task allocation amount of each round;

[0027] If it is judged that the height or the width of the resolution is not a multiple of the task allocation amount of each round, determining irregular parts and regular parts in the target scene model, and storing the irregular parts in a preset atomic task pool; the irregular parts are parts in the target scene model that cannot be divided by the task allocation amount of each round; the regular parts are parts in the target scene model that can be divided by the task allocation amount of each round;

[0028] For the regular parts, assigning corresponding pixel rendering tasks to the threads based on a preset task allocation rule and a local preset storage structure;

[0029] Correspondingly, the rendering of the next round of the task allocation amount corresponding number of pixel points in the current unrendered pixels according to the preset task allocation rule and the preset load balancing strategy until the plurality of to-be-rendered pixels are rendered, comprises:

[0030] After the threads complete the corresponding pixel rendering tasks, locating the spatial positions of the pixel points of the next round of rendering in the regular parts according to the preset task allocation rule, rendering the located pixel points, and jumping to the step of locating the spatial positions of the pixel points of the next round of rendering in the regular parts according to the preset task allocation rule until the spatial positions of the located pixel points exceed the height or the width of the resolution;

[0031] Determining the number of pixel points of the irregular parts in the atomic task pool, and a preset variable value corresponding to the atomic task pool for recording the current rendering task number;

[0032] After the threads locate the spatial positions of the pixel points, comparing the current preset variable value with the number of pixel points, if the current preset variable value is less than the number of pixel points, adding one to the preset variable value, and taking out the target to-be-rendered pixel points in the irregular parts corresponding to the preset variable value;

[0033] Rendering the target to-be-rendered pixel points by the threads, and jumping to the step of comparing the current preset variable value with the number of pixel points until the current preset variable value is equal to the number of pixel points.

[0034] Optionally, the plurality of threads execute the respective corresponding pixel rendering tasks by using a preset path tracking technology, the target acceleration scene structure and the rendering information, comprising:

[0035] determining a camera point in the rendering information, and determining a target pixel point of the pixel rendering task corresponding to each thread;

[0036] determining a direction vector as a direction of a line connecting the camera point and the target pixel point, and generating an initial ray based on the direction vector and the camera point;

[0037] traversing the initial ray and the target acceleration scene structure to find a target hit point in the target acceleration scene structure intersecting with the initial ray, to obtain a corresponding search result; the target hit point is a hit point with the smallest time point among a plurality of hit points in the target acceleration scene structure intersecting with the initial ray;

[0038] if the search result indicates that there is a target hit point in the target acceleration scene structure intersecting with the initial ray, taking out triangle patch information in the target hit point, and generating an outgoing direction according to material information in the triangle patch information;

[0039] performing ray tracing according to the outgoing direction, and determining whether a light source is hit;

[0040] if the light source is not hit, recording an absorption coefficient of a current hit material, and constructing a secondary ray with the current hit point as a starting point and the outgoing direction as a direction, determining the secondary ray as the initial ray, and jumping to the step of traversing the initial ray and the target acceleration scene structure, until a preset bouncing number is reached, or the light source is hit;

[0041] when it is determined that the light source is hit, calculating a rendered target pixel according to the recorded absorption coefficient and a current pixel value, to complete the pixel rendering task.

[0042] Optionally, the step of traversing the initial ray and the target acceleration scene structure to find a target hit point in the target acceleration scene structure intersecting with the initial ray, to obtain a corresponding search result, comprises:

[0043] traversing the initial ray and an initial node of the target acceleration scene structure, and saving a target child node of a target node intersecting with the initial ray to a second target stack in a traversing process; the initial node is a child node directly connected with a root node in the target acceleration scene structure;

[0044] taking out the target sub-node in the second target stack as the initial node for next recursion, and jumping to the step of traversing the initial ray and the initial node of the target acceleration scene structure until the second target stack is empty to find a target hit point intersecting with the initial ray in the target acceleration scene structure, and obtaining a corresponding search result;

[0045] Correspondingly, in the process of taking the target sub-node as the initial node for next recursion, and jumping to the step of traversing the initial ray and the initial node of the target acceleration scene structure until the second target stack is empty, the process comprises:

[0046] When traversing to a leaf node in the target acceleration scene structure, judging intersection between a triangular patch in the leaf node and the initial ray, if it is determined that the initial ray intersects with the leaf node, determining the leaf node currently intersecting with the initial ray as a hit point, and comparing a time point of the hit point with a time point of a currently recorded target hit point to obtain a corresponding comparison result;

[0047] If the comparison result represents that the time point of the hit point is less than the time point of the currently recorded target hit point, the hit point is determined as the target hit point.

[0048] In a second aspect, the application provides a scene rendering device based on path tracing, applied to a target processor of MIMD architecture, comprising:

[0049] A structure construction module is configured to acquire rendering information related to a target scene model to be rendered transmitted by a target host, and construct a target acceleration scene structure based on the rendering information and a target thread of the target processor; the target thread is a thread of a plurality of threads of the target processor, which is used to initialize the target acceleration scene structure; the target acceleration scene structure is a bounding box tree composed of a plurality of bounding boxes;

[0050] A unit determination module is configured to allocate corresponding pixel rendering tasks to the plurality of threads based on a preset task allocation rule and a local preset storage structure, and determine a corresponding task allocation amount of each round; the pixel rendering task is a task of rendering any one pixel point of a plurality of pixels to be rendered in the target scene model, and corresponds to the thread one by one;

[0051] a pixel rendering module, configured to perform, by the threads, respective pixel rendering tasks by using a preset path tracing technique, the target acceleration scene structure and the rendering information, so as to complete rendering tasks of a quantity of pixel points corresponding to the task allocation quantity of the current round, and then perform rendering on pixel points corresponding to a quantity of pixel points of the next round of the task allocation quantity in the current unrendered pixels according to the preset task allocation rule and a preset load balancing strategy, until all the to-be-rendered pixels are rendered, so as to obtain a plurality of rendered pixels;

[0052] a pixel transmission module, configured to transmit the plurality of rendered pixels to the target host, so that the target host obtains a rendered scene for the target scene model based on the plurality of rendered pixels.

[0053] In a third aspect, the present application provides an electronic device, comprising:

[0054] a memory, configured to save a computer program;

[0055] a processor, configured to execute the computer program to implement the path tracing based scene rendering method described above.

[0056] In a fourth aspect, the present application provides a computer readable storage medium, configured to save a computer program; wherein the computer program is executed by a processor to implement the path tracing based scene rendering method described above.

[0057] In the present application, the target processor of the MIMD architecture obtains rendering information related to a target scene model to be rendered transmitted by a target host, and constructs a target acceleration scene structure based on the rendering information and a target thread of the target processor; the target thread is a thread of a plurality of threads of the target processor for initializing the target acceleration scene structure; the target acceleration scene structure is a bounding box tree composed of a plurality of bounding boxes; based on a preset task allocation rule and a local preset storage structure, the corresponding pixel rendering tasks are allocated to the plurality of threads, and the corresponding task allocation amount of each round is determined; the pixel rendering task is a task for rendering any one pixel point of a plurality of pixels to be rendered in the target scene model, and corresponds to the thread one by one; through the plurality of threads, the corresponding pixel rendering tasks are executed by using a preset path tracking technology, the target acceleration scene structure and the rendering information, so as to complete the rendering tasks of a corresponding number of pixel points corresponding to the task allocation amount of the current round, and then the corresponding number of pixel points corresponding to the task allocation amount of the next round in the current unrendered pixels are rendered according to the preset task allocation rule and a preset load balancing strategy, until the plurality of pixels to be rendered are all rendered, so as to obtain a plurality of rendered pixels; the plurality of rendered pixels are transmitted to the target host, so that the target host obtains a rendered scene for the target scene model based on the plurality of rendered pixels. As can be seen from the above, the target processor of the MIMD architecture of the present application obtains the rendering information transmitted by the target host, constructs the target acceleration scene structure composed of a plurality of bounding boxes by using the target thread and the rendering information, then allocates the rendering tasks for the pixel points of the target scene model to the plurality of threads according to the preset task allocation rule and the preset storage structure, and determines the task allocation amount of each round, then executes the pixel rendering tasks by the plurality of threads with the help of the preset path tracking technology, the target acceleration scene structure and the rendering information, and continues to render the current unrendered pixels after completion according to the preset task allocation rule and the load balancing strategy, until all the pixels to be rendered are processed, finally the rendered pixels are transmitted back to the target host, so that the target host generates a rendered scene. In this way, through the above process of the present application, the target processor improves the rendering efficiency by constructing the acceleration scene structure, reasonably allocates and dynamically adjusts the tasks to realize multi-thread parallel processing; the target processor uses the MIMD architecture for rendering processing, which can effectively solve the control divergence in the algorithm of accessing the tree-shaped data structure representing the scene; the tasks are allocated according to the storage structure of the processor, and the atomic task pool is built to avoid waste of thread resources, ensure efficient and balanced pixel rendering, fully utilize the processor cache hierarchy and hardware resources, realize efficient model rendering, and further solve the memory divergence and load imbalance problems existing in the path tracking rendering process. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only are a part of the present application, and for those skilled in the art, other drawings can be obtained based on the provided drawings without any creative effort.

[0059] Figure 1 A flow chart of a scene rendering method based on path tracing disclosed by the present application;

[0060] Figure 2 A schematic diagram of a regular part and an irregular part disclosed by the present application;

[0061] Figure 3 A timing diagram of a light path tracing flow disclosed by the present application;

[0062] Figure 4 A structural schematic diagram of a four-branch bounding volume tree disclosed by the present application;

[0063] Figure 5 A schematic diagram of PE cache-in thread task allocation disclosed by the present application;

[0064] Figure 6 A schematic diagram of city cache-in PE task allocation disclosed by the present application;

[0065] Figure 7 A schematic diagram of city cache-in PE task allocation disclosed by the present application;

[0066] Figure 8 A structural schematic diagram of a scene rendering device based on path tracing disclosed by the present application;

[0067] Figure 9 A structural diagram of an electronic device disclosed by the present application. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative effort are within the scope of protection of the present application.

[0069] Path tracing is a very important technology in rendering, which is used to render high realistic images and plays an important role in many fields such as animation production and game. Usually, the rendering is performed by using the Monte Carlo method through the SIMD (Single Instruction Multiple Data) and SIMT (Single Instruction Multiple Threads) architecture, but the technology is prone to the problem of control divergence in accessing the tree-shaped data structure representing the scene in the algorithm due to the inherent characteristics of frequent branching and irregular memory access, the utilization efficiency of the architecture hardware is low, the advantages of the architecture hardware cannot be fully utilized, and there is a phenomenon of unbalanced load, which greatly affects the performance.

[0070] In order to overcome the above technical problems, the application provides a scene rendering method based on path tracing, to solve the problems of memory divergence and unbalanced load in the path tracing rendering process.

[0071] Referring to Figure 1 The embodiment of the application discloses a scene rendering method based on path tracing, which is applied to a target processor of MIMD architecture, and comprises the following steps:

[0072] In step S11, rendering information related to a target scene model to be rendered is acquired from a target host, and a target acceleration scene structure is constructed based on the rendering information and a target thread of the target processor; the target thread is a thread of a plurality of threads of the target processor, which is used to initialize the target acceleration scene structure; and the target acceleration scene structure is a bounding box tree composed of a plurality of bounding boxes.

[0073] In this embodiment, a target processor of MIMD (i.e. Multiple Instruction Multiple Datastream) architecture acquires rendering information related to a target scene model to be rendered transmitted by a connected target host, and constructs a target acceleration scene structure based on the rendering information and a target thread in the target processor for initializing the target acceleration scene structure. The target acceleration scene structure is a bounding volume tree (i.e. Bounding Volume Hierarchies) tree composed of a plurality of bounding boxes, and the rendering information includes but is not limited to a triangular patch data structure array, a camera point (i.e. coordinate value of a space position for observing a scene), a view orientation vector (i.e. direction of space observation at the camera point), a pitch angle, a resolution (including h representing height and w representing width) of a rendering picture of the target scene model, a sampling number, etc. The triangular patch data structure array stores space information by three vertex data structures, each vertex data structure is composed of coordinate values on three dimensions x, y, z, and stores material information by a material data structure. The material data structure is PBR (i.e. Physically Based Rendering) map related information for storing information such as emission coefficient, reflection coefficient, refraction coefficient, transmission coefficient, scattering coefficient, diffuse reflection coefficient, and absorption coefficient.

[0074] It should be noted that the embodiment constructs the target acceleration scene structure by single thread and controls other threads to wait, and the processing flow is as follows: determining a triangle patch data structure array in the rendering information; the triangle patch data structure array is loaded by a plurality of triangle patch information corresponding to the target scene model, and the plurality of triangle patch information is obtained by analyzing the target scene model by the target host; determining the number of corresponding bounding boxes based on the number of local vector units, and defining a first bounding box data structure of independent bounding boxes; defining a second bounding box data structure of a target multi-way bounding box; the target multi-way bounding box is a combined bounding box composed of a preset number of independent bounding boxes as child nodes; the preset number is consistent with the number of bounding boxes; defining the target multi-way bounding box and a target data structure as a bounding box node by a target thread of the target processor, and constructing based on the bounding box node, the first bounding box data structure and the second bounding box data structure to obtain a constructed target acceleration scene structure; the target data structure is a data structure of a pointer pointing to the preset number of child nodes. Wherein, the first bounding box data structure is composed of two vertex data structures, one is the three coordinate values of the minimum in x, y and z dimensions, and the other is the maximum coordinate value in x, y and z dimensions, and the cubic box surrounded by the two vertices is the logical independent bounding box; the second bounding box data structure is used to store the minimum value of the preset number (N) of independent bounding boxes in x dimension, N minimum values constitute a floatN (a single precision floating point number type) type variable x_min, and the minimum values of y and z dimensions are stored as y_min and z_min, and the maximum values of three dimensions are stored as x_max, y_max and z_max.That is, the target host of the embodiment loads the target scene model data and parses it to obtain information of a plurality of triangular patches constituting the target scene model, and loads the information into a preset triangular patch data structure array to obtain a triangular patch data structure array, and then transmits rendering information containing the triangular patch data structure array to the target processor. The target processor determines the number of bounding boxes based on the number of vector unit bits provided by the MIMD architecture chip itself. For example, if there is a 128-bit wide vector unit in the device, it supports four floating point calculations at the same time, so the number of bounding boxes can be determined to be four. Four nodes are merged into one to construct a target acceleration scene structure for vectorized intersection judgment calculation. Then define a first bounding box data structure of an independent bounding box and a second bounding box data structure of a target multi-way bounding box, and define the data structure of the target multi-way bounding box and the pointer to the preset number of sub-nodes as a bounding box node through the target thread of the target processor, and construct based on the bounding box node, the first bounding box data structure and the second bounding box data structure to obtain the constructed target acceleration scene structure.

[0075] It needs to be further pointed out that the process flow of constructing the target acceleration scene structure based on the bounding box node, the first bounding box data structure and the second bounding box data structure is as follows: dividing the triangle face data structure array into the preset number of target subsets; constructing the corresponding bounding box node for each target subset, and storing the bounding box node into the first target stack; the bounding box node is a node composed of the target multi-branch bounding box and the target data structure; the target data structure is a data structure of a pointer pointing to the preset number of the subnode; the operation of dividing into the preset number of target subsets and the operation of constructing the corresponding bounding box node for each target subset and storing the bounding box node into the first target stack are performed in a recursive manner for the bounding box node in the first target stack, until it is detected that the number of triangles in the divided target subset is not higher than the preset number, and the currently constructed bounding box node is determined as a leaf node; the independent bounding box is constructed based on the spatial coordinates of the triangle in the leaf node and the first bounding box data structure, and the independent bounding box is merged according to the second bounding box data structure, so as to fill the leaf node with the constructed target multi-branch bounding box, to obtain the target acceleration scene structure containing the bounding box node. That is, the triangle face data structure data is divided by the target thread in the preset number, and the corresponding bounding box node is constructed and stored into the first target stack, and then the above division, construction and storage operations are performed in a recursive manner for the bounding box node in the first target stack, until it is detected that the number of triangles in the divided target subset is not higher than the preset number, and the currently constructed bounding box node is determined as a leaf node, and the independent bounding box is constructed based on the spatial coordinates of the triangle in the leaf node and the first bounding box data structure, and the independent bounding box is merged according to the second bounding box data structure, so as to fill the leaf node with the constructed target multi-branch bounding box, to obtain the target acceleration scene structure containing the bounding box node. In this way, the target processor of the embodiment first constructs the target acceleration scene structure based on the obtained rendering information, which can help to quickly locate and process objects in the scene, reduce unnecessary calculation and data retrieval time, and significantly improve rendering efficiency; the construction of the target acceleration scene structure is performed by a specific thread in the target processor, which realizes reasonable allocation of resources, fully utilizes the performance advantages of the processor, avoids thread resource conflicts, and ensures smooth progress of the rendering process; the vectorization of the ray and scene intersection judgment calculation is performed based on the number of vector units locally provided by the target processor, which can fully utilize the processor resources for calculation acceleration and further improve the rendering efficiency.

[0076] In step S12, the pixel rendering tasks are allocated to the threads based on preset task allocation rules and a preset storage structure, and the amount of each round of task allocation is determined. The pixel rendering task is a task of rendering any one pixel point of the pixels to be rendered in the target scene model, and is in one-to-one correspondence with the thread.

[0077] In this embodiment, after the target acceleration scene structure is constructed, considering that a processor with a general MIMD architecture generally has a multi-layer cache hierarchy, the pixel rendering tasks can be allocated to the threads based on preset task allocation rules and a preset storage structure, and the amount of each round of task allocation is determined.

[0078] It should be noted that according to the characteristics of the path tracking algorithm, the rays with adjacent spatial positions tend to access the same node of the scene tree, and when rendering the pixel points with adjacent spatial positions, the initial rays (i.e. the rays with the camera point as the starting point and the direction from the camera point to the pixel point as the direction) tend to be more adjacent in spatial position (the starting point is the same and the direction is similar). Therefore, the basic unit of the pixel rendering task allocated to each thread can be set to one pixel point instead of a larger block, that is, each thread is responsible for more adjacent pixel points, and each thread performs only one pixel point at a time.

[0079] Specifically, a local preset storage structure and a resolution of the target scene model in the rendering information are determined; the threads are divided into cache levels according to the preset storage structure and the resolution, and threads sharing the same level of cache level are controlled to be responsible for pixel point rendering tasks of spatially adjacent positions in the target scene model; thread numbers corresponding to the threads and level numbers of the cache levels to which the threads are divided are obtained based on a preset function, and pixel point spatial positions corresponding to the pixel point rendering tasks for which the threads are respectively responsible are determined based on the thread numbers and the level numbers, so that the threads perform the pixel rendering tasks for which the threads are respectively responsible according to the pixel point spatial positions; and the number of tasks allocated in each round is determined according to the cache level division of the threads. The preset function is a built-in function provided locally for obtaining thread numbers and level numbers. That is, the threads are divided into cache levels according to the local preset storage structure and the resolution of the target scene model in the rendering information, and threads sharing the same level of cache level are controlled to be responsible for pixel point rendering tasks of spatially adjacent positions in the target scene model, for example, threads sharing L1 level cache are controlled to be responsible for pixel point rendering tasks of spatially adjacent positions, and on the basis of the allocation rule, threads sharing L2 level cache are controlled to be responsible for pixel point rendering tasks of spatially adjacent positions, and if the target processor has a higher number of storage structure levels such as L3 level cache, the task allocation is performed according to the above rule. Then, thread numbers corresponding to the threads and level numbers of the cache levels to which the threads are divided are obtained based on a preset function, and pixel point spatial positions corresponding to the pixel point rendering tasks for which the threads are respectively responsible are determined based on the thread numbers and the level numbers, so that the threads perform the pixel rendering tasks for which the threads are respectively responsible according to the pixel point spatial positions, and the number of tasks allocated in each round is determined according to the cache level division of the threads, that is, the size of the layout block of the pixel rendering tasks allocated at a time. It can be understood that for a MIMD architecture processor, which is composed of a large number of small units with logical control units, threads sharing the same level of cache will be responsible for pixel point rendering of more adjacent spatial positions after task allocation. However, for all threads, after grouping according to the cache level, there are still a number of groups. Different layout modes of the number of groups still have different effects on performance. In the path tracking algorithm, the distribution of the scene model is often uneven, which will lead to different workloads of rendering pixel points of different spatial positions. In practice, the most intuitive reflection is that the rendering time difference of different regional pixel points is very large, which reflects the unbalanced workload of the multi-thread processor. Therefore, for the purpose of balancing the workload between threads, the embodiment can allocate tasks according to the most adjacent layout of spatial positions of the number of pixel blocks.

[0080] It should be noted that, considering that the resolution of the target scene model to be rendered is not necessarily divisible by the per-round task allocation amount, some threads may be responsible for more pixel rendering tasks, exacerbating the phenomenon of uneven workload among threads, therefore, before allocating pixel rendering tasks, the target image can be divided into a part that can be divided by the basic task unit width and height and a part that cannot be divided, and the former is referred to as a regular part and the latter is referred to as an irregular part, as shown in Figure 2 A schematic diagram of a regular part and an irregular part provided by the present application is shown, and the processing flow is as follows: the resolution of the target scene model in the rendering information is determined, and it is judged whether the height or width of the resolution is a multiple of the per-round task allocation amount; if it is judged that the height or width of the resolution is not a multiple of the per-round task allocation amount, the irregular part and the regular part in the target scene model are determined, and the irregular part is stored in a preset atomic task pool; the irregular part is the part in the target scene model that cannot be divided by the per-round task allocation amount; the regular part is the part in the target scene model that can be divided by the per-round task allocation amount; for the regular part, the corresponding pixel rendering tasks are allocated to the threads based on the preset task allocation rule and the local preset storage structure. The atomic task pool is a task pool provided by a target processor supporting atomic operations. That is, it is judged whether the height or width of the resolution in the rendering information is a multiple of the per-round task allocation amount, and if not, it indicates that there is an irregular part that cannot be divided, therefore, the irregular part and the regular part in the target scene model can be determined first, and the irregular part is stored in a preset atomic task pool, and for the regular part, the corresponding pixel rendering tasks are allocated to the threads based on the preset task allocation rule and the local preset storage structure. In this way, the present embodiment allocates pixel rendering tasks to threads based on the local preset storage structure, which can fully exploit the multi-level cache potential, reduce data conflicts and thread waiting time, realize efficient use of processor cache resources, accelerate parallel processing of pixel rendering tasks, and significantly improve the overall execution efficiency of rendering tasks; controlling sharing the same level and a plurality of groups responsible for the most adjacent pixels in space position to balance the workload among threads and ensure the performance of rendering; the basic unit of pixel rendering tasks allocated to each thread is 1 pixel, which can make the pixels responsible by each thread more adjacent and improve the accuracy of rendering.

[0081] Step S13, by the threads, using a preset path tracing technique, the target accelerated scene structure and the rendering information, performing the respective corresponding pixel rendering tasks to complete the rendering tasks of the corresponding number of pixel points corresponding to the current task allocation amount, and then rendering the corresponding number of pixel points corresponding to the next task allocation amount in the current unrendered pixels according to the preset task allocation rule and a preset load balancing strategy until the several to-be-rendered pixels are all rendered to obtain several rendered pixels.

[0082] In this embodiment, by the threads, using a preset path tracing technique, the target accelerated scene structure and the rendering information, performing the respective corresponding pixel rendering tasks to complete the rendering tasks of the corresponding number of pixel points corresponding to the current task allocation amount, and then rendering the corresponding number of pixel points corresponding to the next task allocation amount in the current unrendered pixels according to the preset task allocation rule and a preset load balancing strategy until the several to-be-rendered pixels are all rendered to obtain several rendered pixels.

[0083] It should be noted that, as Figure 3A light path tracking flow timing diagram provided by the application is shown, and the processing flow of the pixel rendering task allocated by the threads responsible for the respective pixel points is as follows: determining the camera point in the rendering information and determining the target pixel point of the pixel rendering task corresponding to the respective threads; the camera point is the coordinate value of the space position used for observing the target scene model; the direction of the line connecting the camera point and the target pixel point is determined as a direction vector, and an initial light ray is generated based on the direction vector and the camera point; the initial light ray is traversed with the target acceleration scene structure to find the target hit point in the target acceleration scene structure that intersects the initial light ray, to obtain a corresponding search result; the target hit point is the hit point with the smallest time point among the hit points in the target acceleration scene structure that intersect the initial light ray; if the search result indicates that there is a target hit point in the target acceleration scene structure that intersects the initial light ray, the triangle patch information in the target hit point is taken out, and the outgoing direction is generated according to the material information in the triangle patch information; the light ray is tracked according to the outgoing direction, and it is determined whether it hits a light source; if it does not hit a light source, the absorption coefficient of the current hit material is recorded, and a secondary light ray is constructed with the current hit point as the starting point and the outgoing direction as the direction, the secondary light ray is determined as the initial light ray, and the step of traversing the initial light ray with the target acceleration scene structure is jumped to, until a preset number of ejections is reached, or a light source is hit; when it is determined that a light source is hit, the rendered target pixel is calculated according to the recorded absorption coefficient and the current pixel value, and the pixel rendering task is completed. The light ray data structure of the initial light ray is composed of the starting point coordinate, the direction vector, the minimum value of the effective time region, and the maximum value of the effective time region (i.e. the time of light ray and scene intersection within the region is considered as an effective hit).That is, the direction of the line connecting the target pixel corresponding to the camera point and the thread is determined as a direction vector, and an initial light ray is generated based on the direction vector, the camera point, a preset effective time minimum value, and a preset effective time maximum value. Subsequently, the initial light ray is traversed with the target acceleration scene structure to find a target hit point in the target acceleration scene structure that has the smallest time point of intersection with the initial light ray. If the target hit point does not exist, the subsequent process is terminated, and the current pixel value is directly determined as the target pixel. If the target hit point exists, the triangle patch information therein is taken out, the behavior after hitting the triangle patch is calculated according to the material information in the triangle patch information, and an outgoing direction is generated according to the characteristics thereof, for example, if it is reflection, the outgoing direction is calculated according to the normal of the hit point and the direction of the incident light ray, if it is scattering, a random outgoing direction is generated, and the like. Then, ray tracing is performed according to the outgoing direction. If a light source is hit, the tracing is ended, and the light emission value is returned. If not, the absorption coefficient of the current hit material is recorded, the color of the light is represented by the absorption coefficient, and a secondary light ray is constructed with the current hit point as the starting point and the outgoing direction as the direction. The above process of the initial light ray is performed with the secondary light ray until a preset bounce number is reached, or a light source is hit. If it is determined that a light source is hit, the rendered target pixel is calculated according to the recorded absorption coefficient and the current pixel value, and the pixel rendering task is completed.

[0084] It needs to be further pointed out that the process flow of finding the target hit point is as follows: traversing the initial light ray and the initial node of the target acceleration scene structure, and in the process of traversal, saving the target child node of the target node intersecting with the initial light ray to the second target stack; the initial node is the child node directly connected with the root node in the target acceleration scene structure; taking out the target child node in the second target stack, and taking the target child node as the initial node of the next recursion, and jumping to the step of traversing the initial light ray and the initial node of the target acceleration scene structure, until the second target stack is empty, to find the target hit point intersecting with the initial light ray in the target acceleration scene structure, and obtain the corresponding finding result. That is, each node of the target acceleration scene structure stores a target multi-branch bounding box, the initial light ray is first traversed with the child node directly connected with the root node, and the target child node intersecting with the initial light ray is saved to the second target stack, specifically by calculating the time point of the light ray passing through the minimum value and the maximum value in each coordinate dimension, the time period is the time domain of the light ray passing through the bounding box in this coordinate dimension for intersection judgment, if there is an intersection subset through the time period of the minimum value and the maximum value of the three coordinate dimensions, it means intersection, then the target child node in the second target stack is taken as the initial node of the next recursion, and the step of traversal is jumped to, until the second target stack is empty. It needs to be explained that the process flow in the process of traversal is as follows: when traversing to the leaf node in the target acceleration scene structure, the triangular patches in the leaf node are judged for intersection with the initial light ray, if it is judged to intersect with the initial light ray, it is determined that the leaf node currently intersecting with the initial light ray is the hit point, and the time point of the hit point is compared with the time point of the currently recorded target hit point to obtain the corresponding comparison result; if the comparison result represents that the time point of the hit point is less than the time point of the currently recorded target hit point, the hit point is determined as the target hit point. Wherein, the record is used to store the latest triangular patch of the hit. That is, for the leaf node, the triangular patches therein are judged with the initial light ray, if intersecting, the current hit point is compared with the time point recorded, if less, the current hit point is updated to the record.

[0085] It needs to be explained that the rendering process of the current unrendered pixel is as follows: after the thread completes the corresponding pixel rendering task, the spatial position of the pixel point to be rendered in the next round in the regular part is located according to the preset task allocation rule, and the located pixel point is rendered, and the step of jumping to the step of locating the spatial position of the pixel point to be rendered in the next round in the regular part according to the preset task allocation rule is performed until the spatial position of the located pixel point exceeds the height or width of the resolution; the number of pixel points of the irregular part in the atomic task pool is determined, and the preset variable value corresponding to the atomic task pool for recording the current rendering task number is determined; after the thread locates the spatial position of the pixel point, the current preset variable value is compared with the number of pixel points if the current preset variable value is less than the number of pixel points, the preset variable value is increased by one, and the target pixel point to be rendered in the irregular part corresponding to the preset variable value is taken out; the target pixel point to be rendered is rendered by the thread, and the step of comparing the current preset variable value with the number of pixel points is jumped to until the current preset variable value is equal to the number of pixel points. That is, after the thread completes the pixel rendering task, the spatial position of the pixel point to be rendered in the next round in the regular part is located with the task allocation amount of each round as the span, and the located pixel point is rendered, and the same rendering is repeated for the number of sampling times in x dimension (width) and y dimension (height) with the task allocation amount of each round as the span until the x dimension coordinate value of the located pixel point is greater than w, the y dimension coordinate value is greater than h, and the same rendering is repeated for the number of sampling times at each pixel point. Finally, the results are averaged to reduce noise and more approach the true results. After the thread renders all the pixel points in the regular part corresponding to itself, the number of pixel points of the irregular part in the atomic task pool is determined, and a preset variable value for recording the current rendering task number is stored in the atomic cache. The current preset variable value is compared with the number of pixel points, if it is less than the number of pixel points, the preset variable value is increased by one, and the target pixel point to be rendered corresponding to the preset variable value is taken out for rendering, and the comparison step is jumped to until the current preset variable value is equal to the number of pixel points. In this way, the embodiment can make the thread with faster execution speed bear according to the task allocation of the irregular part according to the preset load balancing strategy, balance the work load of each thread as a whole, and further perform dynamic load balancing on the basis of ensuring maximum possible static load balancing.

[0086] Step S14, transmitting the several rendered pixels to the target host, so that the target host obtains a rendered scene for the target scene model based on the several rendered pixels.

[0087] In this embodiment, after obtaining the several rendered pixels, the several rendered pixels are transmitted to the target host, so that the target host outputs the several rendered pixels as a rendered scene for the target scene model, and completes the rendering work.

[0088] It should be noted that the performance of the method of the present application can be evaluated by using the rendering time of a picture with the same rendering quality as the evaluation standard, and the time difference between the fastest thread and the slowest execution thread is used to evaluate the balance of the load, and the quality of the image is measured by using the mean square error, and the formula of the mean square error (MSE) can be as follows:

[0089] ;

[0090] wherein M and N respectively represent the height and width of the image, is the pixel value of the image to be evaluated at the (i, j) position, is the pixel value of the standard image at the (i, j) position. The pixel value of the standard image is used as the reference to calculate the MSE value, and under the premise that each rendering scheme has the same MSE value, the rendering time is used as the evaluation standard, and the baseline of the CPU (Central Processing Unit) is compared. The method has advantages on each scene data set.

[0091] As can be seen, the target processor of the MIMD architecture of the embodiment of the present application acquires the rendering information transmitted by the target host, constructs a target acceleration scene structure composed of a plurality of bounding boxes by using the target threads and the rendering information, then allocates rendering tasks for a plurality of threads for pixel points of the target scene model according to a preset task allocation rule and a preset storage structure, and determines the amount of task allocation in each round, then executes the pixel rendering task by the plurality of threads by means of a preset path tracking technology, the target acceleration scene structure and the rendering information, and continues to render the current unrendered pixels according to the preset task allocation rule and load balancing strategy after completion, until all the to-be-rendered pixels are processed, and finally transmits the rendered pixels back to the target host, so that the target host generates a rendered scene. In this way, through the above process of the embodiment of the present application, on the one hand, the target processor constructs the target acceleration scene structure based on the acquired rendering information, which can help to quickly locate and process objects in the scene, reduce unnecessary calculation and data retrieval time, and significantly improve rendering efficiency; on the other hand, the construction of the target acceleration scene structure by the specific threads in the plurality of threads of the target processor realizes the reasonable allocation of resources, fully utilizes the performance advantages of the processor, avoids thread resource conflicts, and ensures the smooth progress of the rendering process; on the one hand, the vectorization of the ray and scene intersection judgment calculation based on the number of vector units locally provided by the target processor can fully utilize the processor resources for calculation acceleration, and further improve the rendering efficiency; on the one hand, the allocation of pixel rendering tasks for a plurality of threads based on the local preset storage structure can fully tap the potential of multi-level cache, reduce data conflicts and thread waiting time, realize efficient utilization of processor cache resources, accelerate parallel processing of pixel rendering tasks, and significantly improve the overall execution efficiency of rendering tasks; on the one hand, controlling the same level and a plurality of groups responsible for the most adjacent pixels in space position can balance the work load among threads and ensure the performance of rendering; on the one hand, the basic unit of pixel rendering task allocated to each thread is 1 pixel point, which can make the pixel points responsible by each thread more adjacent and improve the accuracy of rendering; on the one hand, the task allocation according to the preset load balancing strategy for irregular parts can balance the work load of each thread on the whole, and further use atomic cache for dynamic load balancing on the basis of ensuring the maximum possible static load balancing; on the other hand, the target processor uses the MIMD architecture for rendering processing, which can effectively solve the control divergence in accessing the tree-shaped data structure representing the scene in the algorithm, and further solve the memory divergence and load imbalance problems existing in the path tracking rendering process.

[0092] Based on the above embodiment, the application discloses a scene rendering method based on path tracing, which can solve the memory divergence and load imbalance problems existing in the path tracing rendering process. Next, taking the MIMD processor PEZY-SC3s (a kind of MIMD processor) with 4096 hardware threads as an example, the scene rendering method based on path tracing will be described in detail.

[0093] First, the rendering information transmitted by the target host is received, and the single-threaded acceleration scene structure is constructed according to the rendering information. PEZY-SC3s has 4096 threads, and the thread with thread number 0 constructs the acceleration scene structure, and the remaining threads wait. At the same time, the vector unit is fully utilized for calculation acceleration. There is a 128-bit wide vector unit in this device, which supports four floating-point calculations at the same time. Utilizing this feature, the vectorization of ray and scene intersection judgment calculation is carried out, and the 128-bit vector unit is used to construct the target acceleration scene structure MBVH (Multi-Bounding Volume Hierarchy, four-branch bounding box tree) for vectorized intersection judgment calculation, which combines four scene nodes into one. Specifically, the MBVH is constructed with a data structure containing a multi-branch bounding box and a pointer to a four-word node pointer as a node (MBVH node). Thread 0 divides the triangle patch data structure array in the rendering information into four parts, and constructs an empty MBVH node for each part and stores it in the stack. Recursively divide and construct empty MBVH nodes until the number of elements in the triangle patch data structure array is less than or equal to 4, then construct a bounding box based on the spatial coordinates of each of these three patches and form a quadtree bounding box to fill the MBVH node constructed for it, and mark the node as a leaf node. Remove the empty MBVH node from the stack and construct the quadtree bounding box of the current node based on the spatial coordinates of the bounding boxes of the four child MBVH nodes pointed to by the node, to form an MBVH. As shown in the following figure, it is a structure diagram of a four-branch bounding box tree provided by the application. Figure 4 As shown in the following figure, it is a structure diagram of a four-branch bounding box tree provided by the application.

[0094] Subsequently, according to the processor storage hierarchy, the 4096 threads are divided into prefecture, city, and pe from top to bottom. 128 threads share an L2 level cache to form a city, and 8 threads share an L1 level cache to form a pe. That is, the 8 threads in the pe share the L1 level cache, and the 8 threads control the most adjacent 8 pixel points, i.e. 2*8 pixel point tasks, as shown in the following figure. Figure 5The diagram illustrates a thread task allocation method within a PE cache provided in this application. Sixteen PEs form a city, and the 128 threads within it share an L2 cache. Similarly, these 16 PEs are controlled to allocate tasks in a 4x4 layout while adhering to the internal thread task allocation method of each PE. Figure 6 The diagram illustrates a PE task allocation method within a city cache, as provided in this application. 128 threads within a city are responsible for an 8*16 pixel block task. The device uses built-in functions to obtain the thread number and PE number, and calculates the row and column offsets of the pixels each thread is responsible for within its 8*16 pixel block in each city. The calculation formula is as follows:

[0095] ;

[0096] ;

[0097] Where offset_row represents the row offset, offset_col represents the column offset, tid is the thread number, and PE_id is the PE number. Thus, the 4096 threads in the processor are divided into 32 groups based on the L2 cache for pixel block tasks. To balance the workload among the threads, these groups of pixel blocks can be assigned tasks according to their spatially adjacent layout, that is, the 32 groups are assigned tasks in an 8*4 layout. This allows the 32 threads in the processor to be responsible for the adjacent pixel blocks while following the task allocation scheme described above. With an 8*4 layout, the entire processor will handle 64*64 pixel blocks in one execution. Figure 7 The diagram shown illustrates a city task allocation method within a processor, as provided in this application. According to this task allocation method, the processor performs a 64*64 pixel rendering task at a time, which is the basic task allocation unit. A thread can calculate the row and column offsets of its assigned pixels within the basic task allocation unit based on the city's ID (i.e., Identity document). The calculation formula is as follows:

[0098] ;

[0099] ;

[0100] Where city_id is the ID number of the city. After each thread finishes rendering the current pixel, it locates the spatial position of the next pixel in the next round of work with a span of 64*64. Specifically, it loops in the x-dimension (width) and y-dimension (height), with each step being 64. When the coordinate value in the x-dimension is greater than the resolution width, it exits the loop in the x-dimension; when the coordinate value in the y-dimension is greater than the resolution height, it exits the loop in the y-dimension.

[0101] According to the above process, each thread performs the rendering task for each pixel in a loop. If a thread has not yet finished rendering after completing its assigned task, it needs to wait. When rendering a target image whose resolution width or height is not a multiple of 64, some threads may be responsible for rendering more pixels, exacerbating the workload imbalance between threads. Therefore, the image to be rendered can be divided into parts that are divisible by the width and height of a 64*64 pixel block and parts that are not. The former is called the regular part, and the latter is called the irregular part, such as... Figure 2 The diagram illustrates the regular and irregular parts provided in this application. In the regular part, tasks are allocated according to the aforementioned task allocation rules. Since this allocation is divisible by the basic task unit, each thread is responsible for the same number of pixels. The irregular part is stored in an atomic task pool, utilizing hardware supporting atomic operations to implement a dynamic load balancing strategy. Specifically, an atomic cache stores a variable value recording the current task, initially set to 0. Simultaneously, the number of pixels (task) in the irregular part is calculated. When this variable value is less than the task value, the corresponding pixel is retrieved for rendering. After a thread finishes rendering its assigned task, it enters an infinite loop, retrieving the task value from the atomic pool, incrementing the variable, and retrieving the corresponding pixel rendering task. Finally, when the variable value equals the task value, the loop ends.

[0102] Each thread writes the pixel values ​​of the assigned pixels back to the result and transmits them back to the target host, which then outputs the pixel values ​​as an image, completing the rendering process.

[0103] Accordingly, see Figure 8 As shown in the illustration, this application also provides a path-tracing-based scene rendering apparatus, applied to a target processor of a MIMD architecture, comprising:

[0104] A structure constructing module 11 is configured to acquire rendering information transmitted by a target host and related to a target scene model to be rendered, and to construct a target acceleration scene structure based on the rendering information and a target thread of a target processor; the target thread is a thread of a plurality of threads of the target processor, which is used to initialize the target acceleration scene structure; the target acceleration scene structure is a bounding box tree composed of a plurality of bounding boxes;

[0105] A unit determining module 12 is configured to allocate a corresponding pixel rendering task to each of the plurality of threads based on a preset task allocation rule and a preset storage structure, and to determine a corresponding task allocation amount of each round; the pixel rendering task is a task of rendering any one of a plurality of pixel points in the target scene model, and is one-to-one corresponding to the thread;

[0106] A pixel rendering module 13 is configured to execute the corresponding pixel rendering task by the plurality of threads using a preset path tracing technique, the target acceleration scene structure and the rendering information, to complete the rendering task of a corresponding number of pixel points of the task allocation amount of the current round, and then to render a corresponding number of pixel points of the task allocation amount of the next round in the current unrendered pixels according to the preset task allocation rule and a preset load balancing strategy, until the plurality of to-be-rendered pixels are all rendered, to obtain a plurality of rendered pixels.

[0107] A pixel transmission module 14 is configured to transmit the plurality of rendered pixels to the target host, so that the target host acquires a rendered scene for the target scene model based on the plurality of rendered pixels.

[0108] As can be seen from the above, the target processor of the MIMD architecture in this application obtains the rendering information transmitted by the target host, constructs a target accelerated scene structure composed of several bounding boxes using the target thread and the rendering information, and then allocates rendering tasks for the target scene model pixels to several threads according to the preset task allocation rules and preset storage structure, and determines the task allocation amount in each round. Then, the several threads execute pixel rendering tasks with the help of preset path tracing technology, the target accelerated scene structure and the rendering information, and continue to render the currently unrendered pixels according to the preset task allocation rules and load balancing strategy after completion, until all pixels to be rendered are processed. Finally, the rendered pixels are transmitted back to the target host so that the target host can generate the rendered scene. In this way, through the above process of the embodiments of this application, the target processor improves rendering efficiency by constructing an accelerated scene structure, and achieves multi-threaded parallel processing by reasonably allocating and dynamically adjusting tasks; the target processor adopts the MIMD architecture for rendering processing, which can effectively solve the control divergence that occurs when accessing the tree data structure representing the scene in the algorithm; tasks are allocated according to the processor's storage structure, and an atomic task pool is built to avoid wasting thread resources, ensure efficient and balanced pixel rendering, make full use of the processor cache hierarchy and hardware resources, achieve efficient model rendering, and thus solve the memory divergence and load imbalance problems in the path tracing rendering process.

[0109] In some specific embodiments, the structural construction module 11 may specifically include:

[0110] An array determination unit is used to determine the triangular facet data structure array in the rendering information; the triangular facet data structure array is loaded from several triangular facet information corresponding to the target scene model, and the several triangular facet information is the information obtained by the target host parsing the target scene model;

[0111] The first structure definition unit is used to determine the corresponding number of bounding boxes based on the number of bits of the local vector unit, and to define the first bounding box data structure of the independent bounding boxes;

[0112] The second structure definition unit is used to define the second bounding box data structure of the target multi-branch bounding box; the target multi-branch bounding box is a combined bounding box composed of a preset number of independent bounding boxes as child nodes; the preset number is the same as the number of bounding boxes.

[0113] The structure construction sub-module is configured to define the target multi-way bounding box and a target data structure as a bounding box node by a target thread of the target processor, and construct the target multi-way bounding box based on the bounding box node, the first bounding box data structure and the second bounding box data structure to obtain a constructed target acceleration scene structure; the target data structure is a data structure of pointers pointing to the preset number of sub-nodes.

[0114] In some embodiments, the structure construction sub-module can specifically include:

[0115] The subset division unit is configured to divide the triangle patch data structure array into the preset number of target subsets;

[0116] The node storage unit is configured to respectively construct corresponding bounding box nodes for the target subsets, and store the bounding box nodes into a first target stack; the bounding box node is a node composed of the target multi-way bounding box and a target data structure; the target data structure is a data structure of pointers pointing to the preset number of sub-nodes;

[0117] The node determination unit is configured to perform the operation of dividing the target subsets in a recursive manner for the bounding box nodes in the first target stack, and the operation of respectively constructing corresponding bounding box nodes for the target subsets and storing the bounding box nodes into the first target stack, until it is detected that the number of triangle patches in the divided target subsets is not higher than the preset number, and the currently constructed bounding box node is determined as a leaf node;

[0118] The bounding box merging unit is configured to construct the independent bounding box based on the spatial coordinates of the triangle patches in the leaf node and the first bounding box data structure, and perform a merging operation on the independent bounding box according to the second bounding box data structure, so as to fill the leaf node with the constructed target multi-way bounding box to obtain a target acceleration scene structure containing the bounding box node.

[0119] In some embodiments, the unit determination module 12 can specifically include:

[0120] The resolution determination unit is configured to determine the resolution of the target scene model in the local preset storage structure and the rendering information;

[0121] The thread control unit is configured to divide the plurality of threads according to the preset storage structure and the resolution, and control threads sharing the same cache level in the plurality of threads to be responsible for pixel point rendering tasks in spatial positions adjacent to the target scene model;

[0122] A position determining unit is configured to obtain a thread number corresponding to each of the threads and a level number of the cache level to which each of the threads is divided based on a preset function, and determine a pixel point spatial position corresponding to the pixel point rendering task for which each of the threads is responsible based on the thread number and the level number, so that each of the threads executes the pixel rendering task for which it is responsible according to the pixel point spatial position.

[0123] A distribution amount determining unit is configured to determine a distribution amount of each round of tasks according to the cache level division of the threads.

[0124] In some embodiments, the unit determining module 12 can specifically include:

[0125] A condition judging unit is configured to determine a resolution of the target scene model in the rendering information, and judge whether the height or width of the resolution is a multiple of the distribution amount of each round of tasks.

[0126] A partial storing unit is configured to determine an irregular part and a regular part in the target scene model if it is judged that the height or width of the resolution is not a multiple of the distribution amount of each round of tasks, and store the irregular part in a preset atomic task pool; the irregular part is a part in the target scene model that cannot be divided by the distribution amount of each round of tasks; and the regular part is a part in the target scene model that can be divided by the distribution amount of each round of tasks.

[0127] A task distribution unit is configured to distribute corresponding pixel rendering tasks to the threads based on a preset task distribution rule and a local preset storage structure for the regular part.

[0128] Correspondingly, the pixel rendering module 13 can specifically include:

[0129] A first step jumping unit is configured to, after the thread completes the corresponding pixel rendering task, locate a spatial position of a pixel point to be rendered in the next round in the regular part according to the preset task distribution rule, render the located pixel point, and jump to the step of locating the spatial position of the pixel point to be rendered in the next round in the regular part according to the preset task distribution rule until the located spatial position of the pixel point exceeds the height or width of the resolution.

[0130] A variable value determining unit is configured to determine a number of pixel points of the irregular part in the atomic task pool and a preset variable value corresponding to the atomic task pool and used to record a current number of rendering tasks.

[0131] The pixel point extraction unit is configured to compare the preset variable value with the number of pixel points when the spatial position of the pixel point positioned by the thread exceeds the height or width of the resolution, and if the preset variable value is less than the number of pixel points, increase the preset variable value by one and extract a target pixel point in the irregular part corresponding to the preset variable value.

[0132] The second step jump unit is configured to render the target pixel point by the thread and jump to the step of comparing the preset variable value with the number of pixel points until the preset variable value is equal to the number of pixel points.

[0133] In some embodiments, the pixel rendering module 13 can specifically include:

[0134] The pixel point determination unit is configured to determine a camera point in the rendering information and determine a target pixel point of the pixel rendering task corresponding to each thread; the camera point is a coordinate value of a spatial position preset for observing the target scene model.

[0135] The ray generation unit is configured to determine a direction vector of a direction connecting the camera point and the target pixel point and generate an initial ray based on the direction vector and the camera point.

[0136] The ray traversal submodule is configured to traverse the initial ray and the target accelerated scene structure to find a target hit point intersecting the initial ray in the target accelerated scene structure to obtain a corresponding search result; the target hit point is a hit point with the smallest time point among a plurality of hit points intersecting the initial ray in the target accelerated scene structure.

[0137] The direction generation unit is configured to extract triangle patch information in the target hit point if the search result indicates that there is a target hit point intersecting the initial ray in the target accelerated scene structure, and generate an outgoing direction according to material information in the triangle patch information.

[0138] The hit determination unit is configured to perform ray tracing according to the outgoing direction and determine whether a light source is hit.

[0139] The third step jump unit is configured to record an absorption coefficient of a current hit material if the light source is not hit, take the current hit point as a starting point and the outgoing direction as a direction to construct a secondary ray, determine the secondary ray as the initial ray, and jump to the step of traversing the initial ray and the target accelerated scene structure until a preset bouncing number is reached or the light source is hit.

[0140] A pixel calculation unit is configured to calculate a rendered target pixel according to the recorded absorption coefficient and a current pixel value when it is determined that the light source is hit, so as to complete the pixel rendering task.

[0141] In some embodiments, the ray traversal submodule can specifically include:

[0142] A child node saving unit is configured to traverse the initial ray and an initial node of the target acceleration scene structure, and save a target child node of a target node intersected with the initial ray to a second target stack during the traversal; the initial node is a child node directly connected with a root node in the target acceleration scene structure.

[0143] A fourth step jump unit is configured to take out the target child node in the second target stack, take the target child node as the initial node for next recursion, and jump to the step of traversing the initial ray and the initial node of the target acceleration scene structure until the second target stack is empty, so as to find a target hit point intersected with the initial ray in the target acceleration scene structure and obtain a corresponding search result.

[0144] Correspondingly, the fourth step jump unit is specifically configured to, when a leaf node in the target acceleration scene structure is traversed, perform intersection judgment on a triangular patch in the leaf node and the initial ray, determine the leaf node intersected with the initial ray as a hit point if it is determined that the leaf node is intersected with the initial ray, and compare a time point of the hit point with a time point of a currently recorded target hit point, so as to obtain a corresponding comparison result; and determine the hit point as the target hit point if the comparison result indicates that the time point of the hit point is less than the time point of the currently recorded target hit point.

[0145] Further, the embodiment of the present application further discloses an electronic device, Figure 9 is a structure diagram of an electronic device 20 according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the use range of the present application. The electronic device 20 can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is configured to store a computer program, the computer program is loaded and executed by the processor 21, so as to realize the related steps in the path-tracing-based scene rendering method disclosed in any of the preceding embodiments. In addition, the electronic device 20 in the embodiment can be an electronic computer.

[0146] In this embodiment, the power supply 23 is configured to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 is configured to create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which will not be specifically limited herein; the input / output interface 25 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which will not be specifically limited herein.

[0147] In addition, the memory 22 as a carrier of resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0148] The operating system 221 is configured to manage and control each hardware device on the electronic device 20 and the computer program 222, and can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the path tracking based scene rendering method executed by the electronic device 20 disclosed in any of the preceding embodiments, the computer program 222 can further include a computer program capable of completing other specific work.

[0149] Further, the present application also discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the path tracking based scene rendering method disclosed above. For the specific steps of the method, please refer to the corresponding content disclosed in the preceding embodiments, which will not be repeated here.

[0150] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0151] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in a general manner in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0152] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. The

[0153] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and do not imply or require any such actual relationship or order. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0154] The above detailed description of the technical solutions provided by the present application has been described in detail, and the principles and implementation modes of the present application have been described by applying specific examples; the above description of the embodiments is only for the purpose of helping to understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description of the content of the specification should not be understood as a limitation of the present application.

Claims

1. A scene rendering method based on path tracing, characterized in that, Target processors used in MIMD architecture include: The system acquires rendering information related to the target scene model to be rendered, transmitted from the target host, and constructs a target accelerated scene structure based on the rendering information and the target thread of the target processor. The target thread is one of several threads of the target processor used to initialize the target accelerated scene structure. The target accelerated scene structure is a bounding box tree composed of several bounding boxes. Based on the preset task allocation rules and the local preset storage structure, corresponding pixel rendering tasks are allocated to the several threads, and the corresponding task allocation amount for each round is determined; the pixel rendering task is a task that renders any one pixel of several pixels to be rendered in the target scene model, and corresponds one-to-one with the thread. Through the aforementioned threads, the corresponding pixel rendering tasks are executed using preset path tracing technology, the target accelerated scene structure, and the rendering information to complete the rendering tasks of the number of pixels corresponding to the task allocation amount in this round. Then, according to the preset task allocation rules and preset load balancing strategy, the number of pixels in the currently unrendered pixels corresponding to the task allocation amount in the next round are rendered until all the pixels to be rendered are rendered to obtain several rendered pixels. The rendered pixels are transmitted to the target host so that the target host can obtain the rendered scene for the target scene model based on the rendered pixels. The step of executing the corresponding pixel rendering tasks through the plurality of threads using preset path tracing technology, the target accelerated scene structure, and the rendering information includes: The camera points in the rendering information are determined, and the target pixel points of the pixel rendering tasks corresponding to the plurality of threads are determined respectively; the camera points are preset coordinate values ​​of the spatial location used to observe the target scene model. The direction of the line connecting the camera point and the target pixel point is determined as a direction vector, and an initial ray is generated based on the direction vector and the camera point; The initial ray is traversed along the target acceleration scene structure to find the target hit point in the target acceleration scene structure that intersects with the initial ray, and the corresponding search result is obtained; the target hit point is the hit point with the smallest time among several hit points in the target acceleration scene structure that intersect with the initial ray. If the search result indicates that there is a target hit point in the target acceleration scene structure that intersects with the initial ray, then the triangular facet information in the target hit point is extracted, and the emission direction is generated based on the material information in the triangular facet information; Ray tracing is performed based on the emission direction, and it is determined whether the light source is hit; If the light source is not hit, the absorption coefficient of the material hit is recorded, and a secondary ray is constructed with the current hit point as the starting point and the emission direction as the direction. The secondary ray is determined as the initial ray, and the process jumps to the step of traversing the initial ray and the target acceleration scene structure until the preset number of ejections is reached, or the light source is hit. Once a light source is determined to be hit, the target pixel after rendering is calculated based on the recorded absorption coefficient and the current pixel value, thus completing the pixel rendering task.

2. The scene rendering method based on path tracing according to claim 1, characterized in that, The construction of the target accelerated scene structure based on the rendering information and the target thread of the target processor includes: The triangular facet data structure array in the rendering information is determined; the triangular facet data structure array is loaded from several triangular facet information corresponding to the target scene model, and the several triangular facet information is the information obtained by the target host parsing the target scene model; The number of bounding boxes is determined based on the number of bits of the local vector unit, and the first bounding box data structure of the independent bounding boxes is defined. Define a second bounding box data structure for the target multi-branch bounding box; the target multi-branch bounding box is a combined bounding box composed of a preset number of independent bounding boxes as child nodes; the preset number is the same as the number of bounding boxes. The target processor's target thread defines the target multi-branch bounding box and the target data structure as bounding box nodes, and constructs a target accelerated scene structure based on the bounding box nodes, the first bounding box data structure, and the second bounding box data structure; the target data structure is a data structure that points to the preset number of child nodes.

3. The scene rendering method based on path tracing according to claim 2, characterized in that, The definition of the target multi-branch bounding box and the target data structure as bounding box nodes, and the construction of the target acceleration scene structure based on the bounding box nodes, the first bounding box data structure, and the second bounding box data structure, includes: Divide the triangular facet data structure array into the preset number of target subsets; Construct corresponding bounding box nodes for each of the target subsets, and store the bounding box nodes in the first target stack; the bounding box node is a node composed of the target multi-branch bounding box and the target data structure; the target data structure is a data structure that points to the preset number of the child nodes; The operation of dividing the bounding box node in the first target stack into the preset number of target subsets is performed recursively, and the operation of constructing corresponding bounding box nodes for the target subsets and storing the bounding box nodes in the first target stack is performed until the number of triangular faces in the divided target subsets is not higher than the preset number, and the currently constructed bounding box node is determined as a leaf node. The independent bounding boxes are constructed based on the spatial coordinates of the triangular facets in the leaf nodes and the first bounding box data structure. The independent bounding boxes are then merged according to the second bounding box data structure to fill the leaf nodes with the constructed target multi-branch bounding boxes, thereby obtaining a target accelerated scene structure containing the bounding box nodes.

4. The scene rendering method based on path tracing according to claim 1, characterized in that, The process of allocating corresponding pixel rendering tasks to the plurality of threads based on preset task allocation rules and local preset storage structure, and determining the corresponding task allocation amount for each round, includes: Determine the local preset storage structure and the resolution of the target scene model in the rendering information; The cache levels of the plurality of threads are divided according to the preset storage structure and the resolution, and the threads that share the same cache level are controlled to be responsible for rendering the pixels that are spatially adjacent in the target scene model. The thread number and the level number of the cache level assigned to each of the several threads are obtained based on a preset function. Based on the thread number and the level number, the spatial position of the pixel point rendering task that each of the several threads is responsible for is determined, so that the several threads can execute the pixel rendering task they are responsible for according to the pixel point spatial position. The corresponding task allocation amount for each round is determined based on the cache hierarchy of the aforementioned threads.

5. The scene rendering method based on path tracing according to claim 1, characterized in that, The process of allocating corresponding pixel rendering tasks to the plurality of threads based on preset task allocation rules and local preset storage structure includes: Determine the resolution of the target scene model in the rendering information, and determine whether the height or width of the resolution is a multiple of the amount allocated for each round of tasks; If it is determined that the height or width of the resolution is not a multiple of the task allocation amount in each round, then the irregular and regular parts in the target scene model are identified, and the irregular parts are stored in a preset atomic task pool; the irregular parts are the parts of the target scene model that are not divisible by the task allocation amount in each round; the regular parts are the parts of the target scene model that are divisible by the task allocation amount in each round. Regarding the rules section, corresponding pixel rendering tasks are assigned to the several threads based on preset task allocation rules and local preset storage structure; Accordingly, the step of rendering the number of pixels in the currently unrendered pixels corresponding to the task allocation amount in the next round according to the preset task allocation rules and preset load balancing strategy, until all the pixels to be rendered are rendered, includes: After the thread completes the corresponding pixel rendering task, the spatial position of the pixel to be rendered in the next round in the rule part is located according to the preset task allocation rule, and the located pixel is rendered. Then, the process jumps to the step of locating the spatial position of the pixel to be rendered in the next round in the rule part according to the preset task allocation rule, until the spatial position of the located pixel exceeds the height or width of the resolution. Determine the number of pixels in the irregular part of the atomic task pool, and the preset variable value corresponding to the atomic task pool for recording the number of current rendering tasks; After the spatial position of the pixel located by the thread exceeds the height or width of the resolution, the current preset variable value is compared with the number of pixels. If the current preset variable value is less than the number of pixels, the preset variable value is incremented by one, and the target pixel to be rendered in the irregular part corresponding to the preset variable value is extracted. The thread renders the target pixels to be rendered, and then jumps to the step of comparing the current preset variable value with the number of pixels until the current preset variable value equals the number of pixels.

6. The scene rendering method based on path tracing according to claim 1, characterized in that, The step of traversing the initial ray and the target acceleration scene structure to find the target hit point in the target acceleration scene structure that intersects with the initial ray and obtaining the corresponding search results includes: The initial ray is traversed with the initial nodes of the target acceleration scene structure, and during the traversal, the target child nodes of the target nodes that intersect with the initial ray are saved to the second target stack; the initial node is a child node that is directly connected to the root node in the target acceleration scene structure. The target child node is retrieved from the second target stack and used as the initial node for the next recursion. The process then jumps to the step of traversing the initial ray and the initial node of the target acceleration scene structure until the second target stack is empty. This process is used to find the target hit point in the target acceleration scene structure that intersects with the initial ray and obtain the corresponding search result. Correspondingly, the step of using the target child node as the initial node for the next recursion, and jumping to the step of traversing the initial ray and the initial node of the target acceleration scene structure until the second target stack is empty, includes: When traversing to a leaf node in the target acceleration scene structure, the triangular facet in the leaf node is intersected with the initial ray. If it is determined that it intersects with the initial ray, the leaf node that intersects with the initial ray is determined as the hit point. The time point of the hit point is compared with the time point of the currently recorded target hit point to obtain the corresponding comparison result. If the comparison result indicates that the time point of the hit point is less than the time point of the currently recorded target hit point, then the hit point is determined as the target hit point.

7. A scene rendering apparatus based on the path tracing-based scene rendering method according to any one of claims 1 to 6, characterized in that, Target processors used in MIMD architecture include: The structure construction module is used to acquire rendering information related to the target scene model to be rendered transmitted by the target host, and construct a target accelerated scene structure based on the rendering information and the target thread of the target processor; the target thread is one of the several threads of the target processor used to initialize the target accelerated scene structure; the target accelerated scene structure is a bounding box tree composed of several bounding boxes; The unit determination module is used to allocate corresponding pixel rendering tasks to the plurality of threads based on preset task allocation rules and local preset storage structure, and to determine the corresponding task allocation amount for each round; the pixel rendering task is a task that renders any one pixel of a plurality of pixels to be rendered in the target scene model, and corresponds one-to-one with the thread. The pixel rendering module is used to execute the corresponding pixel rendering tasks through the plurality of threads using preset path tracing technology, the target accelerated scene structure and the rendering information, so as to complete the rendering task of a number of pixels corresponding to the task allocation in the current round. Then, according to the preset task allocation rules and preset load balancing strategy, the number of pixels in the currently unrendered pixels corresponding to the task allocation in the next round are rendered until all the pixels to be rendered are rendered to obtain a number of rendered pixels. A pixel transmission module is used to transmit the plurality of rendered pixels to the target host, so that the target host can obtain the rendered scene for the target scene model based on the plurality of rendered pixels.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the path-tracing-based scene rendering method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the path-tracing-based scene rendering method as described in any one of claims 1 to 6.

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