Ultrasonic fingerprint chip packaging structure and packaging method thereof

Abstract

The application provides an ultrasonic fingerprint chip packaging structure and a packaging method thereof. The ultrasonic fingerprint chip packaging structure prepared by the packaging method comprises a wafer, a first surface of the wafer is provided with, from bottom to top, a bottom electrode, a piezoelectric layer, a top electrode and a protective layer, and the bottom electrode is a plurality of discontinuous partition structures; the partition structures of the bottom electrode are not electrically connected; the surfaces of the partition structures of the bottom electrode are provided with the piezoelectric layer, the top electrode and the protective layer, the top electrode is prepared by means of pulse plating combined with double-layer plating, and the protective layer completely covers all exposed surfaces of the top electrode and the piezoelectric layer; and the first surface of the wafer is further provided with a connecting column for connecting with an external circuit. The application improves the yield and service life of the chip, realizes high reliability, high performance and large-scale stable production of the ultrasonic fingerprint chip, and can be widely applied to the fields of mobile terminals, payment security and biological identification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, more particularly to an ultrasonic fingerprint chip packaging structure and a packaging method thereof. BACKGROUND

[0002] With the rapid development of biometric technology, fingerprint recognition has become the core identity verification method in mobile terminals, payment systems and security fields due to its convenience and security. The current mainstream fingerprint recognition technology mainly includes optical and capacitive types, but these traditional schemes have obvious limitations in reliability, environmental adaptability and anti-fake ability.

[0003] Optical fingerprint recognition obtains fingerprint information through optical imaging, but it can only collect the two-dimensional image of the skin surface and cannot distinguish between real fingerprints and high-imitation fake fingerprints (such as silicone film or 3D printed fingerprints), so the anti-fake ability is weak. In addition, optical sensors are extremely sensitive to stains, water stains or oil stains, and the recognition rate significantly decreases in complex environments such as wet hands and dirty hands, and even completely fails. Capacitive fingerprint recognition detects the small capacitance change between the fingerprint ridge and the sensor, but it is also limited by the surface contact quality. When the finger is dry, wet or has oil stains, the signal attenuation is serious, leading to recognition failure. The common defect of these two technologies is that they cannot penetrate the skin surface to obtain the three-dimensional detail information of the fingerprint, which limits the security and application scenarios.

[0004] To solve the above problems, ultrasonic fingerprint recognition technology has emerged, which transmits and receives ultrasonic signals to penetrate the skin surface and obtain the deep three-dimensional features of the fingerprint, significantly improving the anti-fake ability and environmental adaptability. However, the existing ultrasonic fingerprint chip still has the following technical bottlenecks in the manufacturing and packaging process:

[0005] 1. The bottom electrode of the traditional ultrasonic sensor is a single continuous structure. If the local piezoelectric layer fails due to process defects or stress concentration, the entire electrode region will lose its function, the electrode interconnection reliability is insufficient, and the device yield and service life are reduced.

[0006] 2. In the preparation of the top electrode seed layer, the conventional sputtering process has a high temperature, which easily damages the ferroelectric properties of the piezoelectric material, leading to a decrease in resonance efficiency or even functional failure.

[0007] 3. The existing top electrode mostly uses silver paste printing process, which has residual organic impurities that can cause uneven conductivity. In addition, the high flowability of silver paste leads to uncontrollable thickness, resulting in low yield. Although single-layer direct current plating can improve conductivity, it still has problems such as rough plating layer, hydrogen embrittlement and concentration polarization, affecting the mechanical strength and signal transmission stability of the electrode.

[0008] Therefore, there is an urgent need for a new ultrasonic fingerprint chip packaging method and structure to solve the problems of electrode interconnection reliability, piezoelectric layer protection, top electrode performance optimization, and packaging adaptability, so as to improve the comprehensive performance of ultrasonic fingerprint recognition. SUMMARY

[0009] To solve the above problems, the application provides an ultrasonic fingerprint chip packaging structure and a packaging method thereof, which realizes high reliability, high performance and large-scale stable production of ultrasonic fingerprint chips, and can be widely applied to mobile terminals, payment security and biometric identification fields.

[0010] In a first aspect, the application discloses an ultrasonic fingerprint chip packaging method, which comprises the following steps:

[0011] S1, providing a wafer, forming a bottom electrode and a post on a first surface of the wafer, the bottom electrode being a plurality of non-continuous partition structures; the partition structures of the bottom electrode are not electrically connected; the post comprises a bottom electrode post and a top electrode post, and the bottom electrode is electrically connected with the bottom electrode post;

[0012] S2, preparing a piezoelectric layer on the surface of the bottom electrode;

[0013] S3, preparing a top electrode on the surface of the piezoelectric layer, the top electrode being electrically connected with the top electrode post, and the top electrode being prepared by means of pulse plating combined with double-layer plating, and the specific method being as follows:

[0014] S301, sputtering a metal conductive layer on the surface of the piezoelectric layer and the post at a temperature not higher than 95 DEG C, coating a fourth photoresist on the first surface of the wafer, the fourth photoresist covering the metal conductive layer; forming a photoresist pattern with a fourth opening through an exposure and development process, the fourth opening exposing part of the metal conductive layer on the surface of the piezoelectric layer, and the metal conductive layer on the edge of the surface of the piezoelectric layer not being exposed in the fourth opening to prevent short circuit phenomenon;

[0015] S302, performing first pulse plating in the fourth opening to form a first conductive metal part;

[0016] S303, removing the fourth photoresist, re-coating a fifth photoresist, forming a photoresist pattern with a fifth opening through an exposure and development process, the fifth opening being arranged on the side of the piezoelectric layer and the first conductive metal part close to the post; performing second pulse plating in the fifth opening and on the surface of the first conductive metal part to form a second conductive metal part, the second conductive metal part enabling the first conductive metal part to be interconnected with the side of the piezoelectric layer close to the post; removing the remaining fifth photoresist and part of the metal conductive layer to complete the preparation of the top electrode;

[0017] S4, forming a protective layer on the surface of the top electrode, the protective layer completely covers the top electrode and the piezoelectric layer all exposed surfaces, forming an ultrasonic fingerprint chip package.

[0018] Preferably, in step S1, the preparation method of the bottom electrode and the post is:

[0019] S101, sputtering a metal seed layer on the first surface of the incoming wafer, forming a photoresist pattern with a first opening on the surface of the metal seed layer by coating the first photoresist, exposing and developing, the first opening exposes the surface of the metal seed layer, and the bottom electrode post and the top electrode post are formed by electroplating in the first opening;

[0020] S102, remove the first photoresist, re-coat the second photoresist, and form a photoresist pattern by second exposure and development process, the photoresist pattern has a plurality of second openings exposing the surface of the metal seed layer;

[0021] S103, remove the metal seed layer in the second opening; remove the second photoresist to obtain a plurality of discontinuous bottom electrodes;

[0022] Among them, the second opening includes a first partition opening and a second partition opening, the first partition opening is arranged on one side of the post, and there is no electrical connection between the bottom electrode post and the top electrode post, which will not short circuit; the second partition opening separates the bottom electrode into a plurality of non-continuous partition structures, and there is no electrical connection between the partition structures of the bottom electrode after removing the metal seed layer.

[0023] Preferably, in step S2, the preparation method of the piezoelectric layer is:

[0024] S201, coating a piezoelectric film material on the first surface of the incoming wafer, the piezoelectric film material covering the bottom electrode and the post;

[0025] S202, forming a photoresist pattern with a third opening on the surface of the piezoelectric film material by coating a third photoresist, exposing and developing, the third opening exposing the surface of the piezoelectric film material at the position of the first partition opening in the second opening and the post;

[0026] S203, after dry etching the piezoelectric film material exposed by the third opening, removing the excess third photoresist, forming a piezoelectric layer with a thickness of 10±2μm and a uniformity of not more than 5%.

[0027] Preferably, silane coupling agent is coated between the bottom electrode and the piezoelectric film material to increase the bonding force.

[0028] Preferably, in step S4, the preparation step of the protective layer is: forming a layer of film on all exposed surfaces of the top electrode and the piezoelectric layer by coating, exposing and developing, and curing the film by oxygen-free oven baking to form the protective layer.

[0029] Preferably, the metal seed layer and the metal conductive layer adopt the same metal material, and the same metal material has good coupling effect.

[0030] Preferably, the incoming wafer is a CMOS architecture wafer with a circuit.

[0031] In a second aspect, the application also discloses an ultrasonic fingerprint chip packaging structure prepared by the packaging method, which comprises an incoming wafer, and a bottom electrode, a piezoelectric layer, a top electrode and a protective layer are arranged on a first surface of the incoming wafer from bottom to top; the bottom electrode is in a plurality of non-continuous partition structures; the partition structures of the bottom electrode are not electrically connected; the piezoelectric layer, the top electrode and the protective layer are arranged on surfaces of the partition structures of the bottom electrode; the top electrode is prepared by means of pulse electroplating combined with double-layer electroplating; and the protective layer completely covers all exposed surfaces of the top electrode and the piezoelectric layer; and the first surface of the incoming wafer is further provided with a connecting column for connecting with an external circuit.

[0032] Compared with the prior art, the application has the following beneficial effects:

[0033] By means of the partition structure design of the bottom electrode, the piezoelectric layer is arranged on surfaces of the partition structures of the bottom electrode, so that when a problem occurs in a region of the piezoelectric layer, another region of the piezoelectric layer can still be normally used; the process and structure can solve the interconnection problem between the top electrode and the bottom electrode, avoid the loss of the whole sensor function caused by the local piezoelectric layer failure, and improve the yield and service life of the chip.

[0034] The top electrode seed layer is prepared by means of a low-temperature sputtering process (temperature ≤ 95℃), so as to avoid the damage of high temperature to the piezoelectric material and ensure the high-efficiency resonance characteristics of the piezoelectric layer.

[0035] The pulse electroplating combined with double-layer electroplating process is adopted to replace the traditional silver paste printing or single-layer direct-current electroplating, so as to solve the problems of rough plating layer, hydrogen embrittlement, concentration polarization and the like, improve the conductivity, wear resistance and adhesion of the electrode, simultaneously realize the precise thickness control, and improve the production yield. The double-layer electroplating process is used to cover the side surface of the piezoelectric layer, so as to ensure the mechanical oscillation efficiency of each layer of the resonator, support the non-contact type and multi-angle recognition, and improve the response speed and recognition accuracy.

[0036] By means of the above technical improvement, the ultrasonic fingerprint chip has high reliability, high performance and large-scale stable production, and can be widely applied to the fields of mobile terminals, payment security and biological recognition. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is a schematic diagram of an ultrasonic fingerprint chip packaging structure in the application;

[0038] Figure 2 and Figure 3The preparation process flow chart of the bottom electrode and the bottom electrode terminal post in the application;

[0039] Figure 4 The connection schematic diagram of the bottom electrode and the bottom electrode terminal post prepared on the incoming wafer is shown in the figure;

[0040] Figure 5 The preparation process flow chart of the piezoelectric layer is shown in the figure;

[0041] Figure 6 and Figure 7 The preparation process flow chart of the top electrode is shown in the figure;

[0042] Figure 8 The connection schematic diagram of the top electrode and the top electrode terminal post is shown in the figure.

[0043] Label explanation: incoming wafer 1; bottom electrode 2; piezoelectric layer 3; piezoelectric thin film material 301; top electrode 4; first conductive metal part 401; second conductive metal part 402; protective layer 5; terminal post 6; bottom electrode terminal post 601; top electrode terminal post 602; first photoresist 7; first opening 701; second photoresist 8; second opening 80; first partition opening 801; second partition opening 802; third photoresist 9; third opening 901; fourth photoresist 10; fourth opening 1001; fifth photoresist 11; fifth opening 1101; metal seed layer 12; metal conductive layer 13; connecting post 14. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application.

[0045] As shown in the figure, Figure 1 The application discloses an ultrasonic fingerprint chip packaging structure, which comprises an incoming wafer 1, and the first surface of the incoming wafer 1 is provided with, from bottom to top, a bottom electrode 2, a piezoelectric layer 3, a top electrode 4 and a protective layer 5; the bottom electrode 2 is a plurality of non-continuous partition structures; the partition structures of the bottom electrode 2 are not electrically connected; the partition structure surface of the bottom electrode 2 is provided with the piezoelectric layer 3, the top electrode 4 and the protective layer 5; the top electrode 4 is prepared by means of pulse plating combined with double-layer plating; and the protective layer 5 completely covers all exposed surfaces of the top electrode 4 and the piezoelectric layer 3; the first surface of the incoming wafer 1 is also provided with a connecting post 14, which is used for connecting with an external circuit, such as being connected with a module in a FPC soft cable manner.

[0046] The incoming wafer 1 in the application is a CMOS architecture circuit wafer.

[0047] The ultrasonic fingerprint chip packaging structure disclosed by the application has high reliability and high performance, can be mass-produced stably, and can be widely applied to mobile terminals, payment security and biological identification fields.

[0048] To realize the ultrasonic fingerprint chip packaging structure, the application further discloses an ultrasonic fingerprint chip packaging method, which comprises the following steps.

[0049] S1, a wafer 1 is provided, a bottom electrode 2 and a connecting post 6 are formed on a first surface of the wafer 1, the bottom electrode 2 is a plurality of non-continuous partition structures, and there is no electrical connection between the partition structures of the bottom electrode 2. The connecting post 6 comprises a bottom electrode connecting post 601 and a top electrode connecting post 602, and the bottom electrode 2 is electrically connected with the bottom electrode connecting post 601.

[0050] In this step, the bottom electrode 2 is innovatively arranged as a plurality of non-continuous partition structures, the surface of the partition structure of the bottom electrode 2 is provided with a piezoelectric layer 3, when a problem occurs in one area of the piezoelectric layer 3, another area of the piezoelectric layer 3 can still be used normally, this structure can solve the interconnection problem of the top electrode 4 and the bottom electrode 2, avoid the loss of the whole sensor function caused by the failure of the local piezoelectric layer 3, and improve the yield and service life of the chip.

[0051] In the specific implementation, the preparation method of the bottom electrode 2 and the connecting post 6 is as follows.

[0052] S101, a metal seed layer 12 is sputtered on the first surface of the wafer 1, a photoresist pattern with a first opening 701 is formed on the surface of the metal seed layer 12 by coating a first photoresist 7, exposing and developing, the first opening 701 exposes the surface of the metal seed layer 12, and the bottom electrode connecting post 601 and the top electrode connecting post 602 are formed by electroplating in the first opening 701; the process flow chart is as shown in Figure 2 .

[0053] The metal seed layer 12 is a 1000A titanium layer and an 8000A copper layer.

[0054] The material of the connecting post 6 is nickel, and the height of the connecting post 6 is about 4μm.

[0055] S102, the first photoresist 7 is removed, a second photoresist 8 is re-coated, a second exposure and development process are performed to form a photoresist pattern, and the photoresist pattern has a plurality of second openings 80 exposing the surface of the metal seed layer 12;

[0056] S103, the metal seed layer 12 in the second opening 80 is removed; the second photoresist 8 is removed, and a plurality of non-continuous bottom electrodes 2 are obtained; the process flow chart of S102 and S103 is as shown in Figure 3 .

[0057] The structure diagram of the second opening 80 is as shown inFigure 4 As shown, it includes a first partition opening 801 and a second partition opening 802, the first partition opening 801 is arranged on one side of the connecting post 6, so that there is no electrical connection between the bottom electrode connecting post 601 and the top electrode connecting post 602, and no short circuit. The second partition opening 802 separates the bottom electrode 2 into a plurality of non-continuous partition structures, and after removing the metal seed layer 12, there is no electrical connection between the partition structures of the bottom electrode 2. The second partition opening 802 is arranged along the periphery of the partition structure of the bottom electrode 2. Figure 4 In the middle, between the connecting posts 6, there is also an "H" shaped structure, which is a SPI communication interface. At the same time of electroplating the connecting post 6, the connecting post 14 is electroplated, which is used for connecting with external circuit.

[0058] S2, prepare a piezoelectric layer 3 on the surface of the bottom electrode 2.

[0059] Figure 5 The preparation method steps of the piezoelectric layer 3 are shown, which are specifically:

[0060] S201, coat a piezoelectric film material 301 on the first surface of the incoming wafer 1, and the piezoelectric film material 301 covers the bottom electrode 2 and the connecting post 6;

[0061] S202, form a photoresist pattern with a third opening 901 on the surface of the piezoelectric film material 301 by coating a third photoresist 9, exposing and developing process, and the third opening 901 exposes the surface of the piezoelectric film material 301 at the position of the first partition opening 801 in the second opening 80 and the connecting post 6;

[0062] S203, after dry etching the piezoelectric film material 301 exposed by the third opening 901, remove the excess third photoresist 9, and form a piezoelectric layer 3 with a thickness of 10±2μm and a uniformity of not more than 5%.

[0063] Silane coupling agent is coated between the bottom electrode 2 and the piezoelectric film material 301 to increase the bonding force.

[0064] S3, prepare a top electrode 4 on the surface of the piezoelectric layer 3, and the top electrode 4 is electrically connected with the top electrode connecting post 602, as shown in Figure 6 、 Figure 7 and Figure 8 As shown, the preparation of the top electrode 4 adopts the mode of pulse electroplating combined with double-layer electroplating, and the specific method is:

[0065] S301, sputtering a metal conductive layer 13 on the surface of the piezoelectric layer 3 and the terminal post 6 at a temperature not exceeding 95 DEG C, coating the fourth photoresist 10 on the first surface of the incoming wafer 1, the fourth photoresist 10 covering the metal conductive layer 13; forming a photoresist pattern with a fourth opening 1001 through the exposure and development process, the fourth opening 1001 exposing part of the metal conductive layer 13 on the surface of the piezoelectric layer 3, the metal conductive layer 13 on the edge of the surface of the piezoelectric layer 3 not being exposed in the fourth opening 1001, preventing the short circuit phenomenon;

[0066] S302, performing first pulse plating in the fourth opening 1001 to form a first conductive metal part 401;

[0067] S303, removing the fourth photoresist 10, re-coating the fifth photoresist 11, forming a photoresist pattern with a fifth opening 1101 through the exposure and development process, the fifth opening 1101 being arranged on the side of the piezoelectric layer 3 close to the terminal post 6 and the first conductive metal part 401; performing second pulse plating in the fifth opening 1101 and on the surface of the first conductive metal part 401 to form a second conductive metal part 402, the second conductive metal part 402 enabling the first conductive metal part 401 to be interconnected with the side of the piezoelectric layer 3 close to the terminal post 6; removing the remaining fifth photoresist 11 and part of the metal conductive layer 13, completing the preparation of the top electrode 4, that is, the first conductive metal part 401 and the second conductive metal part 402 constitute the top electrode 4.

[0068] The application adopts a low-temperature sputtering process (temperature ≤ 95 DEG C) to prepare the seed layer of the top electrode 4, avoids the damage of high temperature to the piezoelectric material, and ensures the high-efficiency resonance characteristics of the piezoelectric layer 3.

[0069] The application adopts pulse plating combined with a double-layer plating process to replace the traditional silver paste printing or single-layer direct current plating, solves the problems of rough plating layer, hydrogen embrittlement, concentration polarization and the like, improves the conductivity, wear resistance and adhesion of the electrode, simultaneously realizes precise thickness control, and improves the production yield. The double-layer plating process covers the side of the piezoelectric layer 3, ensures the mechanical oscillation efficiency of each layer of the resonator, supports non-contact, multi-angle identification, and improves the response speed and identification accuracy.

[0070] S4, forming a protective layer 5 on the surface of the top electrode 4, the protective layer 5 completely covering the top electrode 4 and all exposed surfaces of the piezoelectric layer 3, forming an ultrasonic fingerprint chip package.

[0071] In step S4, the preparation steps of the protective layer 5 are as follows: forming a film on the top electrode 4 and all exposed surfaces of the piezoelectric layer 3 by means of gluing, exposure and development, baking the film in an oxygen-free oven to solidify, and finally forming the protective layer 5 as shown in Figure 1 .

[0072] In the application, the metal seed layer 12 and the metal conductive layer 13 adopt the same metal material, and the same metal material has good coupling effect.

[0073] The above merely describes some embodiments of the present application, and it should be noted that, for those skilled in the art, other modifications and improvements can be made without departing from the inventive concept of the present application, and these all fall within the protection scope of the present application.

Claims

1. A method of ultrasonic fingerprint chip packaging, characterized by, The method comprises the following steps: S1, providing a wafer, forming a bottom electrode and a post on a first surface of the wafer, the bottom electrode being a plurality of non-continuous partition structures, and there being no electrical connection between the partition structures of the bottom electrode; the post comprising a bottom electrode post and a top electrode post, and the bottom electrode being electrically connected with the bottom electrode post; S2, preparing a piezoelectric layer on the surface of the bottom electrode; S3, preparing a top electrode on the surface of the piezoelectric layer, the top electrode being electrically connected with the top electrode post, and the top electrode being prepared by means of pulse plating combined with double-layer plating, and the specific method being as follows: S301, sputtering a metal conductive layer on the surfaces of the piezoelectric layer and the post at a temperature not exceeding 95 DEG C, coating a fourth photoresist on the first surface of the wafer, the fourth photoresist covering the metal conductive layer; forming a photoresist pattern with a fourth opening by means of exposure and development process, the fourth opening exposing part of the metal conductive layer on the surface of the piezoelectric layer, and the metal conductive layer on the edge of the surface of the piezoelectric layer not being exposed in the fourth opening, so as to prevent short circuit phenomenon; S302, performing first pulse plating in the fourth opening to form a first conductive metal part; S303, removing the fourth photoresist, re-coating a fifth photoresist, forming a photoresist pattern with a fifth opening by means of exposure and development process, the fifth opening being arranged on the side of the piezoelectric layer close to the post and the first conductive metal part; performing second pulse plating in the fifth opening and on the surface of the first conductive metal part to form a second conductive metal part, the second conductive metal part enabling the first conductive metal part to be interconnected with the side of the piezoelectric layer close to the post; removing the remaining fifth photoresist and part of the metal conductive layer, and completing the preparation of the top electrode; S4, forming a protective layer on the surface of the top electrode, the protective layer completely covering the top electrode and all exposed surfaces of the piezoelectric layer, and forming an ultrasonic fingerprint chip package.

2. The packaging method according to claim 1, characterized in that, In step S1, the preparation method of the bottom electrode and the post is as follows: S101, sputtering a metal seed layer on the first surface of the wafer, coating a first photoresist on the surface of the metal seed layer, forming a photoresist pattern with a first opening by means of exposure and development process, the first opening exposing the surface of the metal seed layer, and performing electroplating in the first opening to form a bottom electrode post and a top electrode post; S102, removing the first photoresist, re-coating a second photoresist, and performing second exposure and development process to form a photoresist pattern, the photoresist pattern having a plurality of second openings exposing the surface of the metal seed layer; S103, removing the metal seed layer in the second openings; removing the second photoresist to obtain a plurality of non-continuous bottom electrodes; The second openings comprise a first partition opening and a second partition opening, the first partition opening being arranged on one side of the post, and there being no electrical connection between the bottom electrode post and the top electrode post, so as to prevent short circuit; the second partition opening separating the bottom electrode into a plurality of non-continuous partition structures, and there being no electrical connection between the partition structures of the bottom electrode after the metal seed layer is removed.

3. The packaging method according to claim 2, wherein, In step S2, the preparation method of the piezoelectric layer is as follows: S201, coating a piezoelectric thin film material on the first surface of the wafer, the piezoelectric thin film material covering the bottom electrode and the post; S202, a third photoresist is coated on the surface of the piezoelectric film material, and a photoresist pattern with a third opening is formed through an exposure and development process, the third opening exposes the surface of the piezoelectric film material at the position of the first partition opening in the second opening and the connecting post; S203, after dry etching the piezoelectric film material exposed by the third opening, the excess third photoresist is removed to form a piezoelectric layer with a thickness of 10±2 μm and a uniformity of not more than 5%.

4. The packaging method according to claim 3, wherein, Silane coupling agent is coated between the bottom electrode and the piezoelectric film material to increase the bonding force.

5. The packaging method according to claim 4, characterized in that, In step S4, the preparation of the protective layer is as follows: a film is formed on the top electrode and the exposed surface of the piezoelectric layer by means of glue coating, exposure and development, and the film is cured by an oxygen-free oven to finally form the protective layer.

6. The packaging method according to claim 5, characterized in that, The metal seed layer and the metal conductive layer are made of the same metal material.

7. The packaging method of claim 1, wherein, The incoming wafer is a CMOS architecture wafer with circuit.

8. The packaging method of claim 1, wherein, The first surface of the incoming wafer is also provided with a connecting post for connecting with an external circuit.

9. An ultrasonic fingerprint chip package structure, characterized in that, The ultrasonic fingerprint chip packaging structure is prepared by the packaging method of any one of claims 1-8, and the ultrasonic fingerprint chip packaging structure comprises an incoming wafer, the first surface of the incoming wafer is provided from bottom to top with a bottom electrode, a piezoelectric layer, a top electrode and a protective layer, the bottom electrode is a plurality of non-continuous partition structures; the partition structures of the bottom electrode are not electrically connected; the surfaces of the partition structures of the bottom electrode are provided with the piezoelectric layer, the top electrode and the protective layer, the top electrode is prepared by means of pulse electroplating combined with double-layer electroplating, and the protective layer completely covers all exposed surfaces of the top electrode and the piezoelectric layer; the first surface of the incoming wafer is also provided with a connecting post for connecting with an external circuit. The ultrasonic fingerprint chip packaging structure is prepared by the packaging method of any one of claims 1-8, and the ultrasonic fingerprint chip packaging structure comprises an incoming wafer, the first surface of the incoming wafer is provided from bottom to top with a bottom electrode, a piezoelectric layer, a top electrode and a protective layer, the bottom electrode is a plurality of non-continuous partition structures; the partition structures of the bottom electrode are not electrically connected; the surfaces of the partition structures of the bottom electrode are provided with the piezoelectric layer, the top electrode and the protective layer, the top electrode is prepared by means of pulse electroplating combined with double-layer electroplating, and the protective layer completely covers all exposed surfaces of the top electrode and the piezoelectric layer; the first surface of the incoming wafer is also provided with a connecting post for connecting with an external circuit.

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