Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a first semiconductor contact layer, a second semiconductor contact layer and a first electrode layer. A first surface of the first semiconductor contact layer comprises a plurality of connected step surfaces, the step surfaces comprising connected main surfaces and connecting surfaces. A main surface of one step surface is connected with a connecting surface of an adjacent step surface. The second semiconductor contact layer is in contact with the main surfaces, and the second semiconductor contact layer has nanoscale grooves above the main surfaces. The nanoscale grooves are located at corners formed by the main surface of one step surface and the connecting surface of another step surface. The first electrode layer is located on a side of the second semiconductor contact layer away from the first semiconductor contact layer and extends into the nanoscale grooves.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN)-based light-emitting diodes (LEDs), a third-generation semiconductor material, have been widely used in lighting and display fields. GaN-based LEDs in white lighting, LED rear-projection televisions, and micro-LED displays have all revolutionized their respective industries. Meanwhile, GaN-based semiconductor lasers, with their more complex epitaxial structures, possess advantages such as good monochromaticity, high efficiency, high power density, good directionality, low cost, and small size, making them even more promising for applications in laser projection displays, laser lighting, and industrial laser processing. However, semiconductor lasers operate under high current injection conditions, which places higher demands on their contact resistance. Summary of the Invention

[0003] This invention provides a semiconductor structure including a first semiconductor contact layer, a second semiconductor contact layer, and a first electrode layer; wherein, a first surface of the first semiconductor contact layer includes a plurality of connected stepped surfaces, each stepped surface including a connected main surface and a connecting surface; the main surface of one stepped surface is connected to the connecting surface of an adjacent stepped surface; wherein, the second semiconductor contact layer is in contact with the main surface, and the second semiconductor contact layer has a nanogroove located above the main surface; the nanogroove is located at a corner formed by the main surface of one stepped surface and the connecting surface of another stepped surface; wherein, the first electrode layer is located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extends into the nanogroove.

[0004] Optionally, the stepped surface extends along a first direction, and adjacent stepped surfaces are arranged along a second direction, which intersects with the first direction; the dimension of the main surface along the first direction is greater than the dimension of the main surface along the second direction; wherein, at least a portion of the nanogrooves have a dimension along the first direction that is greater than twice the dimension of the nanogrooves along the second direction.

[0005] Optionally, at least a portion of the nanogrooves have a dimension of 1 nm to 500 nm along the first direction and a dimension of 1 nm to 200 nm along the second direction.

[0006] Optionally, the thickness of the second semiconductor contact layer along a third direction is 1nm to 10nm, where the third direction is the arrangement direction from the first semiconductor contact layer to the second semiconductor contact layer.

[0007] Optionally, the ratio of the area of ​​the end of the nanogroove facing the main surface to the first surface is greater than or equal to 10% and less than or equal to 90%.

[0008] Optionally, the material of the first semiconductor contact layer is Al. m1 Ga 1-m1 N, 0≤m1≤0.75; the material of the second semiconductor contact layer is In. m2 Ga 1-m2 N, 0.01 <m2<0.5。

[0009] Optionally, the chamfer angle θ of the first surface is greater than 0° and less than or equal to 1°.

[0010] Optionally, the semiconductor structure further includes a substrate layer located on the side of the first semiconductor contact layer away from the second semiconductor contact layer; the surface of the substrate layer facing the first semiconductor contact layer has a chamfer angle θ greater than 0° and less than or equal to 1°.

[0011] Optionally, at least a portion of the stepped surfaces have a height of less than or equal to 5 nm along a third direction and a width of less than or equal to 500 nm along a second direction; wherein the third direction is the arrangement direction from the first semiconductor contact layer to the second semiconductor contact layer, and the second direction is the arrangement direction of adjacent stepped surfaces.

[0012] Optionally, in a cross section perpendicular to the third direction, at any 10*10µm... 2 Within the cross-sectional area of ​​the range, more than or equal to half of the stepped surfaces have a height of less than or equal to 5 nm along the third direction and a width of less than or equal to 500 nm along the second direction.

[0013] Optionally, the lattice constant of the second semiconductor contact layer is different from that of the first semiconductor contact layer.

[0014] Optionally, it further includes: a first confinement layer, a first waveguide layer, an active layer, a second waveguide layer, and a second confinement layer stacked together; wherein, the first semiconductor contact layer is located on the side of the second confinement layer opposite to the second waveguide layer; and the second semiconductor contact layer is located on the side of the first semiconductor contact layer opposite to the second confinement layer.

[0015] This application also provides a method for fabricating a semiconductor structure, comprising: forming a first semiconductor contact layer; a first surface of the first semiconductor contact layer including a plurality of connected stepped surfaces, the stepped surfaces including a connected main surface and a connecting surface; the main surface of one of the stepped surfaces being connected to the connecting surface of an adjacent stepped surface; forming a second semiconductor contact layer, the second semiconductor contact layer being in contact with the main surface, the second semiconductor contact layer having a nanogroove located above the main surface; the nanogroove being located at a corner formed by the main surface of one stepped surface and the connecting surface of another stepped surface; forming a first electrode layer, the first electrode layer being located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extending into the nanogroove.

[0016] Optionally, forming the first semiconductor contact layer includes: forming the first semiconductor contact layer by step flow epitaxial growth on one side of a substrate layer; the surface of the substrate layer has a chamfer angle θ, the chamfer angle θ being greater than 0° and less than or equal to 1°; wherein the first semiconductor contact layer, away from the first surface of the substrate layer, includes a plurality of connected step surfaces; or, forming the first semiconductor contact layer includes: forming a first initial semiconductor contact layer; grinding and polishing the first initial surface of the first initial semiconductor contact layer to form the first semiconductor contact layer, and making the first initial surface form the first surface.

[0017] Optionally, forming the second semiconductor contact layer includes: performing a first stage and a second stage sequentially; in the first stage, introducing a group III gas source and a group V gas source into the epitaxial chamber to form a second initial semiconductor contact layer on the first surface; in the second stage, stopping the introduction of the group III gas source and introducing a decomposition gas containing H into the epitaxial chamber, the decomposition gas decomposes the portion of the second initial semiconductor contact layer located at the corner formed by the main surface of one step surface and the connecting surface of the other step surface, so that the second initial semiconductor contact layer forms a second semiconductor contact layer with nanogrooves.

[0018] Optionally, the temperature of the second stage is greater than or equal to 550°C.

[0019] Optionally, the average temperature of the second stage is lower than the average temperature of the first stage.

[0020] The present invention has the following technical effects:

[0021] The semiconductor structure provided by this invention includes a second semiconductor contact layer with nanogrooves. A first electrode layer is located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extends into the nanogrooves. The first electrode layer can contact not only the areas of the second semiconductor contact layer without nanogrooves, but also the inner wall of the nanogrooves, increasing the contact area between the first electrode layer and the second semiconductor contact layer and reducing the contact resistance. Since the first surface of the first semiconductor contact layer includes multiple connected stepped surfaces, the second semiconductor contact layer is formed based on this first surface. During the formation of the second semiconductor contact layer, a heat treatment involving gas decomposition is performed, allowing nanogrooves to be formed at the corner formed by the main surface of the stepped surface and the connecting surface of another stepped surface. The entire process can be directly completed during the epitaxial growth of the semiconductor stack without the need for additional, complex etching processes.

[0022] In the semiconductor structure fabrication method provided by this invention, a second semiconductor contact layer with nanogrooves is formed. A first electrode layer is formed, located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extending into the nanogrooves. The first electrode layer can contact not only the areas of the second semiconductor contact layer without nanogrooves, but also the inner wall of the nanogrooves, increasing the contact area between the first electrode layer and the second semiconductor contact layer and reducing the contact resistance. Furthermore, since the first surface of the first semiconductor contact layer includes multiple connected stepped surfaces, the second semiconductor contact layer is formed based on this first surface. During the formation of the second semiconductor contact layer, a heat treatment of the decomposed gas is performed, allowing nanogrooves to be formed at the corner formed by the main surface of the stepped surface and the connecting surface of another stepped surface. The entire process can be directly completed during the epitaxial growth of the semiconductor stack without the need for additional, complex etching processes. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0025] Figure 2 for Figure 1 A schematic diagram of the structure of the first semiconductor contact layer;

[0026] Figure 3 This is a schematic diagram of the structure of the first semiconductor contact layer and the second semiconductor contact layer;

[0027] Figure 4 A schematic diagram of a semiconductor structure provided in another embodiment of the present invention;

[0028] Figure 5 This is an atomic force microscopy image of the surface of the second semiconductor contact layer. Detailed Implementation

[0029] A method for fabricating a semiconductor structure increases the contact area and thus reduces contact resistance by altering the surface morphology of the contact layer. This is primarily achieved by creating a certain degree of roughness on the contact layer surface to increase the contact area between the contact layer and the front electrode. The roughness of the contact layer surface is typically achieved using methods such as wet etching or dry etching. After depositing the front electrode, processes such as thermal annealing are used to create a good ohmic contact between these nanostructures and the front electrode, thereby reducing contact resistance.

[0030] However, the above-mentioned technical solutions have some problems, often requiring complex process control and resulting in high costs. In addition, increased surface roughness of the contact layer may affect the internal structure of the contact layer, potentially impacting other properties of the semiconductor structure, such as the light output efficiency and current injection efficiency when the semiconductor structure is a light-emitting structure.

[0031] The technical problem that needs to be solved is how to effectively reduce the contact resistance between the contact layer and the front electrode without using complex process steps, while avoiding affecting the internal structure of the contact layer to ensure other properties of the semiconductor structure.

[0032] To address the aforementioned issues, the present invention provides a semiconductor structure and its fabrication method, which effectively reduces the contact resistance between the contact layer and the front electrode without using complex process steps, while avoiding any impact on the internal structure of the contact layer to ensure other performance characteristics of the semiconductor structure.

[0033] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0036] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] One embodiment of the present invention provides a semiconductor structure, with reference to Figure 1 , Figure 2 and Figure 3 It includes a first semiconductor contact layer 301, a second semiconductor contact layer 302 and a first electrode layer 305.

[0038] The first surface of the first semiconductor contact layer 301 includes a plurality of connected step surfaces 3013, each step surface 3013 including a connected main surface 3011 and a connecting surface 3012; the main surface 3011 of one step surface 3013 is connected to the connecting surface 3012 of the adjacent step surface 3013.

[0039] The second semiconductor contact layer 302 is in contact with the main surface 3011, and the second semiconductor contact layer 302 has a nanogroove 3021 located above the main surface; the nanogroove 3021 is located at the corner formed by the connection surface 3012 of the main surface 3011 of one step surface 3013 and the connection surface 3012 of another step surface 3013.

[0040] The first electrode layer 305 is located on the side of the second semiconductor contact layer 302 away from the first semiconductor contact layer 301 and extends into the nanogroove 3021.

[0041] In this embodiment, the second semiconductor contact layer 302 has nanogrooves 3021, and the first electrode layer 305 is located on the side of the second semiconductor contact layer 302 away from the first semiconductor contact layer 301 and extends into the nanogrooves 3021. The first electrode layer 305 can contact not only the area of ​​the second semiconductor contact layer 302 without nanogrooves 3021, but also the inner wall of the nanogrooves 3021, increasing the contact area between the first electrode layer 305 and the second semiconductor contact layer 302 and reducing the contact resistance. Since the first surface of the first semiconductor contact layer 301 includes multiple connected stepped surfaces 3013, the second semiconductor contact layer 302 is formed based on the first surface including multiple connected stepped surfaces 3013. During the formation of the second semiconductor contact layer 302, the heat treatment of the decomposed gas is carried out, and the nanogrooves 3021 can be formed at the corner formed by the main surface 3011 of the stepped surface 3013 and the connecting surface of another stepped surface 3013. The whole process can be directly completed during the epitaxial growth of the semiconductor stack without additional and complex etching processes.

[0042] The differences between the main surface 3011 and the connecting surface 3012 include: the inclination of the main surface 3011 is greater than that of the connecting surface 3012 relative to the side of the first semiconductor contact layer 301 that is away from the second semiconductor contact layer 302; and the area of ​​the main surface 3011 in any step surface 3013 is greater than the area of ​​the connecting surface 3012.

[0043] In some embodiments, the lattice constant of the second semiconductor contact layer 302 is different from that of the first semiconductor contact layer 301.

[0044] In one specific embodiment, the lattice constant of the second semiconductor contact layer is less than that of the first semiconductor contact layer. In another specific embodiment, the lattice constant of the second semiconductor contact layer 302 is greater than that of the first semiconductor contact layer.

[0045] In some embodiments, the stepped surface 3013 extends along a first direction, and adjacent stepped surfaces are arranged along a second direction X, which intersects with the first direction; the dimension of the main surface 3011 along the first direction is larger than the dimension of the main surface 3011 along the second direction X. That is, the main surface 3011 is elongated, and there are no multiple stepped surfaces 3013 arranged in the first direction. At least a portion of the nanogrooves 3021 have a dimension along the first direction that is more than twice the dimension of the nanogrooves 3021 along the second direction X, and the nanogrooves 3021 are strip-shaped nanogrooves.

[0046] The first direction intersects the second direction X, for example, the first direction is perpendicular to the second direction X.

[0047] In some embodiments, at least a portion of the nanogrooves 3021 have a dimension of 1 nm to 500 nm along a first direction and a dimension of 1 nm to 200 nm along a second direction X. The nanogrooves 3021 have a dimension of 1 nm to 500 nm along the first direction, for example, 3 nm, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, or 500 nm. The nanogrooves 3021 have a dimension of 1 nm to 200 nm along the second direction X, for example, 1 nm, 10 nm, 50 nm, 100 nm, or 200 nm.

[0048] In some embodiments, the thickness of the second semiconductor contact layer 302 along the third direction Z is 1nm to 10nm, for example 1nm, 3nm, 5nm, 7nm or 10nm.

[0049] The third direction Z is the arrangement direction from the first semiconductor contact layer 301 to the second semiconductor contact layer 302.

[0050] The third direction Z intersects the first direction and the second direction X. For example, the third direction Z is perpendicular to the first direction and the second direction X.

[0051] In some embodiments, the nanogrooves 3021, which account for 90% or more of the total number of nanogrooves, have a size of 1 nm to 500 nm along the first direction and a size of 1 nm to 200 nm along the second direction X.

[0052] In some embodiments, the ratio of the area of ​​the end of the nanogroove 3021 facing the main surface 3011 to the first surface is greater than or equal to 10% and less than or equal to 90%. If the ratio of the area of ​​the end of the nanogroove 3021 facing the main surface 3011 to the first surface is too small, the area of ​​the region where the nanogroove 3021 is located is small, and the area of ​​the sidewall surface of the nanogroove 3021 is small, then the effect of improving the ohmic contact is weak. If the ratio of the area of ​​the end of the nanogroove 3021 facing the main surface 3011 to the first surface is too large, the area of ​​the region where the nanogroove 3021 is located is too large, the area of ​​the first semiconductor contact layer 301 exposed by the nanogroove 3021 is too large, and the area of ​​the sidewall surface of the nanogroove 3021 is too small, then the effect of improving the ohmic contact is also not significant. Preferably, the ratio of the area of ​​the end of the nanogroove 3021 facing the main surface 3011 to the first surface is greater than or equal to 10% and less than or equal to 50%. More preferably, the ratio of the area of ​​the end of the nanogroove 3021 facing the main surface 3011 to the first surface is greater than or equal to 10% and less than or equal to 30%.

[0053] In some embodiments, the material of the first semiconductor contact layer 301 is Al. m1 Ga 1-m1 N, where 0 ≤ m1 ≤ 0.75; the material of the second semiconductor contact layer 302 is In.m2 Ga 1-m2 N, where 0.01 < m2 < 0.5. In other embodiments, the materials of the first semiconductor contact layer 301 and the second semiconductor contact layer 302 are not limited.

[0054] In some embodiments, the chamfer angle θ of the first surface is greater than 0° and less than or equal to 1°. Tan (chamfer angle θ) = D / L. L is the dimension of the main surface 3011 along the second direction X, and D is the height of the main surface 3011 along the third direction Z. The height of the main surface 3011 along the third direction Z is: the distance between the bottom end and the top end of the main surface 3011 along the third direction Z.

[0055] In some embodiments, referring to Figure 4 , the semiconductor structure further includes a substrate layer, and the substrate layer is located on a side of the first semiconductor contact layer 301 away from the second semiconductor contact layer 302; the surface of the substrate layer facing the first semiconductor contact layer 301 has a chamfer angle θ greater than 0° and less than or equal to 1°.

[0056] In other embodiments, the surface of the substrate layer facing the first semiconductor contact layer 301 has no chamfer angle θ.

[0057] In some embodiments, the height of at least a portion of the step surfaces 3013 along the third direction Z is less than or equal to 5 nm and the width along the second direction X is less than or equal to 500 nm. Wherein, the third direction Z is the arrangement direction from the first semiconductor contact layer to the second semiconductor contact layer, and the second direction X is the arrangement direction of adjacent step surfaces 3013.

[0058] In some embodiments, in a cross-section perpendicular to the third direction Z, within a cross-sectional area of any 10 * 10 um 2 range, the height of greater than or equal to half of the step surfaces 3013 along the third direction Z is less than or equal to 5 nm and the width along the second direction X is less than or equal to 500 nm.

[0059] In other embodiments, in a cross-section perpendicular to the third direction Z, the height of all the step surfaces 3013 along the third direction Z is less than or equal to 5 nm and the width along the second direction X is less than or equal to 500 nm.

[0060] In some embodiments, the first semiconductor contact layer 301 is doped with first conductive ions, and the first conductive ions are uniformly doped in the first semiconductor contact layer 301. Further, the doping concentration of the first conductive ions in the first semiconductor contact layer 301 is 1E18 atoms / cm 3 ~3E21 atoms / cm3 .

[0061] The first conducting ion includes Mg ions.

[0062] In other embodiments, the first semiconductor contact layer 301 is doped with first conductive ions, which are non-uniformly doped in the first semiconductor contact layer 301; further, the doping concentration of the first semiconductor contact layer 301 in at least a portion of the region is greater than or equal to 1E20 atoms / cm². 3 And less than or equal to 9E21 atoms / cm 3 The doping concentration of the first conductive ion in the first semiconductor contact layer 301 is 1E18 atoms / cm². 3 ~9E21atoms / cm 3 .

[0063] In some embodiments, the second semiconductor contact layer 302 is doped with a second conductive ion.

[0064] The second conducting ion and the first conducting ion have the same conductivity type. For example, both the second and first conducting ions are N-type, or both are P-type.

[0065] In one embodiment, the doping concentration of the second conductive ion is greater than the doping concentration of the first conductive ion. In other embodiments, the doping concentration of the second conductive ion is equal to the doping concentration of the first conductive ion.

[0066] In one embodiment, the first electrode layer 305 is a metal electrode layer, such as Ti, Pt, Au, Ni, Co, Pb, Ag, or Cu. In another embodiment, the first electrode layer 305 is a transparent oxide conductive layer, such as indium tin oxide (ITO), fluorine-doped tin oxide (FTO), AZO (aluminum-doped zinc oxide), SnO2:Sb, CdIn2O4, Cd2SnO4, ZnSnO3, Zn2SnO4, MgIn2O4, Zn2In2O5, GaInO3, or In4Sn3O4. 12 .

[0067] refer to Figure 4 The semiconductor structure is a semiconductor laser. The semiconductor structure also includes: a first confinement layer 100, a first waveguide layer 110, an active layer 200, a second waveguide layer 304, and a second confinement layer 303 stacked together; wherein, the first semiconductor contact layer 301 is located on the side of the second confinement layer 303 opposite to the second waveguide layer 304; and the second semiconductor contact layer 302 is located on the side of the first semiconductor contact layer 301 opposite to the second confinement layer 303.

[0068] Because this invention can effectively reduce contact resistance, it improves the overall performance of the semiconductor structure, such as current injection efficiency and luminous efficiency, resulting in better performance of the semiconductor structure.

[0069] The conductivity type of the first confinement layer 100 is opposite to that of the second confinement layer 303.

[0070] In one embodiment, the first confinement layer 100 has an n-type conductivity and the second confinement layer 303 has a p-type conductivity.

[0071] The conductivity type of the first waveguide layer 110 is opposite to that of the second waveguide layer 304.

[0072] In one embodiment, the first waveguide layer 110 has an n-type conductivity and the second waveguide layer 304 has a p-type conductivity.

[0073] The first confinement layer 100 and the first waveguide layer 110 have the same conductivity type, and the second confinement layer 303 and the second waveguide layer 304 have the same conductivity type.

[0074] The second confinement layer 303, the first semiconductor contact layer 301, and the second semiconductor contact layer 302 have the same conductivity type.

[0075] In one embodiment, the refractive index of the first semiconductor contact layer 301 is less than or equal to the refractive index of the second confinement layer 303.

[0076] In one embodiment, the material of the second confinement layer 303 includes p-type Al. x2 Ga 1-x2 N. The material of the first semiconductor contact layer 301 is Al. m1 Ga 1-m1 N.

[0077] In one embodiment, m1 is less than x2.

[0078] In this embodiment, the substrate layer is located on the side of the first confinement layer 100 away from the first waveguide layer 110; the semiconductor structure also includes a second electrode layer (not shown), which is located on the side of the substrate layer away from the first confinement layer 100.

[0079] In one embodiment, the semiconductor structure has a front cavity surface and a rear cavity surface disposed opposite to each other; the semiconductor structure further includes an antireflective coating located on the front cavity surface and a reflective coating located on the rear cavity surface.

[0080] refer to Figure 5 Whether the required second semiconductor contact layer 302 has formed can be observed using an atomic force microscope.

[0081] Another embodiment of this application provides a method for fabricating a semiconductor structure, characterized in that it includes:

[0082] A first semiconductor contact layer is formed; the first surface of the first semiconductor contact layer includes a plurality of connected stepped surfaces, each stepped surface including a connected main surface and a connecting surface; the main surface of one stepped surface is connected to the connecting surface of an adjacent stepped surface;

[0083] A second semiconductor contact layer is formed, which contacts the main surface. The second semiconductor contact layer has a nanogroove located above the main surface. The nanogroove is located at the corner formed by the connecting surface of one of the stepped surfaces and the connecting surface of the other stepped surface.

[0084] A first electrode layer is formed, which is located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extends into the nanogroove.

[0085] Since the first surface of the first semiconductor contact layer includes multiple connected stepped surfaces, a second semiconductor contact layer is formed based on this first surface. During the formation of the second semiconductor contact layer, a heat treatment involving gas decomposition is performed, allowing nanogrooves to be formed at the corner formed by the main surface of one stepped surface and the connecting surface of another stepped surface. This entire process can be directly completed during the epitaxial growth of the semiconductor stack without the need for additional, complex etching processes. After forming the nanogrooves, the first electrode layer can also contact the inner wall of the nanogrooves, increasing the contact area between the first electrode layer and the second semiconductor contact layer and reducing the contact resistance.

[0086] In one embodiment, forming a first semiconductor contact layer includes: forming a first semiconductor contact layer by step flow epitaxial growth on one side of a substrate layer; the surface of the substrate layer has a chamfer angle θ, the chamfer angle θ being greater than 0° and less than or equal to 1°; wherein the first semiconductor contact layer, away from the first surface of the substrate layer, includes a plurality of connected step surfaces.

[0087] In another embodiment, forming the first semiconductor contact layer includes: forming a first initial semiconductor contact layer; grinding and polishing a first initial surface of the first initial semiconductor contact layer to form the first semiconductor contact layer, and making the first initial surface form the first surface.

[0088] In one embodiment, the process of forming the second semiconductor contact layer includes an epitaxial growth process, wherein the epitaxial growth process is performed using an epitaxial growth chamber.

[0089] The epitaxial process for forming the second semiconductor contact layer includes MOCVD epitaxial process or MBE epitaxial growth.

[0090] In one embodiment, forming a second semiconductor contact layer includes: sequentially performing a first stage and a second stage; in the first stage, introducing a group III gas source and a group V gas source into the epitaxial chamber to form a second initial semiconductor contact layer on a first surface; in the second stage, stopping the introduction of the group III gas source and introducing a decomposition gas containing H into the epitaxial chamber, the decomposition gas decomposes the portion of the second initial semiconductor contact layer located at the corner formed by the main surface of one step surface and the connecting surface of the other step surface, so that the second initial semiconductor contact layer forms a second semiconductor contact layer with nanogrooves.

[0091] In one embodiment, forming the second semiconductor contact layer includes performing a second stage followed by a third stage, wherein the third stage is a cooling stage.

[0092] The first and second stages were carried out in the same epitaxial growth chamber.

[0093] Due to the potential energy difference between the main surface and the connecting surface of adjacent step surfaces at the corner, the decomposition of the second initial semiconductor contact layer by the decomposition gas is more likely to occur at the corner formed by the main surface of one step surface and the connecting surface of the other step surface. Therefore, by controlling the decomposition conditions, nanogrooves can be formed at the corner while retaining a portion of the second initial semiconductor contact layer on the main surface. This eliminates the need for complex process steps, greatly simplifying the production process and reducing production costs. Thus, the size and surface area ratio of the nanogrooves can be controlled by utilizing the morphology of the step surface.

[0094] In one embodiment, the temperature of the second stage is greater than or equal to 550°C.

[0095] In one embodiment, the average temperature of the second stage is lower than the average temperature of the first stage. The second stage is part of the cooling stage of the process for forming the second semiconductor contact layer. This helps to shorten the process time.

[0096] In this embodiment, nanogrooves are formed during the epitaxial growth process of the second semiconductor contact layer. The formation of nanogrooves does not require additional dry or wet etching, thus avoiding etching damage to the internal structure of the first and second semiconductor contact layers, and also avoiding the influence of surface states formed during the etching process on the ohmic contact.

[0097] In one specific embodiment, in the first stage, a group III gas source and a group V gas source are introduced into the epitaxial chamber to form a second initial semiconductor contact layer on the first surface. The group III gas source includes a Ga source and an In source, and the group V gas source includes an N source. In the second stage, the introduction of the Ga source and the In source is stopped, and a decomposition gas containing H is introduced into the epitaxial chamber. The decomposition gas containing H includes any one or a combination of two of NH3 and H2, and the decomposition gas containing H is introduced at a temperature not lower than 550°C. After that, the third stage is performed.

[0098] In one embodiment, the semiconductor structure is a semiconductor laser. Forming the semiconductor structure further includes forming a stacked first confinement layer 100, a first waveguide layer 110, an active layer 200, a second waveguide layer 304, and a second confinement layer 303. Exemplarily, the stacked first confinement layer 100, first waveguide layer 110, active layer 200, second waveguide layer 304, and second confinement layer 303 are formed on one side of a substrate layer. Forming the first semiconductor contact layer 301 includes forming the first semiconductor contact layer 301 on the side of the second confinement layer 303 opposite to the second waveguide layer 304. Forming the second semiconductor contact layer 302 includes forming the second semiconductor contact layer 302 on the side of the first semiconductor contact layer 301 opposite to the second confinement layer 303.

[0099] The description of the first semiconductor contact layer and the second semiconductor contact layer is the same as that of the foregoing embodiments and will not be repeated in detail.

[0100] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor structure, characterized in that, It includes a first semiconductor contact layer, a second semiconductor contact layer, and a first electrode layer; Wherein, the first surface of the first semiconductor contact layer includes a plurality of connected stepped surfaces, each stepped surface including a connected main surface and a connecting surface; the main surface of one stepped surface is connected to the connecting surface of an adjacent stepped surface; The second semiconductor contact layer is in contact with the main surface, and the second semiconductor contact layer has a nanogroove located above the main surface; the nanogroove is located at the corner formed by the connecting surface of one of the stepped surfaces and the connecting surface of the other stepped surface; The first electrode layer is located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extends into the nanogroove.

2. The semiconductor structure according to claim 1, characterized in that, The stepped surface extends along a first direction, and adjacent stepped surfaces are arranged along a second direction, which intersects with the first direction; the dimension of the main surface along the first direction is greater than the dimension of the main surface along the second direction. In this configuration, at least a portion of the nanogrooves have a dimension along the first direction that is more than twice the dimension along the second direction.

3. The semiconductor structure according to claim 2, characterized in that, At least a portion of the nanogrooves have dimensions of 1 nm to 500 nm along the first direction and 1 nm to 200 nm along the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the second semiconductor contact layer along a third direction is 1nm to 10nm, where the third direction is the arrangement direction from the first semiconductor contact layer to the second semiconductor contact layer.

5. The semiconductor structure according to claim 1, characterized in that, The ratio of the area of ​​the end of the nanogroove facing the main surface to the first surface is greater than or equal to 10% and less than or equal to 90%.

6. The semiconductor structure according to claim 1, characterized in that, The material of the first semiconductor contact layer is Al m1 Ga 1-m1 N, 0≤m1≤0.75; the material of the second semiconductor contact layer is In. m2 Ga 1-m2 N, 0.01 <m2<0.5。 7. The semiconductor structure according to claim 1, characterized in that, The bevel angle θ of the first surface is greater than 0° and less than or equal to 1°.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a substrate layer located on the side of the first semiconductor contact layer away from the second semiconductor contact layer; the surface of the substrate layer facing the first semiconductor contact layer has a chamfer angle θ greater than 0° and less than or equal to 1°.

9. The semiconductor structure according to claim 1, characterized in that, At least a portion of the stepped surfaces have a height of less than or equal to 5 nm along a third direction and a width of less than or equal to 500 nm along a second direction; Wherein, the third direction is the arrangement direction from the first semiconductor contact layer to the second semiconductor contact layer, and the second direction is the arrangement direction of the adjacent step surfaces.

10. The semiconductor structure according to claim 9, characterized in that, In a cross section perpendicular to the third direction, at any 10*10µm 2 Within the cross-sectional area of ​​the range, more than or equal to half of the stepped surfaces have a height of less than or equal to 5 nm along the third direction and a width of less than or equal to 500 nm along the second direction.

11. The semiconductor structure according to claim 1, characterized in that, The lattice constant of the second semiconductor contact layer is different from that of the first semiconductor contact layer.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: The stacked first confinement layer, first waveguide layer, active layer, second waveguide layer, and second confinement layer; Wherein, the first semiconductor contact layer is located on the side of the second confinement layer opposite to the second waveguide layer; the second semiconductor contact layer is located on the side of the first semiconductor contact layer opposite to the second confinement layer.

13. A method for fabricating a semiconductor structure, characterized in that, include: Forming the first semiconductor contact layer; The first surface of the first semiconductor contact layer includes a plurality of connected stepped surfaces, the stepped surfaces including connected main surfaces and connecting surfaces; The main surface of one of the stepped surfaces is connected to the connecting surface of the adjacent stepped surface; A second semiconductor contact layer is formed, which contacts the main surface. The second semiconductor contact layer has a nanogroove located above the main surface. The nanogroove is located at the corner formed by the connecting surface of one of the stepped surfaces and the connecting surface of the other stepped surface. A first electrode layer is formed, which is located on the side of the second semiconductor contact layer opposite to the first semiconductor contact layer and extends into the nanogroove.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming the first semiconductor contact layer includes: forming the first semiconductor contact layer by step flow epitaxial growth on one side of a substrate layer; the surface of the substrate layer has a chamfer angle θ, the chamfer angle θ being greater than 0° and less than or equal to 1°; wherein, the first semiconductor contact layer, on a first surface away from the substrate layer, includes a plurality of connected step surfaces; Alternatively, forming the first semiconductor contact layer includes: forming a first initial semiconductor contact layer; grinding and polishing a first initial surface of the first initial semiconductor contact layer to form the first semiconductor contact layer, and making the first initial surface form the first surface.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming the second semiconductor contact layer includes: The first and second phases are performed sequentially. In the first stage, a group III gas source and a group V gas source are introduced into the epitaxial chamber to form a second initial semiconductor contact layer on the first surface; In the second stage, the supply of the three-group gas source is stopped, and a decomposition gas containing H is introduced into the epitaxial chamber. The decomposition gas decomposes the portion of the second initial semiconductor contact layer located at the corner formed by the main surface of one of the stepped surfaces and the connecting surface of the other stepped surface, so that the second initial semiconductor contact layer forms a second semiconductor contact layer with nanogrooves. The average temperature in the second stage is lower than the average temperature in the first stage.

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