High-voltage switch control circuit based on thin gate tube
By using a high-voltage switch control circuit based on thin-gate transistors, the problems of poor process compatibility and low carrier mobility of thick-gate devices are solved. This enables reliable conduction and gate protection of the high-voltage switch at voltages up to 36V, is compatible with standard CMOS processes, reduces costs, and improves design reusability and system energy efficiency.
Patent Information
- Application Number
- CN202511048891.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-28
AI Technical Summary
In existing high-voltage switch designs, thick-gate devices have poor process compatibility, low carrier mobility, and limited design flexibility. They cannot be compatible with standard CMOS processes and achieve reliable conduction and gate withstand voltage protection at voltages up to 36V.
A high-voltage switching control circuit based on thin-gate transistors is adopted. Through PMOS and NMOS path circuits and dynamic control logic and protection circuits, high-voltage conduction and gate protection of thin-gate transistors are realized. It is compatible with standard CMOS process. By utilizing the high mobility characteristics of thin-gate devices and combining pulse acceleration-static shutdown control mechanism, static power consumption is reduced.
It achieves reliable conduction of high-voltage switches at voltages up to 36V and gate withstand voltage protection of thin-gate transistors, with good compatibility, reduced chip area and manufacturing cost, supports highly integrated and high-performance circuit designs, and is suitable for automotive electronics and energy-sensitive systems.
Smart Images
Figure CN121036741A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of microelectronic technology, and in particular to a high-voltage switch control circuit based on a thin-gate tube. BACKGROUND
[0002] In the design of high-voltage switches of analog integrated circuits, thick-gate devices significantly improve the gate-source and gate-drain voltage resistance by increasing the thickness of the gate oxide layer, making it the mainstream solution for implementing 0-36V high-voltage switches in the current industry. This solution usually controls the gate turn-on voltage with a simple level conversion or driving circuit, and has the characteristics of simple structure and high reliability. However, despite the maturity of the thick-gate tube solution, it still has the following fundamental limitations: poor process compatibility: the thick-gate device process is independent of the standard CMOS process flow, requiring additional oxide layer growth procedures; at the same time, advanced processes generally do not provide thick-gate device options, limiting the development of high-performance and high-integration high-voltage circuits. Performance and cost disadvantage: the carrier mobility of thick-gate devices is usually lower than that of thin-gate tubes, resulting in higher on-resistance and significantly lower switching efficiency. Limited design flexibility: the high-voltage switch solution based on thick-gate tubes cannot fully utilize thin-gate technology, resulting in low design reuse rate. Therefore, the current industry urgently needs a high-voltage switch solution that does not rely on thick-gate tubes, which must meet two major requirements: compatibility with standard thin-gate technology, and reliable turn-on and gate voltage protection of devices under high voltage up to 36V. SUMMARY
[0003] The present application provides a high-voltage switch control circuit based on a thin-gate tube, which realizes reliable high-voltage turn-on of the core high-voltage switch circuit composed of thin-gate tubes and protection of the thin-gate tube gate through dynamic control logic and protection circuit.
[0004] Technical solution: To achieve the above purpose, a high-voltage switch control circuit based on a thin-gate tube according to the present application comprises a PMOS gate drive circuit, an NMOS gate drive circuit and a core high-voltage switch circuit; the core high-voltage switch circuit comprises a PMOS path circuit and an NMOS path circuit; the collection end of the PMOS gate drive circuit collects the input voltage in the PMOS path circuit, and the output end of the PMOS gate drive circuit is electrically connected to the control end of the PMOS path circuit, outputting the PMOS_CTL signal to control the turn-on and turn-off of the PMOS path circuit; the collection end of the NMOS gate drive circuit collects the input voltage in the NMOS path circuit, and the output end of the NMOS gate drive circuit is electrically connected to the control end of the NMOS path circuit, outputting the NMOS_CTL signal to control the turn-on and turn-off of the NMOS path circuit.
[0005] Further, the PMOS path circuit comprises MP1 transistor and MP2 transistor; the NMOS path circuit comprises MN1 transistor and MN2 transistor; the drain of the MP1 transistor is electrically connected with the drain of the MN1 transistor, and serves as an IN terminal of the core high-voltage switch circuit; the source of the MP1 transistor is electrically connected with the source of the MP2 transistor, the source of the MN1 transistor is electrically connected with the source of the MN2 transistor; the drain of the MP2 transistor is electrically connected with the drain of the MN2 transistor, and serves as an OUT terminal of the core high-voltage switch circuit.
[0006] Further, the gates of the MP1 transistor and the MP2 transistor are electrically connected with the output terminal of the PMOS gate drive circuit, the gates of the MN1 transistor and the MN2 transistor are electrically connected with the output terminal of the NMOS gate drive circuit; the source of the MP1 transistor and the source of the MP2 transistor are electrically connected with the collection terminal of the PMOS gate drive circuit, the source of the MN1 transistor and the source of the MN2 transistor are electrically connected with the collection terminal of the NMOS gate drive circuit.
[0007] Further, the PMOS gate drive circuit comprises first signal processing circuit and first drive circuit; the input terminal of the first signal processing circuit inputs CTL2N signal; the output terminal of the first signal processing circuit is electrically connected with the input terminal of the first drive circuit, and inputs P_PULSE signal obtained by signal processing of the CTL2N signal to the input terminal of the first drive circuit; the output terminal of the first drive circuit outputs PMOS_CTL signal as the output terminal of the PMOS gate drive circuit.
[0008] Further, the NMOS gate drive circuit comprises second signal processing circuit and second drive circuit; the input terminal of the second signal processing circuit inputs CTL1 signal, the output terminal of the second signal processing circuit is electrically connected with the input terminal of the second drive circuit, and inputs N_PULSE signal obtained by signal processing of the CTL1 signal to the input terminal of the second drive circuit; the output terminal of the second drive circuit outputs NMOS_CTL signal as the output terminal of the NMOS gate drive circuit.
[0009] Further, the first signal processing circuit includes a NAND1 NAND gate circuit, a NOT1 NOT gate circuit, a M12 transistor, a M13 transistor, a NOT2 NOT gate circuit, a NOT3 NOT gate circuit and a NOT4 NOT gate circuit; an input end of the NOT1 NOT gate circuit inputs a CTL2N signal, and an output end of the NOT1 NOT gate circuit is electrically connected with a gate of the M12 transistor and the M13 transistor; a drain of the M12 transistor is electrically connected with a drain of the M13 transistor through an R1 resistor, a source of the M12 transistor is electrically connected with an HVEE power supply, a source of the M13 transistor is grounded, and a drain of the M13 transistor is electrically connected with an input end of the NOT4 NOT gate circuit; an output end of the NOT4 NOT gate circuit is electrically connected with one input end of the NAND1 NAND gate circuit, and the other input end of the NAND1 NAND gate circuit inputs the CTL2N signal; an output end of the NAND1 NAND gate circuit is electrically connected with an input end of the NOT2 NOT gate circuit, an output end of the NOT2 NOT gate circuit is electrically connected with an input end of the NOT3 NOT gate circuit, and an output end of the NOT3 NOT gate circuit outputs a P_PULSE signal as an output end of the first signal processing circuit.
[0010] Further, the first driving circuit includes eleven transistors of M1 to M11; a gate of the M11 transistor is electrically connected with an output end of the NOT3 NOT gate circuit, a drain of the M11 transistor is electrically connected with a gate of the M10 transistor and a gate of the M8 transistor; a drain and a gate of the M10 transistor are electrically connected with a VCC power supply through a current source, and a source of the M10 transistor is grounded; a drain of the M8 transistor is electrically connected with a source of the M7 transistor and a drain of the M9 transistor, a gate of the M9 transistor inputs a Vb bias voltage signal, a source of the M9 transistor is grounded, and a gate of the M7 transistor inputs a CTL2 signal; a gate of the M1 transistor and the M2 transistor both inputs a CTL1 signal, and a source of the M1 transistor and the M2 transistor are both electrically connected with the VCC power supply; a drain of the M2 transistor is electrically connected with a gate of the M3 transistor and one end of an R3 resistor, and the other end of the R3 resistor is used as a collection end of the PMOS gate driving circuit; a source of the M3 transistor is electrically connected with the VCC power supply through an R2 resistor, a drain of the M3 transistor is electrically connected with a drain and a gate of the M4 transistor, a source of the M4 transistor is electrically connected with a drain and a gate of the M5 transistor, a source of the M5 transistor is electrically connected with a drain and a gate of the M6 transistor, a drain of the M1 transistor and a source of the M6 transistor are both electrically connected with a drain of the M7 transistor, and the source of the M6 transistor outputs a PMOS_CTL signal as an output end of the first driving circuit.
[0011] Further, the second signal processing circuit comprises a NOR1 NOR circuit, a NOT5 NOT circuit, a M32 transistor, a M33 transistor, a NOT6 NOT circuit, a NOT7 NOT circuit and a NOT8 NOT circuit; an input end of the NOT5 NOT circuit inputs a CTL1 signal, output ends of the NOT5 NOT circuit are electrically connected to gate electrodes of the M32 transistor and the M33 transistor; a drain electrode of the M32 transistor is electrically connected to a drain electrode of the M33 transistor through a R4 resistor, a source electrode of the M32 transistor is electrically connected to a VCC power supply, a source electrode of the M33 transistor is grounded, and a drain electrode of the M33 transistor is electrically connected to an input end of the NOT8 NOT circuit; an output end of the NOT8 NOT circuit is electrically connected to one input end of the NOR1 NOR circuit, and the other input end of the NOR1 NOR circuit inputs the CTL1 signal; an output end of the NOR1 NOR circuit is electrically connected to an input end of the NOT6 NOT circuit, an output end of the NOT6 NOT circuit is electrically connected to an input end of the NOT7 NOT circuit, and an output end of the NOT7 NOT circuit outputs a N_PULSE signal as an output end of the second signal processing circuit.
[0012] Further, the second driving circuit comprises eleven transistors of M21 to M31; a gate electrode of the M29 transistor is electrically connected to the NOT7 NOT circuit, a drain electrode of the M29 transistor is electrically connected to a gate electrode of the M22 transistor and a gate electrode of the M31 transistor; a source electrode and a gate electrode of the M31 transistor are electrically connected to a VCC power supply, a drain electrode of the M31 transistor is grounded through a current source; a source electrode of the M22 transistor is electrically connected to the VCC power supply, a drain electrode of the M22 transistor is electrically connected to a source electrode of the M23 transistor and a drain electrode of the M21 transistor, a gate electrode of the M21 transistor inputs a Vb bias voltage signal, a source electrode of the M21 transistor is electrically connected to the VCC power supply, and a gate electrode of the M23 transistor inputs a CTL1N signal; gate electrodes of the M28 transistor and the M30 transistor both input a CTL3 signal, source electrodes of the M28 transistor and the M30 transistor are both grounded, a drain electrode of the M30 transistor is electrically connected to a gate electrode of the M27 transistor and one end of a R5 resistor, the other end of the R5 resistor is used as a collection end of the NMOS gate driving circuit; a source electrode of the M27 transistor is grounded through a R6 resistor, a drain electrode of the M27 transistor is electrically connected to a source electrode of the M26 transistor, a gate electrode and a drain electrode of the M26 transistor are electrically connected to a source electrode of the M25 transistor, a gate electrode and a drain electrode of the M25 transistor are electrically connected to a source electrode of the M24 transistor, a drain electrode of the M28 transistor, a gate electrode and a drain electrode of the M24 transistor are all electrically connected to a drain electrode of the M23 transistor, and the drain electrode of the M24 transistor outputs an NMOS_CTL signal as an output end of the second driving circuit.
[0013] Beneficial effects: a high-voltage switch control circuit based on a thin gate tube of the present application, advanced process compatibility: completely get rid of the dependence on thick gate devices, can realize 0-36V high-voltage switch in advanced process which only provides thin gate devices, break through the technical blockade caused by the absence of thick gate tube process in traditional scheme, open up a new path for high-voltage circuit to evolve towards high integration and high performance; Comprehensive cost disruptive reduction: based on the high mobility characteristics of the carrier of the thin gate device, under the same on-resistance requirement, the chip area is significantly reduced, at the same time, the additional mask layer and oxidation layer growth process exclusive to thick gate process are saved, the wafer manufacturing cost is reduced, and the product competitiveness is significantly improved; Design reuse rate and system energy efficiency jump: this scheme is fully compatible with the basic CMOS process library, supports single-chip integration of high-voltage modules and digital / analog cores, and through the pulse acceleration-static off control mechanism, it realizes low opening time of switch while significantly reducing static power consumption, suitable for automotive electronics, energy-sensitive systems and other application scenarios; Make the high-voltage switch control circuit compatible with the standard thin gate process, and ensure the reliable conduction of the thin gate tube device under the voltage of up to 36V and the voltage protection of the thin gate tube gate. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 It is a circuit diagram of a high-voltage switch control circuit based on a thin gate tube.
[0015] Figure 2 It is a circuit diagram of a core high-voltage switch circuit.
[0016] Figure 3 It is a circuit diagram of a PMOS gate drive circuit.
[0017] Figure 4 It is a circuit diagram of an NMOS gate drive circuit.
[0018] Figure 5 It is a comprehensive timing diagram of the core high-voltage switch. DETAILED DESCRIPTION
[0019] The present application will be further described below in conjunction with the drawings.
[0020] As Figure 1As shown, a high-voltage switch control circuit based on a thin gate tube includes a PMOS gate drive circuit 1, an NMOS gate drive circuit 2, and a core high-voltage switch circuit 3; the core high-voltage switch circuit 2 includes a PMOS path circuit and an NMOS path circuit; the collection end of the PMOS gate drive circuit 1 collects the input voltage in the PMOS path circuit, and the output end of the PMOS gate drive circuit 1 is electrically connected to the control end of the PMOS path circuit, and outputs the PMOS_CTL signal to control the conduction and turn-off of the PMOS path circuit; the collection end of the NMOS gate drive circuit 2 collects the input voltage in the NMOS path circuit, and the output end of the NMOS gate drive circuit 2 is electrically connected to the control end of the NMOS path circuit, and outputs the NMOS_CTL signal to control the conduction and turn-off of the NMOS path circuit. The core high-voltage switch circuit 3 is a high-voltage switch, the PMOS gate drive circuit 1 is a Driver_PMOS drive module, and the NMOS gate drive circuit 2 is a Driver_NMOS drive module.
[0021] In the high-voltage switch off state of the core high-voltage switch circuit 3, the gate control voltage PMOS_CTL of the PMOS switch tube in the PMOS path circuit is high, about 36V, by pull-up; the gate control voltage NMOS_CTL of the NMOS switch tube in the NMOS path circuit is low, about 0V, by pull-down; at this time, the gate-source voltage is Vgs=0, and the gate-drain voltage is Vgd=VCC-Vin, and the characteristics of thin gate tube gate-drain voltage and gate-source voltage are used to realize the safe turn-off of the high-voltage switch. In the high-voltage switch on state of the core high-voltage switch circuit 3, the Driver_PMOS drive module and the Driver_NMOS drive module are cooperatively controlled, that is, the PMOS gate drive circuit 1 and the NMOS gate drive circuit 2 are cooperatively controlled, so that the difference between the gate-source voltage and the gate-drain voltage of the PMOS switch tube and the NMOS switch tube in the core high-voltage switch circuit 3 is Vgs=Vgd= Vin-4Vth, so that the voltage is dynamically stabilized in the 5V safe interval, which not only guarantees the low resistance conduction of the core high-voltage switch circuit in the 0-36V high-voltage channel, but also ensures that the thin gate device always works within the voltage limit, which fundamentally breaks through the low voltage limit of the traditional thin gate device gate-drain.
[0022] As Figure 2As shown, the core high-voltage switching circuit 3 is composed of symmetrical PMOS and NMOS path circuits. The PMOS path circuit consists of two interconnected PMOS transistors, and the NMOS path circuit consists of two interconnected NMOS transistors. Both the PMOS transistors in the PMOS path circuit and the NMOS transistors in the NMOS path circuit are thin-gate MOS transistors. The PMOS path circuit includes MP1 and MP2 transistors, both of which are PMOS transistors. The NMOS path circuit includes MN1 and MN2 transistors, both of which are NMOS transistors. The drain of the MP1 transistor is electrically connected to the drain of the MN1 transistor and serves as the IN terminal of the core high-voltage switching circuit 3. The source of the MP1 transistor is electrically connected to the source of the MP2 transistor, and the source of the MN1 transistor is electrically connected to the source of the MN2 transistor. The drain of the MP2 transistor is electrically connected to the drain of the MN2 transistor and serves as the OUT terminal of the core high-voltage switching circuit 3.
[0023] like Figures 2-4 As shown, the gates of transistors MP1 and MP2 are electrically connected to the output terminal of PMOS gate driving circuit 1, and the gates of transistors MN1 and MN2 are electrically connected to the output terminal of NMOS gate driving circuit 2. The sources of transistors MP1 and MP2 are electrically connected to the acquisition terminal of PMOS gate driving circuit 1, which acquires the input voltage of the PMOS path circuit. The sources of transistors MN1 and MN2 are electrically connected to the acquisition terminal of NMOS gate driving circuit 1, which acquires the input voltage of the NMOS path circuit.
[0024] like Figure 3 As shown, the PMOS gate driving circuit 1 includes a first signal processing circuit 11 and a first driving circuit 12. The input terminal of the first signal processing circuit 11 receives the CTL2N signal. The output terminal of the first signal processing circuit 11 is electrically connected to the input terminal of the first driving circuit 12, and inputs the P_PULSE signal obtained after signal processing of the CTL2N signal to the input terminal of the first driving circuit 12. The output terminal of the first driving circuit 12 serves as the output terminal of the PMOS gate driving circuit 1, outputting the PMOS_CTL signal. The PMOS gate driving circuit 1 receives CTL1, CTL2, and CTL2N signals, and controls the PMOS_CTL signal output by the PMOS gate driving circuit 1 through the CTL1, CTL2, and CTL2N signals, thereby enabling the safe turn-on and turn-off of the PMOS path circuit in the core high-voltage switching circuit 3.
[0025] like Figure 4As shown, the NMOS gate driving circuit 2 includes a second signal processing circuit 21 and a second driving circuit 22. The input terminal of the second signal processing circuit 21 receives the CTL1 signal, and the output terminal of the second signal processing circuit 21 is electrically connected to the input terminal of the second driving circuit 22. The N_PULSE signal obtained after signal processing of the CTL1 signal is input to the input terminal of the second driving circuit 22. The output terminal of the second driving circuit 22 serves as the output terminal of the NMOS gate driving circuit 2, outputting the NMOS_CTL signal. The NMOS gate driving circuit 2 receives the CTL1, CTL1N, and CTL3 signals, and controls the NMOS_CTL signal output by the NMOS gate driving circuit 2 through the CTL1, CTL1N, and CTL3 signals, thereby enabling the safe turn-on and turn-off of the NMOS path circuit in the core high-voltage switching circuit 3.
[0026] like Figure 3 As shown, the first signal processing circuit 11 includes a NAND1 NOT gate, a NOT1 NOT gate, an M12 transistor, an M13 transistor, a NOT2 NOT gate, a NOT3 NOT gate, and a NOT4 NOT gate. The input terminal of the NOT1 NOT gate receives a CTL2N signal, and its output terminal is electrically connected to the gates of the M12 and M13 transistors. The drain of the M12 transistor is electrically connected to the drain of the M13 transistor via a resistor R1. The source of the M12 transistor is electrically connected to the HVEE power supply, and the source of the M13 transistor is grounded, meaning the source of the M13 transistor is electrically connected to VEE. The drain of the M13 transistor is... The NOT4 NOT gate is electrically connected to its input terminal, which is grounded through capacitor C1. This means the NOT4 NOT gate's input terminal is electrically connected to VEE via capacitor C1. The NOT4 NOT gate's output terminal is electrically connected to one input terminal of the NAND1 NAND gate, and the other input terminal of the NAND1 NAND gate receives the CTL2N signal. The NAND1 NAND gate's output terminal is electrically connected to the NOT2 NOT gate's input terminal, and the NOT2 NOT gate's output terminal is electrically connected to the NOT3 NOT gate's input terminal. The NOT3 NOT gate's output terminal serves as the output terminal of the first signal processing circuit 11, outputting the P_PULSE signal.
[0027] like Figure 3As shown, the first driving circuit 12 includes eleven transistors, M1 to M11, namely, transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11. The gate of transistor M11 is electrically connected to the output of the NOT3 gate circuit, and its source is grounded, meaning its source is electrically connected to VEE. The drain of transistor M11 is electrically connected to the gates of transistors M10 and M8. The drain and gate of transistor M10 are electrically connected to the VCC power supply via a current source, and its source is grounded, meaning its source is electrically connected to VEE. The drain of transistor M8 is electrically connected to the sources of transistors M7 and M9, and its source is grounded, meaning its source is electrically connected to VEE. The gate of transistor M9 receives Vb input. The bias voltage signal is applied, the source of transistor M9 is grounded, i.e., the source of transistor M9 is electrically connected to VEE, and the gate of transistor M7 receives the CTL2 signal; the gates of transistors M1 and M2 both receive the CTL1 signal, and the sources of transistors M1 and M2 are both electrically connected to the VCC power supply; the drain of transistor M2 is electrically connected to the gate of transistor M3 and one end of resistor R3, and the other end of resistor R3 serves as the acquisition terminal of PMOS gate drive circuit 1; the source of transistor M3 is electrically connected to the VCC power supply through resistor R2, the drain of transistor M3 is electrically connected to the drain and gate of transistor M4, the source of transistor M4 is electrically connected to the drain and gate of transistor M5, the source of transistor M5 is electrically connected to the drain and gate of transistor M6, the drain of transistor M1 and the source of transistor M6 are both electrically connected to the drain of transistor M7, and the source of transistor M6 serves as the output terminal of the first drive circuit 12, outputting the PMOS_CTL signal.
[0028] Transistors M1, M2, M3, and M12 are all PMOS transistors; transistors M4, M5, M6, M7, M8, M9, M10, M11, and M13 are all NMOS transistors.
[0029] like Figure 4As shown, the second signal processing circuit 21 includes a NOR1 NOT gate, a NOT5 NOT gate, an M32 transistor, an M33 transistor, a NOT6 NOT gate, a NOT7 NOT gate, and a NOT8 NOT gate. The input terminal of the NOT5 NOT gate receives the CTL1 signal, and its output terminal is electrically connected to the gates of the M32 and M33 transistors. The drain of the M32 transistor is electrically connected to the drain of the M33 transistor via resistor R4. The source of the M32 transistor is electrically connected to the VCC power supply, and the source of the M33 transistor is grounded, meaning the source of the M33 transistor is electrically connected to VEE. The drain of the M33 transistor... The NOT8 NOT gate is electrically connected to its input terminal, which is grounded through capacitor C2. This means the NOT8 NOT gate's input terminal is electrically connected to VEE via capacitor C2. The NOT8 NOT gate's output terminal is electrically connected to one input terminal of the NOR1 NAND gate, and the other input terminal of the NOR1 NAND gate receives the CTL1 signal. The NOR1 NAND gate's output terminal is electrically connected to the NOT6 NOT gate's input terminal, and the NOT6 NOT gate's output terminal is electrically connected to the NOT7 NOT gate's input terminal. The NOT7 NOT gate's output terminal serves as the output terminal of the second signal processing circuit 21, outputting the N_PULSE signal.
[0030] like Figure 4As shown, the second driving circuit 22 includes eleven transistors, from M21 to M31, namely transistors M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, and M31. The gate of transistor M29 is electrically connected to a NOT7 gate, its source is electrically connected to the VCC power supply, and its drain is electrically connected to the gates of transistors M22 and M31. The source and gate of transistor M31 are electrically connected to the VCC power supply, and its drain is grounded through a current source, i.e., its drain is electrically connected to VEE through a current source. The source of transistor M22 is electrically connected to the VCC power supply, and its drain is electrically connected to the source of transistor M23 and the drain of transistor M21. The gate of transistor M21 receives the Vb bias voltage signal, and its source is electrically connected to the VCC power supply. The gate of transistor M23 receives the CTL1N signal. The gates of transistors M28 and M30 both receive the CTL3 signal, and their sources are both grounded, meaning their sources are electrically connected to VEE. The drain of transistor M30 is electrically connected to the gate of transistor M27 and one end of resistor R5, with the other end of R5 serving as the acquisition terminal for the NMOS gate drive circuit 2. The source of transistor M27 is grounded through resistor R6, meaning the source of transistor M27 is electrically connected to VEE through resistor R6. The drain of transistor M27 is electrically connected to the source of transistor M26. The gate and drain of transistor M26 are electrically connected to the source of transistor M25. The gate and drain of transistor M25 are electrically connected to the source of transistor M24. The drain of transistor M28, the gate and drain of transistor M24 are all electrically connected to the drain of transistor M23. The drain of transistor M24 serves as the output terminal of the second driving circuit 22, outputting the NMOS_CTL signal.
[0031] Transistors M21, M22, M23, M29, M31, and M32 are all PMOS transistors, while transistors M24, M25, M26, M27, M28, M30, and M33 are all NMOS transistors.
[0032] like Figure 5As shown, the PMOS gate drive circuit 1 controls the switching state of the PMOS path circuit through the coordinated control of CTL1, CTL2, and CTL2N signals. Utilizing the difference in gate-source voltage and gate-drain voltage characteristics of the thin-gate device, it achieves safe turn-on and turn-off of the PMOS switch in the core high-voltage switching circuit 3. When the PMOS path circuit is off, both CTL1 and CTL2 signals are low, and CTL2N signal is high. At this time, transistor M1 is turned on, while transistor M7 is turned off, causing the PMOS_CTL signal to be pulled up to the VCC power supply voltage, forcibly turning off the PMOS switch in the PMOS path circuit. Therefore, the PMOS_CTL signal is specifically represented as: PMOS_CTL = PU_R = VCC.
[0033] When the PMOS path circuit is turned on, both CTL1 and CTL2 signals are high, and CTL2N signal is low, triggering transistor M1 to turn off and transistor M7 to turn on. Transistors M3, M4, M5, M6, M7, and M9 form the voltage path from the VCC power supply to VEE ground, thereby driving the PMOS switch in the external PMOS path circuit into a subthreshold conduction state. The acquisition terminal of PMOS gate drive circuit 1 acquires the input voltage PU_R at the source connection of transistors MP1 and MP2, and generates a precise gate control voltage PMOS_CTL through the threshold voltage drop of the four-stage MOS transistors (M3, M4, M5, and M6). This voltage ensures that the PMOS switch in the PMOS path circuit can reliably conduct under a safe voltage difference. The calculation of the PMOS_CTL signal is as follows:
[0034]
[0035] In the formula, V th3 V th4 V th5 and V th6 The threshold voltage drops of transistors M3, M4, M5, and M6 are given respectively, and the threshold voltage drops of transistors M3, M4, M5, and M6 are the same; PU_R is the input voltage at the connection between the source of transistor MP1 and the source of transistor MP2, or V can be used. in1 express.
[0036] During the state transition from the off state to the on state in the PMOS path circuit, the rising edge of the CTL2N signal triggers its delayed inverse signal CTL2N_B. The two signals, CTL2N and CTL2N_B, generate a low-level pulse P_PULSE signal through a NAND gate. During the pulse of the P_PULSE signal, the M11 transistor is turned off, and a large current is injected into the branches containing the M8 and M10 transistors to accelerate the conduction process of the PMOS switches in the PMOS path circuit. After the P_PULSE signal pulse ends, the M11 transistor is turned on again, pulling down the gates of the M8 and M10 transistors to VEE to cut off the bias path, significantly reducing static power consumption.
[0037] like Figure 5 As shown, the NMOS gate drive circuit 2 coordinates the switching state of the NMOS path circuit through the CTL1, CTL1N, and CTL3 signals. Utilizing the difference in gate-source voltage and gate-drain voltage characteristics of the thin-gate device, it achieves safe turn-on and turn-off of the NMOS switch in the core high-voltage switching circuit 3. When the NMOS path circuit is off, both CTL1N and CTL3 signals are low, and CTL1 signal is high. At this time, transistor M28 is turned on, while transistor M23 is turned off, causing the NMPS_CTL signal to be pulled down to VEE, forcibly turning off the NMOS switch in the NMOS path circuit. Therefore, the NMOS_CTL signal is specifically represented as: PMOS_CTL = PU_D = 0.
[0038] When the NMOS path circuit is turned on, both CTL1N and CTL3 signals are high, and CTL1 signal is low, triggering transistor M28 to turn off and transistor M23 to turn on. Transistors M21, M23, M24, M25, M26, and M27 form the voltage path from the VCC power supply to VEE ground, thereby driving the NMOS switch in the external NMOS path circuit into a subthreshold conduction state. The acquisition terminal of NMOS gate drive circuit 2 acquires the input voltage PU_D at the source connection of transistors MN1 and MN2, and generates a precise gate control voltage NMOS_CTL through the threshold voltage drop of the four-stage MOS transistors formed by transistors M24, M25, M26, and M27. This voltage ensures that the NMOS switch in the NMOS path circuit can reliably conduct under a safe voltage difference. The calculation of the NMOS_CTL signal is as follows:
[0039]
[0040] In the formula, V th24 V th25 V th26 and Vth27 The threshold voltage drops of transistors M24, M25, M26, and M27 are given respectively, and the threshold voltage drops of transistors M24, M25, M26, and M27 are the same; PU_D is the input voltage at the source connection of transistor MN1 and transistor MN2, or V can be used. in2 express.
[0041] During the state transition from the off state to the on state in the NMOS path circuit, the falling edge of the CTL1 signal triggers its delayed inverse signal CTL1_B. The two signals, CTL1 and CTL1_B, generate a high-level pulse N_PULSE signal through a NOR gate. During the pulse of the N_PULSE signal, transistor M29 is turned off, which injects a large current into the branches containing transistors M22 and M31 to accelerate the conduction process of the PMOS switches in the PMOS path circuit. After the pulse of the P_PULSE signal ends, transistor M29 is turned on again, pulling the gates of transistors M22 and M31 up to the VCC power supply voltage to cut off the bias path, significantly reducing static power consumption.
[0042] The above description is merely a preferred embodiment of the present invention. Those skilled in the art can make several modifications and optimizations based on the above disclosure without departing from the basic principles described above. These modifications and optimizations should be considered within the scope of protection as understood by the present invention.
Claims
1. A high-voltage switching control circuit based on a thin-gate transistor, characterized in that: It includes a PMOS gate drive circuit (1), an NMOS gate drive circuit (2), and a core high-voltage switch circuit (3); the core high-voltage switch circuit (2) includes a PMOS path circuit and an NMOS path circuit; the acquisition terminal of the PMOS gate drive circuit (1) acquires the input voltage in the PMOS path circuit, and the output terminal of the PMOS gate drive circuit (1) is electrically connected to the control terminal of the PMOS path circuit, and outputs a PMOS_CTL signal to control the conduction and turn-off of the PMOS path circuit; the acquisition terminal of the NMOS gate drive circuit (2) acquires the input voltage in the NMOS path circuit, and the output terminal of the NMOS gate drive circuit (2) is electrically connected to the control terminal of the NMOS path circuit, and outputs an NMOS_CTL signal to control the conduction and turn-off of the NMOS path circuit.
2. The high-voltage switching control circuit based on a thin-gate transistor according to claim 1, characterized in that: The PMOS path circuit includes MP1 transistor and MP2 transistor; the NMOS path circuit includes MN1 transistor and MN2 transistor; the drain of MP1 transistor is electrically connected to the drain of MN1 transistor and serves as the IN terminal of the core high-voltage switching circuit (3); the source of MP1 transistor is electrically connected to the source of MP2 transistor, and the source of MN1 transistor is electrically connected to the source of MN2 transistor; the drain of MP2 transistor is electrically connected to the drain of MN2 transistor and serves as the OUT terminal of the core high-voltage switching circuit (3).
3. The high-voltage switching control circuit based on a thin-gate transistor according to claim 2, characterized in that: The gates of the MP1 and MP2 transistors are electrically connected to the output terminal of the PMOS gate drive circuit (1), and the gates of the MN1 and MN2 transistors are electrically connected to the output terminal of the NMOS gate drive circuit (2). The sources of the MP1 and MP2 transistors are electrically connected to the acquisition terminal of the PMOS gate drive circuit (1), and the sources of the MN1 and MN2 transistors are electrically connected to the acquisition terminal of the NMOS gate drive circuit (1).
4. The high-voltage switching control circuit based on a thin-gate transistor according to claim 3, characterized in that: The PMOS gate driving circuit (1) includes a first signal processing circuit (11) and a first driving circuit (12); the input terminal of the first signal processing circuit (11) receives the CTL2N signal; the output terminal of the first signal processing circuit (11) is electrically connected to the input terminal of the first driving circuit (12), and inputs the P_PULSE signal obtained after signal processing of the CTL2N signal to the input terminal of the first driving circuit (12); the output terminal of the first driving circuit (12) serves as the output terminal of the PMOS gate driving circuit (1) to output the PMOS_CTL signal.
5. The high-voltage switching control circuit based on a thin-gate transistor according to claim 3, characterized in that: The NMOS gate drive circuit (2) includes a second signal processing circuit (21) and a second drive circuit (22); the input terminal of the second signal processing circuit (21) receives the CTL1 signal, the output terminal of the second signal processing circuit (21) is electrically connected to the input terminal of the second drive circuit (22), and the N_PULSE signal obtained after signal processing of the CTL1 signal is input to the input terminal of the second drive circuit (22); the output terminal of the second drive circuit (22) serves as the output terminal of the NMOS gate drive circuit (2) to output the NMOS_CTL signal.
6. The high-voltage switching control circuit based on a thin-gate transistor according to claim 4, characterized in that: The first signal processing circuit (11) includes a NAND1 NOT gate circuit, a NOT1 NOT gate circuit, an M12 transistor, an M13 transistor, a NOT2 NOT gate circuit, a NOT3 NOT gate circuit and a NOT4 NOT gate circuit; The input terminal of the NOT1 NOT gate circuit receives the CTL2N signal, and the output terminal of the NOT1 NOT gate circuit is electrically connected to the gates of transistors M12 and M13. The drain of transistor M12 is electrically connected to the drain of transistor M13 through resistor R1. The source of transistor M12 is electrically connected to the HVEE power supply. The source of transistor M13 is grounded. The drain of transistor M13 is electrically connected to the input terminal of NOT4 NOT gate circuit. The output terminal of NOT4 NOT gate circuit is electrically connected to one input terminal of NAND1 NAND gate circuit. The other input terminal of NAND1 NAND gate circuit receives the CTL2N signal. The output terminal of NAND1 NAND gate circuit is electrically connected to the input terminal of NOT2 NOT gate circuit. The output terminal of NOT2 NOT gate circuit is electrically connected to the input terminal of NOT3 NOT gate circuit. The output terminal of NOT3 NOT gate circuit serves as the output terminal of the first signal processing circuit (11) and outputs the P_PULSE signal.
7. The high-voltage switching control circuit based on a thin-gate transistor according to claim 6, characterized in that: The first driving circuit (12) includes eleven transistors, M1 to M11; the gate of transistor M11 is electrically connected to the output of NOT3, and the drain of transistor M11 is electrically connected to the gate of transistor M10 and the gate of transistor M8; the drain and gate of transistor M10 are electrically connected to VCC power supply through a current source, and the source of transistor M10 is grounded; the drain of transistor M8 is electrically connected to the source of transistor M7 and the drain of transistor M9, the gate of transistor M9 receives a Vb bias voltage signal, the source of transistor M9 is grounded, and the gate of transistor M7 receives a CTL2 signal; the gates of transistors M1 and M2 both receive a CTL1 signal, and the gates of transistors M1 and M8 are connected to the output of transistor M11. The sources of transistors M2 and M3 are electrically connected to the VCC power supply. The drain of transistor M2 is electrically connected to the gate of transistor M3 and one end of resistor R3. The other end of resistor R3 serves as the acquisition terminal of PMOS gate drive circuit (1). The source of transistor M3 is electrically connected to the VCC power supply through resistor R2. The drain of transistor M3 is electrically connected to the drain and gate of transistor M4. The source of transistor M4 is electrically connected to the drain and gate of transistor M5. The source of transistor M5 is electrically connected to the drain and gate of transistor M6. The drain of transistor M1 and the source of transistor M6 are both electrically connected to the drain of transistor M7. The source of transistor M6 serves as the output terminal of the first drive circuit (12) to output the PMOS_CTL signal.
8. A high-voltage switching control circuit based on a thin-gate transistor according to claim 5, characterized in that: The second signal processing circuit (21) includes a NOR1 NOT gate, a NOT5 NOT gate, an M32 transistor, an M33 transistor, a NOT6 NOT gate, a NOT7 NOT gate, and a NOT8 NOT gate; the input terminal of the NOT5 NOT gate receives the CTL1 signal, and the output terminal of the NOT5 NOT gate is electrically connected to the gates of the M32 transistor and the M33 transistor; the drain of the M32 transistor is electrically connected to the drain of the M33 transistor through a resistor R4, and the source of the M32 transistor is electrically connected to the VCC power supply; the source of the M33 transistor... The drain of transistor M33 is grounded, and its drain is electrically connected to the input of NOT8 NOT gate. The output of NOT8 NOT gate is electrically connected to one input of NOR1 NAND gate, and the other input of NOR1 NAND gate is the input of CTL1 signal. The output of NOR1 NAND gate is electrically connected to the input of NOT6 NOT gate, and the output of NOT6 NOT gate is electrically connected to the input of NOT7 NOT gate. The output of NOT7 NOT gate is used as the output of the second signal processing circuit (21) to output the N_PULSE signal.
9. A high-voltage switching control circuit based on a thin-gate transistor according to claim 8, characterized in that: The second driving circuit (22) includes eleven transistors, from M21 to M31; the gate of transistor M29 is electrically connected to a NOT7 gate, and the drain of transistor M29 is electrically connected to the gates of transistors M22 and M31; the source and gate of transistor M31 are electrically connected to the VCC power supply, and the drain of transistor M31 is grounded through a current source; the source of transistor M22 is electrically connected to the VCC power supply, and the drain of transistor M22 is electrically connected to the source of transistor M23 and M2... The drain of transistor M1, the gate of transistor M21 is input with Vb bias voltage signal, the source of transistor M21 is electrically connected to VCC power supply, and the gate of transistor M23 is input with CTL1N signal; the gates of transistors M28 and M30 are both input with CTL3 signal, the sources of transistors M28 and M30 are both grounded, the drain of transistor M30 is electrically connected to the gate of transistor M27 and one end of resistor R5, and the other end of resistor R5 is used as the acquisition terminal of NMOS gate drive circuit (2); The source of transistor M27 is grounded through resistor R6. The drain of transistor M27 is electrically connected to the source of transistor M26. The gate and drain of transistor M26 are electrically connected to the source of transistor M25. The gate and drain of transistor M25 are electrically connected to the source of transistor M24. The drain of transistor M28, the gate and drain of transistor M24 are all electrically connected to the drain of transistor M23. The drain of transistor M24 serves as the output terminal of the second driving circuit (22) to output the NMOS_CTL signal.