Driving circuit, driving chip, control method and laser radar

Abstract

The application relates to a driving circuit, a driving chip, a control method and a laser radar. The driving circuit comprises a first high-side switching transistor, a first bootstrap driving module for driving the first high-side switching transistor and a charging module. The first high-side switching transistor has a parasitic gate capacitor. A first end of the first high-side switching transistor is used for inputting a high-voltage side power supply signal, and a second end of the first high-side switching transistor is used for connecting a load. The charging module is used for charging the gate capacitor for a first time length in a time period during which the first high-side switching transistor is turned on under the control of the first control signal of the first bootstrap driving module, so as to compensate for at least part of the electric charge of the gate capacitor charged by the first bootstrap driving module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a driving circuit, a driving chip, a control method and a laser radar. BACKGROUND

[0002] In a laser radar system, the laser driver circuit is one of the core components, and its performance directly affects the detection distance, accuracy and reliability of the entire system. In laser radar applications, high-side switch transistor driving circuits usually use bootstrap driving technology to achieve high-efficiency and low-power laser driver. In the high-side switch driving circuit, the bootstrap capacitor is a key element to realize the gate drive of the high-side switch transistor. The bootstrap capacitor provides a driving voltage for the gate of the high-side switch transistor by charging when the high-side switch transistor is turned on.

[0003] In laser radar high-side driving applications, Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) transistors are widely used as high-side switch transistors due to their high voltage resistance and low on-resistance. However, LDMOS transistors usually have a large gate capacitance, and a large amount of charge is needed to raise the gate voltage to the required level. In laser radar high-side driving switch applications, due to the large gate capacitance of LDMOS, the existing bootstrap driving scheme is difficult to provide sufficient charge for the gate capacitance in a short time.

[0004] Therefore, how to solve the problem of insufficient charging under large gate capacitance load and improve the peak current of the high-side switch transistor is an urgent problem to be solved. SUMMARY

[0005] Therefore, the embodiments of the present application provide a driving circuit, a driving chip, a control method and a laser radar to solve the problems in the background art.

[0006] According to a first aspect of the embodiments of the present disclosure, a driving circuit is provided, the driving circuit comprising: a first high-side switch transistor, a first bootstrap driving module for driving the first high-side switch transistor, and a charging module; wherein,

[0007] The first high-side switch transistor has a parasitic gate capacitance; the first end of the first high-side switch transistor is used for inputting a high-voltage side power supply signal, and the second end of the first high-side switch transistor is used for connecting a load.

[0008] The charging module is configured to charge the gate capacitor for a first duration during a time period in which the first bootstrap drive module is controlled to turn on the first high-side switch transistor based on a first control signal.

[0009] In some embodiments, the charging module is configured to do one of:

[0010] charge the gate capacitor before a starting time at which the first bootstrap drive module controls the first high-side switch transistor to turn on, and stop charging the gate capacitor during the turn-on duration;

[0011] charge the gate capacitor for a first duration starting from the starting time;

[0012] charge the gate capacitor for a first duration after the starting time, wherein an ending time of the first duration is before an ending time of the turn-on duration;

[0013] charge the gate capacitor for a first duration before the starting time.

[0014] In some embodiments, the first bootstrap drive module comprises a first bootstrap capacitor, a first buffer module, and a first diode, wherein:

[0015] an anode of the first diode is configured to input a first low-voltage side power signal;

[0016] a cathode of the first diode is connected to an upper plate of the first bootstrap capacitor;

[0017] the upper plate of the first bootstrap capacitor is connected to a first power supply end of the first buffer module;

[0018] a lower plate of the first bootstrap capacitor is connected to a second power supply end of the first buffer module;

[0019] an input end of the first buffer module is configured to input the first control signal;

[0020] an output end of the first buffer module is connected to a gate of the first high-side switch transistor;

[0021] the second power supply end of the first buffer module is connected to a second terminal of the first high-side switch transistor.

[0022] In some embodiments, the charging module comprises a second bootstrap drive module and a second high-side switch transistor, wherein:

[0023] The first end of the second high-side switch transistor is configured to input a high-voltage side power supply signal, and the second end of the second high-side switch transistor is configured to connect to the gate of the first high-side switch transistor.

[0024] The second bootstrap driving module is configured to drive the second high-side switch transistor to turn on for the first time length to charge the gate capacitor.

[0025] In some embodiments, the second bootstrap driving module comprises a second buffer module, a second diode, and a second bootstrap capacitor.

[0026] The anode of the second diode is configured to input a second low-voltage side power supply signal.

[0027] The upper plate of the second bootstrap capacitor is connected to the cathode of the second diode.

[0028] The upper plate of the second bootstrap capacitor is connected to the first power supply end of the second buffer module.

[0029] The lower plate of the second bootstrap capacitor is connected to the second power supply end of the second buffer module.

[0030] The input end of the second buffer module is configured to receive a second control signal.

[0031] The output end of the second buffer module is connected to the control end of the second high-side switch transistor.

[0032] The second power supply end of the second buffer module is connected to the second end of the second high-side switch transistor.

[0033] In some embodiments, the first control signal and the second control signal are the same control signal, and the second buffer module is configured to drive the second high-side switch transistor to turn on for the first time length based on the first control signal; or

[0034] The first control signal and the second control signal are different control signals, and the second control signal is configured to control the second buffer module to drive the second high-side switch transistor to turn on for the first time length.

[0035] In some embodiments, the second buffer module comprises a digital buffer module configured to perform a time delay based on the first control signal to adjust a starting time of the first time length, wherein the time delay is associated with a first register value of the digital buffer module; and / or

[0036] The first time length is associated with a second register value of the digital buffer module.

[0037] In some embodiments, the on-state current between the first high-side switch transistor first end and the first high-side switch transistor second end is positively correlated with the first time length.

[0038] In some embodiments, the first bootstrap drive module further comprises a clamping component for clamping a voltage difference between the first high-side switch transistor gate and the first high-side switch transistor second end.

[0039] In some embodiments, the clamping component comprises a Zener diode, wherein a cathode of the Zener diode is connected to the first high-side switch transistor gate, and an anode of the Zener diode is connected to the first high-side switch transistor second end.

[0040] According to a second aspect of the embodiments of the present disclosure, a driving chip is provided, and the driving chip comprises at least one driving channel, and each driving channel comprises the driving circuit according to the first aspect.

[0041] According to a third aspect of the embodiments of the present disclosure, a laser radar is provided, and the laser radar comprises the driving circuit according to the first aspect or the driving chip according to the second aspect,

[0042] The laser radar further comprises at least one laser.

[0043] The driving circuit is used for driving the at least one laser, or each driving channel of the driving chip is used for driving the at least one laser.

[0044] According to a fourth aspect of the embodiments of the present disclosure, a driving circuit control method is provided, and the driving circuit control method is applied to the driving circuit according to the first aspect, and the driving circuit control method comprises:

[0045] Controlling the charging module to charge the gate capacitor for a first time length in an associated time period in which the first bootstrap drive module is controlled to turn on the first high-side switch transistor based on the first control signal.

[0046] The embodiment of the present application provides a driving circuit, a driving chip, a control method and a laser radar. The driving circuit comprises a first high-side switch transistor, a first bootstrap driving module for driving the first high-side switch transistor and a charging module. The first high-side switch transistor has a parasitic gate capacitor. A first end of the first high-side switch transistor is used for inputting a high-voltage side power supply signal, and a second end of the first high-side switch transistor is used for connecting a load. The charging module is used for charging the gate capacitor for a first time duration in an associated time period in which the first high-side switch transistor is turned on under the control of the first bootstrap driving module based on a first control signal, so as to compensate for at least part of the electric charge of the gate capacitor charged by the first bootstrap driving module. In this way, in the associated time period in which the first high-side switch transistor is turned on under the control of the first bootstrap driving module based on the first control signal, the charging module can charge the gate capacitor, so as to reduce the amount of electric charge required by the first bootstrap driving module for turning on the first high-side switch transistor, thereby reducing the electric charge loss of the bootstrap capacitor of the first bootstrap driving module, improving the gate-source voltage of the first high-side switch transistor, and further improving the peak current of the high-side switch transistor, so as to meet the driving requirement. Since the electric charge loss of the bootstrap capacitor is small, the bootstrap capacitor can adopt a small capacitance value, so that the capacity and / or the number of the bootstrap capacitor do not need to be increased, and the chip area occupation, parasitic effect and wiring complexity caused by the increase of too many capacitors can be reduced, and the performance of the driving chip is improved.

[0047] The additional aspects and advantages of the embodiments of the present application will be partially given in the following description, partially become obvious from the following description, or be known by the practice of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0048] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application, in which the drawings are not necessarily drawn to scale, and partial features can be enlarged or reduced to show the details of the partial features more clearly. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0049] Figure 1 One of the circuit block diagrams of the driving circuit provided by the embodiments of the present application;

[0050] Figure 2 The charging pulse timing diagram provided by the embodiments of the present application;

[0051] Figure 3 The second circuit block diagram of the driving circuit provided by the embodiments of the present application;

[0052] Figure 4 The third circuit block diagram of the driving circuit provided by the embodiments of the present application;

[0053] Figure 5 Figure 4 is a circuit block diagram of a driving circuit according to an embodiment of the present application;

[0054] Figure 6 Figure 5 is a circuit block diagram of a driving circuit according to an embodiment of the present application;

[0055] Figure 7 Figure 6 is a circuit block diagram of a driving chip according to an embodiment of the present application;

[0056] Figure 8 Figure 7 is a structural diagram of a laser radar according to an embodiment of the present application;

[0057] Figure 9 Figure 8 is a structural diagram of a laser radar according to an embodiment of the present application;

[0058] Figure 10 Figure 9 is a flow diagram of a control method according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the technical solutions and advantages of the present application more obvious and easy to understand, the following will be described in detail by way of listing specific embodiments. The drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as the technical and scientific terms in the technical field to which the present application belongs.

[0060] The embodiments of the present application are not exhaustive, but only illustrate some embodiments, and do not specifically limit the scope of protection of the present application. In the case of no contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily, for example, the scheme after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be exchanged arbitrarily, in addition, the optional implementation manners in an embodiment can be combined arbitrarily; in addition, the embodiments can be combined arbitrarily, for example, the steps of different embodiments or all steps of different embodiments can be combined arbitrarily, an embodiment can be combined with the optional implementation manners of other embodiments.

[0061] In each embodiment of the present application, the terms and / or descriptions of the embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0062] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and not as a limitation of the present application.

[0063] In the embodiments of the present application, an element expressed in singular form, such as "a", "an", "the", "said", "the aforementioned", "the foregoing", "this", and the like, unless otherwise specified, can represent "one and only one", or can represent "one or more", "at least one", and the like. For example, in the case of using articles such as "a", "an", "the" in English, the noun following the article can be understood as a singular expression, or can be understood as a plural expression.

[0064] In the embodiments of the present application, "plurality" refers to two or more.

[0065] In some embodiments, the terms "at least one of", "one or more of", "a plurality of", "multiple", and the like can be replaced with each other.

[0066] The prefix words "first", "second", and the like in the embodiments of the present application are merely used to distinguish different description objects, and do not constitute a limitation on the position, order, priority, value, or content of the description objects. The description of the description objects is referred to the description in the context of the claims or embodiments, and should not be construed as a redundant limitation because of the use of the prefix words. For example, the value of the description object is not limited by the ordinal number, and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different, for example, the description object is "device", and "first device" and "second device" can be the same device or different devices, and their types can be the same or different.

[0067] In some embodiments, the term "connected" can mean that there is a transfer of electrical signals or data between the connected end and the connected end, which can be understood as "electrically connected", "communicatively connected", and the like. The "connection" can be a direct connection between two components, or an indirect connection established through other components, or a communication within two components, or any other possible connection form.

[0068] In some embodiments, the terms "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", "exceeding", and the like can be replaced with each other, and the terms "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", and the like can be replaced with each other.

[0069] In addition, each element, each row, or each column in the table of the embodiments of the present disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0070] It should be noted that the switch transistor (including the first high-side switch transistor, the second high-side switch transistor, and / or the third high-side switch transistor) in the embodiments of the present application can be an N-type transistor (MOS) without contradiction. For the N-type transistor, the on level is high, and the off level is low. That is, when the gate of the N-type transistor is high, the input and output ends thereof are turned on, and when the gate of the N-type transistor is low, the input and output ends thereof are turned off. In a specific implementation, the gate of each switch transistor described above serves as the control end thereof. In the embodiments of the present application, the drain and the source are determined according to the type of the transistor: for the N-type transistor, the drain can serve as the first end, and the source can serve as the second end. In addition, the on level and the off level in the embodiments of the present application are generic. The on level refers to any level that can turn on the transistor, and the off level refers to any level that can turn off / turn off the transistor. It can be understood that the on of the transistor can include the on of the source and the drain of the transistor. The off of the transistor can include the off of the source and the drain of the transistor.

[0071] In a multi-channel high-side laser driver application, the high-side driver switch (i.e., the high-side driver switch transistor) of each drive channel is a kind of switch circuit for connecting the positive pole of the power supply (such as VDD) to the positive end of the load. It is commonly used in applications that require precise control of the on-off of the positive power supply, and is particularly suitable for systems with load ground and low-voltage logic control signals.

[0072] The key application scenario is a laser driver for a laser radar. The high-side driver switch transistor is a performance lever for laser radar. The ranging, resolution, and eye safety limit all depend on how much peak optical power you can squeeze out of the laser pulse. When the laser cathode is grounded, the high-side driver switch transistor can make the laser anode swing cleanly, simplifying optical / mechanical integration. Each drive channel must output a 20A level, 2-10 nanosecond pulse from a 30V-40V power supply.

[0073] The high-side driver switch transistor can select an LDNMOS, which can withstand a voltage of 40V and is less expensive than GaN. The disadvantage of the LDNMOS is that the gate capacitance is very large. When the LDNMOS gate is driven, it requires that the Vgs be kept higher than the rising source node voltage (which rises to about 15-20V) by about 5V during the entire pulse.

[0074] To achieve clean overdrive, each drive channel needs to be equipped with at least 1-3 nF bootstrap capacitor for bootstrap drive circuit. Because the gate-source capacitance Cgs of LDNMOS is 200-500 pF, which means that 1-2.5 nC of charge is needed to raise the gate voltage to +5V, which is about 10 times the demand of GaN devices.

[0075] To meet the 1-3 nF on-chip bootstrap capacitor: it will bring >20 mm² of metal-metal capacitance area; long distance top metal connection will introduce inductance and resistance, slow down the rise time of 5V gate voltage, and cause pulse flattening.

[0076] If the capacitor is externally hung outside the chip, on the one hand, multiple large-size MLCC capacitors and their pins will crowd the circuit board, and on the other hand, about 2-3 nH inductance of each capacitor loop will consume voltage during the fast edge, causing pulse flattening.

[0077] If a smaller bootstrap capacitor is used, the bootstrap capacitor has less charge, resulting in insufficient gate charge. As a result, the gate voltage Vgs drops, which in turn increases the on-resistance Rds(on), reduces the peak current, and shortens the detection distance of the laser radar; the rising / falling edge of the gate voltage Vgs slows down, which expands the light pulse and reduces the depth accuracy.

[0078] Therefore, how to solve the problem of insufficient charging under the load of large gate capacitance and improve the peak current of the high-side switch transistor is a problem to be solved.

[0079] The embodiment of the present disclosure provides a driving circuit 100, as shown in the figure, the driving circuit 100 comprises: a first high-side switch transistor Q1, a first bootstrap drive module 110 and a charging module 120 for driving the first high-side switch transistor Q1; wherein, Figure 1

[0080] The first high-side switch transistor Q1 has a parasitic gate capacitance Cgs; the first end of the first high-side switch transistor Q1 is used for inputting a high-voltage side power supply signal VDDH, and the second end of the first high-side switch transistor Q1 is used for connecting a load;

[0081] The charging module 120 is used for charging the gate capacitance Cgs for a first time length in a time period in which the first bootstrap drive module 110 turns on the first high-side switch transistor Q1 based on the control of a first control signal (Fire1), so as to compensate for at least part of the charge of the gate capacitance Cgs charged by the first bootstrap drive module 110.

[0082] ​In one possible implementation, the drive circuit 100 may include circuitry within a drive chip. A drive chip may include one or more drive channels, and each drive channel may include one drive circuit 100. Each drive channel can be used to drive a different load.

[0083] In one possible implementation, the drive circuit 100 may include a circuit composed of multiple electronic devices (including active electronic devices and / or passive electronic devices).

[0084] In one possible implementation, the load may include at least one of the following: laser D0, LED light, or motor.

[0085] For example, the driving circuit 100 may be a circuit in a multi-channel high-side laser driver used to drive a semiconductor laser diode. Multiple driving channels are integrated on the same integrated circuit chip, and each driving channel has a driving circuit 100. The load of the driving circuit 100 is a laser D0 (such as a semiconductor laser diode). One driving channel on a multi-channel high-side laser driver can drive one or more common-cathode semiconductor laser diodes.

[0086] The first high-side switching transistor Q1 can be implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0087] In one possible implementation, the first high-side switching transistor Q1 can be a laterally diffused metal-oxide-semiconductor (LDMOS) transistor to accommodate larger load currents and withstand excessive drain-source stress. LDMOS has a smaller drain-source on-resistance Rds(on) when turned on. For example, the first high-side switching transistor Q1 can be implemented using an N-channel LDMOS.

[0088] like Figure 1 As shown, the first high-side switching transistor Q1 is powered by a high-voltage power supply. For example, the drain of an N-channel LDMOS receives the high-voltage power supply signal VDDH, the source of the N-channel LDMOS is connected to the load, and the gate voltage of the drain of the N-channel LDMOS is used to control the turn-on and turn-off of the drain and source. The voltage value of the high-voltage power supply signal is higher than the operating voltage value of the first bootstrap driving module 110. Therefore, when the first bootstrap driving module 110 drives the first high-side switching transistor Q1, a bootstrap capacitor is needed to maintain the voltage of the gate of the first high-side switching transistor Q1 (such as the gate of an N-channel LDMOS). Figure 1In some embodiments, the capacitor C0 is used to filter the high-voltage side power signal VDDH. The driving circuit 100 can include or exclude the capacitor C0.

[0089] In one possible implementation, the first end of the first high-side switch transistor Q1 is a drain, and the second end of the first high-side switch transistor Q1 is a source.

[0090] When the first bootstrap driving module 110 drives the first high-side switch transistor Q1 to turn on, the gate capacitor Cgs of the first high-side switch transistor Q1 needs to be charged by the first bootstrap capacitor C1 of the first bootstrap driving module 110 to increase the gate voltage Vg, so as to make the first high-side switch transistor Q1 turn on. The charge of the first bootstrap capacitor C1 of the first bootstrap driving module 110 charges the gate capacitor Cgs. If the first bootstrap capacitor C1 is small and the gate capacitor Cgs is large, the gate voltage cannot reach the predetermined voltage value, thereby increasing the on-resistance Rdson of the first high-side switch transistor Q1 and reducing the peak current. The gate capacitor Cgs can include the parasitic capacitor between the gate of the first high-side switch transistor Q1 and the source of the first high-side switch transistor Q1.

[0091] Here, the charging module 120 can be used to charge the gate capacitor Cgs to compensate for the charge of the gate capacitor Cgs by the first bootstrap capacitor C1, reduce the charge loss of the bootstrap capacitor of the first bootstrap driving module 110 when charging the gate capacitor Cgs, and thus reduce the influence of the large gate capacitor Cgs on the gate voltage Vg when the first bootstrap driving module 110 drives the first high-side switch transistor Q1, and increase the voltage value of the gate voltage.

[0092] In one possible implementation, the time period during which the first bootstrap driving module 110 controls the first high-side switch transistor Q1 to turn on based on the first control signal can include at least one of the following: a time period before the first bootstrap capacitor C1 charges the gate capacitor Cgs to turn on the first high-side switch transistor Q1; or a time period during which the first bootstrap capacitor C1 charges the gate capacitor Cgs. A time period after the first bootstrap capacitor C1 charges the gate capacitor Cgs to turn on the first high-side switch transistor Q1.

[0093] The first duration refers to the duration of charging the gate capacitor Cgs of the first high-side switch transistor Q1 by the charging module 120. The first duration can be adjusted according to specific application requirements, for example, it can be 0 nanoseconds to 3 nanoseconds. The selection of the first duration will affect the current size after the first high-side switch transistor Q1 turns on. The longer the first duration, the more fully the gate capacitor Cgs is charged, and the greater the on-current.

[0094] In a possible implementation, the charging module 120 can charge the gate capacitor Cgs for a first duration after a first control signal enable moment. The enable moment of the first control signal enable moment can be a moment at which the first control signal indicates, through level conversion, that the first bootstrap drive module 110 drives the first high-side switch transistor Q1 to turn on. Here, there can be a drive delay between the first control signal enable moment and the moment at which the first bootstrap drive module 110 drives the first high-side switch transistor Q1 to turn on. The drive delay can include a response duration of the first bootstrap drive module 110, and / or a response duration of the first high-side switch transistor Q1, and the like.

[0095] The charging module 120 can charge the gate capacitor Cgs of the first high-side switch transistor Q1 through a charging pulse. The first duration can be a duration of the charging pulse, that is, a pulse width.

[0096] In a possible implementation, the charging module 120 can draw current from the high-voltage side power supply to charge the gate capacitor Cgs.

[0097] In this way, in the associated time period in which the first bootstrap drive module 110 turns on the first high-side switch transistor Q1 based on the control of the first control signal, the charging module 120 can charge the gate capacitor Cgs, so as to reduce the amount of charge required for the first bootstrap drive module 110 to turn on the first high-side switch transistor Q1, thereby reducing the charge loss of the bootstrap capacitor of the first bootstrap drive module 110, improving the gate-source voltage of the first high-side switch transistor Q1, and further improving the peak current of the high-side switch transistor, to meet the driving requirement. Since the charge loss of the bootstrap capacitor is less, the bootstrap capacitor can have a smaller capacitance value, so that it is not necessary to increase the capacity and / or quantity of the bootstrap capacitor, and the chip area occupation, parasitic effect, and wiring complexity caused by excessive increase of the capacitor can be reduced, and the performance of the driving chip can be improved.

[0098] In some embodiments, the charging module 120 is configured to perform one of the following:

[0099] charge the gate capacitor Cgs before a start moment at which the first bootstrap drive module 110 controls the first high-side switch transistor Q1 to turn on, and stop charging the gate capacitor Cgs in the on duration;

[0100] charge the gate capacitor Cgs for a first duration from the start moment;

[0101] charge the gate capacitor Cgs for a first duration after the start moment, where an end moment of the first duration is before an end moment of the on duration;

[0102] charge the gate capacitor Cgs for a first duration before the start moment.

[0103] In a possible implementation, the first duration is less than a turn-on duration of the first high-side switch transistor Q1. Specifically, Figure 2 is a timing diagram of the turn-on duration of the first high-side switch transistor Q1 and the charging pulse of the charging module 120. As Figure 2 indicated, the high level in the timing P represents the turn-on state of the first high-side switch transistor Q1. The high level in the timings S1-S2 represents the charging pulse, and the duration of the high level is the first duration. The start time ts of the turn-on of the first high-side switch transistor Q1 is approximately the start time of the charging of the gate capacitor Cgs by the first bootstrap drive module 110.

[0104] As Figure 2 indicated, the start time of the charging pulse S1 is before the start time ts of the turn-on of the first high-side switch transistor Q1, the end time of the charging pulse is after the start time ts of the turn-on of the first high-side switch transistor Q1, and before the end time te of the turn-on of the first high-side switch transistor Q1. That is, the charging module 120 charges the gate capacitor Cgs before the first bootstrap drive module 110 turns on the first high-side switch transistor Q1, and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap drive module 110 is turned on. In this way, the lost charge of the charging of the gate capacitor Cgs by the first bootstrap drive module 110 can be reduced, the gate-source voltage of the first high-side switch transistor Q1 can be improved, and the peak current of the high-side switch transistor can be improved to meet the drive requirement.

[0105] As Figure 2 indicated, the start time of the charging pulse S2 is the same as the start time ts of the turn-on of the first high-side switch transistor Q1, the end time of the charging pulse is after the start time ts of the turn-on of the first high-side switch transistor Q1, and before the end time te of the turn-on of the first high-side switch transistor Q1. That is, the charging module 120 charges the gate capacitor Cgs at the same time as the first bootstrap drive module 110, and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap drive module 110 is turned on. In this way, the lost charge of the charging of the gate capacitor Cgs by the first bootstrap drive module 110 can be reduced, the gate-source voltage of the first high-side switch transistor Q1 can be improved, and the peak current of the high-side switch transistor can be improved to meet the drive requirement.

[0106] As Figure 2As shown, the charging pulse S3 is located after the starting time ts of the first high-side switch transistor Q1 being turned on and before the ending time te of the first high-side switch transistor Q1 being turned on. That is, the charging module 120 charges the gate capacitor Cgs after the first bootstrap drive module 110 and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap drive module 110 is turned on. In this way, the charge amount of the gate capacitor Cgs can be increased, so that the gate-source voltage of the first high-side switch transistor Q1 can be increased, and then the peak current of the high-side switch transistor can be increased to meet the driving requirement.

[0107] As shown in FIG. 6, the first bootstrap drive module 110 includes a first bootstrap capacitor C1, a first buffer module U1, and a first diode D1. Figure 2 As shown, the charging pulse S4 is located before the starting time ts of the first high-side switch transistor Q1 being turned on, that is, the charging module 120 completes the charging of the gate capacitor Cgs before the first bootstrap drive module 110 charges the gate capacitor Cgs, and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap drive module 110 is turned on. In this way, the charge amount of the gate capacitor Cgs charged by the first bootstrap drive module 110 can be reduced, so that the gate-source voltage of the first high-side switch transistor Q1 can be increased, and then the peak current of the high-side switch transistor can be increased to meet the driving requirement.

[0108] In some embodiments, as shown in FIG. 6, the first bootstrap drive module 110 includes a first bootstrap capacitor C1, a first buffer module U1, and a first diode D1. Figure 1

[0109] The anode of the first diode D1 is configured to input a first low-voltage side power supply signal VDD1.

[0110] The upper plate of the first bootstrap capacitor C1 is connected to the cathode of the first diode D1.

[0111] The upper plate of the first bootstrap capacitor C1 is connected to the first power supply end of the first buffer module U1.

[0112] The lower plate of the first bootstrap capacitor C1 is connected to the second power supply end of the first buffer module U1.

[0113] The input end of the first buffer module U1 is configured to input the first control signal.

[0114] The output end of the first buffer module U1 is connected to the gate of the first high-side switch transistor Q1.

[0115] The second power supply end of the first buffer module U1 is connected to the second end of the first high-side switch transistor Q1.

[0116] ​Here, the voltage value of the first low-side power supply signal VDD1 is lower than the voltage value of the high-side power supply signal VDDH. For example, the voltage value of the first low-side power supply signal VDD1 is 5V, and the voltage value of the high-side power supply signal VDDH can be greater than 20V, such as 30V. In this way, the driving channel can operate at a lower voltage, reducing the operating loss.

[0117] The gate voltage Vg of the first high-side switch transistor Q1 is determined by the voltage between the two plates of the first bootstrap capacitor C1. Before the first control signal enables the first bootstrap driving module 110, the first low-side power supply signal VDD1 charges the first bootstrap capacitor C1 through the first diode D1. The voltage between the two plates of the first bootstrap capacitor C1 can be higher than the threshold voltage (Vth) at which the first high-side switch transistor Q1 is turned on.

[0118] When the first control signal enables the first bootstrap driving module 110, the voltage at the upper plate of the first bootstrap capacitor C1 is the sum of the voltage value of the first low-side power supply signal VDD1 and the voltage value of the output voltage Vout of the source of the first high-side switch transistor Q1 when the first control signal enables the first bootstrap driving module 110 to drive the first high-side switch transistor Q1 to be open, thereby maintaining the first high-side switch transistor Q1 in an open state. Here, when the first high-side switch transistor Q1 is turned on, the output voltage Vout of the source of the first high-side switch transistor Q1 is the difference between the voltage value of the high-side power supply signal VDDH and the turn-on voltage value of the first high-side switch transistor Q1.

[0119] In one possible implementation, the first buffer module U1 can be used for at least one of the following:

[0120] During the turn-on period of the first high-side switch transistor Q1, the gate of the first high-side switch transistor Q1 and the upper plate of the first bootstrap capacitor C1 are turned on (e.g., by MOS). In this way, the voltage between the two plates of the first bootstrap capacitor C1 can turn on the first high-side switch transistor Q1;

[0121] During the turn-off period of the first high-side switch transistor Q1, the gate of the first high-side switch transistor Q1 and the upper plate of the first bootstrap capacitor C1 are turned off, and the gate of the first high-side switch transistor Q1 and the source of the first high-side switch transistor Q1 are turned on (e.g., by MOS). In this way, the gate charge can be discharged, improving the turn-off speed of the first high-side switch transistor Q1.

[0122] In one possible implementation, the first buffer module U1 can be used to delay the first control signal. The first buffer module U1 can adjust the buffer duration between the time when the first control signal reaches the first buffer module U1 and the time when the signal output from the output end of the first buffer module U1 turns on or turns off the first high-side switch transistor Q1 by internal delay or the like.

[0123] In some embodiments, as shown in FIG. 1, the charging module 120 includes a second bootstrap drive module 121 and a second high-side switch transistor Q2; wherein, Figure 3

[0124] A first end of the second high-side switch transistor Q2 is configured to input a high-voltage side power supply signal VDDH, and a second end of the second high-side switch transistor Q2 is configured to connect a gate of the first high-side switch transistor Q1.

[0125] The second bootstrap drive module 121 is configured to drive the second high-side switch transistor Q2 to turn on for the first time duration, so as to charge the gate capacitance Cgs.

[0126] Here, the second high-side switch transistor Q2 can be configured to draw current from the high-voltage side power supply for charging the gate capacitance Cgs. The second bootstrap drive module 121 can control the turn-on and turn-off of the second high-side switch transistor Q2 through the gate of the second high-side switch transistor Q2. The second bootstrap drive module 121 can control the second high-side switch transistor Q2 to turn on for the first time duration, so as to charge the gate capacitance Cgs with the high-voltage side power supply for the first time duration.

[0127] In one possible implementation, the first end of the second high-side switch transistor Q2 is a drain, and the second end of the second high-side switch transistor Q2 is a source.

[0128] As shown in FIG. 1, the charging module 120 includes a second bootstrap drive module 121 and a second high-side switch transistor Q2; wherein, Figure 3 ​As shown, when the first high-side switch transistor Q1 is turned on, the voltage of the lower plate of the first bootstrap capacitor C1 rises to the voltage value of the output voltage Vout of the source of the first high-side switch transistor Q1. When the first high-side switch transistor Q1 is turned on, the first buffer module U1 turns on the upper plate of the first bootstrap capacitor C1 and the gate of the first high-side switch transistor Q1. The voltage value of the upper plate of the first bootstrap capacitor C1 is the sum of the voltage value of the first low-voltage side power supply signal VDD1 and the voltage value of the output voltage Vout of the source of the first high-side switch transistor Q1. Then, the voltage value of the gate voltage Vg of the first high-side switch transistor Q1 is the sum of the voltage value of the first low-voltage side power supply signal VDD1 and the voltage value of the output voltage Vout of the source of the first high-side switch transistor Q1. The gate of the first high-side switch transistor Q1 is connected to the source of the second high-side switch transistor Q2. Therefore, the voltage value of the source of the second high-side switch transistor Q2 is the sum of the voltage value of the first low-voltage side power supply signal VDD1 and the voltage value of the output voltage Vout of the source of the first high-side switch transistor Q1. Therefore, a higher voltage value is required to control the turn-on and turn-off of the second high-side switch transistor Q2. Therefore, when the second bootstrap drive module 121 drives the second high-side switch transistor Q2, a bootstrap capacitor is required to maintain the voltage of the gate of the second high-side switch transistor Q2.

[0129] Since the second high-side switch transistor Q2 is used to charge the gate capacitance Cgs of the first high-side switch transistor Q1, a smaller current can be used for charging. Therefore, the power of the second high-side switch transistor Q2 can be smaller than the power of the first high-side switch transistor Q1. For example, the power of the second high-side switch transistor Q2 can be 1 / 5~1 / 10 of the power of the first high-side switch transistor Q1.

[0130] In some embodiments, as shown in FIG. 1, the second bootstrap drive module 121 includes a second buffer module U2, a second diode D2, and a second bootstrap capacitor C2. Figure 4

[0131] The anode of the second diode D2 is used to input a second low-voltage side power supply signal VDD2.

[0132] The upper plate of the second bootstrap capacitor C2 is connected to the cathode of the second diode D2.

[0133] The upper plate of the second bootstrap capacitor C2 is connected to the first power supply end of the second buffer module U2.

[0134] The lower plate of the second bootstrap capacitor C2 is connected to the second power supply end of the second buffer module U2.

[0135] The input end of the second buffer module U2 is used for a second control signal (Fire2).​

[0136] The output end of the second buffer module U2 is connected with the control end of the second high-side switch transistor Q2.

[0137] The second power end of the second buffer module U2 is connected with the second end of the second high-side switch transistor Q2.

[0138] Here, the voltage value of the second low-voltage-side power signal VDD2 is lower than the voltage value of the high-voltage-side power signal VDDH. The second bootstrap drive module 121 can work at a lower voltage, reducing the working loss.

[0139] In a possible implementation, the first low-voltage-side power signal VDD1 and the second low-voltage-side power signal VDD2 can be the same low-voltage-side power signal.

[0140] The gate voltage of the second high-side switch transistor Q2 is determined by the voltage between the two poles of the second bootstrap capacitor C2. Before the second control signal enables the second bootstrap drive module 121, the second low-voltage-side power signal VDD2 charges the second bootstrap capacitor C2 through the second diode D2. The voltage between the two poles of the second bootstrap capacitor C2 is higher than the threshold voltage (Vth) at which the second high-side switch transistor Q2 is turned on.

[0141] When the second high-side switch transistor Q2 is turned on, the lower pole of the second bootstrap capacitor C2 is connected with the gate of the first high-side switch transistor Q1, and the voltage between the two poles of the second bootstrap capacitor C2 is the sum of the voltage value of the second low-voltage-side power signal VDD2 and the voltage value of the gate voltage Vg of the first high-side switch transistor Q1.

[0142] In a possible implementation, the second buffer module U2 is configured to at least one of the following: during the on period of the second high-side switch transistor Q2, turn on (e.g., by MOS) the gate of the second high-side switch transistor Q2 and the upper pole of the second bootstrap capacitor C2. In this way, the voltage between the two poles of the second bootstrap capacitor C2 can turn on the second high-side switch transistor Q2; during the off period of the second high-side switch transistor Q2, turn off the gate of the second high-side switch transistor Q2 and the upper pole of the second bootstrap capacitor C2, and turn on (e.g., by MOS) the gate of the second high-side switch transistor Q2 and the source of the second high-side switch transistor Q2. In this way, the gate charge can be released, and the off speed of the second high-side switch transistor Q2 can be improved.

[0143] In a possible implementation, the second buffer module U2 can be configured to delay the second control signal. The second buffer module U2 can adjust the buffer time length between the time when the second control signal reaches the second buffer module U2 and the time when the output signal of the second buffer module U2 enables the second high-side switch transistor Q2 to be turned on or turned off.

[0144] In a possible implementation, the second buffer module U2 can control the time domain position of the on period of the second high-side switch transistor Q2, that is, control the position relationship between the charging pulse and the on period of the first high-side switch transistor Q1.

[0145] In this way, the charging of the gate capacitance Cgs of the first high-side switch transistor Q1 is completed by the second high-side switch transistor Q2, thereby reducing the amount of charge for turning on the first high-side switch transistor Q1, reducing the charge loss of the bootstrap capacitance of the first bootstrap drive module 110, improving the gate-source voltage of the first high-side switch transistor Q1, and further improving the peak current of the high-side switch transistor to meet the drive requirement.

[0146] In some embodiments, the first control signal and the second control signal are the same control signal, and the second buffer module U2 is configured to drive the second high-side switch transistor Q2 to be turned on for the first time length based on the first control signal; or

[0147] The first control signal and the second control signal are different control signals, and the second control signal is configured to control the second buffer module U2 to drive the second high-side switch transistor Q2 to be turned on for the first time length.

[0148] Here, the first control signal for controlling the first buffer module U1 and the second control signal for controlling the second buffer module U2 can be the same control signal. After being triggered by the first control signal (the second control signal), the second buffer module U2 can adjust the time domain position relationship between the charging pulse and the on period of the first high-side switch transistor Q1 by adjusting the response time length of the second buffer module U2.

[0149] The first control signal for controlling the first buffer module U1 and the second control signal for controlling the second buffer module U2 can be different control signals, and the time domain position relationship between the charging pulse of the charging module 120 and the on period of the first high-side switch transistor Q1 can be adjusted by adjusting the time domain position relationship between the first control signal and the second control signal. For example, the second buffer module U2 can have a fixed response time length, and thus the time domain position of the charging pulse of the charging module 120 can be adjusted by adjusting the triggering time of the second control signal.

[0150] Thus, the time domain position of the charging pulse is adjusted by the second buffer module U2 or by the second control signal to meet different charging requirements and improve charging flexibility.

[0151] In some embodiments, the second buffer module U2 includes a digital buffer module configured to delay the first control signal based on a first register value of the digital buffer module to adjust the start time of the first time length.

[0152] The first time length is associated with a second register value of the digital buffer module.

[0153] The digital buffer module can adjust the start time of the first time length by adjusting the response time of the digital buffer module.

[0154] The first register value of the second buffer module U2 can be set by a first register. Different first register values correspond to different time delays.

[0155] The second register value of the second buffer module U2 can be set by a second register. Different second register values correspond to different first time lengths.

[0156] For example, the second register can occupy two bits to indicate four different first time lengths, such as 0 nanoseconds, 1 nanoseconds, 2 nanoseconds, or 3 nanoseconds.

[0157] Thus, the time domain position and / or the pulse width of the charging pulse are adjusted by the digital buffer module to flexibly adjust the charging of the gate capacitor Cgs and meet different requirements.

[0158] In some embodiments, the on-current between the first end of the first high-side switch transistor Q1 and the second end of the first high-side switch transistor Q1 is positively correlated with the first time length.

[0159] Here, the longer the first time length, the longer the charging time of the gate capacitor Cgs by the charging module 120, and the higher the gate-source voltage of the first high-side switch transistor Q1, thereby increasing the on-current of the high-side switch transistor. The shorter the first time length, the shorter the charging time of the gate capacitor Cgs by the charging module 120, and the lower the charge of the first bootstrap capacitor C1 for charging the gate capacitor Cgs, thereby the voltage across the first bootstrap capacitor C1 is smaller, and the gate-source voltage of the first high-side switch transistor Q1 is lower, thereby the on-current of the first high-side switch transistor Q1 is smaller.

[0160] In some embodiments, as Figure 5As shown, the first bootstrap drive module 110 further includes a clamping component 111 for clamping a voltage difference between the gate of the first high-side switch transistor Q1 and the second end of the first high-side switch transistor Q1.

[0161] When the second high-side switch transistor Q2 is turned on, the gate of the first high-side switch transistor Q1 is connected with the high-voltage side power supply signal VDDH. On the one hand, when the first high-side switch transistor Q1 is not turned on, a high gate-source voltage difference of the first high-side switch transistor Q1 is generated, thereby causing a risk of damage to the first high-side switch transistor Q1. On the other hand, when the first buffer module U1 is turned on, the high-voltage side power supply signal VDDH directly flows into the upper plate of the first bootstrap capacitor C1, thereby causing a risk of failure of the first bootstrap drive module 110. Therefore, the clamping component 111 can be arranged between the gate of the first high-side switch transistor Q1 and the second end (source) of the first high-side switch transistor Q1, for clamping the voltage difference between the gate of the first high-side switch transistor Q1 and the second end (source) of the first high-side switch transistor Q1.

[0162] The clamping component 111 can be implemented by a diode, a transistor, a clamping chip, etc.

[0163] The clamping component 111 can keep the voltage between the gate of the first high-side switch transistor Q1 and the second end of the first high-side switch transistor Q1 within a safe range, improve the reliability of the first high-side switch transistor Q1, and reduce the risk of failure of the first bootstrap drive module 110.

[0164] In some embodiments, as Figure 6 As shown, the clamping component 111 includes a Zener diode ZD1, wherein the cathode of the Zener diode ZD1 is connected with the gate of the first high-side switch transistor Q1, and the anode of the Zener diode ZD1 is connected with the second end (source) of the first high-side switch transistor Q1.

[0165] In one possible implementation, the Zener diode ZD1 can keep the voltage between the gate of the first high-side switch transistor Q1 and the second end (source) of the first high-side switch transistor Q1 within a range of 5.7V.

[0166] In one possible implementation, the first control signal and / or the second control signal can be sent by a controller for controlling the driving of the load by the driving circuit.

[0167] A specific example is provided in combination with the above-described embodiments to specifically describe the present application.

[0168] As shown in the above embodiments, the driving circuit includes a charging module. Figure 6 As shown in the above embodiments, the driving circuit includes a charging module.

[0169] The ground reference of the charging module is the gate of the first high-side switch transistor (the gate voltage varies with the source voltage).

[0170] The second bootstrap capacitor in the charging module uses a 50-100 pF capacitor to store a fixed +5 V voltage. That is, the second low-voltage side power signal is 5 V.

[0171] The drain of the second high-side switch transistor is connected to the high-voltage side power signal, and the source of the second high-side switch transistor is connected to the gate of the first high-side switch transistor.

[0172] The size of the second high-side switch transistor is about 1 / 5 to 1 / 10 of the first high-side switch transistor, corresponding to Rds(on) ≈ 1-2 Ω.

[0173] The second buffer module converts the second control signal into a 5 V or 0 V voltage that controls the conduction or cutoff of the second high-side switch transistor.

[0174] The gate of the first high-side switch transistor is clamped:

[0175] A 5.7 V Zener diode is placed between the gate and the source of the first high-side switch transistor; used to prevent overshoot.

[0176] The 5 stages controlled by the drive circuit are shown in Table 1:

[0177] Table 1

[0178]

[0179] The charging module can adjust the voltage Vgs of the gate and source of the first high-side switch transistor.

[0180] When the second high-side switch transistor is turned on, the gate of the second high-side switch transistor will charge the gate of the first high-side switch transistor at a current Ig = (Vhv / Rds(on,SC)). Where Ig represents the charging current, Vhv represents the voltage value of the high-voltage side power signal, and Rds(on,SC) represents the on-resistance between the drain and source of the second high-side switch transistor.

[0181] The longer the pulse width (i.e., the first duration) of the charging pulse of the charging module, the higher the gate voltage of the first high-side switch transistor, until it is clamped by the 5.7 V Zener.

[0182] The gate voltage of the first high-side switch transistor after the charging pulse is approximately: Vsrc + ΔQ / Cgs, where ΔQ = Ig × tsc. Where Vsrc represents the initial voltage of the gate of the first high-side switch transistor. ΔQ represents the amount of charging charge. tsc represents the first duration (pulse width of the charging pulse).

[0183] Thus Vgs∝tsc; for example, for a 300 pF gate capacitance, a 2 ns change in pulse width adjusts Vgs by about 0.5 V.

[0184] By programming tsc in steps of 0.5-1 ns, the peak laser current can be corrected for process variations, or multi-level optical power modulation can be achieved.

[0185] The tsc code for each channel is stored in an on-chip register; factory testing can sweep the pulse width, measure the optical output, and lock the code - no external correction elements are needed.

[0186] Dynamic power control is possible; firmware can adjust tsc in real time, on the fly, to compensate for temperature or eye safety dimming requirements, with a delay of microseconds.

[0187] The advantage is that while preserving the ultra-fast response (<2 ns) advantage of the super-charge architecture, it achieves a laser current accuracy control of ±5%, accommodating PVT variations.

[0188] With the scheme of the present application, the first high-side switch transistor gate rise time is reduced from 8-15 ns to ≤2 ns. Since there is no need to increase the capacitance value of the first bootstrap capacitor, the silicon area of the driving chip can be saved: from an increase of >20 mm2 of the capacitor to <0.3-0.5 mm2 of a tiny FET + a tiny capacitor. There is no need to set a capacitor outside the chip. External device requirement: 8 MLCCs → 0. Reduce loop inductance: multiple nH → <500 pH (on-chip). Peak laser current loss: eliminated; can maintain full 20 A current at high repetition frequency (PRF). By directly injecting charge from the high-voltage power rail through the charge module, parasitic parameters are effectively reduced, protecting the first high-side switch transistor gate, while easily supporting the expansion of high-channel-count laser radar SoCs.

[0189] Since the Vgs of the first high-side switch transistor is only about 5 V, even if Vgs changes by 0.5 V (fine-tuned by a 1-2 ns charge pulse width), it can cause a current change of several amperes.

[0190] By adjusting the first time length, the actual data of the peak current of the first high-side switch transistor is adjusted as shown in Table 2:

[0191] Table 2

[0192]

[0193] In terms of the structure of the driving chip:

[0194] A charge module is provided for each driving channel. The local reference node of the charge module is the gate of the first high-side switch transistor; it rises together with the source voltage during laser emission.

[0195] The second bootstrap capacitor in the charging module is about 1 / 10 of the gate capacitance (Cgs) of the first high-side switch transistor; it provides the energy required for the control circuitry at the first high-side switch transistor gate.

[0196] The second high-side switch transistor drain is connected to the 30-40V supply rail, and the second high-side switch transistor source is connected to the first high-side switch transistor gate. The second high-side switch transistor size is about 10-20% of the first high-side switch transistor, which can provide a large current pulse in a very small silicon area.

[0197] The second buffer module in the second bootstrap drive module converts the second control signal pulse into a 0 / 5V drive signal relative to the second high-side switch transistor gate node.

[0198] The first high-side switch transistor gate-source clamp (≈5.7V Zener or equivalent device) is integrated to limit the Vgs voltage of the first high-side switch transistor under all process / voltage / temperature (PVT) variations and pulse width error conditions, ensuring its safety.

[0199] The charging module provides a time-limited charging pulse sequence. The second high-side switch transistor is controlled to turn on within a narrow window (about 1-3ns), inject charge into the first high-side switch transistor gate from the high-voltage side power supply, and then completely turn off.

[0200] The structure size ratio of robust performance:

[0201] The second bootstrap capacitor is ≤10-20% of the first high-side switch transistor gate capacitance.

[0202] The Rds(on) of the second high-side switch transistor is about 1 / 5 to 1 / 10 of the first high-side switch transistor.

[0203] Automatic charging path for the second bootstrap capacitor:

[0204] Support for pulse repetition frequency ≥10MHz without external components or additional pins.

[0205] Digital fine-tuning of the charging pulse width (achieved by setting the second buffer module):

[0206] Programmable registers per channel to compensate for process, voltage, temperature, and aging variations. Scalability without external bootstrap capacitors. This architecture only adds <0.3-0.5mm² of silicon area per channel, without the need for any additional packaging pins, allowing a chip to integrate 8 or more high-side laser drive channels.

[0207] Charging pulse width modulation charging (PWMSC) is achieved through the charging module.

[0208] A multi-channel high-side laser driver, whose peak laser diode current (first high-side switch transistor peak current) is set by digitally adjusting the duration of a charging pulse.

[0209] The charging pulse drives the second high-side switch transistor, thereby establishing an adjustable gate-source voltage on the first high-side switch transistor.

[0210] Key functional points:

[0211] Time-limited pulse (0-10 ns), issued in sync with the laser trigger command.

[0212] The first high-side switch transistor gate charge is proportional to the charging pulse's pulse width. The first high-side switch transistor Vgs and the first high-side switch transistor on-current Ilaser vary in a predictable ratio.

[0213] The integrated first high-side switch transistor gate clamp ensures that the first high-side switch transistor's Vgs does not exceed safe limits, even at maximum pulse width.

[0214] Performance metric range:

[0215] For example: tsc=0 ns => ~1 A; tsc=3 ns => > 20 A (clamp kicks in).

[0216] <2 ns electrical rise time is maintained at any programmed level.

[0217] Innovation of the charging pulse pulse width modulation charge (PWMSC)

[0218] Digital fine-tuning register:

[0219] Per-channel encoding (e.g., 3-5 bits) is stored in non-volatile or OTP memory, used to eliminate the effects of process differences or mismatches.

[0220] Dynamic power regulation application scenarios:

[0221] Firmware controls tsc updates to support: 1 temperature compensation; 2 eye safety "low beam" vs. "high beam"; 3 multi-bounce / return LiDAR pulse modes.

[0222] Calibration and testing methods; factory flow iterates scanning tsc, measuring light output, and locking the value - no external DACs required.

[0223] Closed-loop adaptation: Monitor photodiode current or power supply rail voltage drop feedback to automatically adjust tsc in real time.

[0224] Pulse width timing range limits: tsc programmable range from 0 ns up to gate clamp turn-on (approx. Vgs ≈ 5.7 V), guaranteeing safe operation.

[0225] Channel scalability: the architecture supports ≥8 channels without increasing the package pins, and each channel reuses the same on-chip timing.

[0226] Embodiments of the present disclosure provide a driving chip, such as Figure 7 As shown, the driving chip 200 includes at least one driving channel 210; the driving channel 210 includes the driving circuit 100. The implementation of the driving circuit 100 is as described in any of the above embodiments, which will not be repeated here.

[0227] Embodiments of the present disclosure provide a laser radar, such as Figure 8 The laser radar 10 includes the driving circuit 100, or, as shown Figure 9 The laser radar 10 includes the driving chip 200.

[0228] The laser radar further includes at least one laser.

[0229] In one possible implementation, the driving chip 200 includes at least one driving channel 210; the driving channel 210 includes the driving circuit 100.

[0230] The driving circuit 100 is used to drive at least one laser; or one driving channel 210 of the driving chip 200 is used to drive at least one laser.

[0231] The specific implementation of the driving circuit 100 or the driving chip 200 is as described in any of the above embodiments, which will not be repeated here.

[0232] The driving circuit 100 or the driving chip 200 can be applied to the following scenarios:

[0233] 1. Vertical-Cavity Surface-Emitting Laser (VCSEL) power supply control.

[0234] The high-side switch transistor (first high-side switch transistor) is used to controllably connect the positive pole of the power supply (such as 5V / 12V) to the anode of the VCSEL laser, for laser pulse emission control.

[0235] Supports fast switching, realizes precise control of short pulses (usually 1ns~10ns), and is used for high-precision ranging.

[0236] 2. Optical power modulation.

[0237] In cooperation with the PWM or pulse modulation signal, the light output power or pulse width is accurately adjusted by controlling the on-time of the high-side switch transistor (first high-side switch transistor), to realize functions such as near-field / far-field power control.

[0238] 3. A multi-channel laser scanning system.

[0239] In a multi-beam or MEMS scanning lidar, high side transistors (first high side transistors) control lasers of multiple driving channels respectively, supporting time division multiplexing (TDM) or space division multiplexing (SDM) strategies.

[0240] 4. Laser safety protection control.

[0241] Upon receiving an abnormal signal (such as overheating, overcurrent, system abnormality), the high side transistors (first high side transistors) can quickly disconnect the laser power supply path, realizing emergency shutdown.

[0242] Embodiments of the present disclosure provide a driving circuit control method, applied to a driving circuit; as shown in the figure, the driving circuit 100 control method comprises: Figure 10

[0243] Step 1001: Control the charging module to charge the gate capacitor for a first time duration within the time period when the first bootstrap driving module turns on the associated first high side transistor based on the first control signal.

[0244] In one possible implementation, the driving chip comprises a driving circuit. The driving circuit and / or the driving chip embodiment is as described in any of the above embodiments, which will not be repeated here.

[0245] In one possible implementation, the driving circuit control method can be executed by a controller.

[0246] In one possible implementation, the driving circuit comprises a controller.

[0247] In one possible implementation, the controller is independent of the driving circuit.

[0248] The embodiment of the driving circuit driving the load under the control of the controller is as described in any of the above embodiments, which will not be repeated here.

[0249] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be mutually referred to.

[0250] ​In the description of the specification, the description of "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the present application. In the description of the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples.

[0251] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, characterized in that, The driving circuit includes: a first high-side switching transistor, a first bootstrap driving module for driving the first high-side switching transistor, and a charging module; wherein... The first high-side switching transistor has a parasitic gate capacitance; the first terminal of the first high-side switching transistor is used to input a high-voltage side power supply signal, and the second terminal of the first high-side switching transistor is used to connect a load; The charging module is used to charge the gate capacitor for a first duration during the associated time period when the first bootstrap driving module turns on the first high-side switching transistor based on the first control signal, so as to compensate for at least part of the charge charged by the first bootstrap driving module to the gate capacitor; wherein, the output terminal of the first bootstrap driving module is connected to the gate of the first high-side switching transistor, and the output terminal of the charging module is connected to the gate of the first high-side switching transistor. The charging module is used to draw current from the high-voltage side power supply signal to charge the gate capacitor. The first bootstrap driving module uses the first low-voltage side power supply signal as the operating voltage, and the voltage value of the first low-voltage side power supply signal is lower than the voltage value of the high-voltage side power supply signal.

2. The driving circuit according to claim 1, characterized in that, The charging module is used for one of the following: The gate capacitor is charged before the start time when the first bootstrap driving module controls the first high-side switching transistor to turn on, and the charging of the gate capacitor is stopped during the turn-on time. The gate capacitor is charged for a first duration starting from the stated start time; The gate capacitor is charged for a first duration after the start time, wherein the end time of the first duration is before the end time of the conduction duration; The gate capacitor is charged for a first duration before the start time.

3. The driving circuit according to claim 1, characterized in that, The first bootstrap driving module includes: a first bootstrap capacitor, a first buffer module, and a first diode; wherein... The anode of the first diode is used to input a first low-voltage side power supply signal; The upper plate of the first bootstrap capacitor is connected to the cathode of the first diode; The upper plate of the first bootstrap capacitor is connected to the first power supply terminal of the first buffer module; The lower plate of the first bootstrap capacitor is connected to the second power supply terminal of the first buffer module; The input terminal of the first buffer module is used to input the first control signal; The output terminal of the first buffer module is connected to the gate of the first high-side switching transistor; The second power supply terminal of the first buffer module is connected to the second terminal of the first high-side switching transistor.

4. The driving circuit according to claim 1, characterized in that, The charging module includes a second bootstrap driving module and a second high-side switching transistor; wherein... The first terminal of the second high-side switching transistor is used to input a high-voltage side power supply signal, and the second terminal of the second high-side switching transistor is used to connect to the gate of the first high-side switching transistor. The second bootstrap driving module is used to drive the second high-side switching transistor to conduct for the first duration in order to charge the gate capacitor.

5. The driving circuit according to claim 4, characterized in that, The second bootstrap driving module includes: a second buffer module, a second diode, and a second bootstrap capacitor; The anode of the second diode is used to input the second low-voltage side power supply signal; The upper plate of the second bootstrap capacitor is connected to the cathode of the second diode; The upper plate of the second bootstrap capacitor is connected to the first power supply terminal of the second buffer module; The lower plate of the second bootstrap capacitor is connected to the second power supply terminal of the second buffer module; The input terminal of the second buffer module is used for the second control signal. The output terminal of the second buffer module is connected to the control terminal of the second high-side switching transistor; The second power supply terminal of the second buffer module is connected to the second terminal of the second high-side switching transistor.

6. The driving circuit according to claim 5, characterized in that, The first control signal and the second control signal are the same control signal, and the second buffer module is used to drive the second high-side switching transistor to conduct for the first duration based on the first control signal; or; The first control signal and the second control signal are different control signals. The second control signal is used to control the second buffer module to drive the second high-side switching transistor to conduct for the first duration.

7. The driving circuit according to claim 6, characterized in that, The second buffer module includes a digital buffer module for adjusting the start time of the first duration based on the first control signal by performing a time delay, wherein the time delay is associated with a first register value of the digital buffer module; and / or The first duration is associated with the second register value of the digital buffer module.

8. The driving circuit according to claim 1, characterized in that, The conduction current between the first terminal of the first high-side switching transistor and the second terminal of the first high-side switching transistor is positively correlated with the first duration.

9. The driving circuit according to any one of claims 1 to 8, characterized in that, The first bootstrap driving module further includes a clamping component for clamping the voltage difference between the gate of the first high-side switching transistor and the second terminal of the first high-side switching transistor.

10. The driving circuit according to claim 9, characterized in that, The clamping component includes a Zener diode, wherein the cathode of the Zener diode is connected to the gate of the first high-side switching transistor, and the anode of the Zener diode is connected to the second terminal of the first high-side switching transistor.

11. A driver chip, characterized in that, The driver chip includes at least one driver channel, and each driver channel includes a driver circuit as described in any one of claims 1 to 10.

12. A lidar, characterized in that, Includes the driving circuit as described in any one of claims 1 to 10 or the driving chip as described in claim 11. The lidar also includes at least one laser; The driving circuit is used to drive at least one laser; or each driving channel of the driving chip is used to drive at least one laser.

13. A method for controlling a drive circuit, characterized in that, Applied to the drive circuit as described in any one of claims 1 to 10; The drive circuit control method includes: The control charging module charges the gate capacitor for a first duration during the associated time period when the first bootstrap driving module controls the first high-side switching transistor to turn on based on the first control signal.

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