A two-dimensional jfet device and method of fabrication thereof

Abstract

The application relates to a two-dimensional JFET device and a manufacturing method thereof. The two-dimensional JFET device comprises an insulating substrate, a few-layer two-dimensional ferroelectric semiconductor thin film located on the surface of the insulating substrate, a two-dimensional semimetal thin film located on the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor thin film, and a metal electrode, which is divided into a source electrode, a drain electrode and a gate electrode. The source electrode and the drain electrode are respectively located on the surface of the few-layer two-dimensional ferroelectric semiconductor thin film on the two sides of the two-dimensional semimetal thin film, and the gate electrode is located on the surface of the two-dimensional semimetal thin film. The two-dimensional JFET device utilizes the high conductivity of the two-dimensional semimetal, the spontaneous polarization, the adjustable control characteristics, the low work function and the absence of dangling bonds of the two-dimensional ferroelectric semiconductor material, reduces the Schottky barrier height of the junction region and the working voltage range of the device, avoids the sharing pressure drop phenomenon, and realizes the nearly ideal sub-threshold swing and the accurate control of the channel conductance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor electronic devices, and more particularly, to a two-dimensional JFET device and a manufacturing method thereof. BACKGROUND

[0002] A junction field effect transistor (JFET) is a three-terminal active electronic device made of semiconductor material of two different types of carriers, and its junction depletion layer is formed by the contact of P-type and N-type semiconductor materials, and the flow of current is controlled by regulating the depletion region of the PN junction. In a conventional JFET, by applying a gate voltage (V GS ), the width of the depletion region can be adjusted to control the conduction and turn-off of the current in the channel. JFET has high input impedance, low noise and other advantages, and is widely used in amplifiers and switching circuits. However, the conventional silicon-based JFET has insufficient performance stability at a small size and relatively high power consumption, which limits its application in ultra-low power consumption and high-density integrated circuits.

[0003] In recent years, in order to solve the problem of insufficient performance stability at a small size and relatively high power consumption, two-dimensional JFET devices based on low-dimensional materials have become a research hotspot. Low-dimensional materials such as black phosphorus, bismuth oxyselenide, and transition metal dichalcogenides exhibit excellent photoelectric and electronic transport properties due to their unique physical and chemical properties, and show great potential in the fields of field effect transistors, photoelectric sensors, and flexible devices.

[0004] Specifically, when two different types of thin films are combined together, they exhibit more diverse functions, such as two-dimensional NiO x / MoS2, SnSe / MoS2 JFET, due to its ideal van der Waals interface contact, has excellent rectification and ultra-fast switching characteristics when the device is switched on, and its reverse saturation current can reach the order of picoampere. However, whether it is electron-type NiO x or hole-type SnSe, there will be a large Schottky barrier in the junction region, and there will be a certain sharing pressure drop phenomenon (when NiO x or SnSe is used as the gate electrode, the voltage induced by the channel material is less than the voltage output by the voltage source), which affects the switching speed and low-power operation of the device. SUMMARY

[0005] Therefore, it is necessary to provide a two-dimensional JFET device and a manufacturing method thereof to reduce the Schottky barrier in the junction region in view of the above problems.

[0006] In order to achieve the above purpose, the technical solutions adopted by the present application are as follows:

[0007] A two-dimensional JFET device, comprising:

[0008] An insulating substrate;

[0009] A few-layer two-dimensional ferroelectric semiconductor film is located on the surface of the insulating substrate.

[0010] A two-dimensional semimetal film is located on the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor film.

[0011] Metal electrodes are divided into source electrodes, drain electrodes and gate electrodes, wherein the source electrodes and the drain electrodes are respectively located on the surfaces of the few-layer two-dimensional ferroelectric semiconductor films on both sides of the two-dimensional semimetal film, and the gate electrode is located on the surface of the two-dimensional semimetal film.

[0012] In one embodiment, the material of the few-layer two-dimensional ferroelectric semiconductor film is alpha-In2Se3, or gamma-InSe, or ReS2, or ReSe2.

[0013] In one embodiment, the thickness of the few-layer two-dimensional ferroelectric semiconductor film is 10nm-50nm.

[0014] In one embodiment, the material of the two-dimensional semimetal film is 1T'-MoTe2, or WTe2, or Bi.

[0015] In one embodiment, the thickness of the two-dimensional semimetal film is 5nm-30nm.

[0016] In one embodiment, the material of the insulating substrate is silicon oxide, aluminum oxide, fluorophlogopite, PI, or glass.

[0017] In one embodiment, the metal electrode includes a buffer metal layer and a protective metal layer, wherein the thickness of the buffer metal layer is 1nm-5nm, and the thickness of the protective metal layer is 10nm-60nm.

[0018] Another embodiment discloses a manufacturing method of a two-dimensional JFET device, comprising:

[0019] Providing an insulating substrate;

[0020] Transferring a few-layer two-dimensional ferroelectric semiconductor film to the surface of the insulating substrate;

[0021] Transferring a two-dimensional semimetal film to the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor film;

[0022] Forming a gate electrode on the surface of the two-dimensional semimetal film, and forming source electrodes and drain electrodes on the surfaces of the few-layer two-dimensional ferroelectric semiconductor films on both sides of the two-dimensional semimetal film.

[0023] In one embodiment, the method for transferring the few-layer two-dimensional ferroelectric semiconductor thin film and the two-dimensional semimetal thin film is mechanical exfoliation, chemical vapor deposition, electrochemical exfoliation or transfer printing process.

[0024] In one embodiment, the two-dimensional JFET device is completed in an environment less than 180 DEG C.

[0025] The two-dimensional JFET device disclosed by the application utilizes the high conductivity of the two-dimensional semimetal, the spontaneous polarization, the controllable characteristics and the low work function and the absence of dangling bonds of the two-dimensional ferroelectric semiconductor material, reduces the Schottky barrier height of the junction region and the working voltage range of the device, avoids the sharing of the voltage drop, realizes the nearly ideal sub-threshold swing and the precise control of the channel conductance.

[0026] Meanwhile, the spontaneous polarization characteristics of the two-dimensional ferroelectric material provide the non-volatile memory function, so that the device can still maintain the polarization state after power-off, and the reliability of data storage is improved. Moreover, by utilizing the characteristics of the two-dimensional ferroelectric material, the application reduces the requirement for the external electric field and reduces the power consumption of the device in operation, and is particularly suitable for low-power application scenarios.

[0027] In addition, the two-dimensional JFET device provided by the application realizes good neuromorphic performance through the programmable polarization function of the two-dimensional ferroelectric material, and can meet different application requirements. Further, by using the combination of two-dimensional materials and ferroelectric materials, the application can simplify the manufacturing process of the device, reduce the production cost, and improve the consistency and repeatability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A two-dimensional JFET device provided by an embodiment of the application is shown in the figure;

[0029] Figure 2 Another two-dimensional JFET device provided by an embodiment of the application is shown in the figure;

[0030] Figures 3-5 A two-dimensional JFET device provided by an embodiment of the application is shown in the figure;

[0031] Figure 6 The channel current curve of the two-dimensional JFET device under different gate voltages is shown in the figure;

[0032] Figure 7 The transfer curve of the two-dimensional JFET device is shown in the figure;

[0033] Figure 8 The pinch-off voltage curve of the two-dimensional JFET device is shown in the figure;

[0034] Figure 9A sub-threshold swing curve diagram of the two-dimensional JFET device provided by the present application;

[0035] Figure 10 An output curve diagram of the two-dimensional JFET device provided by the present application;

[0036] Figure 11 A resistance change characteristic curve diagram of the two-dimensional JFET device provided by the present application;

[0037] Figure 12 A durability curve diagram of the two-dimensional JFET device provided by the present application.

[0038] In the figure, 1, an insulating substrate; 11, a Si substrate; 12, a SiO2 film; 2, a few-layer two-dimensional ferroelectric semiconductor film; 3, a two-dimensional semimetal film; 4, a metal electrode; 41, a source electrode; 42, a drain electrode; 43, a gate electrode. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present application, the present application will be described in more detail below. However, it should be understood that the present application can be realized in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments or examples only and is not intended to be limiting of the present application. As used herein, the term "and / or", which includes a selectable range, includes any one of two or more associated listed items, and also includes any and all combinations of the associated listed items, including a combination of any two associated listed items, a combination of any more associated listed items, or a combination of all associated listed items.

[0041] One embodiment of the present application discloses a two-dimensional JFET device, as shown in the figure, comprising: Figure 1

[0042] An insulating substrate 1;

[0043] A few-layer two-dimensional ferroelectric semiconductor film 2, the few-layer two-dimensional ferroelectric semiconductor film 2 is located on the surface of the insulating substrate 1;

[0044] A two-dimensional semimetal film 3, the two-dimensional semimetal film 3 is located in the middle region of the few-layer two-dimensional ferroelectric semiconductor film 2;

[0045] ​Metal electrode 4, the metal electrode 4 is divided into source electrode 41, drain electrode 42 and gate electrode 43, wherein the source electrode 41 and drain electrode 42 are respectively located on the surface of the few-layer two-dimensional ferroelectric semiconductor film 2 on both sides of the two-dimensional semimetal thin film 3, and the gate electrode 43 is located on the surface of the two-dimensional semimetal thin film 3.

[0046] The two-dimensional JFET device disclosed in the embodiment utilizes the high conductivity of the two-dimensional semimetal, the spontaneous polarization, the controllable characteristics and the low work function of the two-dimensional ferroelectric semiconductor material, and the characteristics of no dangling bond, so as to reduce the Schottky barrier height of the junction region and the working voltage range of the device, avoid the sharing voltage drop phenomenon, and realize the nearly ideal subthreshold swing and the precise control of the channel conductance.

[0047] Meanwhile, the spontaneous polarization characteristics of the two-dimensional ferroelectric material provide a non-volatile memory function, so that the device can still maintain the polarization state after power failure, and the reliability of data storage is improved. Moreover, by utilizing the characteristics of the two-dimensional ferroelectric material, the application reduces the requirement for external electric field and reduces the power consumption of the device in operation, and is particularly suitable for low-power application scenarios.

[0048] In addition, the two-dimensional JFET device provided by the application realizes good neuromorphic performance by the programmable polarization function of the two-dimensional ferroelectric material, and can meet different application requirements.

[0049] In another embodiment, the manufacturing material of the insulating substrate is silicon oxide, or aluminum oxide, or fluorophlogopite, or PI (polymer), or glass.

[0050] Due to the atomic thickness of the two-dimensional material, it is extremely sensitive to the electrical, mechanical and chemical properties of the substrate. Therefore, the selection of the insulating substrate in the embodiment comprehensively considers the electrical performance, mechanical stability, thermal compatibility, interface matching and process feasibility.

[0051] Among them, the silicon oxide substrate can also be a silicon oxide / silicon (SiO2 / Si) substrate, and the dielectric constant is 3.9, and the resistivity is greater than 10 16 Ω·cm, low cost, high process maturity, and compatibility with two-dimensional materials, which is a preferred material of the embodiment. The dielectric constant of PI (polymer) is 3.5~4.5, and the resistivity is 10 12 Ω·cm, low cost, high process maturity, and compatibility with two-dimensional materials, which is another preferred material of the embodiment.

[0052] In another embodiment, the manufacturing material of the few-layer two-dimensional ferroelectric semiconductor film is alpha-In2Se3, or gamma-InSe, or ReS2, or ReSe2.

[0053] In this embodiment, the few-layer two-dimensional ferroelectric semiconductor is a two-dimensional material stacked by 2-40 atomic layers, which has both ferroelectricity (spontaneous polarization and polarization direction can be reversed by external electric field) and semiconductor characteristics (band gap, carrier transport ability). Its atomic level thickness and interlayer van der Waals interaction make it show unique advantages in low-power electronic, flexible device and new type of memory fields.

[0054] wherein the structure of alpha-In2Se3 (indium selenide) is layered rhombohedral crystal system (space group m), each layer is formed by In atoms to form a hexagonal grid, and Se atoms are alternately located in the In atom gap (In-Se-In sandwich structure). The polarization direction is out-of-plane (perpendicular to the layer plane) spontaneous polarization (Ps≈0.5 μC / cm 2 ), and the polarization reversal is realized by the In atom offset induced by the external electric field. Single-layer alpha-In2Se3 still retains ferroelectricity (Ps≈0.3 μC / cm 2 ), but the polarization strength of few-layer (5-40 layers) is higher and more stable (interlayer coupling inhibits depolarization field).

[0055] Gamma-InSe belongs to another polymorphous phase of InSe, and has a crystal structure of orthorhombic system (space group Pnma) and a layered stacking feature. The atoms in the layer are covalently bonded to form a hexagonal grid: In atoms are located at (0, 0, 0) and (1 / 3, 2 / 3, 1 / 2) positions, Se atoms are located at (1 / 3, 2 / 3, 0) and (2 / 3, 1 / 3, 1 / 2) positions, and the In-Se bond length in the layer is about 2.82 Å, and the layers are combined by weak van der Waals force (interlayer spacing is about 0.33 nm). Compared with bulk gamma-InSe, few-layer gamma-InSe (usually refers to the number of layers ≤10 layers) can be obtained by mechanical exfoliation or chemical vapor deposition from its parent material due to the weakening of interlayer van der Waals force, and the layer thickness can be accurately controlled. The few-layer structure retains the covalent bond characteristics in the layer, and the weak interaction between the layers makes it still maintain the intrinsic physical properties at the nanoscale.

[0056] The few-layer (number of layers ≤10 layers) form of ReS2 (rhenium disulfide) tends to be an intrinsic non-centrosymmetric structure, and also has ferroelectricity, semiconductor property and excellent photoelectric property. Bulk ReS2 is usually in 2H phase (hexagonal system) or 3R phase (rhombohedral system), but when stacked by van der Waals force between layers, structural distortion occurs, showing weak ferroelectricity. Few-layer ReS2 can be obtained by mechanical exfoliation or chemical vapor deposition.

[0057] The atomic arrangement of few-layer (layer number ≤10) ReSe2 (rhenium diselenide) approaches the intrinsic non-centrosymmetric structure, and has intrinsic ferroelectricity, semiconductor property and excellent photoelectric anisotropy. Bulk ReSe2 is usually in 2H phase (hexagonal system) or 3R phase (rhombohedral system), but structural distortion occurs when layers are stacked by van der Waals force, and weak ferroelectricity is exhibited. Few-layer ReSe2 can be obtained by mechanical exfoliation or chemical vapor deposition.

[0058] In another embodiment, the thickness of the few-layer two-dimensional ferroelectric semiconductor thin film is 10 nm to 50 nm. If the thickness is too thin (the number of layers is too small, less than 5 layers), the ferroelectric polarization will be shielded by the depolarization field, resulting in weak ferroelectricity. If the thickness is too large (the number of layers is too large, more than 40 layers), the cost of evaporating metal electrodes during device manufacturing is increased. In one embodiment, the thickness of the few-layer two-dimensional ferroelectric semiconductor thin film is 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or a range formed by any two of these values, which can maintain strong ferroelectricity and reduce the cost of evaporating metal electrodes during device manufacturing.

[0059] In another embodiment, the material for manufacturing the two-dimensional semimetal thin film is 1T'-MoTe2, or WTe2, or Bi.

[0060] The two-dimensional semimetal is a layered material with an atomic thickness of 0.7 nm to 2 nm. Its electronic structure is between metal and semiconductor, with a band gap close to zero (or a small band gap), and electron (conduction band) and hole (valence band) states coexist near the Fermi level (E F ). The carrier mobility is extremely high (up to 10 4 cm 2 / (V·s) or more). Such materials have unique advantages in high-speed electronics, topological quantum computing, and new sensors due to their high mobility, quantum effects in low dimensions (such as Dirac cone, topological state), and flexibility / integrability brought by atomic thickness.

[0061] Among them, the two-dimensional semimetal 1T'-MoTe2 is a quasi-two-dimensional non-layered phase of MoTe2 in transition metal dichalcogenides (TMDs), belonging to the trigonal system (space group m1). Its unique crystal structure and electronic properties (such as weak metallicity, charge density wave) make it have important application potential in low-power electronics, quantum materials, and new sensors.

[0062] WTe2 belongs to the family of transition metal dichalcogenides (TMDs), but its structure is different from typical TMDs. Bulk WTe2 is orthorhombic (space group Pnma), and the crystal is stacked by layered structure, and the layers are combined by weak van der Waals force, so that few-layer WTe2 can be prepared by mechanical exfoliation or chemical vapor deposition.

[0063] Two-dimensional semimetal Bi is a layered material with an atomic thickness of 0.7 nm to 2 nm obtained by mechanical exfoliation or chemical vapor deposition of bulk Bi (rhombohedral system). Bulk Bi is rhombohedral (space group m), and its crystal structure is dominated by intralayer covalent bonds (Bi-Bi bond length of about 3.05 Å) and interlayer van der Waals forces (interlayer spacing of about 0.32 nm). Two-dimensional Bi (few layers, 2-10 layers) is obtained by mechanical exfoliation or chemical vapor deposition, which retains the layered structure of the bulk, but the interlayer coupling is weakened due to quantum confinement effect, showing more significant two-dimensional characteristics.

[0064] In another embodiment, the thickness of the two-dimensional semimetal thin film is 5 nm to 30 nm. When the thickness is too thin (less than 3 layers), the two-dimensional semimetal thin film will exhibit semiconductor characteristics, which is not conducive to the reduction of the Schottky barrier of the junction region; if it is too thick (more than 40 layers), it will increase the cost of manufacturing the metal electrode of the device. In one embodiment, the thickness of the two-dimensional semimetal thin film is 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, or a range formed by any two of these values, which is conducive to the reduction of the Schottky barrier of the junction region and reduces the cost of manufacturing the metal electrode of the device.

[0065] In another embodiment, the metal electrode includes a buffer metal layer and a protective metal layer in structure. The thickness of the buffer metal layer is 1 nm to 5 nm, and the thickness of the protective metal layer is 10 nm to 60 nm. The thickness of the protective metal layer is determined according to the thickness of the junction region composed of the two-dimensional semimetal thin film and the few-layer two-dimensional ferroelectric semiconductor thin film, and specifically corresponds to 1.5 to 3 times the thickness of the junction region.

[0066] In one embodiment, the material of the buffer metal layer can be one of scandium, silver, titanium, platinum, nickel, chromium, etc. Since chromium metal has good ohmic contact with α-In2Se3 (indium selenide) thin film, chromium is a preferred buffer metal layer in the embodiment of the present application.

[0067] In one embodiment, the thickness of the buffer metal layer is 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or a range formed by any two of these values.

[0068] In one embodiment, the material of the protective metal layer is mainly a metal stable at room temperature and easy to obtain, such as one of gold, aluminum, silver, copper, platinum, palladium, etc., with a thickness of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, or a range formed by any two of these values.

[0069] Another embodiment discloses a method for manufacturing a two-dimensional JFET device, comprising:

[0070] providing an insulating substrate;

[0071] transferring a few-layer two-dimensional ferroelectric semiconductor film to the surface of the insulating substrate;

[0072] transferring a two-dimensional semimetal film to the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor film;

[0073] forming a gate electrode on the surface of the two-dimensional semimetal film and forming source and drain electrodes on the surfaces of the few-layer two-dimensional ferroelectric semiconductor film on both sides of the two-dimensional semimetal film.

[0074] The two-dimensional JFET device manufactured by the method disclosed in the embodiment uses a combination of two-dimensional materials and ferroelectric materials, which can simplify the manufacturing process of the device, reduce production costs, and improve the consistency and repeatability of the device.

[0075] Moreover, the high conductivity of the two-dimensional semimetal, the spontaneous polarization, the controllable characteristics, the low work function, and the absence of dangling bonds of the two-dimensional ferroelectric semiconductor material reduce the height of the Schottky barrier in the junction region and the operating voltage range of the device, avoid the sharing of voltage drops, and achieve nearly ideal sub-threshold swing and precise control of the channel conductance.

[0076] At the same time, the spontaneous polarization characteristics of the two-dimensional ferroelectric material provide a non-volatile memory function, so that the device can maintain the polarization state after power failure, improving the reliability of data storage. By utilizing the characteristics of the two-dimensional ferroelectric material, the need for an external electric field is reduced, and the power consumption of the device in operation is reduced, making it particularly suitable for low-power application scenarios.

[0077] In addition, the two-dimensional JFET device realizes good neuromorphic performance through the programmable polarization function of the two-dimensional ferroelectric material, and can meet different application requirements.

[0078] In another embodiment, the transfer method of the few-layer two-dimensional ferroelectric semiconductor film and the two-dimensional semimetal film is mechanical peeling, chemical vapor deposition, electrochemical peeling, or transfer printing process.

[0079] Among them, mechanical peeling is to peel off a few layers of thin film from the source substrate by adhesive tape (such as Scotch tape, PDMS transfer film), and transfer to the target substrate by van der Waals force. It is suitable for all two-dimensional materials, especially a few layers of two-dimensional ferroelectric semiconductors and two-dimensional semimetals.

[0080] The method of mechanical peeling includes:

[0081] Source substrate pretreatment: clean the source substrate (such as ultrasonic cleaning with acetone, isopropanol), ensure that the surface is free of contaminants;

[0082] Peeling: gently press the source substrate with adhesive tape, slowly peel off (avoid rapid pulling to cause cracks), and obtain a few layers of thin film (attached to the adhesive tape);

[0083] Transfer: gently press the thin film on the adhesive tape to the target substrate (such as SiO2 / Si), heat (80℃~120℃) or solvent assisted (such as ethanol) to enhance adhesion;

[0084] Remove the adhesive tape residue with acetone.

[0085] The whole process is simple, low cost, and can obtain high-quality thin film with atomic-level flatness. For a few layers of two-dimensional ferroelectric semiconductor thin film α-In2Se3 (indium selenide), the interlayer coupling is strong, the peeling speed needs to be reduced (to avoid interlayer slip), and PDMS transfer film (soft material to reduce stress) is preferred; for two-dimensional semimetal 1T'-MoTe2, its brittleness is high, the peeling angle needs to be controlled (angle with substrate <30°), to avoid edge cracking.

[0086] Chemical vapor deposition is a transfer combined with van der Waals. The specific principle is to first grow a few layers of thin film on the source substrate (such as SiO2 / Si, sapphire) by chemical vapor deposition, and then transfer to the target substrate with polymer (such as PMMA) support. It is suitable for large-area (>100 μm) and uniform thin film (such as chemical vapor deposition grown WTe2, α-In2Se3), which can realize large-area (millimeter level) and uniform thin film (layer number controllable ±1 layer) preparation, suitable for device-level applications (such as transistor array).

[0087] Electrochemical peeling method is to peel off a few layers of thin film on the source substrate (such as metal foil) by electrochemical reaction, and to weaken the interlayer force by ion penetration. It is suitable for materials with stable layered structure and can be peeled off by ion intercalation (such as MoS2, α-In2Se3). It can accurately control the number of layers (adjust the ion penetration depth by voltage and time), and has high peeling efficiency (suitable for batch production).

[0088] The transfer process is to transfer the thin film from the source substrate to the target substrate by using high-precision transfer film (such as silicon rubber, PDMS), and to realize selective transfer (such as preparation of transistor channel) by patterning the transfer film. It is suitable for two-dimensional thin film (such as WTe2 transistor, α-In2Se3 memory) which needs to be patterned (such as array device). It can realize micro-nano scale patterned transfer (precision <1 μm), and is suitable for high integration devices (such as transistor array).

[0089] In another embodiment, the two-dimensional JFET device is completed in an environment less than 180℃. The temperature limit of 180℃ is mainly considered for the phase transition temperature of α-In2Se3. When the temperature is too high, the phase transition of α-In2Se3 will occur, which will affect the formation of the device.

[0090] In the following, the two-dimensional JFET device and the manufacturing method thereof disclosed by the present application will be described through several specific embodiments.

[0091] Embodiment one

[0092] Embodiment one discloses a two-dimensional JFET device, as shown in the figure, comprising: Figure 2

[0093] An insulating substrate 1, the insulating substrate 1 is a SiO2 / Si substrate, specifically comprising a Si substrate 11 and a SiO2 thin film 12 located on the surface of the Si substrate 11;

[0094] A few-layer two-dimensional ferroelectric semiconductor thin film 2, the few-layer two-dimensional ferroelectric semiconductor thin film 2 is located on the surface of the insulating substrate 1, and the few-layer two-dimensional ferroelectric semiconductor thin film 2 is a 20 nm thick α-In2Se3 thin film;

[0095] A two-dimensional semimetal thin film 3, the two-dimensional semimetal thin film 3 is located in the middle region of the few-layer two-dimensional ferroelectric semiconductor thin film 2, and the two-dimensional semimetal thin film 3 is a 15 nm thick 1T’-MoTe2 thin film;

[0096] A metal electrode 4, the metal electrode 4 is divided into a source electrode 41, a drain electrode 42 and a gate electrode 43 in type, wherein the source electrode 41 and the drain electrode 42 are respectively located on the surface of the few-layer two-dimensional ferroelectric semiconductor thin film 2 on both sides of the two-dimensional semimetal thin film 3, and the gate electrode 43 is located on the surface of the two-dimensional semimetal thin film 3. Specifically, the metal electrode 4 includes a buffer metal layer and a protective metal layer in structure, wherein the buffer metal layer is a chromium thin film with a thickness of 3 nm, and the protective metal layer is a gold thin film with a thickness of 50 nm.

[0097] ​The two-dimensional JFET device disclosed in the embodiment one utilizes the high conductivity of the two-dimensional semimetal, the spontaneous polarization, the controllable characteristics and the low work function and the absence of dangling bonds of the two-dimensional ferroelectric semiconductor material, reduces the Schottky barrier height of the junction region and the working voltage range of the device, avoids the sharing of the voltage drop, and realizes the nearly ideal subthreshold swing and the precise control of the channel conductance.

[0098] Meanwhile, the spontaneous polarization characteristics of the two-dimensional ferroelectric material provide the non-volatile memory function, so that the device can still maintain the polarization state after power-off, and the reliability of data storage is improved. Moreover, by utilizing the characteristics of the two-dimensional ferroelectric material, the application reduces the requirement for external electric field and reduces the power consumption of the device in operation, and is particularly suitable for low-power application scenarios.

[0099] In addition, the two-dimensional JFET device provided by the application realizes good neuromorphic performance through the programmable polarization function of the two-dimensional ferroelectric material, and can meet different application requirements.

[0100] Embodiment two

[0101] Embodiment two discloses a manufacturing method of a two-dimensional JFET device, comprising:

[0102] providing an insulating substrate 1 (such as Figure 3 ). The insulating substrate is a SiO2 / Si substrate, which comprises a Si substrate 11 and a SiO2 film 12 on the surface of the Si substrate 11. At the same time, the insulating substrate 1 also needs to be cleaned with high-purity acetone, isopropyl alcohol and deionized water to ensure that the surface is smooth and free of pollution.

[0103] transferring a few-layer two-dimensional ferroelectric semiconductor film 2 to the surface of the insulating substrate 1 (such as Figure 4 ). The few-layer alpha-In2Se3 film obtained by mechanical exfoliation is transferred to the insulating substrate 1. The thickness of the few-layer alpha-In2Se3 film is 20 nm.

[0104] transferring a two-dimensional semimetal film 3 to the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor film 2 (such as Figure 5 ). The two-dimensional semimetal 1T'-MoTe2 film with a thickness of 15 nm is transferred to the few-layer alpha-In2Se3 film by mechanical exfoliation. The two are cross-shaped, and the two-dimensional semimetal film 3 is located in the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor film 2 in the cross-sectional view.

[0105] forming a gate electrode 43 on the surface of the two-dimensional semimetal film 3, and forming a source electrode 41 and a drain electrode 42 on the surface of the few-layer two-dimensional ferroelectric semiconductor film 2 on both sides of the two-dimensional semimetal film 3 (such as Figure 2). Specifically, the gate electrode 43 is plated on the two-dimensional semimetal 1T'-MoTe2 film by laser direct writing technology and thermal evaporation technology, and the source electrode 41 and the drain electrode 42 are plated on the few-layer a-In2Se3 film. The deposited metal is a 3 nm thick buffer metal layer (chromium) and a 50 nm thick protective metal layer (gold).

[0106] Wherein, the thickness (layer number) control of the few-layer two-dimensional ferroelectric semiconductor film 2 and the two-dimensional semimetal film 3 can be observed by optical microscope, or the thickness of the film is measured by AFM. For the film transferred by chemical vapor deposition process, the thickness of the film can be controlled by synthesis time.

[0107] It should be noted that the temperature required in the heating step in the process of manufacturing the two-dimensional JFET device is controlled within 180°C to ensure that the two-dimensional JFET device is manufactured in an environment less than 180°C. Specifically, when spin coating 5350 photoresist, the drying temperature should be 100°C~115°C, and the time is 5min~30min; when depositing metal electrodes, the sample holder heating temperature should be 30°C~50°C.

[0108] The manufacturing method of the two-dimensional JFET device disclosed in the embodiment can simplify the manufacturing process of the device, reduce the production cost, and improve the consistency and repeatability of the device.

[0109] Next, a series of tests are performed on the prepared two-dimensional JFET device to verify the characteristics of the two-dimensional JFET device.

[0110] Wherein, under the application of different gate voltages, the channel current curve of the two-dimensional JFET device is as shown in Figure 6 It can be seen from Figure 6 that the source electrode and the drain electrode of the two-dimensional JFET device have very good ohmic contact.

[0111] The transfer curve of the two-dimensional JFET device is as shown in Figure 7 It can be seen from Figure 7 that the two-dimensional JFET device exhibits good transfer characteristics, and the channel current switching ratio under different bias is up to 10 4 .

[0112] The pinch-off voltage curve of the two-dimensional JFET device is as shown in Figure 8 It can be seen from Figure 8 that the two-dimensional JFET device has a small threshold voltage.

[0113] The sub-threshold swing curve of the two-dimensional JFET device is as shown in Figure 9 It can be seen from Figure 9 that the two-dimensional JFET device has a sub-threshold swing close to the ideal value and good gate control performance.

[0114] Combining Figure 8 and Figure 9 It can be seen that when the bias is 0.1V, the two-dimensional JFET device has a lower working voltage and a subthreshold swing close to the ideal value, indicating that the semimetal contact is beneficial to reduce the power consumption of the device and improve the response rate of the device.

[0115] The output curve of the two-dimensional JFET device under different gate voltages is as shown in Figure 10 It can be seen from Figure 10 that the two-dimensional JFET device has good transistor performance.

[0116] The resistance change characteristic curve of the two-dimensional JFET device is as shown in Figure 11 The endurance curve of the two-dimensional JFET device is as shown in Figure 12 It can be seen from Figure 11 and Figure 12 that the two-dimensional JFET device has certain nonvolatile storage characteristics and stability.

[0117] It can be seen from the above Figures 6-12 that the two-dimensional JFET device disclosed in the application utilizes the high conductivity of the two-dimensional semimetal, the spontaneous polarization, the adjustable control characteristics, the low work function, and the absence of dangling bonds of the two-dimensional ferroelectric semiconductor material, reduces the Schottky barrier height of the junction region and the working voltage range of the device (up to-0.7V~0.2V), avoids the phenomenon of sharing voltage drop, and realizes the nearly ideal subthreshold swing and the precise control of the channel conductance.

[0118] At the same time, the spontaneous polarization characteristics of the two-dimensional ferroelectric material provide a nonvolatile memory function, so that the device can still maintain the polarization state after power failure, improving the reliability of data storage. Moreover, by utilizing the characteristics of the two-dimensional ferroelectric material, the application reduces the need for an external electric field and reduces the power consumption of the device in operation, and is particularly suitable for low-power application scenarios.

[0119] In addition, the two-dimensional JFET device provided by the application realizes good neuromorphic performance through the programmable polarization function of the two-dimensional ferroelectric material, and can meet different application requirements.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, not all possible combinations of the technical features in the above-mentioned embodiments are described, however, as long as the combinations of the technical features do not exist contradictory, it should be considered that it is within the scope of the present application. The "first", "second" in the text is only for distinction, and is not a limitation on the content of the application.

[0121] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A two-dimensional JFET device, characterized in that, include: Insulating substrate; A few-layer two-dimensional ferroelectric semiconductor thin film, wherein the few-layer two-dimensional ferroelectric semiconductor thin film is located on the surface of the insulating substrate, and the material of the few-layer two-dimensional ferroelectric semiconductor thin film is α-In2Se3, or γ-InSe, or ReS2, or ReSe2; A two-dimensional semi-metallic thin film, wherein the two-dimensional semi-metallic thin film is located in the middle region of the surface of the few-layer two-dimensional ferroelectric semiconductor thin film, and the material of the two-dimensional semi-metallic thin film is 1T'-MoTe2, or WTe2, or Bi; The metal electrode is divided into a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are located on the surfaces of a few-layer two-dimensional ferroelectric semiconductor thin film on both sides of the two-dimensional semi-metallic thin film, and the gate electrode is located on the surface of the two-dimensional semi-metallic thin film.

2. The two-dimensional JFET device according to claim 1, characterized in that, The thickness of the few-layer two-dimensional ferroelectric semiconductor thin film is 10nm~50nm.

3. The two-dimensional JFET device according to claim 1, characterized in that, The thickness of the two-dimensional semi-metallic thin film is 5nm~30nm.

4. The two-dimensional JFET device according to claim 1, characterized in that, The insulating substrate is made of silicon oxide, or aluminum oxide, or fluorophlogopite, or PI, or glass.

5. The two-dimensional JFET device according to claim 1, characterized in that, The metal electrode includes a buffer metal layer and a protective metal layer, wherein the thickness of the buffer metal layer is 1 nm to 5 nm and the thickness of the protective metal layer is 10 nm to 60 nm.

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