Display substrate and display device

Abstract

A display substrate comprises a substrate (10), a plurality of sub-pixels (PX), a plurality of first wires and a compensation polar plate (36). The substrate (10) comprises a display area (A1) and a peripheral area located on at least one side of the display area (A1). The plurality of sub-pixels (PX) are provided on one side of the substrate (10) and located in the display region (A1). The plurality of first wires are located in the peripheral area and are electrically connected with the plurality of sub-pixels (PX). The compensation pole plate (36) is located in the peripheral area, and at least one insulating layer is arranged between the compensation pole plate (36) and the first wires. The orthographic projection of the compensation pole plate (36) on the substrate (10) is partially overlapped with the orthographic projection of the plurality of first wires on the substrate (10). The compensation pole plate (36) is provided with a hollow structure, and the orthographic projection of the hollow structure on the substrate (10) is partially overlapped with the orthographic projection of the at least one first wire on the substrate (10).

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first wirings, and a compensation plate. The substrate comprises a display area and a peripheral area located on at least one side of the display area. The plurality of sub-pixels are arranged on one side of the substrate and are located in the display area. The plurality of first wirings are located in the peripheral area and are electrically connected to the plurality of sub-pixels. The compensation plate is located in the peripheral area, and at least one insulating layer is provided between the compensation plate and the plurality of first wirings. The orthographic projection of the compensation plate on the substrate partially overlaps with the orthographic projection of the plurality of first wirings on the substrate. The compensation plate has a hollow structure, and the orthographic projection of the hollow structure on the substrate partially overlaps with the orthographic projection of at least one of the plurality of first wirings on the substrate.

[0007] In some exemplary embodiments, the substrate further includes a hole area, the peripheral area includes a winding area located between the hole area and the display area; and the plurality of first traces and the compensation plate are both located in the winding area.

[0008] In some exemplary embodiments, the hollow structure has at least one first hollow edge, the extension direction of the at least one first hollow edge is parallel to the extension direction of at least one first line among the multiple first lines, and the orthographic projection of the at least one first hollow edge on the substrate is located within the orthographic projection range of the at least one first line on the substrate.

[0009] In some exemplary embodiments, the compensation plate is located on a side of the plurality of first traces close to the substrate.

[0010] In some exemplary embodiments, the multiple first routing lines are alternately arranged in a first gate metal layer and a second gate metal layer, the second gate metal layer is located on a side of the first gate metal layer away from the substrate, and adjacent first routing lines in the multiple first routing lines do not overlap in their orthographic projections on the substrate; the compensation plate is located in the bottom shading metal layer, and the bottom shading metal layer is located on a side of the first gate metal layer close to the substrate.

[0011] In some exemplary embodiments, the multiple first traces include: multiple straight trace segments extending in the same direction; the hollow structure of the compensation plate includes: multiple first hollow portions; at least one first hollow portion among the multiple first hollow portions has a first edge, and the extension direction of the first edge is parallel to the extension direction of the multiple straight trace segments; a first edge of a single first hollow portion is located within the orthographic projection range of a straight trace segment on the substrate.

[0012] In some exemplary embodiments, the at least one first hollow portion has a rectangular projection on the substrate, and the at least one first hollow portion also has a second edge, the extension direction of the second edge is perpendicular to the extension direction of the first edge, and the orthographic projection of the second edge on the substrate overlaps with the orthographic projection of at least two of the multiple straight line segments on the substrate.

[0013] In some exemplary embodiments, the plurality of first hollow portions are arranged in an array along an extension direction of the plurality of straight line segments, and adjacent first hollow portions are aligned in the extension direction of the plurality of straight line segments.

[0014] In some exemplary embodiments, the plurality of first hollow portions are arranged in an array along an extension direction of the plurality of straight line segments, and in the extension direction of the plurality of straight line segments, at least two adjacent first hollow portions are staggered.

[0015] In some exemplary embodiments, the multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions, and the row of first hollow portions includes: a first group of hollow portions and a second group of hollow portions that are alternately arranged, the multiple first hollow portions in the first group of hollow portions are aligned, the multiple first hollow portions in the second group of hollow portions are aligned, and the first group of hollow portions and the second group of hollow portions are staggered.

[0016] In some exemplary embodiments, the multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions, and the row of first hollow portions includes: a third group of hollow portions and a fourth group of hollow portions that are alternately arranged, the multiple first hollow portions in the third group of hollow portions are staggered, and the multiple first hollow portions in the fourth group of hollow portions are staggered; at least one first hollow portion in the third group of hollow portions is aligned with at least one first hollow portion in the fourth group of hollow portions.

[0017] In some exemplary embodiments, the multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions, and the row of first hollow portions includes: multiple fifth groups of hollow portions arranged in sequence, the multiple first hollow portions within the fifth groups of hollow portions are staggered, and adjacent fifth groups of hollow portions are aligned.

[0018] In some exemplary embodiments, the multiple first routing lines include: multiple arc routing segments extending in the same direction; the hollow structure of the compensation plate includes: multiple second hollow portions; the multiple second hollow portions are arranged along the extension direction of the multiple arc routing segments; at least one second hollow portion among the multiple second hollow portions has a third edge, the extension direction of the third edge is parallel to the extension direction of the multiple arc routing segments, and the third edge of a single second hollow portion is located within the orthographic projection range of an arc routing segment on the substrate.

[0019] In some exemplary embodiments, the hollow structure of the compensation plate includes: at least one third hollow portion; the at least one third hollow portion extends along at least a portion of the edge of the hole area; the length of the first routing line that overlaps with the orthographic projection of the at least one third hollow portion on the substrate is greater than the length of the first routing line that does not overlap with the orthographic projection of the at least one third hollow portion on the substrate.

[0020] In some exemplary embodiments, the plurality of first routing lines include: a first group of first routing lines bypassing the hole area from one side of the hole area, and a second group of first routing lines bypassing the hole area from the other side of the hole area; the hollow structure of the compensation plate includes: at least one third hollow portion overlapping with the orthographic projection of the first group of first routing lines on the substrate, and at least one third hollow portion overlapping with the orthographic projection of the second group of first routing lines on the substrate.

[0021] In some exemplary embodiments, at least a portion of an edge of the at least one third hollow portion has a step shape in the orthographic projection of the substrate; the step shape includes: a plurality of step structures connected in sequence, each step structure including a first step and a second step connected to each other; the first step and the second step are straight line segments with different extension directions; the orthographic projection of the first step of each step structure on the substrate is located within the orthographic projection range of a first line on the substrate, and the orthographic projection of the second step on the substrate overlaps with the orthographic projections of at least two adjacent first lines on the substrate.

[0022] In some exemplary embodiments, the step shape further includes: a step connecting segment connecting adjacent step structures, and the step connecting segment is an arc segment.

[0023] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0025] Summary of the Figures

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0027] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0028] FIG2 is a schematic diagram of the grid lines in FIG1 ;

[0029] 3A is a partial cross-sectional schematic diagram of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0030] 3B is another partial cross-sectional schematic diagram of the display region of the display substrate according to at least one embodiment of the present disclosure;

[0031] FIG4 is a schematic partial cross-sectional view along the QQ' direction in FIG2;

[0032] 5 is a schematic diagram showing the positions of a first straight connecting segment of a gate connecting trace and a plurality of first hollow portions of a compensation plate according to at least one embodiment of the present disclosure;

[0033] FIG6A is a partial enlarged schematic diagram of area S1 in FIG1 ;

[0034] FIG6B is a schematic diagram of a first straight line connection segment of a plurality of gate connection lines in FIG6A ;

[0035] FIG6C is a schematic diagram of the compensation plate in FIG6A ;

[0036] 7 is a schematic diagram illustrating another position of the first straight connecting segment of the gate connecting trace and the plurality of first hollow portions of the compensation plate according to at least one embodiment of the present disclosure;

[0037] 8 is a schematic diagram illustrating another position of the first straight connecting segment of the gate connecting trace and the plurality of first hollow portions of the compensation plate according to at least one embodiment of the present disclosure;

[0038] 9 is a schematic diagram illustrating another position of the first straight connecting segment of the gate connecting trace and the plurality of first hollow portions of the compensation plate according to at least one embodiment of the present disclosure;

[0039] FIG10A is another partially enlarged schematic diagram of the area S1 in FIG1 ;

[0040] FIG10B is a schematic diagram of a first straight line connection segment of a plurality of gate connection lines in FIG10A;

[0041] FIG10C is a schematic diagram of the compensation plate in FIG10A;

[0042] FIG11A is a partial enlarged schematic diagram of area S2 in FIG1 ;

[0043] FIG11B is a schematic diagram of multiple arc-shaped connecting segments in FIG11A;

[0044] FIG11C is a schematic diagram of the compensation plate in FIG11A ;

[0045] FIG12 is a schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure;

[0046] FIG13A is a partial schematic diagram of an edge of a third hollow portion according to at least one embodiment of the present disclosure;

[0047] FIG13B is another partial schematic diagram of the edge of the third hollow portion according to at least one embodiment of the present disclosure;

[0048] FIG14 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure;

[0049] FIG15 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure;

[0050] FIG16 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure;

[0051] FIG17 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure;

[0052] FIG18 is another schematic diagram of gate connection routing in the winding area according to at least one embodiment of the present disclosure;

[0053] FIG19 is a schematic diagram showing the positions of the broken line connection segment of the gate connection trace and the first hollow portion of the compensation plate according to at least one embodiment of the present disclosure;

[0054] FIG20 is a schematic diagram showing another position of the broken line connection segment of the gate connection trace and the first hollow portion of the compensation plate according to at least one embodiment of the present disclosure;

[0055] FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0056] Details

[0057] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0058] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0059] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0060] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0061] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0062] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0063] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0064] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0065] In this specification, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, including, for example, a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, including, for example, a state where the angle is greater than 85° and less than 95°.

[0066] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0067] In this disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In this disclosure, "same" means that the values ​​differ by less than 10%, for example, including values ​​that differ by less than 5%.

[0068] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0069] In the present disclosure, "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0070] With the development of display technology, the demand for full-screen and narrow-frame displays is increasing. In order to preserve the photo quality, the display substrate needs to be specially designed to expose the rear camera. Among them, the display area through-hole (AA hole) design is one of the main solutions for full-screen displays. Since no sub-pixels are set in the display area through-hole, the wiring that originally passed through the display area through-hole needs to bypass the display area through-hole to connect the sub-pixels on both sides of the display area through-hole. Therefore, for the wiring that transmits the same signal, the signal load (loading) of the wiring that bypasses the display area through-hole and the signal load of the wiring that does not need to bypass the display area through-hole will be different, resulting in display defects (Mura) and other conditions.

[0071] This embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first wirings, and a compensation plate. The substrate comprises a display area and a peripheral area located on at least one side of the display area. The plurality of sub-pixels are arranged on one side of the substrate and are located in the display area. The plurality of first wirings are located in the peripheral area and are electrically connected to the plurality of sub-pixels. The compensation plate is located in the peripheral area, and at least one insulating layer is provided between the compensation plate and the plurality of first wirings. The orthographic projection of the compensation plate on the substrate partially overlaps with the orthographic projection of the plurality of first wirings on the substrate. The compensation plate has a hollow structure, and the orthographic projection of the hollow structure on the substrate partially overlaps with the orthographic projection of at least one first wiring on the substrate.

[0072] In some examples, the orthographic projection of the compensation plate on the substrate may overlap the orthographic projection of at least one first trace on the substrate; or the orthographic projection of the compensation plate on the substrate partially overlaps the orthographic projection of each of the plurality of first traces on the substrate. The orthographic projection of the hollow structure of the compensation plate on the substrate partially overlaps the orthographic projection of one or more first traces on the substrate. The orthographic projection of the hollow structure of the compensation plate on the substrate may not overlap the orthographic projection of at least one first trace on the substrate.

[0073] In some examples, the hollow structure of the compensation plate can be located within the compensation plate, for example, and can include multiple openings or slots located independently within the compensation plate. The edges of the hollow structure may not be connected to the outer edge of the compensation plate. In other examples, the hollow structure can be located at the outer edge of the compensation plate, such that at least a portion of the edge of the hollow structure can be connected to the outer edge of the compensation plate. For example, the edge of the hollow structure can serve as part of the outer edge of the compensation plate. The outer edge of the compensation plate in this example can be irregularly shaped.

[0074] The display substrate provided in this embodiment can perform capacitance compensation on the first routing line by providing a compensation plate that overlaps with the orthographic projection of the first routing line on the substrate, thereby achieving load compensation for the first routing line; moreover, the compensation plate has a hollow structure, and by providing the hollow structure, the overlapping area between multiple first routing lines and the orthographic projection of the compensation plate on the substrate can be adjusted, thereby achieving differentiated load compensation for different first routing lines.

[0075] In some exemplary embodiments, the substrate may further include an aperture region. The peripheral region may include a wiring region located between the aperture region and the display region. The plurality of first traces and the compensation plate may be located in the wiring region. In this example, by providing the compensation plate in the wiring region, load compensation can be provided for the first traces that bypass the aperture region, thereby reducing signal load differences caused by the aperture region.

[0076] In some exemplary embodiments, the hollow structure may have at least one first hollow edge, the at least one first hollow edge extending in a direction parallel to the at least one first trace extending in a direction, and the orthographic projection of the at least one first hollow edge on the substrate may be located within the orthographic projection of the at least one first trace on the substrate. In this example, by setting the orthographic projection of the first trace on the substrate to overlap the orthographic projection of the first hollow edge of the hollow structure on the substrate, the effect of the hollow structure edge on the film formation of the upper insulating layer, thereby preventing residual material or poor routing in the upper conductive layer, can be reduced.

[0077] In some exemplary embodiments, the multiple first traces may include: multiple linear trace segments extending in the same direction. The hollow structure of the compensation plate may include multiple first hollow portions. At least one first hollow portion may have a first edge, and the first edge may extend in a direction parallel to the direction of extension of the multiple linear trace segments. The orthographic projection of the first edge of a single first hollow portion on the substrate may be within the orthographic projection of a linear trace segment on the substrate. In this example, the first hollow edge of the hollow structure may include the first edges of multiple first hollow portions. In some examples, the first hollow portion may be an opening provided in the compensation plate. For example, the orthographic projection of the first hollow portion on the substrate may be rectangular. However, this embodiment is not limited to this. For example, the orthographic projection of the first hollow portion on the substrate may be annular or another shape. In this example, by providing multiple first hollow portions, and by ensuring that the orthographic projections of the linear trace segments of the first trace on the substrate overlap the orthographic projections of the first edges of the first hollow portions on the substrate, it is possible to mitigate the problem of the edges of the hollow structure affecting the conductive layer above, resulting in residual material or poor routing.

[0078] In some exemplary embodiments, the plurality of first traces may include: a plurality of arc trace segments extending in the same direction. The hollow structure of the compensation plate may include a plurality of second hollow portions. The plurality of second hollow portions may be arranged along the extension direction of the plurality of arc trace segments. At least one second hollow portion may have a third edge, the extension direction of the third edge may be parallel to the extension direction of the plurality of arc trace segments, and the orthographic projection of the third edge of a single second hollow portion on the substrate may be located within the orthographic projection range of a single arc trace segment on the substrate. In this example, the first hollow edge of the hollow structure may include the third edges of the plurality of second hollow portions. In some examples, the second hollow portion may be an opening provided in the hollow plate. For example, the orthographic projection of the second hollow portion on the substrate may be a rectangle. However, this embodiment is not limited to this. For example, the orthographic projection of the second hollow portion on the substrate may be a ring or other shape. In this example, multiple second hollow portions are set up, and the orthographic projection of the arc routing segment of the first routing on the substrate can cover the orthographic projection of the third edge of the second hollow portion on the substrate, thereby improving the situation where the edge of the hollow structure affects the existence of material residue or poor routing in the upper conductive layer.

[0079] In some exemplary embodiments, the hollow structure of the compensation plate may include: at least one third hollow portion; the at least one third hollow portion may extend along at least a portion of the edge of the hole area. The length of the first routing line that overlaps with the orthographic projection of the at least one third hollow portion on the substrate may be greater than the length of the first routing line that does not overlap with the orthographic projection of the at least one third hollow portion on the substrate. In some examples, the orthographic projection of the third hollow portion on the substrate may be an arc-shaped hollow groove provided in the compensation plate. However, this embodiment is not limited to this. For example, the third hollow portion may be an annular hollow groove. In this example, by providing a third hollow portion extending along the edge of the hole area, differentiated load compensation for multiple first routing lines can be achieved.

[0080] In some exemplary embodiments, the orthographic projection of at least a portion of the edge of at least one third hollow portion on the substrate may be in the shape of a step. The step shape may include: a plurality of step structures connected in sequence, each step structure may include a first step and a second step connected to each other; the first step and the second step are straight line segments extending in different directions. The orthographic projection of the first step of each step structure on the substrate may be located within the orthographic projection range of a first routing line on the substrate, and the orthographic projection of the second step on the substrate may overlap with the orthographic projections of at least two adjacent first routing lines on the substrate. In this example, the first hollow edge of the hollow structure may include the first step of multiple step structures. By setting the portion of the edge of the third hollow portion extending along the edge of the hole area to be in the shape of a step, this example can achieve differentiated load compensation for multiple first routing lines, and can also improve the situation where the edge of the hollow structure affects the presence of material residue or poor routing in the conductive layer above.

[0081] The solution of this embodiment is illustrated below through some examples.

[0082] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 2 is a schematic diagram of the gate lines in Figure 1. In some examples, as shown in Figures 1 and 2, the display substrate may include: an aperture area A2, a display area A1 located on at least one side of the aperture area A2, and a peripheral area BB located on at least one side of the display area A1. The peripheral area BB may include: a winding area B5 located between the aperture area A2 and the display area A1; a first peripheral area B1 and a fourth peripheral area B4 located on either side of the display area A1 along the second direction Y; and a second peripheral area B2 and a third peripheral area B3 located on either side of the display area A1 along the first direction X. The first peripheral area B1 may be connected to the second peripheral area B2 and the third peripheral area B3 and connected to the display area A1; the fourth peripheral area B4 may be connected to the second peripheral area B2 and the third peripheral area B3 and connected to the display area A1. The first peripheral area B1, the second peripheral area B2, the third peripheral area B3, and the fourth peripheral area B4 may be connected to surround the display area A1. For example, the first peripheral region B1 may be the lower frame region of the display substrate, the second peripheral region B2 may be the left frame region of the display substrate, the third peripheral region B3 may be the right frame region of the display substrate, and the fourth peripheral region B4 may be the upper frame region of the display substrate. However, this embodiment is not limited to this.

[0083] In some examples, no sub-pixels are set in the hole area A2, and the hole area A2 is not used for display; in other words, the hole area A2 can be a non-display area. No sub-pixels can be set in the winding area B5, and the winding area B5 can be not used for display.

[0084] In some examples, the orthographic projection of the hole area A2 may be circular. For example, the diameter of the hole area A2 may range from 6 mm to 20 mm, such as approximately 12 mm. However, this embodiment is not limited thereto. In other examples, the orthographic projection of the hole area A2 may be rectangular, rounded rectangular, elliptical, semicircular, pentagonal, hexagonal, etc.

[0085] In some examples, the edge of the hole area A2 can be the inner edge of the winding area B5, and the outer edge of the winding area B5 can be connected to the display area A1. For example, the orthographic projection shape of the hole area A2 can be circular, and the orthographic projection shape of the winding area B5 can be an annular ring. However, this embodiment is not limited to this. In other examples, the orthographic projection shape of the winding area can match the shape of the hole area; for example, the orthographic projection shape of the hole area is rectangular, and the orthographic projection shape of the winding area can be a rectangular ring; or, the orthographic projection shape of the hole area is elliptical, and the orthographic projection shape of the winding area can be an elliptical ring.

[0086] In some examples, the hole area A2 can be located in the middle of the display area A1, so that the display area A1 surrounds the hole area A2. However, this embodiment is not limited to this. In other examples, the hole area can be adjacent to the upper edge or lower edge of the display area, so that the display area surrounds at least the left and right sides of the hole area.

[0087] In some examples, the display area A1 may include a plurality of sub-pixels PX forming a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image. For example, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0088] In some examples, the display area A1 may include: multiple gate lines and multiple data lines. The multiple gate lines may extend along a first direction X and be arranged along a second direction Y; the multiple data lines may extend along the second direction Y and be arranged along the first direction X. The orthographic projections of the multiple gate lines and the multiple data lines on the substrate may intersect to form multiple sub-pixel regions, with a sub-pixel PX disposed in each sub-pixel region. The multiple data lines are electrically connected to the multiple sub-pixels PX and may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines are electrically connected to the multiple sub-pixels PX and may be configured to provide gate drive signals to the multiple sub-pixels PX. For example, the gate drive signals may include scan signals, or may include scan signals and light-emitting control signals, or may include scan signals, reset control signals, and light-emitting control signals. In some examples, the second direction Y may be the direction in which the data lines extend within the display area A1; the first direction X may be the direction in which the gate lines extend within the display area A1. The first direction X and the second direction Y may intersect, for example, may be perpendicular to each other.

[0089] In some examples, the plurality of gate lines may include: a plurality of first-class gate lines 311 and a plurality of second-class gate lines 312. Each gate line may connect a plurality of sub-pixels arranged along the first direction X. Since the aperture area A2 is not provided with sub-pixels, the number of sub-pixels connected by at least one first-class gate line 311 may be less than the number of sub-pixels connected by at least one second-class gate line 312. The signal load of at least one first-class gate line 311 may be less than the signal load of at least one second-class gate line 312.

[0090] In some examples, the plurality of second-type gate lines 312 may extend along the first direction X and be arranged along the second direction Y. For example, the plurality of second-type gate lines 312 may be divided into two groups arranged along the second direction Y, and the plurality of first-type gate lines 311 may be located between the two groups of second-type gate lines 312 in the second direction Y.

[0091] In some examples, as shown in FIG2 , a plurality of first-type gate lines 311 are interrupted by the aperture area A2 in the first direction X. The first-type gate lines 311 may include a first gate extension 311-1 and a second gate extension 311-2 located in the display area A1. The first gate extension 311-1 and the second gate extension 311-2 may be connected by a gate connection trace 33 located in the winding area B5. The gate connection trace 33 may be arranged along the aperture area A2.

[0092] In some examples, the first gate extension segment 311-1 and the second gate extension segment 311-2 of the first type gate line 311, and the gate connecting trace 33 can be an integrated structure connected to each other; or, the first gate extension segment 311-1 and the second gate extension segment 311-2 can be located in the same conductive layer, and the conductive layer where the gate connecting trace 33 is located can be different from the conductive layer where the first gate extension segment 311-1 is located.

[0093] In some examples, at least one gate connection trace 33 located in the winding area B5 may include: a first straight connection segment 331, a second straight connection segment 332, and an arcuate connection segment 333. The first straight connection segment 331 and the second straight connection segment 332 may extend along the first direction X and be located on both sides of the hole area A2 along the first direction X. The arcuate connection segment 333 may be connected between the first straight connection segment 331 and the second straight connection segment 332. The first straight connection segment 331 may be connected to the first gate extension segment 311-1, and the second straight connection segment 332 may be connected to the second gate extension segment 311-2. For example, the first straight connection segment 331, the second straight connection segment 332, and the arcuate connection segment 333 may be an integrated structure connected to each other.

[0094] In some examples, the plurality of data lines may include: a plurality of first-type data lines 321 and a plurality of second-type data lines 322. Each data line may connect to a plurality of sub-pixels arranged along the second direction Y. Since no sub-pixels are provided in the aperture area A2, the number of sub-pixels connected to the at least one first-type data line 321 may be smaller than the number of sub-pixels connected to the at least one second-type data line 322, and the signal load of the at least one first-type data line 321 may be smaller than the signal load of the at least one second-type data line 322.

[0095] In some examples, the plurality of second-class data lines 322 may extend along the second direction Y and be arranged along the first direction X. For example, the plurality of second-class data lines 322 may be divided into two groups arranged along the first direction X, and the plurality of first-class data lines 321 may be located between the two groups of second-class data lines 322 in the first direction X.

[0096] In some examples, multiple first-type data lines 321 are interrupted by the aperture area A2 in the second direction Y. The first-type data lines 321 may include a first data connection segment 321-1 and a second data connection segment 321-2 located in the display area A1. The first data connection segment 321-1 and the second data connection segment 321-2 may be connected by a data connection trace 34 located in the routing area B5. The data connection trace 34 may be arranged along the aperture area A2.

[0097] In some examples, the first data connection segment 321-1 and the second data connection segment 321-2 of the first type data line 321, and the data connection trace 34 can be an integrated structure connected to each other; or, the first data connection segment 321-1 and the second data connection segment 321-2 can be located in the same conductive layer, and the conductive layer where the data connection trace 34 is located can be different from the conductive layer where the first data connection segment 321-1 is located.

[0098] In some examples, a pixel unit of the display area A1 may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0099] In some examples, a sub-pixel PX may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.

[0100] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0101] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0102] Figure 3A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure. Figure 3A illustrates the structure of a sub-pixel in the display region as an example. In this example, the multiple pixel transistors in the pixel circuit can be of different transistor types, such as low-temperature polysilicon thin-film transistors and oxide thin-film transistors.

[0103] In some examples, as shown in FIG3A , in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels. In other examples, the display substrate may further include: a touch structure layer located on a side of the encapsulation structure layer away from the substrate. For example, the touch structure layer may include at least one touch conductive layer.

[0104] In some examples, FIG3A illustrates an example of a first transistor 21, a second transistor 22, and a capacitor 23 included in each sub-pixel. The first transistor 21 and the second transistor 22 may be of different transistor types. The first transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second transistor 22 may be an oxide thin-film transistor. Alternatively, the first transistor 21 may be an oxide thin-film transistor, and the second transistor 22 may be a low-temperature polysilicon thin-film transistor.

[0105] In some examples, the circuit structure layer 12 of the display area may include: a bottom shielding metal layer (BSM) arranged on the substrate 10, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source and drain metal layer, and a second source and drain metal layer. A first insulating layer 101 may be provided between the bottom light-shielding metal layer and the first semiconductor layer, and the first insulating layer 101 may also be called a buffer layer; a second insulating layer 102 may be provided between the first semiconductor layer and the first gate metal layer, and a third insulating layer 103 may be provided between the first gate metal layer and the second gate metal layer; a fourth insulating layer 104 may be provided between the second gate metal layer and the second semiconductor layer; a fifth insulating layer 105 may be provided between the second semiconductor layer and the third gate metal layer; the second insulating layer 102 to the fifth insulating layer 105 may also be called gate insulating layers; a sixth insulating layer 106 may be provided between the third gate metal layer and the first source / drain metal layer, and the sixth insulating layer 106 may also be called an interlayer insulating layer; a seventh insulating layer 107 and an eighth insulating layer 108 may be provided between the first source / drain metal layer and the second source / drain metal layer, and the eighth insulating layer 108 may be located on the side of the seventh insulating layer 107 away from the substrate 10; a ninth insulating layer 109 may be provided on the side of the second source / drain metal layer away from the substrate 10. The seventh insulating layer 107 can also be called a passivation layer, the eighth insulating layer 108 can also be called a first flat layer, and the ninth insulating layer 109 can also be called a second flat layer. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, the sixth insulating layer 106 and the seventh insulating layer 107 can be inorganic insulating layers, and the eighth insulating layer 108 and the ninth insulating layer 109 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be provided on the side of the bottom light-shielding metal layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate and can also increase the adhesion of the film layer in the display substrate to the substrate. In other examples, the seventh insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the eighth insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0106] In some examples, as shown in FIG3A , the bottom light-shielding metal layer of the display area may include at least a light-shielding block 25. The light-shielding block 25 may be configured to at least partially cover the active layer of the transistor in the pixel circuit to prevent external light from affecting the transistor's performance. For example, the light-shielding block 25 may be electrically connected to the constant voltage signal line in the peripheral area. For example, the light-shielding block 25 may be configured to receive a first power supply signal. The first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate 213 of the first transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least the second active layer 220 of the second transistor 22. The third gate metal layer may include at least the second gate 223 of the second transistor 22. The orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10.

[0107] In some examples, as shown in FIG3A , the first source-drain metal layer may include at least a first source 211 and a first drain 212 of the first transistor 21, and a second source 221 and a second drain 222 of the second transistor 22. The sixth insulating layer 106 may have a plurality of pixel vias (e.g., a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The sixth insulating layer 106, the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; and the sixth insulating layer 106, the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The sixth insulating layer 106 and the fifth insulating layer 105 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined through the eighth and seventh insulating layers 108 and 107. In this example, the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0108] In some examples, as shown in FIG3A , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the ninth insulating layer 109 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the ninth insulating layer 109. The pixel definition layer 134 is disposed on the first electrode 131 and the ninth insulating layer 109. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first and second electrodes 131 and 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0109] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0110] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0111] In some examples, as shown in FIG3A , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic / inorganic.

[0112] Figure 3B is another partial cross-sectional schematic diagram of the display region of a display substrate according to at least one embodiment of the present disclosure. In this example, the multiple pixel transistors in the pixel circuit can be of the same transistor type, for example, all low-temperature polysilicon thin-film transistors. Figure 3B illustrates an example of a first transistor 21 and a capacitor 23 included in each sub-pixel.

[0113] In some examples, as shown in FIG3B , the circuit structure layer 12 in the display area may include: a bottom light-shielding metal layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on the substrate 10. A first insulating layer 101 may be disposed between the bottom light-shielding metal layer and the first semiconductor layer, a second insulating layer 102 may be disposed between the first semiconductor layer and the first gate metal layer, a third insulating layer 103 may be disposed between the first gate metal layer and the second gate metal layer, a fourth insulating layer 104 may be disposed between the second gate metal layer and the first source-drain metal layer, a seventh insulating layer 107 and an eighth insulating layer 108 may be disposed between the first source-drain metal layer and the second source-drain metal layer, and a ninth insulating layer 109 may be disposed on the side of the second source-drain metal layer away from the substrate 10. The eighth insulating layer 108 and the ninth insulating layer 109 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 may be inorganic insulating layers. The remaining structures of the display area of ​​the display substrate of this example can be referred to the description of the embodiment shown in FIG3A , and therefore will not be described again here.

[0114] In some examples, the pixel circuit may include eight pixel transistors (i.e., first to eighth pixel transistors) and a storage capacitor. The second pixel transistor may be an oxide thin film transistor, and the first, third to eighth pixel transistors may be low-temperature polysilicon thin film transistors.

[0115] In some examples, the gate of the third pixel transistor is electrically connected to the first node, the first electrode of the third pixel transistor is electrically connected to the second node, and the second electrode of the third pixel transistor is electrically connected to the third node. The gate of the fourth pixel transistor is electrically connected to the first scan line, the first electrode of the fourth pixel transistor is electrically connected to the data line, and the second electrode of the fourth pixel transistor is electrically connected to the second node. The gate of the second pixel transistor is electrically connected to the second scan line, the first electrode of the second pixel transistor is electrically connected to the third node, and the second electrode of the second pixel transistor is electrically connected to the first node. The gate of the fifth pixel transistor is electrically connected to the emission control line, the first electrode of the fifth pixel transistor is electrically connected to the first power line, and the second electrode of the fifth pixel transistor is electrically connected to the second node. The gate of the sixth pixel transistor is electrically connected to the emission control line, the first electrode of the sixth pixel transistor is electrically connected to the third node, and the second electrode of the sixth pixel transistor is electrically connected to the fourth node. The gate of the first pixel transistor is electrically connected to the first reset control line, the first electrode of the first pixel transistor is electrically connected to the first initial signal line, and the second electrode of the first pixel transistor is electrically connected to the third node. The first pixel transistor can be configured to reset the third node. The gate of the seventh pixel transistor is electrically connected to the second reset control line, the first electrode of the seventh pixel transistor is electrically connected to the second initial signal line, and the second electrode of the seventh pixel transistor is electrically connected to the fourth node. The seventh pixel transistor can be configured to reset the fourth node. The gate of the eighth pixel transistor is electrically connected to the second reset control line, the first electrode of the eighth pixel transistor is electrically connected to the third initial signal line, and the second electrode of the eighth pixel transistor is electrically connected to the second node. The eighth pixel transistor can be configured to reset the second node. The first electrode of the storage capacitor is electrically connected to the first node, and the second electrode of the storage capacitor is electrically connected to the first power line.

[0116] In some examples, using the film layer structure of the display substrate shown in FIG3A as an example, multiple gate lines can be located in the first gate metal layer and the second gate metal layer, and multiple data lines can be located in the first source / drain metal layer and the second source / drain metal layer. For example, the multiple gate lines can include: multiple first scan lines, multiple second scan lines, multiple light emission control lines, multiple first reset control lines, and multiple second reset control lines; wherein the multiple first scan lines and the multiple first reset control lines can be located in the first gate metal layer, and the multiple second scan lines, the multiple light emission control lines, and the multiple second reset control lines can be located in the second gate metal layer.

[0117] In some examples, multiple gate connection lines located in the winding area can be alternately arranged in the first gate metal layer and the second gate metal layer. For example, the gate connection line connected to the first scan line can be located in the first gate metal layer, the gate connection line connected to the first reset control line can be located in the first gate metal layer, the gate connection line connected to the second scan line can be located in the second gate metal layer, the gate connection line connected to the light emitting control line can be located in the second gate metal layer, and the gate connection line connected to the second reset control line can be located in the second gate metal layer. Multiple data connection lines located in the winding area can be alternately arranged in the first source and drain metal layer and the second source and drain metal layer. However, this embodiment is not limited to this.

[0118] In some examples, the plurality of first routing lines located in the winding area may include: a first group of first routing lines that bypass the aperture area A2 from one side of the aperture area A2, and a second group of first routing lines that bypass the aperture area A2 from the other side of the aperture area A2. For example, the plurality of first routing lines located in the winding area may include: a plurality of gate connection routing lines 33. The aperture area A2 may have a first centerline, which may pass through the center point of the aperture area A2 and extend along the first direction X. The first group of first routing lines may include: a plurality of gate connection routing lines 33 located on one side of the first centerline in the second direction Y, for example, a plurality of gate connection routing lines 33 bypassing the upper side of the aperture area A2; the second group of first routing lines may include: a plurality of gate connection routing lines 33 located on the opposite side of the first centerline in the second direction Y, for example, a plurality of gate connection routing lines bypassing the lower side of the aperture area A2.

[0119] FIG4 is a schematic partial cross-sectional view along the Q-Q' direction in FIG2 . In some examples, as shown in FIG2 and FIG4 , the plurality of gate connection traces 33 located in the winding area B5 may include: a gate connection trace 33a located in the first gate metal layer and a gate connection trace 33b located in the second gate metal layer. The plurality of gate connection traces 33a and the plurality of gate connection traces 33b may be arranged alternately, and the orthographic projections of adjacent gate connection traces 33a and 33b on the substrate 10 may not overlap. The plurality of data connection traces 34 in the winding area B5 may include: a data connection trace 34a located in the first source / drain metal layer and a data connection trace 34b located in the second source / drain metal layer. The orthographic projections of adjacent data connection traces 34a and 34b on the substrate 10 may not overlap.

[0120] In some examples, the winding area B5 may be provided with a compensation plate 36. The compensation plate 36 may be configured to receive a constant voltage signal, such as a first power signal provided by a first power line, or a second power signal provided by a second power line. The compensation plate 36 may be located in the bottom light-shielding metal layer, and the orthographic projection of the compensation plate 36 on the substrate 10 may at least partially overlap with the orthographic projections of the plurality of gate connection traces 33a and 33b on the substrate 10. For example, the orthographic projection of the compensation plate 36 on the substrate 10 may cover the orthographic projection of a portion of the gate connection traces on the substrate 10, and may partially overlap with the orthographic projection of another portion of the gate connection traces on the substrate 10; or, the orthographic projection of the compensation plate 36 on the substrate 10 may partially overlap with the orthographic projections of all gate connection traces on the substrate 10. In this example, by setting a compensation plate 36 on the bottom shading metal layer, the capacitance compensation of the gate connection wiring located in the first gate metal layer and the second gate metal layer in the winding area B5 can be performed, thereby performing load compensation on the first type of gate line connected to the gate connection wiring, so that the load of the first type of gate line and the load of the second type of gate line after compensation can be roughly the same, thereby ensuring the display effect.

[0121] In some examples, a compensation plate 36 can be provided in the winding area B5. The orthographic projection of the compensation plate 36 on the substrate can be a hollowed-out ring. The outer edge of the compensation plate 36 can have a shape roughly identical to the edge of the winding area B5. By providing a large compensation plate in this example, thin wires can be avoided in the bottom light-shielding metal layer, thereby preventing the bottom light-shielding metal layer from affecting the wiring of the upper conductive layer.

[0122] In some examples, the compensation plate 36 may have a hollow structure, and the orthographic projection of the hollow structure on the substrate may partially overlap with the orthographic projection of at least one gate connection line on the substrate. In this example, by providing a hollow structure, the peeling problem of the film layer caused by a large area of ​​the compensation plate can be avoided; and by providing a hollow structure, the overlapping area between the compensation plate and different gate connection lines can be adjusted, which is conducive to differentiated capacitance compensation for different gate connection lines. However, at the edge position of the compensation plate (such as the edge position of the hollow structure), the film forming effect of the inorganic film layer above the compensation plate will deteriorate, for example, a narrow gap or a recessed position will be generated, so that the conductive layer above the inorganic film layer will remain, which can easily lead to poor routing, etc., thereby affecting the display effect of the display substrate. For example, taking the film layer structure of the display substrate shown in FIG3B as an example, the compensation plate can be located in the bottom light-shielding metal layer, and multiple gate connection lines can be located in the first gate metal layer and the second gate metal layer. The film formation effect of the inorganic insulating layer (for example, including the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104) above the edge of the compensation plate will be deteriorated, thereby causing the first source and drain metal layer to easily produce metal residues and poor routing in the area corresponding to the edge of the compensation plate. In this example, by designing the hollow structure of the compensation plate and using the first gate metal layer and the second gate metal layer to cover part of the edge of the hollow structure of the compensation plate, the metal residues or poor routing in the conductive film layer above the edge of the hollow structure of the compensation plate can be improved.

[0123] Figure 5 is a schematic diagram illustrating the positions of the first straight connecting segment of the gate connecting trace and the multiple first hollow portions of the compensation plate according to at least one embodiment of the present disclosure. In this example, the hollow structure of the compensation plate may include multiple first hollow portions; the multiple straight trace segments of the multiple first traces may include: first straight connecting segments and second straight connecting segments of the multiple gate connecting traces. Figure 5 illustrates the positional relationship between the first straight connecting segment and the first hollow portion. The positional relationship between the second straight connecting segment and the first hollow portion can be referenced to the positional relationship between the first straight connecting segment and the first hollow portion, and therefore will not be further described here.

[0124] In some examples, as shown in FIG5 , the first straight connection segments 331 of the plurality of gate connection traces 33 may extend along the first direction X and be arranged sequentially along the second direction Y. The plurality of first straight connection segments 331 may be located in the same conductive layer (e.g., the first gate metal layer or the second gate metal layer), or may be arranged alternately in the first gate metal layer and the second gate metal layer. This embodiment is not limited to this.

[0125] In some examples, as shown in FIG5 , the hollow structure of the compensation plate may include multiple first hollow portions 41. The multiple first hollow portions 41 may be arranged in an array along a first direction X and a second direction Y. In this example, a row of first hollow portions may include multiple first hollow portions 41 arranged along the first direction X, and a column of first hollow portions may include multiple first hollow portions 41 arranged along the second direction Y. A row of first hollow portions may be aligned along the first direction X. A column of first hollow portions may be aligned along the second direction Y.

[0126] In some examples, the first hollow portion 41 may be an opening provided on the compensation plate. The orthographic projection of the first hollow portion 41 on the substrate may be a rectangle. The first hollow portion 41 may have first edges 411 and 412 disposed parallel to each other, and second edges 413 and 414 disposed parallel to each other. The first edge 411, the second edge 413, the first edge 412, and the second edge 414 may be connected in sequence. The extension direction of the first edge 411 may be perpendicular to the extension direction of the second edge 413. The extension direction of the first edges 411 and 412 may be parallel to the extension direction of the plurality of first straight line connecting segments 331, and the extension direction of the second edges 413 and 414 may be perpendicular to the extension direction of the plurality of first straight line connecting segments 331.

[0127] In some examples, the orthographic projection of the first edge 411 of the first hollow portion 41 onto the substrate may be located within the orthographic projection of one first linear connecting segment 331 onto the substrate, and the orthographic projection of the first edge 412 onto the substrate may be located within the orthographic projection of another first linear connecting segment 331 onto the substrate. In some examples, the orthographic projection of the first edge 411 onto the substrate may be located at the middle position of the orthographic projection of one first linear connecting segment 331 onto the substrate along the second direction Y. The orthographic projection of the first edge 412 onto the substrate may be located at the middle position of the orthographic projection of another first linear connecting segment 331 onto the substrate along the second direction Y. For example, the orthographic projection of the first edge 411 onto the substrate may coincide with the midline of the orthographic projection of one first linear connecting segment 331 onto the substrate along the second direction Y. The orthographic projection of the first edge 412 onto the substrate may coincide with the midline of the orthographic projection of another first linear connecting segment 331 onto the substrate along the second direction Y.

[0128] In some examples, the first straight line connecting segment 331 where the orthographic projection of the first edge 411 on the substrate is located may not be adjacent to the first straight line connecting segment 331 where the orthographic projection of the first edge 412 on the substrate is located, and at least one first straight line connecting segment (for example, two first straight line connecting segments) may be set between the two first straight line connecting segments 331.

[0129] In some examples, the orthographic projections of the second edges 413 and 414 of the first hollow portion 41 on the substrate may overlap with the orthographic projections of multiple first linear connecting segments 331 (e.g., four or three first linear connecting segments 331) on the substrate. The second edges 413 and 414 may have the same length, and the length of the second edge 413 may be greater than the width of at least two first linear connecting segments 331. The length of the first edge 411 may be the same as or different from the length of the second edge 413. This embodiment is not limited to this.

[0130] In some examples, the orthographic projection of a first straight line connecting segment 331 on the substrate may cover the orthographic projection of the first edge 411 of multiple first hollow portions 41 in a row of first hollow portions on the substrate, or may cover the orthographic projection of the first edge 412 of multiple first hollow portions 41 in a row of first hollow portions on the substrate.

[0131] The setting method of the first hollow portion in this example can improve the influence of the boundary position of the compensation plate (such as the edge position of the first hollow portion) on the upper inorganic film layer and the conductive layer (such as the first source and drain metal layer), and can prevent material residue and poor routing of the conductive layer.

[0132] Figure 6A is a partially enlarged schematic diagram of region S1 in Figure 1. Figure 6B is a schematic diagram of the first straight connecting segments of the plurality of gate connection traces in Figure 6A. Figure 6C is a schematic diagram of the compensation plate in Figure 6A. Figures 6A to 6C illustrate the partial overlap of the first straight connecting segments of the gate connection traces and the compensation plate.

[0133] In some examples, as shown in Figures 6A to 6C, the first straight connection segment 331a of the gate connection trace 33a located in the first gate metal layer can extend along the first direction X, and the first straight connection segment 331b of the gate connection trace 33b located in the second gate metal layer can extend along the first direction X. The first straight connection segments 331a of the plurality of gate connection traces 33a and the first straight connection segments 331b of the plurality of gate connection traces 33b can be alternately arranged along the second direction Y. The orthographic projections of the first straight connection segments 331a and 331b on the substrate can have no overlap. The line widths of the first straight connection segments 331a and 331b can be the same.

[0134] In some examples, the compensation plate 36 may be located in the bottom light-shielding metal layer. The compensation plate 36 may have a plurality of first hollow portions 41 arranged in an array along a first direction X and a second direction Y. The plurality of first hollow portions 41 may be aligned along the first direction X and the second direction Y.

[0135] In some examples, the orthographic projection of the first hollow portion 41 on the substrate may be rectangular. The first hollow portion 41 may have parallel first edges 411 and 412, and parallel second edges 413 and 414. The first edges 411 and 412 may extend along a first direction X. The first edges 411 and 412 may extend in the same direction as the first linear segments 331a and 331b. The second edges 413 and 414 may extend perpendicular to the direction of the first linear segments 331a and 331b. The orthographic projection of the first edge 411 (or 412) of the first hollow portion 41 on the substrate may be within the orthographic projection of one first linear segment 331a (or 331b) on the substrate. The orthographic projection of the second edge 413 (or 414) of the first hollow portion 41 on the substrate may overlap with the orthographic projections of multiple first linear segments (e.g., four or three first linear segments) on the substrate. The length of the second edge 413 (or 414 ) may be greater than the width of the at least two first straight line connecting segments.

[0136] This example can improve the influence of the boundary position of the compensation plate (such as the edge position of the first hollow portion) on the upper inorganic film layer and the conductive layer, and prevent material residue and poor routing of the upper conductive layer (such as the first source and drain metal layer).

[0137] FIG7 is another schematic diagram of the positions of the first straight connecting section of the gate connection line and the multiple first hollow portions of the compensation plate of at least one embodiment of the present disclosure. In some examples, as shown in FIG7 , the compensation plate may have multiple first hollow portions 41. The multiple first hollow portions 41 may be arranged in an array along the first direction X and the second direction Y. The multiple first hollow portions 41 may be aligned in the second direction Y; along the first direction X, at least two adjacent first hollow portions 41 may be staggered. For example, the adjacent multiple first hollow portions 41 (such as six first hollow portions) in a row of first hollow portions may be arranged in a stepped manner. For example, each first hollow portion 41 may have a center line passing through a center point and extending along the first direction X, and the center lines of the adjacent six first hollow portions 41 in a row of first hollow portions may be arranged in sequence along the second direction Y, and the minimum distance between the center lines of any two adjacent first hollow portions 41 may be the same. This embodiment is not limited to this.

[0138] In some examples, as shown in FIG7 , the orthographic projection of the first hollow portion 41 on the substrate can be rectangular. The first edges 411 and 412 of the first hollow portion 41 extend parallel to the first direction X, and the orthographic projections of the first edges 411 and 412 on the substrate can be located within the orthographic projections of two different first straight line connecting segments 331 on the substrate. The second edges 413 and 414 of the first hollow portion 41 extend parallel to the second direction Y, and the orthographic projections of the second edges 413 and 414 on the substrate overlap with the orthographic projections of multiple (e.g., four) first straight line connecting segments 331 on the substrate.

[0139] In this example, by staggering the plurality of first hollow portions, the loads of the plurality of first straight line connection segments can be made the same after compensation by the compensation plate, thereby achieving differentiated load compensation for the plurality of gate connection lines.

[0140] FIG8 is another schematic diagram of the positions of the first straight connecting section of the gate connection trace and the multiple first hollow portions of the compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG8 , the multiple first hollow portions 41 of the compensation plate can be arranged along the first direction X and the second direction Y. The multiple first hollow portions 41 can be aligned along the second direction Y. The multiple first hollow portions X can be staggered in the first direction X. A row of first hollow portions can include: a first group of hollow portions 41a and a second group of hollow portions 41b arranged alternately along the first direction X. The number of first hollow portions 41 included in the first group of hollow portions 41a and the second group of hollow portions 41b can be the same. However, this embodiment is not limited to this. For example, the number of first hollow portions included in the first group of hollow portions 41a and the second group of hollow portions 41b can be different. For example, the number of first hollow portions included in the first group of hollow portions 41a can be greater than the number of first hollow portions included in the second group of hollow portions 41b.

[0141] In some examples, the first group of hollow portions 41 a may include multiple first hollow portions 41 (e.g., three first hollow portions) aligned along the first direction X; the second group of hollow portions 41 b may include multiple first hollow portions 41 (e.g., three first hollow portions) aligned along the first direction X. Center lines of the multiple first hollow portions 41 in the first group of hollow portions 41 a parallel to the first direction X may coincide, and center lines of the multiple first hollow portions 41 in the second group of hollow portions 41 b parallel to the first direction X may coincide.

[0142] In some examples, the first group of hollow portions 41 a and the second group of hollow portions 41 b may be staggered in the first direction X. For example, a center line of the first group of hollow portions 41 a parallel to the first direction X may be located on one side of a center line of the second group of hollow portions 41 b parallel to the first direction X in the second direction Y.

[0143] In this example, the overlapping area of ​​the orthographic projection of the first straight connection segment 331 of the multiple gate connection lines 33 on the substrate and the orthographic projection of the compensation plate on the substrate can be different. In some examples, the overlapping area of ​​the first straight connection segment (for example, the first straight connection segment 331-1) that overlaps with the orthographic projection of both the first group of hollow portions 41a and the second group of hollow portions 41b on the substrate and the compensation plate can be smaller than the overlapping area of ​​the first straight connection segment (for example, the first straight connection segment 331-2 or 331-3) that overlaps only with the orthographic projection of the first group of hollow portions 41a or the second group of hollow portions 41b on the substrate and the compensation plate. The compensation capacitance of the compensation plate for the first straight connection segment 331-1 can be smaller than the compensation capacitance for the first straight connection segment 331-2 or 331-3. In this way, the compensation plate can focus on signal compensation for the first straight connection segments 331-2 and 331-3, achieving differentiated compensation for different gate connection lines. In this example, the orthographic projection relationship between the edge of a single first hollow portion and the first straight line connecting segment can be referred to the description of the aforementioned embodiment, so it will not be repeated here.

[0144] Figure 9 is another schematic diagram of the positions of the first straight connecting segment of the gate connection trace and the multiple first hollow portions of the compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 9, the multiple first hollow portions 41 of the compensation plate can be arranged along the first direction X and the second direction Y. The multiple first hollow portions 41 can be aligned along the second direction Y. The multiple first hollow portions 41 can be staggered in the first direction X. A row of first hollow portions can include: a third group of hollow portions 41c and a fourth group of hollow portions 41d, arranged alternately along the first direction X. The third group of hollow portions 41c and the fourth group of hollow portions 41d can include the same number of first hollow portions 41. However, this embodiment is not limited to this. For example, the third group of hollow portions 41c and the fourth group of hollow portions 41d can include different numbers of first hollow portions. For example, the number of first hollow portions included in the third group of hollow portions 41c can be greater than the number of first hollow portions included in the fourth group of hollow portions 41d.

[0145] In some examples, the third group of hollow portions 41 c may include multiple first hollow portions 41 (e.g., three first hollow portions) staggered along the first direction X, and the fourth group of hollow portions 41 d may include multiple first hollow portions 41 (e.g., three first hollow portions) staggered along the first direction X. The centerlines of the multiple first hollow portions 41 in the third group of hollow portions 41 c parallel to the first direction X may be arranged sequentially in a direction opposite to the second direction Y, and the minimum distance between the centerlines of any two adjacent first hollow portions 41 in the third group of hollow portions 41 c parallel to the first direction X may be the same. The centerlines of the multiple first hollow portions 41 in the fourth group of hollow portions 41 d parallel to the first direction X may be arranged sequentially along the second direction Y. The minimum distance between the centerlines of any two adjacent first hollow portions 41 in the fourth group of hollow portions 41 d parallel to the first direction X may be the same.

[0146] In some examples, at least one first hollow portion in the third group of hollow portions 41 c and at least one first hollow portion in the fourth group of hollow portions 41 d may be aligned in the first direction X. For example, adjacent hollow portions in the third group 41 c and the fourth group 41 d may be symmetrically arranged about a midline thereof parallel to the second direction Y. However, this embodiment is not limited thereto.

[0147] In this example, the overlapping areas of the orthographic projections of the first straight connecting segments 331 of the plurality of gate connecting traces 33 on the substrate and the orthographic projections of the compensation plate on the substrate can be different. In some examples, the overlapping area of ​​the first straight connecting segment (e.g., first straight connecting segment 331-5 or 331-6) that overlaps with the orthographic projections of all first hollow portions of the third group of hollow portions 41c and the fourth group of hollow portions 41d on the substrate and the compensation plate can be greater than the overlapping area of ​​the first straight connecting segment (e.g., first straight connecting segment 331-4) that overlaps with only the orthographic projections of some first hollow portions of the first group of hollow portions 41a and the second group of hollow portions 41b on the substrate and the compensation plate. The compensation capacitance of the compensation plate for the first straight connecting segment 331-4 can be greater than the compensation capacitance for the first straight connecting segments 331-5 or 331-6. In this way, the compensation plate can focus on signal compensation for the first straight connecting segment 331-4, achieving differentiated compensation for different gate connecting traces. In this example, the orthographic projection relationship between the edge of a single first hollow portion and the first straight line connecting segment can be referred to the description of the aforementioned embodiment, so it will not be repeated here.

[0148] Figure 10A is another partially enlarged schematic diagram of region S1 in Figure 1. Figure 10B is a schematic diagram of the first straight connecting segments of the plurality of gate connection traces in Figure 10A. Figure 10C is a schematic diagram of the compensation plate in Figure 10A. Figures 10A to 10C illustrate the partial overlap of the first straight connecting segments of the gate connection traces and the compensation plate.

[0149] In some examples, the compensation plate 36 can be located in the bottom light-shielding metal layer. The compensation plate 36 can have a plurality of first hollow portions 41 arranged in an array along the first direction X and the second direction Y. The plurality of first hollow portions 41 can include a fifth group of hollow portions 41e arranged in an array along the first direction X and the second direction Y. The plurality of first hollow portions 41 can be aligned in the second direction Y and staggered in the first direction X.

[0150] In some examples, the fifth group of hollow portions 41e may include: six first hollow portions 41 staggered along the first direction X. The center lines of the six first hollow portions 41 in the fifth group of hollow portions 41e parallel to the first direction X may be arranged sequentially along the second direction Y, and the minimum distance between the center lines of any two adjacent first hollow portions 41 parallel to the first direction X may be the same. Adjacent hollow portions 41e in the fifth group of hollow portions arranged along the first direction X may be aligned in the first direction X. For example, the first first hollow portion in the fifth group of hollow portions 41e and the first first hollow portion in the adjacent fifth hollow portion 41e in the first direction X may be aligned in the first direction X. The remaining positional relationships between the first hollow portions and the first straight connecting segments in this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0151] In this example, by staggering the plurality of first hollow portions along the extension direction of the first straight line connection segment, the overlapping area of ​​the orthographic projection of the plurality of first straight line connection segments and the compensation plate on the substrate can be adjusted, thereby achieving differentiated compensation for the plurality of gate connection lines.

[0152] Figure 11A is a partially enlarged schematic diagram of region S2 in Figure 1 . Figure 11B is a schematic diagram of multiple arcuate connecting segments in Figure 11A . Figure 11C is a schematic diagram of the compensation plate in Figure 11A . In this example, the multiple arcuate connecting segments of the first routing lines may include: multiple arcuate connecting segments 333 of the gate connecting routing lines 33 .

[0153] In some examples, as shown in Figures 11A to 11C, the curved connecting segments 333 of the multiple gate connection traces 33 can extend along the curved edge of the hole area B5. The multiple curved connecting segments 333 can be located in the same conductive layer (e.g., the first gate metal layer or the second gate metal layer), or can be arranged alternately in the first gate metal layer and the second gate metal layer. For example, the curved connecting segment 333a of the gate connection trace 33a located in the first gate metal layer can extend along the edge of the hole area B5, and the curved connecting segment 333b of the gate connection trace 33b located in the second gate metal layer can extend along the edge of the hole area B5. The curved connecting segments 333a of the multiple gate connection traces 33a and the curved connecting segments 333b of the multiple gate connection traces 33b can be arranged alternately in a direction away from the hole area B5. The orthographic projections of the curved connecting segments 333a and 333b on the substrate can not overlap. The line widths of the curved connecting segments 333a and 333b can be the same. For example, the arc-shaped connecting segment 333a or 333b may be an arc segment with the center of the hole area B5 as the center of the circle.

[0154] In some examples, the compensating plate 36 may include a plurality of second hollow portions 42, which may be arranged along the extension direction of the arcuate connecting segments 333a and 33b. For example, the plurality of second hollow portions 42 may be arranged in a row along the extension direction of the arcuate connecting segments 333a and 333b, and the plurality of rows of second hollow portions may be arranged in a direction away from the aperture area B5. The spacing between adjacent second hollow portions 42 in a row of second hollow portions near the aperture area B5 may be smaller than the spacing between adjacent second hollow portions 42 in a row of second hollow portions away from the aperture area B5. For example, the plurality of second hollow portions 42 may be arranged radially from the center of the aperture area A2.

[0155] In some examples, the orthographic projection of the second hollow portion 42 onto the substrate can be rectangular. The second hollow portion 42 can have parallel third edges 421 and 422, and parallel fourth edges 423 and 424. The third edges 421 and 422 can extend parallel to the directions of the arcuate connecting segments 333a and 333b, while the fourth edges 423 and 424 can extend perpendicular to the directions of the arcuate connecting segments 333a and 333b. The orthographic projection of the third edge 421 (or 422) onto the substrate can be within the orthographic projection of one arcuate connecting segment 333a (or 333b) onto the substrate. The orthographic projection of the fourth edge 423 (or 424) onto the substrate can overlap with the orthographic projections of multiple arcuate connecting segments (e.g., three or four arcuate connecting segments) onto the substrate. The length of the fourth edge 423 (or 424) can be greater than the line width of at least two of the arcuate connecting segments. The arrangement direction of the plurality of second hollow portions 42 may change with the arc angle of the arc-shaped connecting segment to ensure that the orthographic projection of the third edge of the second hollow portion 42 on the substrate is within the orthographic projection range of the arc-shaped connecting segment on the substrate.

[0156] This example provides multiple second hollow portions arranged along the extension direction of the arc-shaped connecting segments, and the orthographic projections of the multiple arc-shaped connecting segments on the substrate can cover the orthographic projections of the third edges of the multiple second hollow portions on the substrate. This can improve the impact of the boundary position of the compensation plate (e.g., the edge position of the second hollow portion) on the upper inorganic film layer and conductive layer, and can prevent material residue and poor routing in the upper conductive layer (e.g., the first source and drain metal layer). The remaining description of the compensation plate of this example can be referred to the description of the previous embodiment, and will not be repeated here.

[0157] Figure 12 is a schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure. The dashed line within winding area B5 in Figure 12 divides winding area B5 into a first region near aperture area A2 and a second region farther from aperture area A2. The first region houses the curved connecting segments of gate connection traces 33 within winding area B5, while the second region houses the first and second straight connecting segments of gate connection traces 33.

[0158] In some examples, as shown in FIG12 , the hole area A2 may have a first center line O1 extending along a first direction X and a second center line O2 extending along a second direction Y. The first center line O1 and the second center line O2 may divide the winding area B5 into four regions (e.g., an upper left region, an upper right region, a lower left region, and a lower right region). The plurality of gate connection traces may include: a first group of gate connection traces located on one side of the first center line O1 in the second direction Y, and a second group of gate connection traces located on the opposite side of the first center line O1 in the second direction Y. For example, the first group of gate connection traces and the second group of gate connection traces may be symmetrically arranged about the first center line O1. In this example, the first group of first traces that bypass the hole area A2 from one side may include a first group of gate connection traces, and the second group of first traces that bypass the hole area A2 from the other side may include a second group of gate connection traces.

[0159] In some examples, as shown in FIG12 , the compensation plate 36 located in the winding area B5 may have a third hollow portion 43a located in the upper left region and a third hollow portion 43b located in the lower right region. The orthographic projection of the third hollow portion 43a on the substrate may overlap with the orthographic projection of the first group of gate connection traces on the substrate, and the orthographic projection of the third hollow portion 43b on the substrate may overlap with the orthographic projection of the second group of gate connection traces on the substrate.

[0160] In some examples, the third hollow portions 43a and 43b overlap with the orthographic projections of the multiple gate connection traces disposed near the aperture area A2 on the substrate, but may not overlap with the orthographic projections of the multiple gate connection traces disposed away from the area B5 on the substrate. The lengths of the multiple gate connection traces disposed near the aperture area A2 may be greater than the lengths of the multiple gate connection traces disposed away from the aperture area A2. In this example, by disposing the third hollow portion near the aperture area A2, the capacitance compensation for the longer gate connection traces can be reduced, while the capacitance compensation for the shorter gate connection traces can be increased, so that the loads of the multiple gate connection traces remain the same after compensation.

[0161] In some examples, the third hollow portions 43a and 43b can both be arcuate hollow grooves extending along the edge of the aperture area A2. The structure of the third hollow portion 43a is used as an example for illustration. The third hollow portion 43a can have a fifth edge 431, a sixth edge 432, a seventh edge 433, and an eighth edge 434. The fifth edge 431, the seventh edge 433, the sixth edge 432, and the eighth edge 433 can be connected in sequence. The fifth edge 431 and the sixth edge 432 can extend in the same direction, for example, along the direction in which the multiple arcuate connecting segments extend. The orthographic projections of the fifth edge 431 and the sixth edge 432 on the substrate can at least partially overlap with the orthographic projections of the multiple arcuate connecting segments on the substrate. For example, the orthographic projection of one arcuate connecting segment on the substrate can overlap the orthographic projection of the fifth edge 431 (or the sixth edge 432) on the substrate. The seventh edge 433 and the eighth edge 434 can extend in a direction perpendicular to the direction in which the arcuate connecting segments extend. For example, the extension line of the seventh edge 433 or the eighth edge 434 may pass through the intersection of the first center line O1 and the second center line O2. However, this embodiment is not limited thereto.

[0162] Figure 13A is a partial schematic diagram of the edge of the third hollow portion of at least one embodiment of the present disclosure. In some examples, the orthographic projection of at least part of the edge of the third hollow portion onto the substrate may be a step shape. For example, the orthographic projection of the seventh edge 433 and the eighth edge 434 of the third hollow portion 43a onto the substrate may be a step shape. The step shape may include: a plurality of step structures 430 connected in sequence. Each step structure 430 may include a first step 430-1 and a second step 430-2 connected to each other. The first step 430-1 and the second step 430-2 are straight line segments extending in different directions. For example, the extension direction of the first step 430-1 may be perpendicular to the extension direction of the second step 430-2.

[0163] In some examples, the extension direction of the first terrace stage 430-1 can be parallel to the extension direction of a local segment (e.g., a straight segment or an arcuate segment) of a gate connection trace. The orthographic projection of the first terrace stage 430-1 on the substrate can be located within the orthographic projection of a gate connection trace 33 (e.g., the arcuate segment 333 of the gate connection trace 33) on the substrate. The orthographic projection of the second terrace stage 430-2 on the substrate can overlap with the orthographic projections of at least two adjacent gate connection traces 33 on the substrate. For example, the orthographic projections of the first terrace stage 430-1 of adjacent stepped structures on the substrate can be located within the orthographic projections of two different gate connection traces on the substrate. However, this embodiment is not limited to this. The edge configuration of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also reduces the impact of the compensation plate's boundary position (e.g., the edge position of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source / drain metal layer), thereby preventing material residue in the conductive layer and poor routing.

[0164] Figure 13B is another partial schematic diagram of the edge of the third hollow portion of at least one embodiment of the present disclosure. In some examples, at least a portion of the edge of the third hollow portion can have a stepped shape when projected onto the substrate. For example, the seventh edge 433 and the eighth edge 434 of the third hollow portion 43a can have a stepped shape when projected onto the substrate. This stepped shape can include: a plurality of step structures 430 connected in sequence. Adjacent step structures 430 can be connected by step connecting segments 430-3. Step connecting segments 430-3 can be arc segments. Each step structure 430 can include a first step 430-1 and a second step 430-2 connected to each other. The first step 430-1 and the second step 430-2 are straight line segments extending in different directions. For example, the direction of extension of the first step 430-1 can be perpendicular to the direction of extension of the second step 430-2. In this example, at least a portion of the edge of the third hollow portion can have a circular arc gradient boundary. The edge arrangement of the third hollow portion in this example not only facilitates the differential compensation of the compensation plate for different gate connection traces, but also reduces the impact of the compensation plate's boundary position (e.g., the edge position of the third hollow portion) on the overlying inorganic film layer and conductive layer (e.g., the first source / drain metal layer), thereby preventing material residue in the conductive layer and poor trace alignment. For further explanation of the edges of this example, please refer to the description of the aforementioned embodiment, and will not be repeated here.

[0165] Figure 14 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14 , the compensation plate 36 in winding area B5 can have third hollow portions 43a and 43c located in the upper left region, and third hollow portions 43b and 43d located in the lower right region. The orthographic projections of the third hollow portions 43a and 43c on the substrate overlap with the orthographic projections of the first group of gate connection traces on the substrate, while the orthographic projections of the third hollow portions 43b and 43d on the substrate overlap with the orthographic projections of the second group of gate connection traces on the substrate.

[0166] In some examples, as shown in FIG14 , the third hollow portions 43a, 43b, 43c, and 43d can each be an arc-shaped hollow groove extending along the edge of the aperture area A2. The third hollow portion 43c can be located on a side of the third hollow portion 43a away from the aperture area A2, and the third hollow portion 43d can be located on a side of the third hollow portion 43b away from the aperture area A2. The length of the third hollow portion 43c can be less than the length of the third hollow portion 43a, and the length of the third hollow portion 43d can be less than the length of the third hollow portion 43b.

[0167] The edge arrangement of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also mitigates the impact of the compensation plate's boundary (e.g., the edge of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source / drain metal layer), thereby preventing residual conductive layer material and poor traceability. The remaining structure of the third hollow portion in this example can be found in the description of the preceding embodiment, and will not be further elaborated here.

[0168] FIG15 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG15 , the compensation plate 36 in winding area B5 may have third hollow portions 43a and 43c located in the upper left region, and third hollow portions 43e and 43f located in the lower left region. The orthographic projections of the third hollow portions 43a and 43c on the substrate overlap with the orthographic projections of the first group of gate connection traces on the substrate, while the orthographic projections of the third hollow portions 43e and 43f on the substrate overlap with the orthographic projections of the second group of gate connection traces on the substrate.

[0169] In some examples, as shown in FIG15 , the third hollow portions 43a, 43c, 43e, and 43f can each be an arc-shaped hollow groove extending along the edge of the aperture area A2. The third hollow portion 43c can be located on the side of the third hollow portion 43a away from the aperture area A2, and the third hollow portion 43f can be located on the side of the third hollow portion 43e away from the aperture area A2. The length of the third hollow portion 43c can be less than the length of the third hollow portion 43a, and the length of the third hollow portion 43f can be less than the length of the third hollow portion 43e. For example, the third hollow portions 43a and 43e can be approximately symmetrical about the first centerline O1, and the third hollow portions 43c and 43f can be approximately symmetrical about the first centerline O1. However, this embodiment is not limited to this.

[0170] The edge arrangement of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also mitigates the impact of the compensation plate's boundary (e.g., the edge of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source / drain metal layer), thereby preventing residual conductive layer material and poor traceability. The remaining structure of the third hollow portion in this example can be found in the description of the preceding embodiment, and will not be further elaborated here.

[0171] FIG16 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG16 , the compensation plate 36 in winding area B5 may include third hollow portions 43a and 43c in the upper left region, third hollow portions 43e and 43f in the lower left region, third hollow portions 43g and 43h in the upper right region, and third hollow portions 43b and 43d in the lower right region. The orthographic projections of the third hollow portions 43a, 43c, 43g, and 43h on the substrate overlap with the orthographic projections of the first group of gate connection traces on the substrate, and the orthographic projections of the third hollow portions 43e, 43f, 43b, and 43d on the substrate overlap with the orthographic projections of the second group of gate connection traces on the substrate.

[0172] In some examples, as shown in FIG16 , the third hollow portions 43a, 43b, 43c, 43d, 43e, 43f, 43g, and 43h can all be arc-shaped hollow grooves extending along the edge of the aperture area A2. The third hollow portion 43c can be located on the side of the third hollow portion 43a away from the aperture area A2, the third hollow portion 43f can be located on the side of the third hollow portion 43e away from the aperture area A2, the third hollow portion 43d can be located on the side of the third hollow portion 43b away from the aperture area A2, and the third hollow portion 43h can be located on the side of the third hollow portion 43g away from the aperture area B5. For example, the third hollow portions 43a and 43e can be approximately symmetrical about the first centerline O1, and the third hollow portions 43g and 43a can be approximately symmetrical about the second centerline O2. However, this embodiment is not limited to this.

[0173] The edge arrangement of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also mitigates the impact of the compensation plate's boundary (e.g., the edge of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source / drain metal layer), thereby preventing residual conductive layer material and poor traceability. The remaining structure of the third hollow portion in this example can be found in the description of the preceding embodiment, and will not be further elaborated here.

[0174] In other examples, the third hollow portions 43a, 43g, 43b, and 43e may be connected to form an annular hollow groove to reduce the load compensation for multiple gate connection lines near the hole area A2. In other examples, the third hollow portions 43c, 43h, 43d, and 43f may be connected to form an annular hollow groove to reduce the load compensation for multiple gate connection lines near the hole area A2.

[0175] Figure 17 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the compensation plate 36 in the winding area B5 may have a third hollow portion 43i located in the upper left region and a third hollow portion 43j located in the lower right region. The third hollow portions 43i and 43j may communicate with the edge of the compensation plate 36 near the aperture area A2. The edges of the third hollow portions 43i and 43j may be part of the edge of the compensation plate 36. For example, the third hollow portions 43i and 43j are not independently disposed within the compensation plate 36, but are instead disposed at the edge of the compensation plate 36 near the aperture area A2, such that the edge of the compensation plate 36 forms a recessed recess away from the aperture area A2. In this way, the overlap area between the compensation plate and the orthographic projection of the gate connection trace located near the aperture area on the substrate can be smaller than the overlap area between the compensation plate and the orthographic projection of the gate connection trace located away from the aperture area on the substrate, thereby increasing the load compensation for the gate connection trace located away from the aperture area.

[0176] In some examples, the edge shape of the compensation plate near the hole area can adopt a stepped boundary as shown in Figure 13A, or an arc gradient boundary as shown in Figure 13B. Differentiated compensation is achieved for different gate connection lines by setting the edge of the compensation plate, and the influence of the boundary position of the compensation plate (for example, the edge position of the third hollow portion) on the upper inorganic film layer and the conductive layer (for example, the first source and drain metal layer) can be improved, which can prevent material residue and poor routing of the conductive layer. The rest of the structure of the compensation plate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0177] FIG18 is another schematic diagram of the gate connection routing of the winding area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG18 , the gate connection routing 33 of the winding area B5 may include: a first straight connection segment 331, a second straight connection segment 332, and a folded line connection segment 334. The folded line connection segment 334 may be connected between the first straight line connection segment 331 and the second straight line connection segment 332. The folded line connection segment 334 may include a plurality of sub-straight line segments extending in different extension directions. For other explanations of the gate connection routing of this example, reference may be made to the description of the aforementioned embodiment, so it will not be repeated here.

[0178] FIG19 is a schematic diagram illustrating the positions of the zigzag connecting segments of the gate connection traces and the first hollow portion of the compensation plate in at least one embodiment of the present disclosure. In some examples, as shown in FIG19 , the multiple straight line segments of the multiple first traces of this example may include: multiple first straight line connecting segments 331 extending in the same direction, multiple second straight line connecting segments 332 extending in the same direction, and multiple sub-straight line segments extending in the same direction of the multiple zigzag connecting segments 334. The hollow structure of the compensation plate may include multiple first hollow portions 41. The multiple first hollow portions 41 may be arranged in an array along the extension direction of the multiple sub-straight line segments of the multiple zigzag connecting segments 334. The orthographic projections of the edges of the first hollow portion 41 that extend in the same direction as the sub-straight segments of the fold-line connecting segment 334 (e.g., first edges 411 and 412) on the substrate can be located within the orthographic projections of the corresponding sub-straight segments on the substrate. The orthographic projections of the edges of the first hollow portion 41 that extend perpendicular to the sub-straight segments (e.g., second edges 413 and 414) on the substrate can overlap with the orthographic projections of multiple sub-straight segments on the substrate. The remaining description of the compensation plate of this example can be found in the description of the aforementioned embodiment, and will not be repeated here.

[0179] FIG20 is another schematic diagram of the positions of the zigzag connection segment of the gate connection trace and the first hollow portion of the compensation plate of at least one embodiment of the present disclosure. In some examples, as shown in FIG20 , the hollow structure of the compensation plate may include a plurality of first hollow portions 41. The plurality of first hollow portions 41 may be arranged divergently along the direction of the radial line passing through the center point of the hole area. For example, the center lines of the plurality of first hollow portions 41 arranged in a direction away from the hole area A2 may overlap and be perpendicular to the extension direction of the sub-straight line segments of the plurality of zigzag connection segments 334. The remaining description of the compensation plate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0180] In some examples, if the first routing line located in the winding area has only straight routing segments, the hollow structure of the compensation plate may include multiple first hollow portions, and the orthographic projections of the straight routing segments on the substrate may cover portions of the edges of the first hollow portions. If the first routing line located in the winding area has both straight routing segments and curved routing segments, the hollow structure of the compensation plate may include multiple first hollow portions and multiple second hollow portions, or may include multiple first hollow portions and at least one third hollow portion. The orthographic projections of the straight routing segments on the substrate may cover portions of the edges of the first hollow portion, and the orthographic projections of the curved routing segments on the substrate may cover portions of the edges of the second or third hollow portions. This embodiment is not limited to this.

[0181] In other examples, multiple compensation plates may be provided in the winding area. For example, the winding area B5 may be divided into four regions along the first centerline O1 and the second centerline O2. Each of the four regions may be provided with a compensation plate, and the compensation plates in adjacent regions may be provided independently. Alternatively, a compensation plate may be provided independently in each of the two regions divided by the first centerline (or the second centerline). The hollow structure of each compensation plate may be as described in the previous embodiment, and therefore will not be further described here.

[0182] In other examples, the film layer structure of the display substrate may be as shown in FIG3A , where the compensation plate may be located in the third gate metal layer. The compensation plate located in the third gate metal layer is arranged to overlap with the orthographic projections of gate connection traces located in the first gate metal layer and the second gate metal layer on the substrate, thereby providing load compensation for first-category gate lines connected to different gate connection traces. Alternatively, the compensation plate located in the third gate metal layer may be arranged to overlap with the orthographic projections of data connection traces located in the first source / drain metal layer and the second source / drain metal layer on the substrate, thereby providing load compensation for first-category data lines connected to different data connection traces.

[0183] In other examples, the peripheral area may also include: a first corner area connected between the first peripheral area and the second peripheral area (for example, it may also be called the lower left corner area), and a second corner area connected between the first peripheral area and the third peripheral area (for example, it may also be called the lower right corner area). The orthographic projection of the wiring located in the bottom light-shielding metal layer in the first corner area and the second corner area on the substrate may not overlap with the orthographic projection of the wiring located in the first gate metal layer and the second gate metal layer in the region on the substrate. In other words, in the first corner area and the second corner area, the wiring of the bottom light-shielding metal layer may avoid the wiring settings of the first gate metal layer and the second gate metal layer to avoid the unevenness of the upper inorganic layer caused by the boundary of the bottom light-shielding metal layer, resulting in material residue in the conductive layer and poor wiring.

[0184] Figure 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 21 , the display panel 910 may be an OLED display panel. The display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.

[0185] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0186] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: a substrate comprising a display area and a peripheral area located on at least one side of the display area; A plurality of sub-pixels are arranged on one side of the substrate and located in the display area; a plurality of first wirings, located in the peripheral area, the plurality of first wirings being electrically connected to the plurality of sub-pixels; a compensation plate, located in the peripheral area, with at least one insulating layer provided between the compensation plate and the plurality of first traces; The orthographic projection of the compensation plate on the substrate overlaps with the orthographic projection of the multiple first lines on the substrate; the compensation plate has a hollow structure, and the orthographic projection of the hollow structure on the substrate overlaps with the orthographic projection of at least one first line among the multiple first lines on the substrate.

2. The display substrate according to claim 1, wherein The substrate further includes a hole area, the peripheral area includes a winding area located between the hole area and the display area; the plurality of first traces and the compensation plate are both located in the winding area.

3. The display substrate according to claim 1 or 2, wherein: The hollow structure has at least one first hollow edge, the extension direction of the at least one first hollow edge is parallel to the extension direction of at least one first routing line among the multiple first routing lines, and the orthographic projection of the at least one first hollow edge on the substrate is located within the orthographic projection range of the at least one first routing line on the substrate.

4. The display substrate according to any one of claims 1 to 3, wherein The compensation plate is located on a side of the plurality of first traces close to the substrate.

5. The display substrate according to claim 4, wherein: The plurality of first routing lines are alternately arranged in a first gate metal layer and a second gate metal layer, the second gate metal layer is located on a side of the first gate metal layer away from the substrate, and orthographic projections of adjacent first routing lines in the plurality of first routing lines on the substrate do not overlap; The compensation plate is located on the bottom light-shielding metal layer, and the bottom light-shielding metal layer is located on a side of the first gate metal layer close to the substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: The plurality of first routing lines include: a plurality of straight routing segments extending in the same direction; The hollow structure of the compensation plate includes: a plurality of first hollow portions; At least one of the multiple first hollow portions has a first edge, and the extension direction of the first edge is parallel to the extension direction of the multiple straight line segments; the orthographic projection of a first edge of a single first hollow portion on the substrate is located within the orthographic projection range of a straight line segment on the substrate.

7. The display substrate according to claim 6, wherein: The at least one first hollow portion has a rectangular projection on the substrate, and the at least one first hollow portion also has a second edge, the extension direction of the second edge is perpendicular to the extension direction of the first edge, and the orthographic projection of the second edge on the substrate overlaps with the orthographic projection of at least two of the multiple straight line segments on the substrate.

8. The display substrate according to claim 6, wherein: The plurality of first hollow portions are arranged in an array along the extension direction of the plurality of straight line segments, and adjacent first hollow portions are aligned in the extension direction of the plurality of straight line segments.

9. The display substrate according to claim 6, wherein: The plurality of first hollow portions are arranged in an array along the extension direction of the plurality of straight line segments, and in the extension direction of the plurality of straight line segments, at least two adjacent first hollow portions are staggered.

10. The display substrate according to claim 9, wherein: The multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions, and the row of first hollow portions includes: a first group of hollow portions and a second group of hollow portions that are alternately arranged, the multiple first hollow portions in the first group of hollow portions are aligned, the multiple first hollow portions in the second group of hollow portions are aligned, and the first group of hollow portions and the second group of hollow portions are staggered.

11. The display substrate according to claim 9, wherein: The multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions, and the row of first hollow portions includes: a third group of hollow portions and a fourth group of hollow portions arranged alternately, the multiple first hollow portions in the third group of hollow portions are staggered, and the multiple first hollow portions in the fourth group of hollow portions are staggered; at least one first hollow portion in the third group of hollow portions is aligned with at least one first hollow portion in the fourth group of hollow portions.

12. The display substrate according to claim 9, wherein: The multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions, and the row of first hollow portions includes: multiple fifth groups of hollow portions arranged in sequence, the multiple first hollow portions in the fifth group of hollow portions are staggered, and adjacent fifth groups of hollow portions are aligned.

13. The display substrate according to any one of claims 1 to 5, wherein: The plurality of first routing lines include: a plurality of arc routing segments extending in the same direction; The hollow structure of the compensation plate includes: a plurality of second hollow portions; the plurality of second hollow portions are arranged along the extension direction of the plurality of arc line segments; At least one of the multiple second hollow portions has a third edge, the extension direction of the third edge is parallel to the extension direction of the multiple arc routing segments, and the orthographic projection of the third edge of a single second hollow portion on the substrate is located within the orthographic projection range of an arc routing segment on the substrate.

14. The display substrate according to claim 2, wherein: The hollow structure of the compensation plate includes: at least one third hollow portion; the at least one third hollow portion extends along at least a portion of the edge of the hole area; The length of the first routing line that overlaps with the orthographic projection of the at least one third hollow portion on the substrate is greater than the length of the first routing line that does not overlap with the orthographic projection of the at least one third hollow portion on the substrate.

15. The display substrate according to claim 14, wherein: The plurality of first routing lines include: a first group of first routing lines bypassing the hole area from one side of the hole area, and a second group of first routing lines bypassing the hole area from the other side of the hole area; The hollow structure of the compensation plate includes: at least one third hollow portion overlapping with the orthographic projection of the first group of first traces on the substrate, and at least one third hollow portion overlapping with the orthographic projection of the second group of first traces on the substrate.

16. The display substrate according to claim 14, wherein: At least a portion of an edge of the at least one third hollow portion is in a step-shaped orthographic projection on the substrate; the step-shaped structure comprises: a plurality of step structures connected in sequence, each step structure comprising a first step and a second step connected to each other; the first step and the second step are straight line segments extending in different directions; The orthographic projection of the first stage of each stepped structure on the substrate is within the orthographic projection range of a first routing line on the substrate, and the orthographic projection of the second stage on the substrate overlaps with the orthographic projections of at least two adjacent first routing lines on the substrate.

17. The display substrate according to claim 16, wherein: The step shape further includes: a step connecting segment connecting adjacent step structures, and the step connecting segment is an arc segment.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

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