Cache performance verification method, electronic device and storage medium
By using automated performance verification methods, and by configuring test cases and measuring performance data, the problems of low efficiency and poor accuracy in cache performance verification are solved, and an efficient and accurate verification process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2025-10-29
- Publication Date
- 2026-05-12
AI Technical Summary
Current technologies for verifying cache performance are inefficient, difficult to guarantee accuracy, prone to omissions in manual verification, and costly.
By defining test cases for the cache, configuring access operations and state types, measuring the corresponding performance data, and comparing it with preset thresholds, automated performance verification can be achieved.
It automates cache performance verification, improving efficiency, ensuring accuracy, and reducing maintenance costs.
Smart Images
Figure CN121050960B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification technology, and in particular to a method for verifying cache performance, an electronic device, and a storage medium. Background Technology
[0002] Cache performance verification is a crucial step in the chip design process. The mainstream verification method involves examining the FSDB (Fast Signal Database) file to check for invalid clock cycles in the cache read / write channels, thereby determining whether the cache design's performance meets expectations.
[0003] However, given the large number of performance test cases, verifiers need to check the waveforms of each test case individually, leading to low efficiency in cache performance verification. Furthermore, this manual verification method is prone to omissions and cannot achieve precise comparisons, making it difficult to guarantee the comprehensiveness and accuracy of cache performance verification, and resulting in high verification costs. Summary of the Invention
[0004] This invention provides a method, electronic device, and storage medium for verifying cache performance, in order to solve the shortcomings of poor accuracy and low efficiency in manual cache performance verification in related technologies.
[0005] This invention provides a method for verifying cache performance, comprising:
[0006] Determine test cases for the cache, wherein the test cases include thresholds corresponding to performance data of the data channel of the cache, the data channel corresponds to the access operation of the test case, and the type of the performance data corresponds to the state type of the access operation of the test case;
[0007] The cache is controlled to run under the test case, and the performance data of the cache's data channel is measured to obtain the measured performance data.
[0008] The performance of the cache is verified based on the measured performance data and the threshold.
[0009] According to a cache performance verification method provided by the present invention, the access operation of the test case includes at least one of read request operation and write request operation;
[0010] The data channel corresponding to the read request operation is the read response channel, and the data channel corresponding to the write request operation is the write data channel.
[0011] According to a cache performance verification method provided by the present invention, when the access operation is a read request operation, the state type of the access operation includes at least one of the following: read hit state, read miss and no write-back state, and read miss and write-back state.
[0012] According to a cache performance verification method provided by the present invention, the measurement of performance data of the data channel of the cache includes:
[0013] When the state type is read hit state, measure at least one of the read bandwidth and read hit rate of the cache;
[0014] When the state type is read missing and no write-back state, measure at least one of the cache's read bandwidth, read hit rate, and read missing data bandwidth;
[0015] When the state type is read-miss and write-back, measure at least one of the cache's read bandwidth, read hit rate, read-miss data bandwidth, and write-back data bandwidth.
[0016] According to a cache performance verification method provided by the present invention, when the access operation is a write request operation, the state type of the access operation includes at least one of the following: write hit and full write state, write hit and partial write state, write miss and full write with no write-back state, write miss and partial write with no write-back state, write miss and full write write-back state, and write miss and partial write write-back state.
[0017] According to a cache performance verification method provided by the present invention, the measurement of performance data of the data channel of the cache includes:
[0018] When the state type is write hit and full write state, measure at least one of the write bandwidth and write hit rate of the cache;
[0019] When the state type is write hit and partial write state, measure at least one of the cache's write bandwidth, write hit rate and read missing data bandwidth;
[0020] When the state type is write miss and full write with no write-back, measure at least one of the write bandwidth and write hit rate of the cache.
[0021] When the state type is write miss and partial write with no write-back state, measure at least one of the cache's write bandwidth, write hit rate, and read miss data bandwidth;
[0022] When the state type is write miss and full write-back state, measure at least one of the following: write bandwidth, write hit rate, and write-back data bandwidth of the cache.
[0023] When the state type is write miss and partially write-back state, measure at least one of the cache's write bandwidth, write hit rate, read miss data bandwidth, and write-back data bandwidth.
[0024] According to a cache performance verification method provided by the present invention, the performance data includes at least one of bandwidth and hit rate.
[0025] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the cache performance verification method as described above.
[0026] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the cache performance verification method as described above.
[0027] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the cache performance verification method as described above.
[0028] The cache performance verification method, electronic device, and storage medium provided by this invention control the cache to run under test cases corresponding to access operations and access operation state types, and perform cache performance verification based on thresholds in the test cases and measured performance data corresponding to access operations and access operation state types. This achieves automated performance verification of the cache, which can be completed without human intervention, effectively improving the efficiency of performance verification, ensuring the accuracy and reliability of performance verification, and reducing the maintenance cost of performance verification. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is one of the flowcharts of the cache performance verification method provided by the present invention.
[0031] Figure 2This is a flowchart illustrating the performance verification method for read request operations provided by the present invention.
[0032] Figure 3 This is a flowchart illustrating the performance verification method for write request operations provided by the present invention.
[0033] Figure 4 This is the second flowchart of the cache performance verification method provided by the present invention.
[0034] Figure 5 This is a schematic diagram of the high-speed cache performance verification device provided by the present invention.
[0035] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0037] In the design flow of modern high-performance chips, exemplified by artificial intelligence chips, functional verification is a crucial step and a core element in ensuring product quality. Here, an artificial intelligence chip can be a Graphics Processing Unit (GPU), or it can be an NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), or GPGPU (General-Purpose Computing on Graphics Processing Unit), etc.
[0038] To meet the data throughput and low latency requirements of algorithms such as neural networks, artificial intelligence chips typically integrate high-speed caches. Verifying these caches has become a crucial aspect of the design and verification process for artificial intelligence chips.
[0039] Currently, the mainstream method for verifying cache performance relies on examining the FSDB file. Specifically, verification personnel need to use waveform viewing tools to observe various signals on the cache's read and write channels in the FSDB file, and then identify whether there are bubbles, i.e., whether there are invalid clock cycles, in order to determine whether the cache's design performance meets expectations.
[0040] However, this manual verification method based on FSDB files has obvious limitations.
[0041] Specifically, this verification method relies entirely on the subjective judgment of the verifiers, lacking automated analysis tools. When dealing with a large set of verification test cases, verifiers need to open each FSDB file to examine the waveforms, which is time-consuming and labor-intensive, resulting in low efficiency in cache performance verification. Furthermore, this manual verification method is prone to omissions or misjudgments, especially when the signal waveforms are complex and the number of test cases is large. It is difficult to ensure that every bubble is accurately identified, which compromises the accuracy and reliability of cache performance verification. Moreover, manual verification not only consumes a significant amount of time but also requires verifiers to have extensive experience. For large-scale verification projects, this verification method has poor scalability and struggles to meet the design requirements of rapid iteration.
[0042] To address the aforementioned problems, this invention provides a method for verifying cache performance. This performance verification method can be applied to the performance verification of caches, such as the performance verification of L2 caches. Figure 1 This is one of the flowcharts illustrating the cache performance verification method provided by this invention, such as... Figure 1 As shown, the method includes:
[0043] Step 110: Determine test cases for the cache. The test cases include thresholds corresponding to the performance data of the data channel of the cache. The data channel corresponds to the access operation of the test case. The type of the performance data corresponds to the state type of the access operation of the test case.
[0044] Specifically, test cases for the cache can be pre-configured. The number of test cases can be one or more, and each test case is set for a specific access operation and the state type under the access operation.
[0045] Furthermore, the access operations of a test case refer to the access operations performed on the cache when the application test case performs performance verification on the cache. It can be understood that the access operations of a test case determine the verification result obtained based on that test case, specifically reflecting the performance of the cache under what type of access operation. For example, the access operation of a test case can be a read request operation or a write request operation.
[0046] The cache uses different data channels for different access operations. For example, for read requests, data transmission is performed through the read response channel; for write requests, data transmission is performed through the write data channel. Therefore, in this embodiment of the invention, the access operations of the test cases can correspond to the data channels of the cache.
[0047] When performing a type of access operation on a cache, there may be several different state types. Here, state type refers to the type of cache access state when performing a type of access operation. For example, for the case of a read request operation, the state type of the access operation can be a read hit state or a read miss state. Furthermore, the read miss state can be further subdivided into read miss with no write-back state, read miss with write-back state, etc.
[0048] It is understandable that the data operations performed by the cache differ under different state types. For example, in a read hit state, the hit data can be directly input into the read response channel for transmission. In a read miss state, the missing data needs to be read from the lower-level storage and then input into the read response channel for transmission. Therefore, the performance data required for cache performance verification varies depending on the state type. Here, performance data refers to data that reflects the data transmission performance of the cache, such as bandwidth or hit ratio. This embodiment of the invention does not specifically limit this. Thus, in this embodiment of the invention, the state type of the access operation of the test case can correspond to the type of performance data of the cache's data channel.
[0049] Based on this, for a single test case, there is a corresponding access operation and its state type. Accordingly, the test case includes a threshold corresponding to the performance data of the cache's data channel, where the data channel corresponds to the access operation, and the type of performance data corresponds to the state type of the access operation. Thus, given an access operation and its state type, the test case can indicate the type of performance data to be measured when the cache is in that state type. Furthermore, the threshold included in the test case can be used to compare with actual measured performance data, thereby achieving cache performance verification.
[0050] In step 110 of this embodiment of the invention, determining the test cases for the cache can be done by configuring test cases for the cache. For example, to verify the performance of the cache under a certain state type, corresponding test cases are configured, and thresholds in the test cases are configured according to the design goals. Alternatively, determining the test cases for the cache can be done by selecting one or more test cases required for this performance verification from pre-configured test cases. This embodiment of the invention does not specifically limit this.
[0051] Step 120: Control the cache to run under the test case, and measure the performance data of the cache's data channel to obtain the measured performance data.
[0052] Specifically, after determining the test cases, the cache can be controlled to run under those test cases. This can be achieved by controlling the cache to execute the access operations of the test cases, so that the cache is in the state type of the access operations of the test cases. During this process, the performance data of the cache's data channels can be measured. Specifically, the performance data of the data channels corresponding to the access operations of the test cases and the state type corresponding to the access operations of the test cases can be measured. The data obtained from this measurement is recorded as the measured performance data in this embodiment of the invention.
[0053] It is understandable that the type of measured performance data is consistent with the type of performance data corresponding to the threshold in the test case. For example, if the test case includes a threshold for the read data bandwidth of the read response channel, then the measured performance data will also include the measured value of the read data bandwidth of the read response channel.
[0054] Step 130: Based on the measured performance data and the threshold, perform performance verification on the cache.
[0055] Specifically, after obtaining the measured performance data of the cache under test cases, the measured performance data can be compared with the threshold values in the test cases, thereby achieving performance verification for the cache. For example, if every measured value in the measured performance data is better than or equal to the threshold value in the test cases, the performance verification for the cache is determined to be successful; if there is a measured value in the measured performance data that is worse than the threshold value in the test cases, the performance verification for the cache is determined to be unsuccessful.
[0056] In the method provided in this embodiment of the invention, the cache is controlled to run under test cases corresponding to the access operation and the state type of the access operation. Based on the threshold in the test cases and the measured performance data corresponding to the access operation and the state type of the access operation, the performance of the cache is verified. This realizes automated performance verification of the cache, which can be completed without human intervention, effectively improving the efficiency of performance verification, ensuring the accuracy and reliability of performance verification, and reducing the maintenance cost of performance verification.
[0057] Based on the above embodiments, the access operations of the test cases include at least one of read request operations and write request operations;
[0058] The data channel corresponding to the read request operation is the read response channel, and the data channel corresponding to the write request operation is the write data channel.
[0059] Specifically, access operations may include at least one of read request operations and write request operations.
[0060] The read request operation is used to read data from the cache. A read request operation can trigger a cache lookup and return the read data through the read response channel. In other words, the cache's read response channel can be considered as the data channel for the read request operation.
[0061] Write request operations are used to write data to the cache. Write request operations can transfer data to the cache through the write data channel to trigger the cache to write data. That is, the cache's write data channel can be regarded as the data channel for write request operations.
[0062] Therefore, when the access operation is a read request operation, the performance data of the cache's read response channel can be measured to verify the cache's performance when performing a read request operation; when the access operation is a write request operation, the performance data of the cache's write data channel can be measured to verify the cache's performance when performing a write request operation.
[0063] Based on any of the above embodiments, when the access operation is a read request operation, the state type of the access operation includes at least one of the following: read hit state, read miss and no write-back state, and read miss and write-back state.
[0064] Specifically, for access operations that are read request operations, the cache may correspond to various state types.
[0065] In this context, a read hit status means that the data required by a read request is found directly in the cache.
[0066] A read miss occurs when the data required by a read request is not in the cache, and the data needs to be loaded from the lower-level storage. To load the data from the lower-level storage, space needs to be freed up in the cache for the required data. This requires discarding a cache line. If the discarded cache line is clean and has not been modified, it does not need to be written back to the lower-level storage (i.e., no write-back is required). However, if the discarded cache line is dirty, has been modified, or is inconsistent with the data in the lower-level storage, it needs to be written back to the lower-level storage to ensure data consistency (i.e., a write-back is required).
[0067] The "read missing and no write-back" state refers to a state where a read is missing but no write-back is required. Specifically, it means that the data required by the read request is not in the cache, and when the cache makes room for the required data, the old cache line being replaced is clean and unmodified, so there is no need to write the old cache line being replaced back to the next level of storage.
[0068] The read-miss and write-back state refers to a state where a read is missing and a write-back is required. Specifically, it means that the data required by the read request is not in the cache, and when the cache makes room for the required data, the old cache line being replaced is dirty and has been modified. Therefore, the old cache line being replaced needs to be written back to the next level of storage.
[0069] Based on any of the above embodiments, when the access operation is a read request operation, in step 120, measuring the performance data of the cache data channel includes:
[0070] When the state type is read hit state, measure at least one of the read bandwidth and read hit rate of the cache;
[0071] When the state type is read missing and no write-back state, measure at least one of the cache's read bandwidth, read hit rate, and read missing data bandwidth;
[0072] When the state type is read-miss and write-back, measure at least one of the cache's read bandwidth, read hit rate, read-miss data bandwidth, and write-back data bandwidth.
[0073] Specifically, for the read-hit state, the data required by the read request is directly found in the cache, and the cache can directly return the read data through the read response channel. Therefore, at least one of the read bandwidth and read hit rate of the read response channel can be measured as actual performance data in the read-hit state. Accordingly, in the test cases for the read-hit state, there are at least one threshold for the read bandwidth and read hit rate of the read response channel. For example, the threshold for the read bandwidth can be denoted as avg_RDBW (read data Bandwidth), and the threshold for the read hit rate can be denoted as hit ratio. In the read-hit state, the hit ratio can be set to 100%.
[0074] For the read-miss and no-write-back scenario, the data required by the read request is not in the cache. When the cache makes room for the required data, the replaced old cache line is clean and unmodified, so there's no need to write it back to the lower-level storage. The cache needs to load the data required by the read request from the lower-level storage and then return the loaded data through the read response channel. Therefore, it's possible to measure not only at least one of the read bandwidth and read hit rate of the read response channel, but also the read-miss data bandwidth. Read-miss data bandwidth refers to the bandwidth the cache uses to read the missing data required by the read request from the lower-level storage. Accordingly, in the read-miss and no-write-back test cases, there are at least one of the following thresholds: read bandwidth threshold, read hit rate threshold, and read-miss data bandwidth threshold. The read hit rate threshold (hit ratio) can be set to 0, and the read-miss data bandwidth threshold can be denoted as avg_RMDBW (read missdata Bandwidth).
[0075] For the read-miss and write-back state scenario, where the data required by the read request is not in the cache, and the old cache line being replaced is dirty or modified while the cache is freeing up space for the required data, the discarded cache line needs to be written back to the lower-level storage. The cache needs to write the discarded cache line back to the lower-level storage, load the data required by the read request from the lower-level storage, and then return the loaded data through the read response channel. Therefore, it is possible to measure not only at least one of the read bandwidth and read hit rate of the read response channel, but also the read-miss data bandwidth and write-back data bandwidth. Write-back data bandwidth refers to the bandwidth by which the cache writes the discarded cache line to the lower-level storage, which is the bandwidth for cache write-back. Accordingly, in the read-miss and write-back state test cases, there are at least one of the following thresholds: read bandwidth threshold, read hit rate threshold, read-miss data bandwidth threshold, and write-back data bandwidth threshold. The read hit rate threshold (hitratio) can be set to 0, and the write-back data bandwidth threshold can be denoted as avg_WEDBW (write evict dataBandwidth).
[0076] It should be noted that the read bandwidth, read missing data bandwidth, and write-back data bandwidth mentioned above are all average bandwidth values during the operation of the cache under test cases. Specifically, read bandwidth refers to the bandwidth of the cache input port, while read missing data bandwidth and write-back data bandwidth refer to the bandwidth of the cache output port.
[0077] Figure 2 This is a flowchart illustrating the performance verification method for read request operations provided by the present invention, as shown below. Figure 2 As shown, when performing performance verification on the cache in response to read request operations, initialization is performed first. Specifically, the entire cache's RAM (Random Access Memory) can be initialized.
[0078] Subsequently, thresholds can be set in the test cases for each state type of read request operation. Here, read request operation can include sending read requests to multiple random addresses. The state types can be categorized based on whether a hit or replacement occurs. For a hit (read hit state), thresholds for read bandwidth and read hit rate can be set in the test cases. For a miss without replacement (read missing state with no write-back), thresholds for read bandwidth, read hit rate, and read missing data bandwidth can be set in the test cases. For a miss with replacement required (read missing state with write-back), thresholds for read bandwidth, read hit rate, read missing data bandwidth, and write-back data bandwidth can be set in the test cases.
[0079] After the test cases are set up, performance verification of the cache can be triggered based on the test cases. While the cache is running under the test cases, performance data is collected and measured to obtain actual performance data.
[0080] Subsequently, the measured performance data is compared with the threshold of the performance data in the test cases to obtain the performance verification results of the cache for read request operations.
[0081] Based on any of the above embodiments, when the access operation is a write request operation, the state type of the access operation includes at least one of the following: write hit and full write state, write hit and partial write state, write miss and full write with no write-back state, write miss and partial write with no write-back state, write miss and full write write-back state, and write miss and partial write write-back state.
[0082] Specifically, when the access operation is a write request, the cache may correspond to various state types.
[0083] In this context, a write hit means the address to be written to is in the cache; a write miss means the address to be written to is not in the cache. In order to load the address to be written from the lower-level storage, space needs to be made in the cache for the required address. In this case, a cache line needs to be discarded. If the discarded cache line is clean and has not been modified, it does not need to be written back to the lower-level storage, i.e., no write-back is required. If the discarded cache line is dirty, has been modified, or is inconsistent with the data in the lower-level storage, it needs to be written back to the lower-level storage to ensure data consistency, i.e., a write-back is required.
[0084] Full write means that the amount of data in a single write request is equal to the size of a complete cache line, that is, a single write can directly overwrite an old cache line; partial write means that the amount of data in a single write request is less than the size of a complete cache line, that is, a single write only modifies a portion of the bytes in a cache line.
[0085] Based on whether the write request operation is hit, whether it is fully written, and whether it is written back, the state types of the write request operation can be divided into: write hit and fully written state, write hit and partially written state, write miss and fully written state with no write back state, write miss and partially written state with no write back state, write miss and fully written state with write back state, and write miss and partially written state with write back state.
[0086] In this context, a write hit and full write state means that the address to be written to is in the cache, and the write operation will overwrite all bytes of the cache line; a write hit and partial write state means that the address to be written to is in the cache, and the write operation will only modify a portion of the cache line.
[0087] A write-miss and full-write-without-write-back state means that the address to be written to is not in the cache. This write operation will overwrite all bytes of the cache line, and the discarded cache line is clean and does not require a write-back. A write-miss and partial-write-without-write-back state means that the address to be written to is not in the cache. This write operation only modifies a portion of the cache line, and the discarded cache line is clean and does not require a write-back.
[0088] A write-miss and full-write-back state means that the address to be written to is not in the cache. This write operation will overwrite all bytes of the cache line, and the discarded cache line is dirty and needs to be written back. A write-miss and partial-write-back state means that the address to be written to is not in the cache. This write operation only modifies a portion of the cache line, and the discarded cache line is dirty and needs to be written back.
[0089] Based on any of the above embodiments, when the access operation is a write request operation, step 120, measuring the performance data of the cache data channel, includes:
[0090] When the state type is write hit and full write state, measure at least one of the write bandwidth and write hit rate of the cache;
[0091] When the state type is write hit and partial write state, measure at least one of the cache's write bandwidth, write hit rate and read missing data bandwidth;
[0092] When the state type is write miss and full write with no write-back, measure at least one of the write bandwidth and write hit rate of the cache.
[0093] When the state type is write miss and partial write with no write-back state, measure at least one of the cache's write bandwidth, write hit rate, and read miss data bandwidth;
[0094] When the state type is write miss and full write-back state, measure at least one of the following: write bandwidth, write hit rate, and write-back data bandwidth of the cache.
[0095] When the state type is write miss and partially write-back state, measure at least one of the cache's write bandwidth, write hit rate, read miss data bandwidth, and write-back data bandwidth.
[0096] Specifically, for the write-hit and full-write state, the address requested by the write request is directly found in the cache, and the write operation can directly overwrite all bytes in the cache line. Therefore, at least one of the write bandwidth and write hit rate of the cache's write data channel can be directly measured as actual performance data in the write-hit and full-write state. Correspondingly, in the test cases for the write-hit and full-write state, there is at least one of the threshold values for the write bandwidth and write hit rate of the write data channel. For example, the threshold value for write bandwidth can be denoted as avg_WDBW (writedata Bandwidth), and the threshold value for write hit rate can be denoted as hit ratio. In the write-hit state, the hit ratio can be set to 100%.
[0097] For the write-hit and partially-written state, the address requested by the write request is directly found in the cache, and the write operation only modifies a portion of the cache line. In this case, to ensure data consistency, the cache needs to load the complete cache line data at that address from the lower-level cache, and then perform a partial write on the loaded complete cache line data. Therefore, in addition to measuring at least one of the write bandwidth and write hit rate of the cache's write data channel, the read-missing data bandwidth can also be measured. Here, the read-missing data bandwidth is the bandwidth for reading the cache line to be partially written from the lower-level cache. Accordingly, in the write-hit and partially-written state test cases, there is at least one of the following thresholds: write bandwidth threshold, write hit rate threshold, and read-missing data bandwidth threshold.
[0098] For the write-miss and full-write-without-write-back state, the address requested by the write request is not in the cache. When the cache makes room for the address to be written, the old cache line being replaced is clean and unmodified, so there is no need to write it back to the lower-level storage. Therefore, at least one of the write bandwidth and write hit rate of the cache's write data channel can be directly measured as actual performance data under the write-miss and full-write-without-write-back state. Accordingly, in the test cases of the write-miss and full-write-without-write-back state, there is at least one of the threshold values for the write bandwidth and write hit rate of the write data channel. In the write-miss state, the hit ratio can be set to 0.
[0099] In the case of a write-missing and partially write-without-write-back state, the address requested by the write request is not in the cache. When the cache makes room for the address to be written, the old cache line being replaced is clean and unmodified, so there is no need to write the replaced old cache line back to the lower-level storage. In this case, to ensure data consistency, the cache needs to load the complete cache line data for that address from the lower-level cache, and then partially write the loaded complete cache line data. Therefore, in addition to measuring at least one of the write bandwidth and write hit rate of the cache's write data channel, the read-missing data bandwidth can also be measured. Accordingly, in the test case of write-missing and partially write-without-write-back state, there is at least one of the following thresholds: write bandwidth threshold, write hit rate threshold, and read-missing data bandwidth threshold.
[0100] For the write-miss and write-back state, where the address requested by the write request is not in the cache, if the old cache line being replaced is dirty or modified while the cache is freeing up space for the address to be written, then the discarded cache line needs to be written back to the lower-level storage. Therefore, in addition to measuring at least one of the write bandwidth and write hit rate of the cache's write data channel, the cache's write-back data bandwidth can also be measured. Accordingly, in the write-miss and write-back state test cases, there is at least one of the following thresholds: write bandwidth threshold, write hit rate threshold, and write-back data bandwidth threshold.
[0101] For the write-miss and partially write-back state, where the address requested by the write request is not in the cache, if the old cache line being replaced is dirty or modified while the cache is freeing up space for the address to be written, the discarded cache line needs to be written back to the lower-level storage. Furthermore, to ensure data consistency, the cache needs to load the complete cache line data for that address from the lower-level cache, and then partially write to the loaded complete cache line data. Therefore, in addition to measuring at least one of the write bandwidth and write hit rate of the cache's write data channel, at least one of the write-back data bandwidth and read-miss data bandwidth can also be measured. Accordingly, in the test case of write-miss and partially write-back state, there is at least one of the following thresholds: write bandwidth threshold, write hit rate threshold, read-miss data bandwidth threshold, and write-back data bandwidth threshold.
[0102] It should be noted that the write bandwidth, read missing data bandwidth, and write-back data bandwidth mentioned above are all average bandwidth values during the operation of the cache under test cases. Specifically, write bandwidth refers to the bandwidth of the cache input port, while read missing data bandwidth and write-back data bandwidth refer to the bandwidth of the cache output port.
[0103] Figure 3 This is a flowchart illustrating the performance verification method for write request operations provided by the present invention, as shown below. Figure 3 As shown, when performing performance verification on the cache in response to write request operations, initialization is performed first. Specifically, the entire cache's RAM can be initialized.
[0104] Subsequently, thresholds can be set in test cases for each state type of write request operation. Write request operation can include sending write requests to multiple random addresses. Here, each state type can be categorized based on whether it's a hit, replacement, or full write. For a hit, it can be divided into full write and partial write. For a write hit and full write state, thresholds for write bandwidth and write hit rate of the write data channel can be set in the test cases. For a write hit and partial write state, thresholds for write bandwidth, write hit rate, and read missing data bandwidth of the write data channel can be set in the test cases. For a miss and no replacement state, it can also be divided into full write and partial write. For a write missing and full write with no write-back state, thresholds for write bandwidth and write hit rate of the write data channel can be set in the test cases. For the state type of write missing and partial write with no write-back, the thresholds for write bandwidth, write hit rate, and read missing data bandwidth of the write data channel can be set in the test case. For the case of no hit and need to be replaced, it can also be divided into full write and partial write. For the state type of write missing and full write with write-back, the thresholds for write bandwidth, write hit rate, and write-back data bandwidth can be set in the test case. For the state type of write missing and partial write with write-back, the thresholds for write bandwidth, write hit rate, read missing data bandwidth, and write-back data bandwidth can be set in the test case.
[0105] After the test cases are set up, performance verification of the cache can be triggered based on the test cases. While the cache is running under the test cases, performance data is collected and measured to obtain actual performance data.
[0106] Subsequently, the measured performance data is compared with the threshold of the performance data in the test cases to obtain the performance verification results of the cache for write request operations.
[0107] Based on any of the above embodiments, the performance data includes at least one of bandwidth and hit rate.
[0108] Specifically, for each access operation's state type, the threshold for performance data in the test cases, as well as the measured performance data, can include at least one of bandwidth and hit rate. That is, both bandwidth and hit rate can be used to evaluate cache performance independently, and bandwidth and hit rate can also be combined to evaluate cache performance.
[0109] During cache operation, cache bandwidth can be monitored using the Perf Event Agent. Additionally, cache hit rate can be monitored using the Hit Ratio Agent. Based on these two agents, real-time measurement of cache performance data can be achieved. Alternatively, cache bandwidth and hit rate can be queried via sim log queries or FSDB-related signals.
[0110] For example, Figure 4 This is the second flowchart of the cache performance verification method provided by the present invention, as shown below. Figure 4 As shown, stimuli can be sent to the Device Under Test (DUT). Here, the stimuli can be read requests or write requests, and the DUT is the cache. Under the stimulus of read or write requests, the cache runs, and at the same time, the performance event broker collects relevant signals on the cache's input and output ports in real time, specifically signals from the write data channel and read response channel, thereby calculating bandwidth; the hit rate broker collects cache signals in real time and calculates the hit rate.
[0111] This yields the measured performance data of the cache, including measured bandwidth and hit rate. Based on this, the MON (Monitor) component can be used to compare the measured performance data with the thresholds in the corresponding test cases, thereby outputting the performance verification results. Here, if the measured performance data is greater than or equal to the threshold, the verification passes and the cache performance meets the standard; otherwise, the verification fails. The resulting performance verification results can be output to the sim log.
[0112] The cache performance verification device provided by the present invention is described below. The cache performance verification device described below and the cache performance verification method described above can be referred to in correspondence.
[0113] Figure 5 This is a schematic diagram of the high-speed cache performance verification device provided by the present invention, as shown below. Figure 5 As shown, the device includes:
[0114] The test case determination unit 510 is used to determine test cases for the cache. The test cases include a threshold corresponding to the performance data of the data channel of the cache. The data channel corresponds to the access operation of the test case. The type of the performance data corresponds to the state type of the access operation of the test case.
[0115] The test unit 520 is used to control the cache to run under the test case and simultaneously measure the performance data of the cache's data channel to obtain the test performance data.
[0116] Verification unit 530 is used to perform performance verification on the cache based on the measured performance data and the threshold.
[0117] In the apparatus provided in this embodiment of the invention, the cache is controlled to run under test cases corresponding to the access operation and the state type of the access operation, and the performance of the cache is verified based on the threshold in the test cases and the measured performance data corresponding to the access operation and the state type of the access operation. This realizes automated performance verification of the cache, which can be completed without human intervention, effectively improving the efficiency of performance verification, ensuring the accuracy and reliability of performance verification, and reducing the maintenance cost of performance verification.
[0118] Based on any of the above embodiments, the access operation of the test case includes at least one of a read request operation and a write request operation;
[0119] The data channel corresponding to the read request operation is the read response channel, and the data channel corresponding to the write request operation is the write data channel.
[0120] Based on any of the above embodiments, when the access operation is a read request operation, the state type of the access operation includes at least one of the following: read hit state, read miss and no write-back state, and read miss and write-back state.
[0121] Based on any of the above embodiments, the measurement unit is specifically used for:
[0122] When the state type is read hit state, measure at least one of the read bandwidth and read hit rate of the cache;
[0123] When the state type is read missing and no write-back state, measure at least one of the cache's read bandwidth, read hit rate, and read missing data bandwidth;
[0124] When the state type is read-miss and write-back, measure at least one of the cache's read bandwidth, read hit rate, read-miss data bandwidth, and write-back data bandwidth.
[0125] Based on any of the above embodiments, when the access operation is a write request operation, the state type of the access operation includes at least one of the following: write hit and full write state, write hit and partial write state, write miss and full write with no write-back state, write miss and partial write with no write-back state, write miss and full write write-back state, and write miss and partial write write-back state.
[0126] Based on any of the above embodiments, the measurement unit is specifically used for:
[0127] When the state type is write hit and full write state, measure at least one of the write bandwidth and write hit rate of the cache;
[0128] When the state type is write hit and partial write state, measure at least one of the cache's write bandwidth, write hit rate and read missing data bandwidth;
[0129] When the state type is write miss and full write with no write-back, measure at least one of the write bandwidth and write hit rate of the cache.
[0130] When the state type is write miss and partial write with no write-back state, measure at least one of the cache's write bandwidth, write hit rate, and read miss data bandwidth;
[0131] When the state type is write miss and full write-back state, measure at least one of the following: write bandwidth, write hit rate, and write-back data bandwidth of the cache.
[0132] When the state type is write miss and partially write-back state, measure at least one of the cache's write bandwidth, write hit rate, read miss data bandwidth, and write-back data bandwidth.
[0133] Based on any of the above embodiments, the performance data includes at least one of bandwidth and hit rate.
[0134] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute a cache performance verification method, which includes:
[0135] Determine test cases for the cache, wherein the test cases include thresholds corresponding to performance data of the data channel of the cache, the data channel corresponds to the access operation of the test case, and the type of the performance data corresponds to the state type of the access operation of the test case;
[0136] The cache is controlled to run under the test case, and the performance data of the cache's data channel is measured to obtain the measured performance data.
[0137] The performance of the cache is verified based on the measured performance data and the threshold.
[0138] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0139] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is able to execute the cache performance verification method provided by the above methods, the method comprising:
[0140] Determine test cases for the cache, wherein the test cases include thresholds corresponding to performance data of the data channel of the cache, the data channel corresponds to the access operation of the test case, and the type of the performance data corresponds to the state type of the access operation of the test case;
[0141] The cache is controlled to run under the test case, and the performance data of the cache's data channel is measured to obtain the measured performance data.
[0142] The performance of the cache is verified based on the measured performance data and the threshold.
[0143] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the cache performance verification method provided by the methods described above, the method comprising:
[0144] Determine test cases for the cache, wherein the test cases include thresholds corresponding to performance data of the data channel of the cache, the data channel corresponds to the access operation of the test case, and the type of the performance data corresponds to the state type of the access operation of the test case;
[0145] The cache is controlled to run under the test case, and the performance data of the cache's data channel is measured to obtain the measured performance data.
[0146] The performance of the cache is verified based on the measured performance data and the threshold.
[0147] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0148] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for verifying cache performance, characterized in that, include: Determine test cases for the cache, wherein the test cases include thresholds corresponding to performance data of the data channel of the cache, the data channel corresponds to the access operation of the test case, and the type of the performance data corresponds to the state type of the access operation of the test case; The cache is controlled to run under the test case, and the performance data of the cache's data channel is measured to obtain the measured performance data. The performance of the cache is verified based on the measured performance data and the threshold. The access operation of the test case includes a read request operation, and the data channel corresponding to the read request operation is a read response channel. When the access operation is a read request operation, the status type of the access operation includes at least one of the following: read hit status, read miss and no write-back status, and read miss and write-back status.
2. The cache performance verification method according to claim 1, characterized in that, The access operations of the test cases also include write request operations; The data channel corresponding to the write request operation is the write data channel.
3. The cache performance verification method according to claim 1, characterized in that, The performance data of the data channel of the cache is measured, including: When the state type is read hit state, measure at least one of the read bandwidth and read hit rate of the cache; When the state type is read missing and no write-back state, measure at least one of the cache's read bandwidth, read hit rate, and read missing data bandwidth; When the state type is read-miss and write-back, measure at least one of the cache's read bandwidth, read hit rate, read-miss data bandwidth, and write-back data bandwidth.
4. The cache performance verification method according to claim 2, characterized in that, When the access operation is a write request operation, the state type of the access operation includes at least one of the following: write hit and full write state, write hit and partial write state, write miss and full write with no write-back state, write miss and partial write with no write-back state, write miss and full write with write-back state, and write miss and partial write with write-back state.
5. The cache performance verification method according to claim 4, characterized in that, The performance data of the data channel of the cache is measured, including: When the state type is write hit and full write state, measure at least one of the write bandwidth and write hit rate of the cache; When the state type is write hit and partial write state, measure at least one of the cache's write bandwidth, write hit rate and read missing data bandwidth; When the state type is write miss and full write with no write-back, measure at least one of the cache's write bandwidth and write hit rate; When the state type is write miss and partial write with no write-back state, measure at least one of the cache's write bandwidth, write hit rate, and read miss data bandwidth; When the state type is write miss and full write-back state, measure at least one of the cache's write bandwidth, write hit rate, and write-back data bandwidth. When the state type is write miss and partially write-back state, measure at least one of the cache's write bandwidth, write hit rate, read miss data bandwidth, and write-back data bandwidth.
6. The cache performance verification method according to any one of claims 1 to 5, characterized in that, The performance data includes at least one of bandwidth and hit rate.
7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the cache performance verification method as described in any one of claims 1 to 6.
8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the cache performance verification method as described in any one of claims 1 to 6.
9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the cache performance verification method as described in any one of claims 1 to 6.