Memory expansion card

Abstract

The application provides a memory expansion card, which can be applied to the technical field of memory expansion. The memory expansion card comprises a bandwidth mode controller, a routing control module and a plurality of interconnection controllers. The bandwidth mode controller is used for determining a memory bandwidth configuration mode of a host according to a received host control signal, attribute information of a plurality of memory modules and attribute information of a plurality of storage controllers, and generating a memory switching instruction according to the memory bandwidth configuration mode and the attribute information of the plurality of interconnection controllers. The routing control module comprises a link switching submodule and the plurality of interconnection controllers. The link switching submodule is used for connecting the memory link among the host, the interconnection controllers and the storage controllers according to the memory switching instruction, so that the interconnection controllers generate interconnection control signals according to the host data signal and the memory switching instruction. The plurality of storage controllers are used for determining target memory modules according to the interconnection control signals, so that the target memory modules receive and store host data in the host data signal.

Description

Technical Field

[0001] This application relates to the field of memory expansion technology, and more specifically to a memory expansion card. Background Technology

[0002] As the number of processors and workloads within server hosts increase, traditional memory architectures struggle to meet the demands for high capacity and high bandwidth. This necessitates the use of high-speed interconnect buses to connect memory expansion cards to expand the host's memory. However, existing memory expansion cards only support single-host memory expansion, failing to meet the current need for memory expansion across multiple hosts, and also making it difficult to allocate appropriate bandwidth based on the host's bandwidth requirements. Summary of the Invention

[0003] In view of the above problems, this application provides a memory expansion card.

[0004] According to a first aspect of this application, a memory expansion card is provided, comprising: a bandwidth mode controller, configured to determine a memory bandwidth configuration mode of at least one host based on received at least one host control signal, attribute information of multiple memory modules, and attribute information of multiple storage controllers, and to generate a memory switching instruction based on the memory bandwidth configuration mode and attribute information of multiple interconnect controllers; a routing control module, electrically connected to the bandwidth mode controller, including a link switching submodule and multiple interconnect controllers, the link switching submodule being configured to connect memory links between at least one host, at least one interconnect controller, and at least one storage controller according to the memory switching instruction, so that at least one interconnect controller generates an interconnect control signal based on at least one host data signal and the memory switching instruction; and multiple storage controllers, electrically connected to the routing control module, configured to determine a target memory module based on at least one interconnect control signal, so that the target memory module receives and stores host data from the host data signal.

[0005] A second aspect of this application provides a storage method, comprising: synchronizing a clock with at least one host after the memory initialization of a memory expansion card is completed and it is electrically connected to at least one host; a bandwidth mode controller determining a memory bandwidth configuration mode of at least one host based on host control signals from at least one host, attribute information of multiple memory modules, and attribute information of multiple storage controllers, and generating a memory switching instruction based on the memory bandwidth configuration mode and attribute information of multiple interconnect controllers; a routing control module connecting memory links between at least one host, at least one interconnect controller, and at least one storage controller based on the memory switching instruction, and generating an interconnect control signal based on at least one host data signal and the memory switching instruction; and at least one storage controller determining a target memory module based on the interconnect control signal, so that the target memory module receives and stores host data from the host data signal.

[0006] A third aspect of this application provides a storage system comprising: a plurality of hosts for sending at least one host control signal and at least one host data signal to a memory expansion card; a memory expansion card as described above; and a plurality of memory modules for receiving and storing host data from the memory expansion card.

[0007] According to embodiments of this application, when at least one host needs to store data, a host control signal can be sent to the bandwidth mode controller. The bandwidth mode controller, by comprehensively assessing the host's bandwidth and memory requirements from multiple dimensions based on relevant control parameters and other information, determines the memory modules, storage controllers, and memory bandwidth configuration modes that the host needs to occupy. This allows for adaptation to the bandwidth regulation and storage needs of single and multiple hosts in various application scenarios, providing hosts with high-efficiency data storage and memory sharing applications.

[0008] According to embodiments of this application, after receiving a memory switching instruction generated by the bandwidth mode controller based on the memory bandwidth configuration mode, the link switching submodule establishes the memory link between the host, the interconnect controller, and the storage controller, and transmits host data to the corresponding target memory module. This allows a single host to connect to multiple interconnect controllers and multiple storage controllers simultaneously. Combined with the interconnect controller's control over the conversion of host data signals and memory switching instructions, this enables memory expansion for single or multiple hosts while providing high-bandwidth data caching or data storage for multiple memory modules. Attached Figure Description

[0009] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of a memory expansion card according to an embodiment of this application is shown;

[0011] Figure 2 A schematic diagram of a memory expansion card according to another embodiment of this application is shown;

[0012] Figure 3 A schematic diagram of a memory expansion card connected to a single host according to an embodiment of this application is shown;

[0013] Figure 4 A schematic diagram of a memory expansion card connected to a single host according to another embodiment of this application is shown;

[0014] Figure 5 A schematic diagram of a memory expansion card connected to multiple hosts according to an embodiment of this application is shown;

[0015] Figure 6 A schematic diagram of a memory expansion card connected to multiple hosts according to another embodiment of this application is shown;

[0016] Figure 7 A schematic diagram of a memory expansion card connected to multiple hosts according to yet another embodiment of this application is shown;

[0017] Figure 8 A schematic diagram of the interface of a memory expansion card according to an embodiment of this application is shown;

[0018] Figure 9 A flowchart of a storage method according to an embodiment of this application is shown. Detailed Implementation

[0019] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0022] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0023] As the number of processors and workloads within server hosts increase, traditional memory architectures struggle to meet the demands for high capacity and high bandwidth. This necessitates the use of high-speed interconnect buses to connect memory expansion cards to expand the host's memory. However, existing memory expansion cards only support single-host memory expansion, failing to meet the current need for memory expansion across multiple hosts, and also making it difficult to allocate appropriate bandwidth based on the host's bandwidth requirements.

[0024] An embodiment of this application provides a memory expansion card, comprising: a bandwidth mode controller, configured to determine a memory bandwidth configuration mode for at least one host based on received at least one host control signal, attribute information of multiple memory modules, and attribute information of multiple storage controllers, and to generate a memory switching instruction based on the memory bandwidth configuration mode and attribute information of multiple interconnect controllers; a routing control module, electrically connected to the bandwidth mode controller, comprising a link switching submodule and multiple interconnect controllers, the link switching submodule being configured to connect memory links between at least one host, at least one interconnect controller, and at least one storage controller according to the memory switching instruction, so that at least one interconnect controller generates an interconnect control signal based on at least one host data signal and the memory switching instruction; and multiple storage controllers, electrically connected to the routing control module, configured to determine a target memory module based on at least one interconnect control signal, so that the target memory module receives and stores host data from the host data signal.

[0025] Figure 1 A schematic diagram of a memory expansion card according to an embodiment of this application is shown.

[0026] like Figure 1 As shown, the memory expansion card 101 can be electrically connected to at least one host 102 (host 1, host 2, host 3) and multiple memory modules 103 (memory module 1, memory module 2, memory module 3, memory module 4, memory module 5, memory module 6), thereby providing memory expansion for at least one host 102 to meet the host 102's requirements for high memory and high bandwidth. The memory expansion card 101 may include a bandwidth mode controller 104, a routing control module 106, and multiple storage controllers 109 (storage controller 1, storage controller 2, storage controller 3). The bandwidth mode controller 104 and the routing control module 106 can be electrically connected to at least one host 102, and each storage controller 109 can be electrically connected to multiple memory modules 103.

[0027] Specifically, the bandwidth mode controller 104 can be used to determine the memory bandwidth configuration mode of at least one host 102 based on the received host control signal, attribute information of multiple memory modules 103, and attribute information of multiple storage controllers 109, and generate memory switching instructions based on the memory bandwidth configuration mode and attribute information of multiple interconnect controllers 108 (interconnect controller 1, interconnect controller 2, interconnect controller 3, and interconnect controller 4). The interconnect controllers can be controllers such as CXL (Compute Express Link) controllers.

[0028] The bandwidth mode controller 104 can be electrically connected to at least one baseboard management controller 105 of the host 102, thereby receiving host control signals sent by the baseboard management controller 105 of the host 102. Attribute information of multiple memory modules 103, attribute information of multiple storage controllers 109, and other basic firmware configuration parameters of the memory expansion card 101 can all be stored in the flash memory module. The bandwidth mode controller 104 can retrieve the required parameter information from the flash memory module after the memory expansion card 101 is powered on.

[0029] The attribute information of memory module 103 may include available capacity information and identification information of memory module 103, but is not limited to these. The attribute information of storage controller 109 may include available bandwidth information and identification information of storage controller 109, but is not limited to these.

[0030] The memory bandwidth configuration mode can include information such as the minimum memory module 103 and minimum storage controller 109 required for the cached host data, whether high-bandwidth transmission is needed, and whether shared memory module 103 is required. For example, host A's memory bandwidth configuration mode can be a low-bandwidth, high-storage configuration mode, requiring one storage controller and three memory modules. Host B's memory bandwidth configuration mode can be a high-bandwidth, shared-storage configuration mode, requiring three storage controllers and three memory modules, one of which is shared by multiple hosts. The memory switching instructions generated based on the memory bandwidth configuration mode can control the link connection at each stage within the routing control module, enabling hosts to transmit data to the memory module under high-bandwidth conditions through the corresponding connected memory links.

[0031] Before the host 102 needs to store host data, it needs to send a host control signal to the bandwidth mode controller 104. Then, based on the host control signal, the attribute information of the multiple memory modules 103 currently connected to the memory expansion card 101, and the attribute information of the multiple storage controllers 109, the memory bandwidth configuration mode matching the host 102 that needs to store host data is determined. This allows the link connectivity within the routing control module 106 to be controlled according to the memory bandwidth configuration mode, thereby supporting various application environments such as single host, multiple hosts, high bandwidth, and shared memory modules.

[0032] The routing control module 106 can be electrically connected to the bandwidth mode controller 104 and includes a link switching submodule 107 and multiple interconnect controllers 108. The link switching submodule 107 is used to connect the memory links between at least one host 102, at least one interconnect controller 108 and at least one storage controller 109 according to the memory switching instruction, so that at least one interconnect controller 108 generates an interconnect control signal according to at least one host data signal and the memory switching instruction.

[0033] After receiving the memory switching instruction sent by the bandwidth mode controller 104, the link switching submodule 107 can control the memory link between the host 102 and the interconnect controller 108 and the memory link between the interconnect controller 108 and the storage controller 109 to be connected, thereby enabling the memory link between the host 102 and the storage controller 109 and the memory module 103 to be connected.

[0034] After the memory link is established, the host 102 will transmit the host data signal to the interconnect controller 108 through the established link. The interconnect controller 108 will perform protocol conversion and other processing based on the received host data signal and memory switching instructions, thereby obtaining data information that can be recognized by the storage controller 109 and the memory module 103.

[0035] Multiple storage controllers 109 can be electrically connected to the routing control module 106 to determine a target memory module based on at least one interconnect control signal, so that the target memory module 103 receives and stores host data from the host data signal. The storage controllers can be controllers such as DDR (Double Data Rate) controllers.

[0036] Each storage controller 109 can be electrically connected to multiple memory modules. The storage controller 109 can determine the target memory module 103 from the multiple memory modules 103 electrically connected to the storage controller 109 according to the received interconnection control signal, and then store the host data.

[0037] Each host 102 can be electrically connected to multiple interconnect controllers 108 and multiple storage controllers 109 to form multiple memory links for simultaneous data transfer caching.

[0038] According to embodiments of this application, when at least one host needs to store data, a host control signal can be sent to the bandwidth mode controller. The bandwidth mode controller, by comprehensively assessing the host's bandwidth and memory requirements from multiple dimensions based on relevant control parameters and other information, determines the memory modules, storage controllers, and memory bandwidth configuration modes that the host needs to occupy. This allows for adaptation to the bandwidth regulation and storage needs of single and multiple hosts in various application scenarios, providing hosts with high-efficiency data storage and memory sharing applications.

[0039] According to embodiments of this application, after receiving a memory switching instruction generated by the bandwidth mode controller based on the memory bandwidth configuration mode, the link switching submodule establishes the memory link between the host, the interconnect controller, and the storage controller, and transmits host data to the corresponding target memory module. This allows a single host to connect to multiple interconnect controllers and multiple storage controllers simultaneously. Combined with the interconnect controller's control over the conversion of host data signals and memory switching instructions, this enables memory expansion for single or multiple hosts while providing high-bandwidth data caching or data storage for multiple memory modules.

[0040] Figure 2 A schematic diagram of a memory expansion card according to another embodiment of this application is shown.

[0041] like Figure 2 As shown, in Figure 1 On this basis, Figure 2 The diagram shows that host 102 can be electrically connected to memory expansion card 101 via host interface 203 located on the memory expansion card, thereby transmitting host data signals. The link switching submodule may include interconnect router 201 and storage route converter 202.

[0042] Specifically, the memory expansion card 101 may include multiple host interfaces 203. These host interfaces 203 can be electrically connected to the routing control module 106 for electrical connection to the interface of at least one host 102. Where the bandwidth (number of channels) of any host interface 203 is less than the interface bandwidth (number of channels) of the host 102 to be connected, the host 102 can be electrically connected to the multiple host interfaces 203 via cables to ensure that the interface bandwidth (number of channels) of the host 102 to be connected is the same as the total bandwidth (number of channels) of the connected host interfaces 203.

[0043] For example, if the host computer has an X8 interface and the memory expansion card has two X4 host interfaces, a single cable can be used to electrically connect the host's X8 interface to both X4 host interfaces simultaneously. Conversely, if the host computer has two X4 interfaces and the memory expansion card has two X4 host interfaces, two separate cables can be used to electrically connect the host's two X4 interfaces to the two X4 host interfaces respectively.

[0044] If the bandwidth (number of channels) of host interfaces 203 on memory expansion card 101 is greater than the interface bandwidth (number of channels) of host 102, select the host interfaces 203 (multiple) with the interface bandwidth (number of channels) closest to host 102.

[0045] According to embodiments of this application, depending on the host's interface bandwidth (number of channels), the host can be electrically connected to the memory expansion card by simultaneously connecting the bandwidth (number of channels) of multiple host interfaces or by connecting only the bandwidth (number of channels) of one host interface, thereby maximizing transmission efficiency.

[0046] The interconnect router can be electrically connected to at least one host interface 203 and a bandwidth mode controller to establish a memory link between at least one host 102 and at least one interconnect controller according to memory switching instructions. At least one host 102 is electrically connected to the interconnect router 201 via at least one host interface 203.

[0047] Storage routing converter 202 can be electrically connected to interconnect routing selector 201 and multiple storage controllers 109 to connect memory links between at least one interconnect controller 108 and at least one storage controller 109 according to memory switching instructions.

[0048] According to the embodiments of this application, the memory links between the host and the interconnect controller and between the interconnect controller and the storage controller are segmented and controlled by a two-level memory link switching controller, which improves the accuracy and reliability of link conduction. Even if a link segment fails, it can be controlled through another memory link.

[0049] According to embodiments of this application, the bandwidth mode controller can also be used to: determine the ideal bandwidth, ideal memory, and adjustment parameters of at least one host from at least one host control signal.

[0050] According to an embodiment of this application, at least one intermediate memory module corresponding to at least one host is determined based on the attribute information of at least one ideal memory and multiple memory modules.

[0051] According to embodiments of this application, at least one intermediate storage controller corresponding to at least one host is determined based on attribute information of at least one ideal bandwidth, at least one intermediate memory module, and multiple storage controllers.

[0052] According to embodiments of this application, a memory bandwidth configuration mode for at least one host is determined based on proportion information obtained after adjusting at least one intermediate memory module, at least one intermediate storage controller, and at least one ideal memory and at least one ideal bandwidth using adjustment parameters. The proportion information represents the ratio between the actual memory usage of the host and the total memory usage of the memory modules and the total bandwidth usage of the storage controller. That is, the proportion information may include the ratio between the actual memory usage of the host and the total memory usage of the memory modules, as well as the ratio between the actual bandwidth usage and the total bandwidth usage of the storage controller.

[0053] The ideal bandwidth and ideal memory corresponding to the host data that the host currently needs to store can be obtained from the host control signals. Ideal memory can be characterized as the storage space expected to be occupied by the host data to be stored, and ideal bandwidth can be characterized as the bandwidth expected to be used by the host during communication and transmission of the host data to be stored with at least one memory module.

[0054] The bandwidth mode controller can extract relevant information corresponding to the host data to be stored from the host control signals. Then, based on the host's ideal memory requirements, the current available memory capacity of each memory module, whether the memory module has storage permissions for the host, and whether there are conflicts between the data already stored in the memory module and the data to be stored, it determines multiple memory modules that the host can use, i.e., intermediate memory modules. Simultaneously, it can also determine multiple storage controllers that the host can use, i.e., intermediate storage controllers, based on the host's ideal bandwidth requirements and the current available bandwidth capacity of each storage controller. The bandwidth of the host during data caching corresponds to the bandwidth provided by the storage controllers, thus providing high-bandwidth configuration for the host when communicating with it through multiple storage controllers.

[0055] Then, based on the initially selected intermediate memory modules and intermediate storage controllers, the ideal bandwidth and ideal memory of the host are adjusted using adjustment parameters. This allows us to determine how much memory each intermediate memory module can provide for the host data and how much bandwidth each intermediate storage controller can provide for the host when allocating memory and bandwidth.

[0056] According to embodiments of this application, the bandwidth mode controller uses ideal memory and ideal bandwidth corresponding to the host data to be stored, sent from the baseboard management controller, to initially select at least one usable intermediate memory module and at least one intermediate storage controller from multiple memory modules and multiple storage controllers. By using the proportion information obtained after adjusting the ideal memory and ideal bandwidth with adjustment parameters, at least one target memory module, at least one storage controller, and their respective usable usage can be determined, resulting in a memory bandwidth configuration mode that is highly adapted to the host requirements and is controllable and adjustable.

[0057] According to embodiments of this application, the proportion information may include bandwidth proportion and memory proportion. Regarding determining the memory bandwidth configuration mode, the bandwidth mode controller is further configured to: determine at least one intermediate storage controller from at least one storage controller electrically connected to at least one intermediate memory module, based on at least one ideal bandwidth and attribute information of multiple storage controllers.

[0058] According to an embodiment of this application, based on the occupancy priority of at least one host and the identification order of at least one intermediate memory module, in the case where there is at least one shared intermediate memory module among multiple hosts, a first target memory module is determined from the at least one shared intermediate memory module according to the memory percentage of the at least one host, and a second target memory module is determined from the intermediate memory modules other than the at least one shared intermediate memory module.

[0059] According to an embodiment of this application, based on the occupancy priority of at least one host and the identification order of at least one intermediate storage controller, in the case where there is at least one shared intermediate storage controller among multiple hosts, a first target storage controller is determined from the at least one shared intermediate storage controller according to the bandwidth ratio of the at least one host, and a second target storage controller is determined from the intermediate storage controllers other than the at least one shared intermediate storage controller.

[0060] According to embodiments of this application, a memory configuration sub-mode for at least one host is determined based on the number of the first target memory module and the second target memory module; and a bandwidth configuration sub-mode for at least one host is determined based on the ideal bandwidth and the number of the first target storage controller and the second target storage controller.

[0061] According to an embodiment of this application, a memory bandwidth configuration mode is determined based on a memory configuration sub-mode, a bandwidth configuration sub-mode, and the occupancy priority of at least one host.

[0062] The memory modules that are electrically connected to the storage controller are usually pre-connected. Therefore, after identifying multiple intermediate memory modules, it is necessary to refer to the connection relationship between the intermediate memory modules and the storage controller in order to identify at least one intermediate storage controller.

[0063] Before adjusting the ideal memory and ideal bandwidth using the adjustment parameters, the ideal memory and ideal bandwidth of at least one host can be normalized first. Then, the memory parameter in the adjustment parameters can be used to adjust the normalized ideal memory to obtain the memory ratio. The bandwidth parameter in the adjustment parameters can be used to adjust the normalized ideal bandwidth to obtain the bandwidth ratio.

[0064] Each host can carry the priority of cached data usage, so that the target memory module and target storage controller can be allocated to the host with higher priority according to the order of usage priority.

[0065] When multiple hosts need to cache data, it's necessary to confirm whether a shared intermediate memory module exists among these hosts. Based on the identification order of each intermediate memory module, if a shared intermediate memory module is required, the available memory capacity is determined from the shared intermediate memory module using memory share, and the shared intermediate memory module with the determined available memory capacity is designated as the first target memory module. Conversely, if only one host needs to use an intermediate memory module, the available memory capacity can be determined based on the currently unallocated available memory capacity and the available capacity of the intermediate memory module, and the intermediate memory module with the determined available memory capacity is designated as the second target memory module.

[0066] Furthermore, an automatic negotiation allocation mechanism can be introduced during memory and bandwidth allocation. If the initial memory or bandwidth allocation is insufficient, after allocating to multiple hosts, it can be checked within the intermediate memory module (including shared intermediate memory modules) to determine if there is any remaining available memory or bandwidth. If so, secondary or multiple allocations can be made to the host with insufficient initial memory or bandwidth allocation, thereby improving the accuracy and flexibility of memory and bandwidth allocation patterns. Secondary or multiple allocations include, but are not limited to, directly allocating all remaining available memory or bandwidth from an intermediate memory module or intermediate storage controller (shared intermediate memory module and shared intermediate storage controller) to the host with insufficient memory or bandwidth. Allocation can also be made to the host with insufficient memory or bandwidth based on the memory and bandwidth percentages, according to a proportional relationship.

[0067] If there is no remaining available memory or bandwidth, or if all remaining available memory or bandwidth has been allocated, and a host still has insufficient memory or bandwidth, data transmission caching can be performed first, and the load can be reported to the host or peripheral device. This allows for additional storage or bandwidth to be provided to the host that still has insufficient memory or bandwidth without affecting the data transmission caching.

[0068] For example, host A has an ideal memory capacity of 50GB, with a memory usage rate of 0.6%. The intermediate memory modules corresponding to host A include a first intermediate memory module with a usable capacity of 20GB, a second intermediate memory module with a usable capacity of 30GB, and a third intermediate memory module with a usable capacity of 40GB. Host B has an ideal memory capacity of 40GB, with a memory usage rate of 0.4%. The intermediate memory modules corresponding to host B include a first intermediate memory module with a usable capacity of 20GB, a third intermediate memory module with a usable capacity of 40GB, and a fourth intermediate memory module with a usable capacity of 30GB. Host A has a higher memory usage priority than host B.

[0069] For host A, based on the identification order of the intermediate memory modules, the usable memory capacity is first determined to be 12G from the shared first intermediate memory module, then the usable memory capacity is determined to be 30G from the second intermediate memory module, and then the usable memory capacity is determined to be 12G from the shared third intermediate memory module. Based on the unallocated memory capacity of 8G, it is determined that the memory capacity to be used from the shared third intermediate memory module is 8G.

[0070] For host B, based on the identification order of the intermediate memory modules, the usable memory capacity is first determined to be 8G from the shared first intermediate memory module, then the usable memory capacity is determined to be 12.8G from the shared third intermediate memory module, and finally the usable memory capacity is determined to be 19.2G from the fourth intermediate memory module.

[0071] After obtaining the target memory module, at least one intermediate storage controller needs to be selected from the storage controllers based on the first and second target memory modules. Then, it needs to be confirmed whether there is a shared intermediate storage controller among multiple hosts. According to the identification order of each intermediate storage controller, if a shared intermediate storage controller needs to be used, the available bandwidth capacity is determined from the intermediate memory storage controllers using bandwidth proportions, and the shared intermediate storage controller with the determined available bandwidth capacity is designated as the first target storage controller. If only one host's intermediate storage controller is used, the available bandwidth capacity can be determined based on the currently unallocated available bandwidth capacity and the available capacity of the intermediate storage controller, and the intermediate storage controller with the determined available bandwidth capacity is designated as the second target storage controller.

[0072] For example, host A has an ideal bandwidth of 50K and a bandwidth utilization rate of 0.3. The intermediate storage controllers corresponding to host A include a first intermediate storage controller with an available capacity of 20K, a second intermediate storage controller with an available capacity of 30K, and a third intermediate storage controller with an available capacity of 40K. Host B has an ideal bandwidth of 40K and a bandwidth utilization rate of 0.7. The intermediate storage controllers corresponding to host B include a first intermediate storage controller with an available capacity of 20K, a third intermediate storage controller with an available capacity of 40K, and a fourth intermediate storage controller with an available capacity of 30K. Host A has a higher utilization priority than host B.

[0073] For host A, based on the identification order of the intermediate storage controllers, the available bandwidth capacity is first determined from the shared first intermediate storage controller as 6K, then from the second intermediate storage controller as 30K, and then from the shared third intermediate storage controller as 12K. With 4K of unallocated bandwidth remaining, the system awaits the bandwidth determination for host B. Therefore, the bandwidth capacity required from the shared third intermediate storage controller is determined to be 8K.

[0074] For host B, based on the identification order of the intermediate storage controllers, the available bandwidth capacity is first determined from the shared first intermediate storage controller as 9.8K, then from the shared third intermediate storage controller as 19.6K, and finally from the fourth intermediate storage controller as 10.6K.

[0075] Then, based on the unallocated bandwidth capacity of 4K of host A, the remaining bandwidth capacity of 4.2K of the shared first intermediate storage controller, and the remaining bandwidth capacity of 8.4K of the shared third intermediate storage controller, it is determined that the bandwidth capacity required from the shared first intermediate storage controller is 10K.

[0076] When the ideal bandwidth of the host is less than the total bandwidth capacity determined from multiple intermediate storage controllers based on bandwidth percentage, the bandwidth configuration sub-mode is determined based on the ideal bandwidth and the number of intermediate storage controllers (including shared intermediate storage controllers) that have a bandwidth capacity less than or equal to the ideal bandwidth and are closest to the ideal bandwidth (either the combined intermediate storage controllers or a single intermediate storage controller).

[0077] For example, host B's ideal bandwidth is 10K. The shared first intermediate storage controller has a usable bandwidth capacity of 9.8K, the shared third intermediate storage controller has a usable bandwidth capacity of 19.6K, and the shared fourth intermediate storage controller has a usable bandwidth capacity of 10.6K. In this case, only the usable bandwidth capacity provided by the shared first intermediate storage controller is less than and closest to the ideal bandwidth. Therefore, host B's bandwidth configuration sub-mode is determined to be a three-to-one (one interconnect controller) mode under low bandwidth conditions, and the memory links of the first intermediate storage controller are independent, while the remaining memory links are all aggregated to the memory links of the first intermediate storage controller.

[0078] For example, host B's ideal bandwidth is 20K. The shared first intermediate storage controller has a usable bandwidth capacity of 9.8K, the shared third intermediate storage controller has a usable bandwidth capacity of 19.6K, and the shared fourth intermediate storage controller has a usable bandwidth capacity of 10.6K. In this case, the sum of the usable bandwidth capacity provided by the shared first intermediate storage controller and the shared fourth intermediate storage controller is less than and closest to the ideal bandwidth. Therefore, host B's bandwidth configuration sub-mode is determined to be a three-to-two (two interconnect controllers) mode under the low bandwidth condition, where the memory links of the first target storage controller (first intermediate storage controller) and the second target storage controller (fourth intermediate storage controller) are independent of each other.

[0079] The host's priority can include the priority between bandwidth and memory for the current data. After obtaining the memory configuration sub-mode and bandwidth configuration sub-mode, the memory bandwidth configuration mode is determined by combining the priority between bandwidth and memory for the current data.

[0080] According to embodiments of this application, after determining the intermediate memory modules, the intermediate storage controller is determined based on the connection relationship between the memory modules and the storage controller, combined with the ideal bandwidth and attribute information of multiple storage controllers. This improves the accuracy and rationality of determining the intermediate storage controller. Then, based on the occupancy priority of at least one host and the identification order of the intermediate memory modules or intermediate storage controllers, and according to both shared and dedicated usage scenarios, accurate available resources are allocated to the hosts from different intermediate memory modules or intermediate storage controllers, and target memory modules and target storage controllers are determined. This allows for the allocation of a memory bandwidth configuration mode with high accuracy, high robustness, and high stability to each host.

[0081] According to embodiments of this application, for generating memory switching instructions, the bandwidth mode controller can also be used to: determine at least one target interconnect controller corresponding to at least one host from among the multiple interconnect controllers based on at least one memory bandwidth configuration mode and bandwidth information determined from attribute information of multiple interconnect controllers.

[0082] According to embodiments of this application, based on at least one memory bandwidth configuration mode, a first link instruction between the host and the target interconnect controller and a second link instruction between the target interconnect controller and the target storage controller are generated according to the identification information of at least one target interconnect controller and the identification information of at least one target storage controller.

[0083] According to embodiments of this application, a memory switching instruction is generated based on at least one memory bandwidth configuration mode, at least one first link instruction, and at least one second link instruction.

[0084] Based on the bandwidth configuration sub-mode in the determined memory bandwidth configuration mode, a target storage controller with independent memory links is determined. Based on the usable bandwidth capacity (number of channels) allocated to the host by the target storage controller with independent memory links, and based on the bandwidth capacity (number of channels) of multiple interconnect controllers, the interconnect controller with the same number of independent memory links and whose bandwidth capacity (number of channels) is greater than and closest to the usable bandwidth capacity (number of channels) allocated to the host by the target storage controller with independent memory links is selected as the target interconnect controller.

[0085] For example, host B's bandwidth configuration sub-mode is a three-to-two (two interconnect controllers) mode under low bandwidth conditions, where the memory links of the first target storage controller (first intermediate storage controller) and the second target storage controller (fourth intermediate storage controller) are independent of each other. The shared first intermediate storage controller has a determined usable bandwidth capacity of 9.8K, the shared third intermediate storage controller has a determined usable bandwidth capacity of 19.6K, and the fourth intermediate storage controller has a determined usable bandwidth capacity of 10.6K. Based on the available bandwidth capacity of 9.8K for the first target storage controller (first intermediate storage controller) and the available bandwidth capacity of 10.6K determined from the fourth intermediate storage controller, a second interconnect controller with a bandwidth capacity of 10K and a third interconnect controller with a bandwidth capacity of 16K are selected from multiple interconnect controllers. This is to facilitate the electrical connection of the links of the first target storage controller (first intermediate storage controller) to the second interconnect controller, and the electrical connection of the links of the second target storage controller (fourth intermediate storage controller) to the third interconnect controller. The memory links of the second target storage controller (third intermediate storage controller) are aggregated to the third interconnect controller based on the principle of proximity in bandwidth capacity.

[0086] When the number of interconnect controllers whose bandwidth capacity (number of channels) is greater than and closest to the number of usable bandwidth capacity (number of channels) allocated to the host by the target storage controller with independent memory links is greater than the number of independent memory links, the target interconnect controller can be selected based on the host's historical interconnect controllers.

[0087] The host control signals may also include, after determining the electrical connection between the host and the host interface of the memory expansion card, the attribute information (identification information) of the determined host interface corresponding to the host. Based on the attribute information (identification information) of the determined host interface corresponding to the host and the identification information of the determined target storage controller, a first link instruction between the host and the interconnect controller can be generated. A second link instruction is generated based on the identification information of the target interconnect controller and the identification information of the storage controller.

[0088] Memory switching instructions can be binary or hexadecimal characters, or instruction signals containing information.

[0089] According to the embodiments of this application, the bandwidth mode controller generates a link instruction for the corresponding memory link based on the memory bandwidth configuration mode, the bandwidth information of multiple interconnect controllers, and the identification information. Then, it generates a memory switching instruction based on the memory bandwidth configuration mode, the first link instruction, and the second link instruction. This allows the connection link between the storage controller and the interconnect controller to be determined, providing multiple application scenarios such as multiple storage controllers corresponding to one interconnect controller and one storage controller corresponding to one interconnect controller, and adapting to various needs such as high bandwidth or shared memory.

[0090] Figure 3 A schematic diagram of a memory expansion card connected to a single host according to an embodiment of this application is shown.

[0091] like Figure 3 As shown, in Figure 2 Based on the connection of some components, a single host (host 1) is electrically connected to the memory expansion card 101. Host 1 has an X8 interface channel and is electrically connected to two host interfaces (host interface 1 and host interface 2, both with X8 channels) simultaneously via a single cable. The baseboard management controller 105 of host 1 is electrically connected to the bandwidth mode controller 104. The bandwidth mode controller 104 generates a memory bandwidth configuration mode and memory switching instructions based on the received host control signals, attribute information of multiple memory modules, attribute information of multiple storage controllers, and attribute information of multiple interconnect controllers. The memory bandwidth configuration mode is that multiple memory modules correspond to multiple storage controllers (interconnect controller 1 has an X8 channel, interconnect controller 2 has an X4 channel), and multiple storage controllers correspond to one interconnect controller. Based on the determined interconnect controller 1 and the determined host interface 1 and host interface 2, multiple host interfaces are determined to correspond to one interconnect controller. The memory switching instructions are sent to the interconnect router and storage router. The interconnect router and storage router connect the memory path according to the memory switching instructions, thus making it suitable for memory-intensive workloads with large memory capacity requirements.

[0092] Figure 4 A schematic diagram of a memory expansion card connected to a single host according to another embodiment of this application is shown.

[0093] like Figure 4 As shown, in Figure 3Based on the connection of some components, a single host (host 1) is electrically connected to the memory expansion card 101. Host 1 has two X4 interface channels, which are electrically connected to two host interfaces (host interface 1 and host interface 2) simultaneously via two cables. The bandwidth mode controller 104 generates a memory bandwidth configuration mode and a memory switching command based on the received host control signals, attribute information of multiple memory modules, attribute information of multiple storage controllers, and attribute information of multiple interconnect controllers. The memory bandwidth configuration mode is that multiple memory modules correspond to multiple storage controllers, and two storage controllers correspond to two interconnect controllers. Based on the determined interconnect controller 1 and interconnect controller 2 and the determined host interface 1 and host interface 2, the two host interfaces are determined to correspond to the two interconnect controllers. The memory switching command is sent to the interconnect router and the storage router. The interconnect router and the storage router connect the memory path according to the memory switching command, thus making it suitable for high-bandwidth, high-performance computing applications.

[0094] Figure 5 A schematic diagram of a memory expansion card connected to multiple hosts according to an embodiment of this application is shown.

[0095] like Figure 5 As shown, in Figure 2 Based on the connection of some components, multiple hosts (host 1 and host 2) are electrically connected to the memory expansion card 101. Host 1 has an X4 interface channel, and host 2 has an X4 interface channel, which are electrically connected to the two host interfaces (host interface 1 and host interface 2) via two cables respectively. The baseboard management controller 105 of host 1 and host 2 is electrically connected to the bandwidth mode controller 104. The bandwidth mode controller 104 generates memory bandwidth configuration modes and memory switching instructions corresponding to host 1 and host 2 respectively based on the received host control signals, attribute information of multiple memory modules, attribute information of multiple storage controllers, and attribute information of multiple interconnect controllers. The memory bandwidth configuration mode of host 1 is one memory module corresponding to one storage controller, and one storage controller corresponding to one interconnect controller. Based on the determined interconnect controller 1 and the determined host interface 1, one host interface is determined to correspond to one interconnect controller. The memory bandwidth configuration mode of host 2 is one memory module corresponding to one storage controller, and one storage controller corresponding to one interconnect controller. Based on the determined interconnect controller 2 and the determined host interface 2, one host interface is determined to correspond to one interconnect controller. At this time, the two hosts do not share memory modules. The memory switching command is sent to the interconnect router and storage route converter. The interconnect router and storage route converter then connect the memory path according to the memory switching command, making it suitable for application scenarios with a large number of hosts and large memory expansion requirements.

[0096] Figure 6A schematic diagram of a memory expansion card connected to multiple hosts according to another embodiment of this application is shown.

[0097] like Figure 6 As shown, in Figure 5 Based on the connection of some components, multiple hosts (host 1 and host 2) are electrically connected to the memory expansion card 101. The bandwidth mode controller 104 generates memory bandwidth configuration modes and memory switching instructions corresponding to host 1 and host 2 respectively, based on the received host control signals, attribute information of multiple memory modules, attribute information of multiple storage controllers, and attribute information of multiple interconnect controllers. The memory bandwidth configuration mode of host 1 is as follows: memory module 1 and memory module 2 correspond to one storage controller 1, memory module 3 and memory module 4 correspond to one storage controller 2, and one storage controller corresponds to multiple interconnect controllers. Based on the determined interconnect controller 1 and the determined host interface 1, one host interface is assigned to one interconnect controller. The memory bandwidth configuration mode of host 2 is as follows: memory module 1 and memory module 2 correspond to one storage controller 1, memory module 3 and memory module 4 correspond to one storage controller 2, and one storage controller corresponds to multiple interconnect controllers. Based on the determined interconnect controller 2 and the determined host interface 2, one host interface is assigned to one interconnect controller. The memory switching instructions are sent to the interconnect router and the storage router. Interconnected routing selectors and storage routing converters can connect memory paths based on memory switching instructions, making them suitable for application scenarios such as distributed databases and collaborative data processing.

[0098] According to embodiments of this application, at least one interconnect controller can also be used to: perform protocol conversion on at least one received host data signal to obtain at least one interconnect memory data signal conforming to the Compute Extended Interconnect Protocol format.

[0099] According to an embodiment of this application, at least one host data to be stored and a cache instruction corresponding to the at least one host data are determined from at least one interconnect memory data signal.

[0100] According to embodiments of this application, at least one interconnect control signal conforming to the Compute Extended Interconnect Protocol format is generated based on memory switching instructions, at least one host data, and at least one cache instruction.

[0101] When the format protocol of the host data signal differs from the recognizable format protocols of the storage controller and memory modules, the interconnect controller needs to perform protocol conversion on the host data signal. The converted interconnect memory data signal is then analyzed to extract the host data to be stored and cached instructions.

[0102] According to embodiments of this application, the interconnect controller can convert the host data signals of different format protocols and then perform parsing processing, thereby generating signals with recognizable format protocols for the storage controller and memory module, so that the storage controller can perform link confirmation and verification.

[0103] According to an embodiment of this application, for the above-mentioned interconnect control signal, at least one interconnect controller can also be used to: perform identification verification on at least one interconnect controller based on the identification information of at least one target interconnect controller extracted from the memory switching instruction.

[0104] According to an embodiment of this application, when the verification is successful and at least one interconnect controller is electrically connected to multiple target storage controllers, the link connection order of the multiple target storage controllers is determined based on the identification information of the multiple target storage controllers determined from at least one memory bandwidth configuration mode and the storage priority of host data indicated by at least one cache instruction.

[0105] According to an embodiment of this application, at least one interconnection control signal is generated based on the multiple link connection sequence, memory switching instructions, and at least one interconnection memory data signal.

[0106] The memory switching instruction can include the identification information of each target interconnect controller, and the identity verification is performed based on the identification stored in the memory switching instruction and the interconnect controller's own identification.

[0107] Due to interleaving and mutual exclusion, when an interconnect controller connects to multiple target storage controllers, only one target storage controller can transmit data through the interconnect controller in a single time period.

[0108] Thus, if the verification passes and at least one interconnect controller is electrically connected to multiple target storage controllers, the link connection order is determined by sequentially querying the identifiers of the target storage controllers with corresponding priorities from the multiple target storage controllers based on the storage priorities of the multiple host data extracted from the interconnect memory data signals.

[0109] For example, host A corresponds to one target interconnect controller, three host data points, and three target storage controllers. The priority order of the three host data points is: second host data point > third host data point > first host data point. The first host data point corresponds to the memory module of the first storage controller, the second host data point corresponds to the memory module of the second storage controller, and the third host data point corresponds to the memory module of the third storage controller. Therefore, the link connection order through one interconnect controller is: first storage controller - third storage controller - second storage controller.

[0110] According to embodiments of this application, after receiving a memory switching instruction, the target interconnect controller can perform identity verification. If the verification passes, it determines whether to connect multiple target storage controllers. If multiple target storage controllers are confirmed to be connected, the link connection order is determined based on information extracted from the cache instructions in the interconnect memory data signals. This improves the efficiency and orderliness of data caching across multiple memory modules of multiple storage controllers via a single interconnect controller, thereby improving caching efficiency and the reliability of the memory expansion card.

[0111] According to embodiments of this application, at least one interconnect controller can also be used to: disconnect the memory link between at least one host and at least one interconnect controller in the event of a failed verification.

[0112] According to an embodiment of this application, a first fault log is generated based on a memory switching instruction and attribute information of at least one storage controller electrically connected to at least one interconnect controller and a plurality of memory modules, and is sent to a bandwidth mode controller.

[0113] The bandwidth mode controller can regenerate memory switching instructions and perform fault self-checks based on the first fault log.

[0114] The interconnect controller can also be electrically connected to the bandwidth mode controller, thereby directly sending the first fault log to the bandwidth mode controller. The interconnect controller can also send the first fault log to the bandwidth mode controller by changing the connectivity link in the interconnect routing selector, causing the memory link of the interconnect controller that fails verification to switch to an electrical connection with the bandwidth mode controller.

[0115] Furthermore, if the memory update switch command sent by the bandwidth mode controller still fails the identity verification in the storage controller, the storage controller can send a fault pause request to the bandwidth mode controller. The bandwidth mode controller will then confirm the suspension of the memory expansion card based on the fault pause request.

[0116] According to an embodiment of this application, if identity verification fails, a report can be sent to the bandwidth mode controller by generating a fault log. This facilitates the bandwidth mode controller instructing the host or peripheral load to perform fault self-checks, thereby improving the link security and reliability of the memory expansion card.

[0117] According to embodiments of this application, at least one storage controller may also be used to: extract identification information of at least one target memory module, at least one memory bandwidth configuration mode, and at least one cache instruction from at least one interconnect control signal.

[0118] According to an embodiment of this application, identification verification is performed on a plurality of memory modules electrically connected to at least one storage controller based on the identification information of at least one target memory module.

[0119] According to an embodiment of this application, when the verification is successful and multiple interconnect control signals from multiple interconnect controllers are received, the receiving order of the receiving host data is determined based on the partition address within at least one target memory module, multiple memory bandwidth configuration modes, and multiple cache instructions.

[0120] The memory switching instruction may include the identification information of each target memory module, and the identity verification is performed based on the identification stored in the memory switching instruction and the identification of the memory module itself that is electrically connected to the storage controller.

[0121] Due to interleaving and mutual exclusion, when a storage controller is connected to multiple target interconnect controllers, only one target interconnect controller can transmit data through the storage controller in a single time period.

[0122] Thus, when the verification is successful and at least one storage controller is electrically connected to multiple target interconnect controllers, based on the identification information of multiple target memory modules determined from the memory bandwidth configuration mode, the storage priority and storage address of multiple host data extracted from the cache instructions, the identification and partition address of the memory module with the corresponding priority are sequentially queried from the multiple target memory modules, and combined with the priority of different partitions within the memory module, the priority of the cached data of the target memory module is determined, and then the link connection order corresponding to the target storage controller is determined.

[0123] According to embodiments of this application, after receiving a memory switching instruction, the target memory module can perform identity verification. If the verification passes, it determines whether to connect to multiple target interconnect controllers. If multiple target interconnect controllers are confirmed to be connected, the link connection order is determined based on information extracted from the cache instructions in the interconnect memory data signals. This improves the efficiency and orderliness of data reception between a storage controller and multiple interconnect controllers, thereby improving cache efficiency and the reliability of the memory expansion card.

[0124] According to embodiments of this application, at least one storage controller can also be used to: periodically poll the target memory module currently receiving host data within a predetermined time period.

[0125] According to an embodiment of this application, if the polling result indicates that no host data has been received, the next host data is received based on the receiving order, and the next host data is sent to the target memory module corresponding to the next host data.

[0126] The storage controller can periodically verify the operation of multiple memory modules electrically connected to the storage controller within a predetermined time period. If the polling result indicates that the target memory module has not received host data, it confirms that the target memory module has completed caching the host data, receives the next host data, and performs real-time monitoring.

[0127] According to the embodiments of this application, by using the storage controller to poll and confirm the working status of received data and memory module cached data, the caching process of the next host data can be started in a timely manner when the current host data has been cached, thereby improving caching efficiency.

[0128] According to embodiments of this application, at least one storage controller can also be used to: disconnect the memory link between at least one interconnect controller and at least one storage controller in the event of a failed verification.

[0129] According to an embodiment of this application, a second fault log is generated based on at least one interconnection control signal and sent to the bandwidth mode controller.

[0130] The bandwidth mode controller can regenerate memory switching instructions and perform fault self-checks based on the second fault log.

[0131] The storage controller can also be electrically connected to the bandwidth mode controller, thereby directly sending the second fault log to the bandwidth mode controller. Alternatively, the storage controller can switch links via the interconnect controller through an already connected memory link, so that the memory link of the interconnect controller that failed verification is switched to an electrical connection with the bandwidth mode controller, thereby sending the second fault log to the bandwidth mode controller.

[0132] Furthermore, if the memory update switch command sent by the bandwidth mode controller still fails the identity verification in the storage controller, the storage controller can send a fault pause request to the bandwidth mode controller. The bandwidth mode controller will then confirm the suspension of the memory expansion card based on the fault pause request.

[0133] According to an embodiment of this application, if identity verification fails, a report can be sent to the bandwidth mode controller by generating a fault log. This facilitates the bandwidth mode controller instructing the host or peripheral load to perform fault self-checks, thereby improving the link security and reliability of the memory expansion card.

[0134] Figure 7 A schematic diagram of a memory expansion card connected to multiple hosts according to yet another embodiment of this application is shown.

[0135] like Figure 7As shown, the memory expansion card 101 may include six host interfaces (host interface 1, host interface 2, host interface 3, host interface 4, host interface 5, and host interface 6), four interconnect controllers (interconnect controller 1, interconnect controller 2, interconnect controller 3, and interconnect controller 4), and seven storage controllers (storage controller 1, storage controller 2, storage controller 3, storage controller 4, storage controller 5, storage controller 6, and storage controller 7). Each storage controller is electrically connected to two memory modules, for a total of fourteen memory modules. When four hosts need to expand their memory capacity through this memory expansion card 101, the baseboard management controller 105 of each host is electrically connected to the bandwidth mode controller 104.

[0136] Host 1 has an X8 interface channel, which is electrically connected to two host interfaces (host interface 1 and host interface 2) simultaneously via a single cable. The memory bandwidth configuration mode is two memory modules corresponding to two storage controllers, and two storage controllers corresponding to two interconnect controllers (storage controller 1 to interconnect controller 1, storage controller 4 to interconnect controller 2). Based on the determined interconnect controllers 1 and 2, and the determined host interfaces 1 and 2, the two host interfaces are matched with the two interconnect controllers.

[0137] Host 2 uses an X16 interface channel and is electrically connected to one host interface (host interface 4) via a single cable. The memory bandwidth configuration is one memory module to one storage controller, and one storage controller to one interconnect controller (storage controller 5 to interconnect controller 3). Based on the determined interconnect controller 3 and host interface 4, one host interface is assigned to one interconnect controller.

[0138] Host 3 has two X4 interface channels, which are electrically connected to two host interfaces (host interface 3 and host interface 5) simultaneously via two cables. The memory bandwidth configuration mode is two memory modules corresponding to two storage controllers, and two storage controllers corresponding to one interconnect controller (storage controller 3 and storage controller 5 to interconnect controller 4). Based on the determined interconnect controller 4 and the determined host interfaces 3 and 4, multiple host interfaces are assigned to one interconnect controller.

[0139] Host 4 has an X4 interface channel, which is electrically connected to a host interface (host interface 6) via a single cable. The memory bandwidth configuration is one memory module to one storage controller, and one storage controller to one interconnect controller (storage controller 7 to interconnect controller 2). Based on the determined interconnect controller 2 and the determined host interface 6, one host interface is assigned to one interconnect controller.

[0140] In this configuration, host 1 performs high-bandwidth data transmission with simultaneous data caching via interconnect controllers 1 and 2, while host 3 performs data transmission with separate data caching via interconnect controller 4 at different times. Host 1 and host 4 share one interconnect controller 2, host 2 and host 3 share one interconnect controller 4, and host 1 and host 3 share one storage controller 1.

[0141] Figure 8 A schematic diagram of the interface of a memory expansion card according to an embodiment of this application is shown.

[0142] like Figure 8 As shown, the memory expansion card may also include a clock interface, a bandwidth mode interface, a repeater interface, a serial peripheral interface, and an indicator light interface.

[0143] Specifically, the clock interface can be electrically connected to a clock generator to receive clock signals from at least one host for clock synchronization, wherein the clock transmission channel can be 100MHz. The bandwidth mode interface can be electrically connected to at least one baseboard management controller to receive at least one host signal and send at least one host signal to the bandwidth mode controller. The repeater interface, electrically connected to a peripheral load, is used to send fault logs to the peripheral load for debugging using the peripheral load, wherein, for example... Figure 8 As shown, the repeater interface can first connect to a 3.3V to 1.8V voltage converter, then to a USB (Universal Serial Bus) interface, and finally to a peripheral load. The serial peripheral interface can be electrically connected to the flash memory module to read the basic configuration from the flash memory module after the memory expansion card is powered on, for memory initialization. The indicator light interface can be electrically connected to the indicator lights to send flashing signals to the indicator lights based on the power-on status of the memory expansion card and the host data storage status, causing the indicator lights to flash at a target frequency. Specifically, a constantly lit indicator light indicates that the memory expansion card has been powered on and initialized, while a flashing indicator light indicates that the memory expansion card is storing data.

[0144] Figure 9 A flowchart of a storage method according to an embodiment of this application is shown.

[0145] like Figure 9 As shown, the storage method of this embodiment may include operations S910 to S940.

[0146] When operating the S910, after the memory expansion card has completed memory initialization and is electrically connected to at least one host, clock synchronization is performed with at least one host.

[0147] When operating the S920, the bandwidth mode controller determines the memory bandwidth configuration mode of at least one host based on host control signals from at least one host, attribute information of multiple memory modules, and attribute information of multiple storage controllers, and generates memory switching instructions based on the memory bandwidth configuration mode and attribute information of multiple interconnect controllers.

[0148] When operating S930, the routing control module connects the memory links between at least one host, at least one interconnect controller and at least one storage controller according to the memory switching instruction, and generates interconnect control signals according to the data signals of at least one host and the memory switching instruction.

[0149] In operation S940, at least one storage controller determines a target memory module based on an interconnect control signal, so that the target memory module receives and stores host data in the host data signal.

[0150] After the memory expansion card is powered on, the initialization firmware can be read from the flash memory module and the initialization can be completed.

[0151] According to embodiments of this application, when at least one host needs to store data, a host control signal can be sent to the bandwidth mode controller. Based on relevant control parameters and other information, a multi-dimensional comprehensive judgment is made on the host's bandwidth and memory requirements to determine the memory bandwidth configuration mode. This allows for adaptation to the bandwidth control and storage needs of single and multiple hosts in various application scenarios, providing hosts with high-efficiency data storage and memory sharing applications. Then, the link switching submodule, according to the memory switching instruction, connects the memory link and transmits host data to the target memory module. This enables a single host to connect to multiple interconnect controllers and multiple storage controllers simultaneously, thereby providing high-bandwidth data caching or data storage for multiple memory modules while simultaneously expanding memory capacity for single or multiple hosts.

[0152] According to embodiments of this application, the storage system may include multiple hosts, the aforementioned memory expansion card, and multiple memory modules. The multiple hosts can be used to send at least one host control signal and at least one host data signal to the memory expansion card. The multiple memory modules can be used to receive and store host data from the memory expansion card.

[0153] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0154] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0155] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0156] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A memory expansion card, characterized in that, The memory expansion card includes: A bandwidth mode controller is used to determine the memory bandwidth configuration mode of at least one host based on the received host control signal, attribute information of multiple memory modules and attribute information of multiple storage controllers, and to generate memory switching instructions based on the memory bandwidth configuration mode and attribute information of multiple interconnect controllers. The routing control module, electrically connected to the bandwidth mode controller, includes a link switching submodule and multiple interconnect controllers. The link switching submodule is used to connect the memory links between the at least one host, the at least one interconnect controller and the at least one storage controller according to the memory switching instruction, so that the at least one interconnect controller generates an interconnect control signal according to the at least one host data signal and the memory switching instruction. Multiple storage controllers, electrically connected to the routing control module, are used to determine a target memory module based on at least one interconnect control signal, so that the target memory module receives and stores host data in the host data signal.

2. The memory expansion card according to claim 1, characterized in that, The bandwidth mode controller is also used for: From the at least one host control signal, determine the ideal bandwidth, ideal memory, and adjustment parameters of the at least one host; Based on the attribute information of at least one ideal memory and multiple memory modules, determine at least one intermediate memory module corresponding to the at least one host; Based on the attribute information of at least one ideal bandwidth, at least one intermediate memory module, and the plurality of storage controllers, determine at least one intermediate storage controller corresponding to the at least one host; Based on the at least one intermediate memory module, at least one intermediate storage controller, and the percentage information obtained after adjusting the at least one ideal memory and the at least one ideal bandwidth using the adjustment parameters, the memory bandwidth configuration mode of the at least one host is determined, wherein the percentage information represents the ratio between the actual usage of the host and the total memory of the memory modules and the total bandwidth of the storage controller.

3. The memory expansion card according to claim 2, characterized in that, The percentage information includes bandwidth percentage and memory percentage, and the bandwidth mode controller is also used for: Based on the at least one ideal bandwidth and the attribute information of the plurality of storage controllers, the at least one intermediate storage controller is determined from the at least one storage controller electrically connected to the at least one intermediate memory module; Based on the occupancy priority of the at least one host and the identification order of the at least one intermediate memory module, in the case where there is at least one shared intermediate memory module among multiple hosts, a first target memory module is determined from the at least one shared intermediate memory module according to the memory proportion of the at least one host, and a second target memory module is determined from the intermediate memory modules other than the at least one shared intermediate memory module. Based on the occupancy priority of the at least one host and the identification order of the at least one intermediate storage controller, in the case where there is at least one shared intermediate storage controller among the multiple hosts, a first target storage controller is determined from the at least one shared intermediate storage controller according to the bandwidth ratio of the at least one host, and a second target storage controller is determined from the intermediate storage controllers other than the at least one shared intermediate storage controller. Based on the number of the first target memory module and the second target memory module, determine the memory configuration sub-mode of the at least one host; Based on the ideal bandwidth, the number of the first target storage controller and the number of the second target storage controller, determine the bandwidth configuration sub-mode of the at least one host; The memory bandwidth configuration mode is determined based on the memory configuration sub-mode, the bandwidth configuration sub-mode, and the occupancy priority of the at least one host.

4. The memory expansion card according to claim 1, characterized in that, The attribute information includes identification information, and the bandwidth mode controller is further configured to: Based on the at least one memory bandwidth configuration mode and the bandwidth information determined from the attribute information of the plurality of interconnect controllers, at least one target interconnect controller corresponding to the at least one host is determined from the plurality of interconnect controllers; Based on the at least one memory bandwidth configuration mode, a first link instruction between the host and the target interconnect controller and a second link instruction between the target interconnect controller and the target storage controller are generated according to the identification information of at least one target interconnect controller and the identification information of at least one target storage controller. The memory switching instruction is generated based on the at least one memory bandwidth configuration mode, at least one first link instruction, and at least one second link instruction.

5. The memory expansion card according to claim 1, characterized in that, The link switching submodule includes: An interconnect router, electrically connected to at least one host interface and the bandwidth mode controller, is used to connect a memory link between the at least one host and the at least one interconnect controller according to the memory switching instruction, wherein the at least one host is electrically connected to the interconnect router through the at least one host interface; A storage routing converter, electrically connected to the interconnect routing selector and the plurality of storage controllers, is used to connect the memory link between the at least one interconnect controller and the at least one storage controller according to the memory switching instruction.

6. The memory expansion card according to claim 1, characterized in that, The at least one interconnect controller is further configured to: The received host data signal is converted into a protocol to obtain at least one interconnect memory data signal conforming to the Compute Extended Interconnect Protocol format; From the at least one interconnect memory data signal, determine at least one host data to be stored and a cache instruction corresponding to the at least one host data; Based on the memory switching instruction, at least one host data, and at least one cache instruction, at least one interconnect control signal conforming to the Compute Extended Interconnect Protocol format is generated.

7. The memory expansion card according to claim 6, characterized in that, The at least one interconnect controller is further configured to: Based on the identification information of at least one target interconnect controller extracted from the memory switching instruction, the identification of the at least one interconnect controller is verified. If the verification passes and the at least one interconnect controller is electrically connected to the plurality of target storage controllers, the link connection order of the plurality of target storage controllers is determined based on the identification information of the plurality of target storage controllers determined from at least one memory bandwidth configuration mode and the storage priority of host data indicated by at least one cache instruction. The at least one interconnect control signal is generated based on the multiple link activation sequence, the memory switching instruction, and at least one interconnect memory data signal; If the verification fails, disconnect the memory link between the at least one host and the at least one interconnect controller; Based on the memory switching instruction and the attribute information of at least one storage controller and multiple memory modules electrically connected to the at least one interconnect controller, a first fault log is generated and sent to the bandwidth mode controller.

8. The memory expansion card according to claim 1, characterized in that, The at least one storage controller is further configured to: Extract at least one target memory module's identification information, at least one memory bandwidth configuration mode, and at least one cache instruction from the at least one interconnect control signal; Based on the identification information of the at least one target memory module, identification verification is performed on multiple memory modules electrically connected to the at least one storage controller; If the verification is successful and multiple interconnect control signals are received from the multiple interconnect controllers, the receiving order of receiving the host data is determined based on the partition address in at least one target memory module, multiple memory bandwidth configuration modes, and multiple cache instructions. If the verification fails, disconnect the memory link between the at least one interconnect controller and the at least one storage controller; generate a second fault log based on at least one interconnect control signal, and send it to the bandwidth mode controller.

9. The memory expansion card according to claim 8, characterized in that, The at least one storage controller is further configured to: The target memory module currently receiving host data is periodically polled during a predetermined time period. If the polling result indicates that no host data has been received, the next host data is received based on the receiving order, and the next host data is sent to the target memory module corresponding to the next host data.

10. The memory expansion card according to claim 1, characterized in that, The memory expansion card also includes: Multiple host interfaces are electrically connected to the routing control module for electrical connection with the interface of at least one host. In the case where the bandwidth of any host interface is less than the interface bandwidth of the host to be connected, the host is electrically connected to the multiple host interfaces via a cable so that the interface bandwidth of the host to be connected is the same as the total bandwidth of the multiple connected host interfaces. A clock interface, electrically connected to a clock generator, is used to receive clock signals from at least one host computer for clock synchronization. A bandwidth mode interface, electrically connected to the at least one baseboard management controller, is used to receive at least one host signal and send the at least one host signal to the bandwidth mode controller; A repeater interface, electrically connected to a peripheral load, is used to send fault logs to the peripheral load for debugging. A serial peripheral interface, electrically connected to the flash memory module, is used to read the basic configuration from the flash memory module after the memory expansion card is powered on, in order to perform memory initialization; An indicator light interface, electrically connected to the indicator light, is used to send a flashing signal to the indicator light based on the power-on status of the memory expansion card and the host data storage status, so that the indicator light flashes at a target frequency.

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